SimtekLow Voltage SoftStore nvSRAM Features Description UL631H256
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UL631H256
SimtekLow Voltage SoftStore nvSRAM
Features Description UL631H256 separate modes operation: SRAM mode nonvolatile mode. SRAM mode, memory operates ordinary static RAM. nonvolatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. UL631H256 fast static ns), with nonvolatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent nonvolatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation), from EEPROM SRAM (the RECALL operation) initiated through software sequences. UL631H256 combines high performance ease fast SRAM with nonvolatile data integrity. Once STORE cycle initiated, further input output disabled until cycle completed. Because sequence addresses used STORE initiation, important that other read write accesses intervene sequence sequence will aborted. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. UL631H256 compatible with standard SRAMs.
High-performance CMOS nonvolatile static 32768 bits Access Times Output Enable Access Times Software STORE Initiation Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Software RECALL Initiation Unlimited RECALL cycles from EEPROM Unlimited Read Write SRAM Wide voltage range: (3.0 type) Operating temperature range: 9000 Quality Standard RoHS compliance free protection 2000 (MIL 883C M3015.7-HBM) Package: (330 mil)
Configuration
Description
TSOP
n.c. n.c.
Signal Name
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
View
View
March 2006
Control #ML0057
UL631H256
Block Diagram
Input Buffers EEPROM Array STORE Decoder SRAM Array Rows Columns
Store/ Recall Control
RECALL
Column Column Decoder
Software Detect
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type
Symbol Tstg
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
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UL631H256
Recommended Operating Conditions Power Supply Voltage Symbol Conditions Pulse Width permitted Min. -0.3 Max. VCC+0.3 Unit
Input Voltage Input High Voltage
C-Type Characteristics Operating Supply Currentb Symbol ICC1 Average Supply Current during STOREc ICC2 Standby Supply Curentd (Stable CMOS Input Levels) ICC(SB) Conditions Min. VCC-0.2 VCC-0.2 VCC-0.2 3.6V VCC-0.2 VCC-0.2 35ns VCC-0.2 VCC-0.2 Max.
K-Type Unit Min. Max.
Average Supply Current (Cycling CMOS Input Levels) Standby Supply Currentd (Cycling Input Levels)
ICC3
ICC(SB)1
ICC1 ICC3 dependent output loading cycle rate. specified values obtained with outputs unloaded current ICC1 measured WRITE/READ ratio 1/2. ICC2 average current required duration STORE cycle (tSTORE). Bringing will produce standby current levels until nonvolatile cycle progress timed out. current ICC(SB)1 measured WRITE/READ ratio 1/2.
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Control #ML0057
UL631H256
C-Type Characteristics Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current VCCmin VCCmin Max. Min. Max. K-Type Unit
SRAM Memory Operations
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Addr. Changeg
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) Min.
Unit Max.
Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both Low. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
Control #ML0057
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UL631H256
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle E-controlled (during Read cycle: VIH)g
Output High Impedance (10) ACTIVE STANDBY
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G)
(11) tdis(E) tdis(G) Output Data Valid
Switching Characteristics Write Cycle Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
Symbol Alt. Alt. Min.
Max. Min.
Unit Max.
tAVAV tWLWH
tAVAV
tw(W)
tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH
tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
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Control #ML0057
UL631H256
Write Cycle W-controlledj
(12)
Input tsu(A)
(15)
Address Valid tsu(E) (17) tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W) (12) Previous Data
th(A) (21)
th(D) (20)
Input Data Valid ten(W) (23) High Impedance
Output
Write Cycle E-controlledj
(12)
Input tsu(A) (15)
Address Valid tw(E) (18) tsu(W) (14) tsu(D) (19) th(D) (20) th(A) (21)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes low, outputs remain high impedance state. must during address transitions.
Control #ML0057
March 2006
UL631H256
Nonvolatile Memory Operations
STORE Cycle Inhibit Automatic Power RECALL
Symbol Min. Alt. tRESTORE VSWITCH Max. Unit
Power RECALL Durationk Voltage Trigger Level
tRESTORE starts from time rises above VSWITCH.
STORE Cycle Inhibit Automatic Power RECALL VSWITCH
STORE inhibit Power RECALL Software Mode Selection (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
(24)
tRESTORE
Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output Data Output Data Output Data Output Data Output Data Output High Output Data Output Data Output Data Output Data Output Data Output High
Power Active
Notes
ICC2 Active
consecutive addresses must order listed. must high during consecutive cycles. STORE cycle RECALL cycle tables diagrams further details. following six-address sequence used testing purposes should used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C. While there addresses UL631H256, only lower used control software modes.
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Control #ML0057
UL631H256
Symbol Software Controlled STORE/RECALL Cyclel, STORE/RECALL Initiation Time Chip Enable Output Inactiveo STORE Cycle Timep RECALL Cycle Timeq Address Setup Chip Enabler Chip Enable Pulse Widthr, Chip Disable Address Changer
Min. Max.
Unit Min. Max.
Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN
tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
software sequence clocked with controlled READs Once software controlled STORE RECALL cycle initiated, completes automatically, ignoring inputs. Note that STORE cycles (but RECALL) aborted VSWITCH (STORE inhibit). automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly. Noise trigger multiple READ cycles from same address abort address sequence. Chip Enable Pulse Width less than ta(E) (see Read Cycle) greater than equal tw(E)SR, than data valid pulse, however STORE RECALL will still initiated.
Software Controlled STORE/RECALL Cyclet, HIGH after STORE initiation)
(25)
(25) ADDRESS
ADDRESS tw(E)SR tsu(A)SR (29)
(30)
th(A)SR
(31)
Output
td(E)S (27) td(E)R (28) VALID tdis(E)SR (26)
High Impedance
VALID
Software Controlled STORE/RECALL Cycler, after STORE initiation)
(25)
ADDRESS tw(E)SR tsu(A)SR (29)
(30) (31) th(A)SR
ADDRESS th(A)SR (31)
(29)
Output
High Impedance
tsu(A)SR
td(E)S (27) VALID tdis(E)SR (26)
td(E)R (28)
VALID
must HIGH when during address sequence order initiate nonvolatile cycle. either HIGH throughout. Addresses through found mode selection table. Address determines wheter UL631H256 performs STORE RECALL. must used clock address sequence Software controlled STORE RECALL cycles.
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UL631H256
Test Configuration Functional Check
VCCw
Input level according
relevant test measurement
ment output pins
Simultaneous measure-
measurement tdis-times ten-times capacitance
Between must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
pins under test must connected with ground capacitors. Ordering Code Example Type Package SOP28 (330mil) Type SOP28 (330mil) Type Operating Temperature Range
special request
UL631H256
Leadfree Option blank Standard Package Leadfree Green Package Access Time (VCC (VCC
Device Marking (example) Product specification
UL631H256S2C 0425
Date manufacture (The first digits indicating year, last digits calendar week.) Leadfree Green Package
Internal Code March 2006 Control #ML0057
UL631H256
Device Operation UL631H256 separate modes operation: SRAM mode nonvolatile mode. memory operates SRAM mode standard fast static RAM. Data transferred nonvolatile mode from SRAM EEPROM shadow (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. SRAM READ UL631H256 performs READ cycle whenever while HIGH. address specified pins determines which 32768 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pins, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE WRITE cycle performed whenever LOW. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pins will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis(W) after goes LOW. Noise Consideration UL631H256 high speed memory therefore must have high frequency bypass capacitor approximately connected between using leads traces that short possible. with high speed CMOS ICs, normal carefull routing power, ground signals will help prevent noise problems. Software Nonvolatile STORE UL631H256 software controlled STORE cycle initiated executing sequential READ cycles from specific address locations. relying READ cycles only, UL631H256 implements nonvolatile operation while remaining compatible with standard SRAMs. During STORE cycle, erase preSTK Control #ML0057 vious nonvolatile data first performed, followed program nonvolatile elements. Once STORE cycle initiated, further inputs outputs disabled until cycle completed. Because sequence addresses used STORE initiation, important that other READ WRITE accesses intervene sequence sequence will aborted STORE RECALL will take place. initiate STORE cycle following READ sequence must performed: Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0FC0 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle
Once sixth address sequence been entered, STORE cycle will commence chip will disabled. important that READ cycles WRITE cycles used sequence, although necessary that sequence valid. After tSTORE cycle time been fulfilled, SRAM will again activated READ WRITE operation. Software Nonvolatile RECALL RECALL cycle EEPROM data into SRAM initiated with sequence READ operations manner similar STORE initiation. initiate RECALL cycle following sequence READ operations must performed: Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0E38 31C7 03E0 3C1F 303F 0C63 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle
Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. Automatic Power RECALL power once exceeds sense voltage VSWITCH, RECALL cycle automatically initiated. voltage must drop below VSWITCH once risen above order March 2006
UL631H256
RECALL,SRAM operation cannot commence until tRESTORE after exceeds VSWITCH. UL631H256 WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between VCC. Hardware Protection UL631H256 offers hardware protection against inadvertent STORE operation through sense. VSWITCH software initiated STORE operation will inhibited. Average Active Power UL631H256 been designed draw significantly less power when (chip enabled) cycle time longer than When HIGH chip consumes only standby current. overall average current drawn part depends following items: CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature level
information describes type component shall considered assured characteristics. Terms delivery rights change design reserved.
March 2006
Control #ML0057
UL631H256
LIFE SUPPORT POLICY Simtek products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Simtek product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized Simtek such purpose.
LIMITED WARRANTY information this document been carefully checked believed reliable. However, Simtek makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. Simtek does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent Simtek's warranty product beyond that forth standard terms conditions sale. Simtek reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 01.11.2001 03.07.2002 25.09.2002 09.01.2003 20.10.2003 05.12.2003 21.04.2004 7.4.2005 31.3.2006 Name Ivonne Steffens Matthias Schniebel Matthias Schniebel Matthias Schniebel Matthias Schniebel Matthias Schniebel Matthias Schniebel Stefan Troy Meester Simtek Change format revision release ,,Memory 2002" adding type with Adding ,,Type SOP28 (330mil) Removing type Voltage Trigger Level VSWITCH (old: adding K-Type with ICC1 ICC(SB)1 12mA adding ,,Leadfree Green Package" ordering information adding ,,Device Marking" adding RoHS compliance free, endurance cycles, 100a data retention, package chippack changed obsolete status Assigned Simtek Document Control Number
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