CapStore nvSRAM Features Description U63764 separate modes operat

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CapStore nvSRAM Features Description U63764 separate modes operat

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U63764
CapStore nvSRAM
Features Description U63764 separate modes operation: SRAM mode nonvolatile mode. SRAM mode, memory operates ordinary static RAM. non-volatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. U63764 static with non-volatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent nonvolatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation) take place automatically upon power down using charge stored integrated capacitor. Transfers from EEPROM SRAM (the RECALL operation) take place automatically power U63764 combines ease SRAM with nonvolatile data integrity. Description STORE cycles also initiated under user control software sequence. Once STORE cycle initiated, further input output disabled until cycle completed. Because sequence addresses used STORE initiation, important that other read write accesses intervene sequence sequence will aborted. RECALL cycles also initiated software sequence. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. U63764 compatible with standard SRAMs standard battery backed SRAMs.
CMOS non- volatile static 8192 bits Access Time Output Enable Access Time Cycle Time Unlimited Read Write Cycles SRAM Automatic STORE EEPROM Power Down using charge stored integrated capacitor Software initiated STORE Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Software RECALL Initiation Unlimited RECALL cycles from EEPROM Single Operation Operating temperature range: 9000 Quality Standard protection 2000 (MIL 883C M3015.7) RoHS compliance free Package: PDIP28 (600 mil)
Configuration
n.c.
n.c.
Signal Name
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
PDIP
View March 2006 Control #ML0055
U63764
Block Diagram
EEPROM Array 128x STORE Decoder SRAM Array 128Rows Columns
Store/ Recall Control
RECALL
Power Control
Input Buffers
Column Column Decoder
Software Detect
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
Symbol
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
C-Type K-Type
Tstg
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Control #ML0055
March 2006
U63764
Recommended Operating Conditions Power Supply Voltage Input Voltage Input High Voltage Symbol Pulse Width permitted Conditions Min. -0.3 Max. VCC+0.3 Unit
C-Type Characteristics Operating Supply Currentb Symbol ICC1 Conditions Min. VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 Max.
K-Type Unit Min. Max.
Average Supply Current duringc STORE
ICC2
Operating Supply Currentb (Cycling CMOS Input Levels) Standby Supply Currentd (Cycling Input Levels) Standby Supply Curentd (Stable CMOS Input Levels)
ICC3
ICC(SB)1
ICC(SB)
ICC1 ICC3 depedent output loading cycle rate. specified values obtained with outputs unloaded. current ICC1 measured WRITE/READ ratio 1/2. ICC2 average current required duration SoftStore STORE cycle. Bringing will produce standby current levels until software initiated nonvolatile cycle progress timed out. MODE SELECTION table. current ICC(SB)1 measured WRITE/READ ratio 1/2.
March 2006
Control #ML0055
U63764
C-Type Characteristics Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current Max. Min. Max. K-Type Unit
SRAM Memory Operations
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Address Change
Symbol Min. Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) Max. Unit
Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both Low. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
Control #ML0055
March 2006
U63764
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle E-controlled (during Read cycle: VIH)g
Output
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G) High Impedance (10) ACTIVE STANDBY
tdis(E) (11) tdis(G) Output Data Valid
Switching Characteristics Write Cycle
Symbol Min. Alt. Alt. tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH tAVAV tw(W) tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W) Max. Unit
Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
March 2006
Control #ML0055
U63764
Write Cycle W-controlledj
(12)
tsu(A)
(15)
Address Valid tsu(E) (17) tsu(A-WH) (16) tw(W) (13) tsu(D) (19) th(D) (20) th(A) (21)
Input
Input Data Valid tdis(W) (22) Previous Data ten(W) (23) High Impedance
Output
Write Cycle E-controlledj
(12)
Input tsu(A) (15)
Address Valid tw(E) (18) th(A) (21)
tsu(W) (14) tsu(D) (19) th(D) (20)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes low, outputs remain high impedance state. must during address transition.
Control #ML0055
March 2006
U63764
Nonvolatile Memory Operations Mode Selection
(hex) 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E
Mode Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output High Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Output Data Output Data Output Data Output Data Output Data Output High
Power Standby Active Active Active
Notes
Active
consecutive addresses must order listed. must high during consecutive cycles. STORE cycle RECALL cycle tables diagrams further details. following six-address sequence used testing purposes should used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C. Activation nonvolatile cycles does depend state state assumes that VIL.
PowerStore Power RECALL
Symbol Conditions Alt. tRESTORE tPDSTORE tDELAY VSWITCH Min. Max. Unit
Power RECALL Durationn STORE Cycle Durationf, Time allowed Complete SRAM Cyclef Voltage Trigger Level
tRESTORE starts from time rises above VSWITCH.
March 2006
Control #ML0055
U63764
PowerStore automatic Power RECALL VSWITCH
PowerStore tPDSTORE
(25)
Power RECALL
(24)
(24)
tRESTORE
tRESTORE tDELAY
POWER RECALL
BROWN STORE SRAM WRITES)
BROWN PowerStore
Software Controlled STORE/ RECALL Cyclek,
Symbol Min. Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR Max. Unit
STORE/RECALL Initiation Time Chip Enable Output Inactivep STORE Cycle Timeq RECALL Cycle Timer Address Setup Chip Enables Chip Enable Pulse Widths, Chip Disable Address Changes
software sequence clocked with controlled READs. Once software controlled STORE RECALL cycle initiated, completes automatically, ignoring inputs. Note that STORE cycles (but RECALL) inhibited VSWITCH (STORE inhibit). automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly. Noise trigger multiple READ cycles from same address abort address sequence. Chip Enable Pulse Width less than ta(E) (see Read Cycle) greater than equal tw(E)SR, than data valid pulse, however STORE RECALL will still initiated.
Control #ML0055
March 2006
U63764
Software Controlled STORE/RECALL Cyclet, HIGH after STORE initiation)
(27)
(27) ADDRESS
Output
ADDRESS tw(E)SR tsu(A)SR (31) High Impedance
(32) (33) th(A)SR
td(E)S (29)
td(E)R (30)
VALID
VALID tdis(E)SR (28)
Software Controlled STORE/RECALL Cyclet, after STORE initiation)
(29)
ADDRESS tw(E)SR
(34)
ADDRESS th(A)SR
(35)
tsu(A)SR (33)
(35) th(A)SR
(33)
Output
High Impedance
tsu(A)SR
td(E)S (31)
td(E)R (32)
VALID
VALID tdis(E)SR (30)
must HIGH when during address sequence order initiate nonvolatile cycle. either HIGH throughout. Addresses through found mode selection table. Address determines wheter U63764 performs STORE RECALL. must used clock address sequence Software controlled STORE RECALL cycles.
March 2006
Control #ML0055
U63764
Test Configuration Functional Check
VCCx
relevant test measurement
Input level according
ment output pins
Simultaneous measure-
measurement tdis-times ten-times capacitance Between must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
Pins under test must connected with ground capacitors. Ordering Code Example Type U63764 Leadfree Option blank Standard Package Leadfree Green Package Access Time Operating Temperature Range
Package PDIP28 (600mil)
special request
Device Marking (example) Product specification
U63764DK 0425
Date manufacture (The first digits indicating year, last digits calendar week.) Leadfree Green Package March 2006
Internal Code
Control #ML0055
U63764
Device Operation U63764 separate modes operation: SRAM mode nonvolatile mode. memory operates SRAM mode standard static RAM. Data transferred nonvolatile mode from SRAM EEPROM (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. STORE cycles initiated under user control software sequence also automatically initiated when power supply voltage level chip falls below VSWITCH. RECALL operations automatically initiated upon power also occur when rises above VSWITCH, after power condition. RECALL cycles also initiated software sequence. SRAM READ U63764 performs READ cycle whenever HIGH. address specified pins determines which 8192 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pins, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE WRITE cycle performed whenever LOW. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pins will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis after goes LOW. Automatic STORE During normal operation, U63764 will draw current from charge integrated capacitor. This stored charge will used chip perform single STORE operation. voltage drops below VSWITCH, part will automatically disconnect internal components from external power supply with typical delay initiate STORE operation with tPDSTORE max. March 2006 Control #ML0055 Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0000 1555 0AAA 1FFF 10F0 0F0F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE Cycle order prevent unneeded STORE operations, automatic STORE will ignored unless least WRITE operation taken place since most recent STORE RECALL cycle. Software initiated STORE cycles performed regardless whether WRITE operation taken place. SRAM READ WRITE operations that progress after automatic STORE cycle power down requested given time complete before STORE operation initiated. During tDELAY multiple SRAM READ operations take place. WRITE progress will allowed time, tDELAY, complete. SRAM WRITE cycles requested after drops below VSWITCH will inhibited. Automatic RECALL During power automatic RECALL takes place. power condition (power supply voltage VSWITCH) internal RECALL request latched. soon power supply voltage exceeds sense voltage VSWITCH, requested RECALL cycle will automatically initiated will take tRESTORE complete. U63764 WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between power supply voltage. Software Nonvolatile STORE U63764 software controlled STORE cycle initiated executing sequential READ cycles from specific address locations. relying READ cycles only, U63764 implements nonvolatile operation while remaining compatible with standard SRAMs. During STORE cycle, erase previous nonvolatile data performed first, followed parallel programming nonvolatile elements. Once STORE cycle initiated, further inputs outputs disabled until cycle completed. Because sequence addresses used STORE initiation, important that other READ WRITE accesses intervene sequence sequence will aborted. initiate STORE cycle following READ sequence must performed:
U63764
Once sixth address sequence been entered, STORE cycle will commence chip will disabled. important that READ cycles WRITE cycles used sequence, although necessary that sequence valid. After tSTORE cycle time been fulfilled, SRAM will again activated READ WRITE operation. When VSWITCH software STORE operations will inhibited. SRAM WRITE cycles requested after drops below VSWITCH will inhibited. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. After td(E)R cycle time SRAM will once again ready READ WRITE operations.The RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. Average Active Power When HIGH chip consumes only standby current. overall average current drawn part depends following items: CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature level
Software Nonvolatile RECALL RECALL cycle EEPROM data into SRAM initiated with sequence READ operations manner similar STORE initiation. initiate RECALL cycle following sequence READ operations must performed: Read addresses Read addresses Read addresses Read addresses Read addresses Read addresses 0000 1555 0AAA 1FFF 10F0 0F0E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Cycle
Control #ML0055
March 2006
U63764
LIFE SUPPORT POLICY Simtek products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Simtek product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized Simtek such purpose.
LIMITED WARRANTY information this document been carefully checked believed reliable. However, Simtek makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. Simtek does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent Simtek's warranty product beyond that forth standard terms conditions sale. Simtek reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 01.11.2001 13.04.2004 21.04.2004 7.4.2005 31.3.2006 Name Ivonne Steffens Matthias Schniebel Matthias Schniebel Stefan Troy Meester Simtek Change format revision release ,,Memory 2002" removing ,,Preliminary" adding ,,Leadfree Green Package" ordering information adding ,,Device Marking" Page1: RoHS compliance free changed obsolete status Assigned Simtek Document Control Number

CapStore nvSRAM Features Description U63764 separate modes operat

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