PowerStore nvSRAM High-performance CMOS nonvolatile static 8192 b
|
|
|
Top Searches for this datasheet
U635H64
PowerStore nvSRAM
High-performance CMOS nonvolatile static 8192 bits Access Times Output Enable Access Times Cycle Time Automatic STORE EEPROM Power Down using system capacitance Software initiated STORE (STORE Cycle Time Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Software RECALL Initiation (RECALL Cycle Time Unlimited RECALL cycles from EEPROM Single Operation Operating temperature ranges: 9000 Quality Standard characterization accordingMIL 883C M3015.7-HBM (classification Code Numbers)
RoHS compliance free Packages: PDIP28 (600 mil) SOP28 (330 mil)
Description U635H64 separate modes operation: SRAM mode nonvolatile mode. SRAM mode, memory operates ordinary static RAM. nonvolatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. U635H64 fast static (25, ns), with nonvolatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent nonvolatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation) take place automatically upon power down using charge stored system capacitance.
Transfers from EEPROM SRAM (the RECALL operation) take place automatically power U635H64 combines high performance ease fast SRAM with nonvolatile data integrity. STORE cycles also initiated under user control software sequence. Once STORE cycle initiated, further input output disabled until cycle completed. Because sequence addresses used STORE initiation, important that other read write accesses intervene sequence sequence will aborted. RECALL cycles also initiated software sequence. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times.
Configuration
n.c. n.c.
Description
Signal Name
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
PDIP
View March 2006 Control #ML0052
U635H64
Block Diagram
EEPROM Array Decoder Input Buffers SRAM Array Rows Columns
Store/ Recall Control
STORE RECALL
Power Control
Column Column Decoder
Software Detect
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
Symbol
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
C-Type K-Type
Tstg
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Control #ML0052
March 2006
U635H64
Recommended Operating Conditions Power Supply Voltage Input Voltage Input High Voltage Symbol Pulse Width permitted Conditions Min. -0.3 Max. VCC+0.3 Unit
C-Type Characteristics Operating Supply Currentb Symbol ICC1 Average Supply Current during STOREc ICC2 Conditions Min. VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 Max.
K-Type Unit Min. Max.
Average Supply Current during PowerStore Cyclec Standby Supply Currentd (Cycling Input Levels)
ICC4
ICC(SB)1
Operating Supply Current (Cycling CMOS Input Levels) Standby Supply Curentd (Stable CMOS Input Levels)
ICC3
ICC(SB)
ICC1 ICC3 depedent output loading cycle rate. specified values obtained with outputs unloaded. current ICC1 measured WRITE/READ ratio 1/2. ICC2 ICC4 average currents required duration respective STORE cycles (STORE Cycle Time). Bringing will produce standby current levels until nonvolatile cycle progress timed out. MODE SELECTION table. current ICC(SB)1 measured WRITE/READ ratio 1/2.
March 2006
Control #ML0052
U635H64
C-Type Characteristics Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current Max. Min. Max. K-Type Unit
SRAM Memory Operations
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Address Change
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A)
Unit
Min. Max. Min. Max. Min. Max.
Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both LOW. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
Control #ML0052
March 2006
U635H64
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle E-controlled (during Read cycle: VIH)g
Output High Impedance (10) ACTIVE STANDBY
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G) Output Data Valid tdis(G) (11) tdis(E)
Switching Characteristics Write Cycle
Symbol Alt. Alt. tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH tAVAV tw(W) tsu(W) tsu(A)
tsu(A-WH)
Unit
Min. Max. Min. Max. Min. Max.
Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
March 2006
Control #ML0052
U635H64
Write Cycle W-controlledj
(12)
tsu(A-WH)
Address Valid tsu(E) (17) th(A) (21)
(16)
Input tsu(A) (15)
tw(W)
(13)
tsu(D) (19)
th(D) (20)
Input Data Valid tdis(W) (22) ten(W) (23) High Impedance
Output
Previous Data
Write Cycle E-controlledj
(12)
tsu(A) (15)
Input
Address Valid tw(E) (18)
th(A) (21)
tsu(W) (14) tsu(D) (19) th(D) (20)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes LOW, outputs remain high impedance state. must during address transition.
Control #ML0052
March 2006
U635H64
Nonvolatile Memory Operations
Mode Selection
(hex) 0000 1555 0AAA 1FFF 10F0 0F0F 0000 1555 0AAA 1FFF 10F0 0F0E
Mode Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output High Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Output Data Output Data Output Data Output Data Output Data Output High
Power Standby Active Active Active
Notes
Active
consecutive addresses must order listed (0000, 1555, 0AAA, 1FFF, 10F0, 0F0F) Store cycle (0000, 1555, 0AAA, 1FFF,10F0, 0F0E) RECALL cycle. must high during consecutive cycles. STORE cycle RECALL cycle tables diagrams further details. following six-address sequence used testing purposes should used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C. Activation nonvolatile cycles does depend state state assumes that VIL.
PowerStore Power RECALL
Symbol Conditions Alt. tRESTORE power supply voltage must stay above least after start STORE operation Min. Max. Unit
Power RECALL Durationn,
STORE Cycle Durationf
tPDSTORE
Time allowed Complete SRAM Cyclef,
tDELAY VSWITCH
Voltage Trigger Level
tRESTORE starts from time rises above VSWITCH.
March 2006
Control #ML0052
U635H64
PowerStore automatic Power RECALL VSWITCH
PowerStore tPDSTOREp Power RECALL
(26) (24) (25)
(24)
tRESTORE
tRESTORE tDELAY
POWER RECALL
BROWN STORE SRAM WRITES)
BROWN PowerStore
Software Controlled STORE/ RECALL Cyclek,
Symbol Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
Unit
Min. Max. Min. Max. Min. Max.
STORE/RECALL Initiation Time Chip Enable Output Inactivep STORE Cycle Timeq RECALL Cycle Timer Address Setup Chip Enables Chip Enable Pulse Widths, Chip Disable Address Changes
software sequence clocked with controlled READs. Once software controlled STORE RECALL cycle initiated, completes automatically, ignoring inputs. Note that STORE cycles (but RECALL) aborted VSWITCH (STORE inhibit). automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly. Noise trigger multiple READ cycles from same address abort address sequence. Chip Enable Pulse Width less than ta(E) (see Read Cycle) greater than equal tw(E)SR, than data valid pulse, however STORE RECALL will still initiated.
Control #ML0052
March 2006
U635H64
Software Controlled STORE/RECALL Cycles, HIGH after STORE initiation)
(27)
(27) ADDRESS th(A)SR (33) tw(E)SR tdis(E)(5) (32) (31) tsu(A)SR td(E)S (29) td(E)R (30) VALID tdis(E)SR (28)
Output
ADDRESS tw(E)SR tsu(A)SR (31) High Impedance
(32) (33) th(A)SR
VALID
Software Controlled STORE/RECALL Cycles, after STORE initiation)
(27)
Output
ADDRESS tw(E)SR tsu(A)SR (31) High Impedance
(32) (33) th(A)SR (31)
ADDRESS th(A)SR (33)
tsu(A)SR
td(E)S (29)
td(E)R (30)
VALID
VALID tdis(E)SR (28)
must HIGH when during address sequence order initiate nonvolatile cycle. either HIGH throughout. Addresses through found mode selection table. Address determines whether U635H64 performs STORE RECALL. must used clock address sequence software controlled STORE RECALL cycles.
March 2006
Control #ML0052
U635H64
Test Configuration Functional Check
VCCx
relevant test measurement
Input level according
ment output pins
Simultaneous measure-
measurement tdis-times ten-times capacitance Between must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
pins under test must connected with ground capacitors. Ordering Code Example Type Class blank 2000 1000 Package PDIP28 (600 mil) SOP28 (330 mil) Type SOP28 (330 mil) Type
special request
U635H64
Leadfree Option blank Standard Package Leadfree Green Package Access Time
Operating Temperature Range
Device Marking (example) Product specification
U635H64S2C 0425
Date manufacture (The first digits indicating year, last digits calendar week.) Leadfree Green Package March 2006
Internal Code
Control #ML0052
U635H64
Device Operation U635H64 separate modes operation: SRAM mode nonvolatile mode. SRAM mode, memory operates standard fast static RAM. nonvolatile mode, data transferred from SRAM EEPROM (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. STORE cycles initiated under user control software sequence also automatically initiated when power supply voltage level chip falls below VSWITCH. RECALL operations automatically initiated upon power occur also when rises above VSWITCH after power condition. RECALL cycles also initiated software sequence. SRAM READ Software Nonvolatile STORE U635H64 performs READ cycle whenever HIGH. address specified pins determines which 8192 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pins, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE WRITE cycle performed whenever LOW. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pins will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis(W) after goes LOW. Automatic STORE U635H64 uses intrinsic system capacitance perform automatic STORE power down. long system power supply take least tPDSTORE decay from VSWITCH down U635H64 will safely automatically STORE SRAM data EEPROM power down. order prevent unneeded STORE operations, autoThe U635H64 software controlled STORE cycle initiated executing sequential READ cycles from specific address locations. relying READ cycles only, U635H64 implements nonvolatile operation while remaining compatible with standard SRAMs. During STORE cycle, erase previous nonvolatile data performed first, followed parallel programming nonvolatile elements. Once STORE cycle initiated, further inputs outputs disabled until cycle completed. Because sequence addresses used STORE initiation, important that other READ WRITE accesses intervene sequence sequence will aborted. initiate STORE cycle following READ sequence must performed: Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0F (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE matic STORE will ignored unless least WRITE operation taken place since most recent STORE RECALL cycle. Software initiated STORE cycles performed regardless whether WRITE operation taken place. Automatic RECALL During power automatic RECALL takes place. After power condition (VCC VSWITCH) internal RECALL request latched. When once again exceeds sense voltage VSWITCH, requested RECALL cycle will automatically initiated will take tRESTORE complete. U635H64 WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between system VCC.
Once sixth address sequence been entered, STORE cycle will commence chip will disabled. important that READ cycles WRITE cycles used sequence, although necessary that sequence valid. After tSTORE cycle time been fulfilled, SRAM will again activated READ WRITE operation.
March 2006
Control #ML0052
U635H64
Software Nonvolatile RECALL RECALL cycle EEPROM data into SRAM initiated with sequence READ operations manner similar STORE initiation. initiate RECALL cycle following sequence READ operations must performed: Read address Read address Read address Read address Read address Read address 0000 1555 0AAA 1FFF 10F0 0F0E (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Hardware Protection U635H64 offers hardware protection against inadvertent STORE operation through Sense. When VSWITCH software controlled STORE operations will inhibited. Average Active Power U635H64 been designed draw significantly less power when (chip enabled) access cycle time longer than When HIGH chip consumes only standby current. overall average current drawn part depends following items: CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature level
Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times.
information describes type component shall considered assured characteristics. Terms delivery rights change design reserved.
Control #ML0052
March 2006
U635H64
LIFE SUPPORT POLICY Simtek products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Simtek product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized Simtek such purpose.
LIMITED WARRANTY information this document been carefully checked believed reliable. However, Simtek makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. Simtek does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent Simtek's warranty product beyond that forth standard terms conditions sale. Simtek reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 01.11.2001 25.09.2002 20.04.2004 7.4.2005 31.3.2006 Name Ivonne Steffens Matthias Schniebel Matthias Schniebel Stefan Troy Meester Simtek Change format revision release ,,Memory 2002" Adding ,,Type SOP28 (330mil) adding ,,Leadfree Green Package" ordering information adding ,,Device Marking" adding RoHS compliance free, chippack delete PDIP28 (300mil) changed obsolete status Assigned Simtek Document Control Number
Other recent searches
PXI-2596 - PXI-2596 PXI-2596 Datasheet
PXI-2597 - PXI-2597 PXI-2597 Datasheet
PXI-2598 - PXI-2598 PXI-2598 Datasheet
PXI-2599 - PXI-2599 PXI-2599 Datasheet
MSC8101 - MSC8101 MSC8101 Datasheet
LM6211 - LM6211 LM6211 Datasheet
AN614 - AN614 AN614 Datasheet
2SD1886 - 2SD1886 2SD1886 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
