PowerStore nvSRAM Features Description U634H256XS separate modes

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PowerStore nvSRAM Features Description U634H256XS separate modes

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U634H256XS
PowerStore nvSRAM
Features Description U634H256XS separate modes operation: SRAM mode nonvolatile mode. SRAM mode, memory operates ordinary static RAM. nonvolatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. U634H256XS fast static (25, ns), with nonvolatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent nonvolatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation) take place automatically upon power down using charge stored external capacitor. Transfers from EEPROM SRAM (the RECALL operation) take place automatically power U634H256XS combines high performance ease fast SRAM with nonvolatile data integrity. Description STORE cycles also initiated under user control software sequence single (HSB). Once STORE cycle initiated, further input output disabled until cycle completed. Because sequence addresses used STORE initiation, important that other read write accesses intervene sequence sequence will aborted. RECALL cycles also initiated software sequence. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. chips tested with restricted wafer probe program room temperature only. Untested parameters marked with number sign (#).
High-performance CMOS nonvolatile static 32768 bits Access Times Output Enable Access Times typ. Cycle Time Automatic STORE EEPROM Power Down using external capacitor Hardware Software initiated STORE (STORE Cycle Time Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Software RECALL Initiation (RECALL Cycle Time Unlimited RECALL cycles from EEPROM Single Operation Operating temperature ranges: 9000 Quality Standard protection 2000 (MIL 883C M3015.7-HBM)
Configuration
VCAP VCCX
Signal Name VCCX VCAP
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground Capacitor Hardware Controlled Store/Busy
VCAP
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U634H256XS
Block Diagram
EEPROM Array Input Buffers STORE Decoder SRAM Array Rows Columns
Store/ Recall Control
VCCX VCAP
Power Control
RECALL
VCCX VCAP
Column Column Decoder
Software Detect
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature
Symbol
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
C-Type K-Type
Tstg
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
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U634H256XS
Recommended Operating Conditions Power Supply Voltageb Input Voltage Input High Voltage Symbol Pulse Width permitted Conditions Min. -0.3 Max. VCC+0.3 Unit
C-Type Characteristics Operating Supply Currentc Symbol ICC1 Average Supply Current during STOREc ICC2 Operating Supply Current (Cycling CMOS Input Levels) Standby Supply Curentd (Stable CMOS Input Levels) ICC3 Conditions Min. VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 Max.
K-Type Unit Min. Max.
100#
Average Supply Current during PowerStore Cycle Standby Supply Currentd (Cycling Input Levels)
ICC4
ICC(SB)1
ICC(SB)
reference levels throughout this datasheet refer VCCX that where power supply connection made, VCAP VCCX connected ground. ICC1 ICC3 depedent output loading cycle rate. specified values obtained with outputs unloaded. current ICC1 measured WRITE/READ ratio 1/2. ICC2 average current required duration STORE cycle (STORE Cycle Time). Bringing will produce standby current levels until nonvolatile cycle progress timed out. MODE SELECTION able. current ICC(SB)1 measured WRITE/READ ratio 1/2.
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C-Type Characteristics Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current 2.4# 0.4# Max. Min. 2.4# 0.4# Max. K-Type Unit
SRAM Memory Operations Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) Unit
Switching Characteristics Read Cycle
Min. Max. Min. Max. Min. Max.
Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Address Change Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both LOW. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
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U634H256XS
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid
Address Valid ta(A) Output Data Valid tv(A)
Read Cycle E-controlled (during Read cycle: VIH)g
Output High Impedance
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G) (10) ACTIVE STANDBY
(11) tdis(E) tdis(G) Output Data Valid
Switching Characteristics Write Cycle
Symbol Alt. tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVEH Alt. tAVAV tw(W) tsu(W) tsu(A) tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
Unit
Min. Max. Min. Max. Min. Max.
Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
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U634H256XS
Write Cycle W-controlledj
(12)
tsu(E)
Address Valid
(17)
th(A) (21)
Input tsu(A-WH) tsu(A)
(15) (16)
tw(W)
(13)
tsu(D) (19) tdis(W) (22)
th(D) (20)
Input Data Valid Previous Data ten(W) (23) High Impedance
Output
Write Cycle E-controlledj
(12)
Input tsu(A)
(15)
Address Valid tw(E)
(18)
th(A)
(21)
tsu(W) (14) tsu(D) (19) th(D)
(20)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes LOW, outputs remain high impedance state. must during address transition.
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U634H256XS
Nonvolatile Memory Operations Mode Selection (hex) 0E38 31C7 03E0 3C1F 303F 0FC0 0E38 31C7 03E0 3C1F 303F 0C63
Mode Selected Read SRAM Write SRAM Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL STORE/Inhibit
Output High Output Data Input Data Output Data Output Data Output Data Output Data Output Data Output High Output Data Output Data Output Data Output Data Output Data Output High Output High
Power Standby Active Active Active
Notes
Active
ICC2/Standby
consecutive addresses must order listed (0E38, 31C7, 03E0, 3C1F, 303F, 0FC0) Store cycle (0E38, 31C7, 03E0,3C1F, 303F, 0C63) RECALL cycle. must high during consecutive cycles. STORE cycle RECALL cycle tables diagrams further details. following six-address sequence used testing purposes should used: 0E38, 31C7, 03E0, 3C1F, 303F, 339C. state assumes that VIL. Activation nonvolatile cycles does depend state initiated STORE operation actually occurs only WRITE been done since last STORE operation. After STORE any) completes, part will into standby mode inhibiting operation until rises.
PowerStore Power RECALL/ Hardware Controlled STORE
Symbol Conditions Alt. tRESTORE tHLQX tHLQZ tHHQX tHLHX IHSBOL IHSBOH VSWITCH td(H)S tdis(H)S ten(H)S tw(H)S 700# 650# Min. Max. Unit
Power RECALL Durationn, STORE Cycle Duration Inhibit High Inhibit Offe External STORE Pulse Widthe Output Currente,o Output High Currente, Voltage Trigger Level
tRESTORE starts from time rises above VSWITCH. that week internal pullup; basically open drain output. meant allow U634H256XS ganged together simultaneous storing. pullup external circuitry other than other U634H256XS pads.
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PowerStore Automatic Power RECALL VCAP VSWITCH
PowerStore Power RECALL POWER BROWN STORE RECALL SRAM WRITES) Hardware Controlled STORE
tw(H)Sq (28) ten(H)S (27) tdis(H)S (26) Previous Data Valid td(H)S (25) High Impedance Data Valid
tPDSTOREp
(24) (24)
tRESTORE
tRESTORE tDELAYp
BROWN PowerStore
Output
Software Controlled STORE/RECALL Cycle
Symbol Alt. tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
Unit
Min. Max. Min. Max. Min. Max. 600# 600# 600#
STORE/RECALL Initiation Time Chip Enable Output Inactives STORE Cycle Time RECALL Cycle Timer Address Setup Chip Enablet Chip Enable Pulse Widths, Chip Disable Address Changet
tPDSTORE approximate td(E)S td(H)S; tDELAY approximate tdis(H)S. After tw(H)S hold down internal STORE operation. automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly. Once software controlled STORE RECALL cycle initiated, completes automatically, ignoring inputs. Noise trigger multiple READ cycles from same address abort address sequence.
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U634H256XS
Software Controlled STORE/RECALL Cyclet, HIGH after STORE initiation)
(29)
(29)
Output
ADDRESS tw(E)SR (34) tsu(A)SR (33) High Impedance VALID
(35)
ADDRESS th(A)SR (35)
w(E)SR
th(A)SR
tsu(A)SR
(33)
(34)
tdis(E) td(E)R (32)
td(E)S (31) VALID tdis(E)SR (30)
Software Controlled STORE/RECALL Cyclet, after STORE initiation)
(29)
Output tsu(A)SR (33)
ADDRESS tw(E)SR (34) th(A)SR
(35)
ADDRESS th(A)SR (35) tsu(A)SR
(33)
td(E)S (31) VALID tdis(E)SR (30)
td(E)R (32)
High Impedance
VALID
chip enable pulse width less then ta(E) (see READ cycle) greater than equal tw(E)SR, then data valid pulse, however STORE RECALL will still initiated. must HIGH when during address sequence order initiate nonvolatile cycle. either HIGH throughout. Addresses through found mode selection table. Address determines whether U634H256XS performs STORE RECALL. must used clock address sequence software controlled STORE RECALL cycles.
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Test Configuration Functional Check
VCCX
VCAPy
relevant test measurement
Input level according
ment output pads
Simultaneous measure-
measurement tdis-times ten-times capacitance Between VCap must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
Pads under test must connected with ground capacitors.
Bonding Instructions U634H256XS relevant bond pads additional pads. additional pads must bonded. Refer bond location identification table complete list pads coordinates. Always both VCAP pads have connected. mandatory bond wires VCAP doublebond pads noise immunity. backside connected VCAP contacted with substrate case same potential. case that automatic STORES should disabled, VCCX bond connected with potential external connected with VCAP.
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U634H256XS
Bond location identification table (origin: down left corner)
VCAP
1170 1445 1653,2 1810,8 2000 2215 2490 2700 2975 3185 3460 3460 3510 3510 3510
8885 9050 9240
VSEF VCCX VBND VCAP VCAP
3505 3275 3085 2875 2685 2405 2165 1740 1576,8 1419,2 1295 1120
9410 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9400 9357,5 9125
pads VSE, VSEF, VBND, must bonded. Applying signal voltage these pads could damage chip influence functionality.
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U634H256XS
VCAP VCCX
Waferdiameter Waferthickness (390 ±10) size (3,73 9,62) (stepping interval)
Bond size (110 110) Passivation openings Polyimidpassivation (100 100) 0.5)
VCAP
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U634H256XS
Device Operation U634H256XS separate modes operation:SRAM mode nonvolatile mode. memory operates SRAM mode standard fast static RAM. Data transferred nonvolatile mode from SRAM EEPROM (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. STORE cycles initiated under user control software sequence assertion also automatically initiated when power supply voltage level chip falls below VSWITCH. RECALL operations automatically initiated upon power also occur when VCCX rises above VSWITCH, after power condition. RECALL cycles also initiated software sequence. SRAM READ U634H256XS performs READ cycle whenever HIGH. address specified pads determines which 32768 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pads, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE Software Nonvolatile STORE WRITE cycle performed whenever HIGH. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pads will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis(W) after goes LOW. Automatic STORE During normal operation, U634H256XS will draw current from VCCX charge capacitor connected VCAP This stored charge will used chip perform single STORE operation. voltage VCCX drops below VSWITCH, part will automatically disconnect VCAP from VCCX initiate March 2006 Control #ML0049 U634H256XS software controlled STORE cycle initiated executing sequential READ cycles from specific address locations. relying READ cycles only, U634H256XS implements nonvolatile operation while remaining compatible with standard SRAMs. During STORE cycle, erase previous nonvolatile data performed first, followed parallel programming nonvolatile elements. Once STORE cycle initiated, further inputs outputs disabled until cycle completed. Because sequence addresses used STORE initiation, important that other READ WRITE accesses intervene sequence sequence will aborted. initiate STORE cycle following READ sequence must performed: STORE operation. Figure shows proper connection capacitors automatic STORE operation. charge storage capacitor should have capacity Each U634H256XS must have capacitor. Each U634H256XS must have high quality, high frequency bypass capacitor connected between VCAP VSS, using leads traces that short possible. This capacitor does replace normal expected high frequency bypass capacitor between power supply voltage VCCX VSS. order prevent unneeded STORE operations, automatic STOREs well those initiated externally driving will ignored unless least WRITE operation taken place since most recent STORE cycle. Note that driven external circuitry WRITES have taken place, part will still disabled until allowed return HIGH. Software initiated STORE cycles performed regardless whether WRITE operation taken place. Automatic RECALL During power automatic RECALL takes place. power condition (power supply voltage VSWITCH) internal RECALL request latched. soon power supply voltage exceeds sense voltage VSWITCH, requested RECALL cycle will automatically initiated will take tRESTORE complete. U634H256XS WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between power supply voltage.
U634H256XS
Read address Read address Read address Read address Read address Read address 0E38 31C7 03E0 3C1F 303F 0FC0 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE been forced LOW, WRITE will occur STORE operation will begin immediately. HARDWARE-STORE-BUSY (HSB) high speed, drive capability bidirectional control line. order allow bank U634H256XSs perform synchronized STORE functions, from number chips connected together. Each chip contains small internal current source pull HIGH when being driven LOW. decrease sensitivity this signal noise generated board, pulled power supply external resistor with value such that combined load resistor parallel chip connections does exceed IHSBOL (see Figure connected external circuits other than other U634H256XSs, external pull-up resistor used. During STORE operation, regardless initiated, U634H256XS will continue drive LOW, releasing only when STORE complete. Upon completion STORE operation, part will disabled until actually goes HIGH. Hardware Protection U634H256XS offers hardware protection against inadvertent STORE operation during voltage conditions. When VCAP VSWITCH, software initiated STORE operations will inhibited. Preventing Automatic STORES PowerStore function disabled holding HIGH with driver capable sourcing least will have overpower internal pull-down device that drives onset PowerStore. When U634H256XS connected PowerStore operation (see Figure VCCX crosses VSWITCH down, U634H256XS will attempt pull LOW; doesnt actually below VIL, part will stop trying pull abort PowerStore attempt. Disabling Automatic STORES PowerStore function required, then VCAP should tied directly power supply VCCX should tied ground. this mode, STORE operation triggered through software control pad. either event, VCAP (Pad must always have proper bypass capacitor connected (Figure
Once sixth address sequence been entered, STORE cycle will commence chip will disabled. important that READ cycles WRITE cycles used sequence, although necessary that sequence valid. After tSTORE cycle time been fulfilled, SRAM will again activated READ WRITE operation. Software Nonvolatile RECALL RECALL cycle EEPROM data into SRAM initiated with sequence READ operations manner similar STORE initiation. initiate RECALL cycle following sequence READ operations must performed: Read address Read address Read address Read address Read address Read address 0E38 31C7 03E0 3C1F 303F 0C63 (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL
Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. Nonvolatile STORE hardware controlled STORE Busy (HSB) connected open drain circuit acting both input output perform different functions. When driven internal chip circuitry indicates that STORE operation (initiated means) progress within chip. When driven external circuitry longer than tw(H)S, chip will conditionally initiate STORE operation after tdis(H)S. READ WRITE operations that progress when driven (either internal external circuitry) will allowed complete before STORE operation performed, following manner. After goes LOW, part will continue normal SRAM operation tdis(H)S. During tdis(H)S, transition address control signal will terminate SRAM operation cause STORE commence. Note that SRAM WRITE attempted after Control #ML0049
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U634H256XS
Disabling Automatic STORES: STORE Cycle Inhibit Automatic Power RECALL VCAP VSWITCH
STORE inhibit Power RECALL
(24)
tRESTORE
Power Supply VCAP VCCX Power Supply (optional, mandatory used with external circuitry) Bypass VCAP VCCX (optional, mandatory used with external circuitry)
Bypass
Figure AUTOMATIC STORE OPERATION Schematic Diagram
Figure DISABLING AUTOMATIC STORES Schematic Diagram
Average Active Power U634H256XS been designed draw significantly less power when (chip enabled) access cycle time longer than When HIGH chip consumes only standby current. overall average current drawn part depends following items: CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature power supply voltage level
information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. March 2006 Control #ML0049
U634H256XS
LIFE SUPPORT POLICY products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized such purpose. LIMITED WARRANTY information this document been carefully checked believed reliable. However Zentrum Mikroelektronik Dresden (ZMD) makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent ZMD's warranty product beyond that forth standard terms conditions sale. reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 01.11.2001 22.04.2002 04.12.2003 Name Ivonne Steffens Thomas Wolf Matthias Schniebel Matthias Schniebel Simtek format revision removing ,,at least" capacitor page (Automatic STORE) typ. Cycle Time Operating Supply Current ICC3 Assigned Simtek Document Control Number Change

PowerStore nvSRAM Features Description U634H256XS separate modes

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