HardStore nvSRAM Features Description U630H16 separate modes oper
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U630H16XS
HardStore nvSRAM
Features Description U630H16 separate modes operation: SRAM mode non-volatile mode, determined state pad. SRAM mode, memory operates ordinary static RAM. non-volatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. U630H16 fast static (25, ns), with non-volatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent non-volatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation), from EEPROM SRAM (the RECALL operation) initiated through state pad. U630H16 combines high performance ease fast SRAM with non-volatile data integrity. Once STORE cycle initiated, further input output disabled until cycle completed. Internally, RECALL step procedure. First, SRAM data cleared second, non-volatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. non-volatile data recalled unlimited number times. chips tested with restricted wafer probe program room temperature only. Untested parameters marked with number sign (#).
High-performance CMOS nonvolatile static 2048 bits Access Times Output Enable Access Times Hardware STORE Initiation (STORE Cycle Time Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Hardware RECALL Initiation (RECALL Cycle Time Unlimited RECALL cycles from EEPROM Unlimited SRAM Read Write Single Operation Operating temperature ranges: 90000 Quality Standard protection 2000 (MIL 883C M3015.7-HBM)
Configuration
VBND
Description
Signal Name
VBND
Signal Description
Address Inputs Data In/Out Chip Enable Output Enable Write Enable Nonvolatile Enable Power Supply Voltage Ground HardStore type enable
March 2006
Control #ML0039
U630H16XS
Block Diagram
EEPROM Array STORE Decoder SRAM Array Rows Columns RECALL
Input Buffers
Column Column Decoder
Store/ Recall Control
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature C-Type K-Type A-Type
Symbol Tstg
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
Storage Temperature
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Control #ML0039
March 2006
U630H16XS
Recommended Operating Conditions Power Supply Voltage Input Voltage Input High Voltage Symbol Pulse Width permitted Conditions Min. -0.3 Max. VCC+0.3 Unit
C-Type Characteristics Operating Supply Currentb Symbol ICC1 Average Supply Current during STOREc ICC2 Average Supply Current (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 Conditions VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 Min. Max.
K-Type Min. Max.
A-Type Min. Max. Unit
Standby Supply Currentd (Cycling Input Levels)
ICC(SB)1
ICC(SB)
ICC1 ICC3 dependent output loading cycle rate. specified values obtained with outputs unloaded. current ICC1 measured WRITE/READ ratio 1/2. ICC2 average current required duration STORE cycle (STORE Cycle Time). Bringing will produce standby current levels until nonvolatile cycle progress timed out. MODE SELECTION table. current ICC(SB)1 measured WRITE/READ ratio 1/2.
March 2006
Control #ML0039
U630H16XS
Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Max. Unit
Characteristics Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current
2.4# 0.4#
SRAM Memory Operations
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Addr. Changeg
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A)
Unit
Min. Max. Min. Max. Min. Max.
Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both LOW. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
Control #ML0039
March 2006
U630H16XS
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle E-controlled (during Read cycle: VIH)g
Output
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G) High Impedance (10) ACTIVE STANDBY Output Data Valid (11) tdis(E)
tdis(G)
Switching Characteristics Write Cycle Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
Symbol Alt. Alt. tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVAV tw(W) tsu(W) tsu(A)
Unit
Min. Max. Min. Max. Min. Max.
tAVEH tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
March 2006
Control #ML0039
U630H16XS
Write Cycle W-controlledj
(12)
tsu(A)
Address Valid tsu(E) (17) tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W)
(22)
th(A) (21)
Input
(15)
th(D) (20)
Output
Previous Data
Input Data Valid ten(W) (23) High Impedance
Write Cycle E-controlledj
(12)
Input ten(E) tsu(A) (15)
Address Valid tw(E) (18) tsu(W) (14) tsu(D) (19) tdis(W) (22)
th(A) (21)
th(D) (20)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes LOW, outputs remain high impedance state. must during address transitions.
Control #ML0039
March 2006
U630H16XS
Nonvolatile Memory Operations
STORE Cycle Inhibit Automatic Power RECALL Power RECALL Durationk, Voltage Trigger Level
Symbol Min. Alt. tRESTORE VSWITCH Max. Unit
tRESTORE starts from time rises above VSWITCH.
STORE Cycle Inhibit Automatic Power RECALL VSWITCH
STORE inhibit Power RECALL
(24)
tRESTORE
Mode Selection
Mode Nonvolatile RECALL Nonvolatile STORE operation
Power Active ICC2 Active
Notes
automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly.
March 2006
Control #ML0039
U630H16XS
STORE Cycles Symbol STORE Cycle W-controlled Alt. STORE Cycle Timem STORE Initiation Cycle Timen Output Disable Setup Fall Setup Chip Enable Setup tWLQX tWLNH tGHNL tNLWL tELWL td(W)S tw(W)S tsu(G)S tsu(N)S tsu(E)S Min. Max. Unit
STORE Cycle: W-controlledo
Output tsu(E)S (29) td(W)S (25) High Impedance
tsu(G)S tsu(N)S
(27) (28)
tw(W)S (26)
Symbol STORE Cycle E-controlled Alt. STORE Cycle Time STORE Initiation Cycle Time Output Disable Setup Fall Setup Write Enable Setup tELQXS tELNHS tGHEL tNLEL tWLEL td(E)S tw(E)S tsu(G)S tsu(N)S tsu(W)S Min. Max. Unit
STORE Cycle: E-controlledo
tsu(N)S
(33)
Output
tsu(G)S (32) tsu(W)S (34) tw(E)S (31) td(E)S (30) High Impedance
Control #ML0039
March 2006
U630H16XS
RECALL Cycles Symbol RECALL Cycle NE-controlled Alt. RECALL Cycle Timep RECALL Initiation Cycle Timeq Output Enable Setup Write Enable Setup Chip Enable Setup Fall Output Inactive tNLQX tNLNH tGLNL tWHNL tELNL tNLQZ td(N)R tw(N)R tsu(G)R tsu(W)R tsu(E)R tdis(N)R Min. Max. Unit
RECALL Cycle: NE-controlledo
tsu(G)R tw(N)R (36)
(37)
tsu(W)R
(38)
tdis(N)R (40) td(N)R (35) High Impedance
tsu(E)R (39)
Output
Symbol RECALL Cycle E-controlled Alt. RECALL Cycle Time RECALL Initiation Cycle Time Setup Output Enable Setup Write Enable Setup tELQXR tELNHR tNLEL tGLEL tWHEL td(E)R tw(E)R tsu(N)R tsu(G)R tsu(W)R Min. Max. Unit
RECALL Cycle: E-controlledo
tsu(N)R
Output
(43)
tsu(G)R (44)
tsu(W)R
(45)
tw(E)R (42) td(E)R (41)
High Impedance
March 2006
Control #ML0039
U630H16XS
Symbol RECALL Cycle G-controlled Alt. RECALL Cycle Time RECALL Initiation Cycle Time Setup Write Enable Setup Chip Enable Setup tGLQXR tGLNH tNLGL tWHGL tELGL td(G)R tw(G)R tsu(N)R tsu(W)R tsu(E)R Min. Max. Unit
RECALL Cycle: G-controlledo,
tsu(N)R
(48)
tw(G)R (47)
Output
tsu(W)R (49) tsu(E)R (50) td(G)R (46) High Impedance
Measured with both returned HIGH, returned LOW. Note that STORE cycles inhibited/aborted VSWITCH (STORE inhibit). Once tw(W)S been satisfied STORE cycle completed automatically. used terminate STORE initiation cycle. period time which HIGH while LOW, than RECALL cycle initiated. E-controlled STORE during tw(E)S have static. Measured with both HIGH, LOW. Once tw(N)R been satisfied RECALL cycle completed automatically. used terminate RECALL initiation cycle. point which both HIGH, than STORE cycle will initiated instead RECALL.
Control #ML0039
March 2006
U630H16XS
Test Configuration Functional Check
VCCt
Input level according
relevant test measurement
ment output pads
Simultaneous measure-
measurement tdis-times ten-times capacitance Between must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
pads under test must connected with ground capacitors. Ordering Code Example Type bare Access Time U630H16
Operating Temperature Range (only
Bonding Instructions U630H16XS relevant bond pads additional pads. additional pads must bonded. Refer bond location identification table complete list bond pads coordinates. mandatory bond wire each bond wires bond noise immunity. backside connected contacted with substrate case same potential. VBND connected with order enable HardStore mode chip. March 2006 Control #ML0039
U630H16XS
Bond location identification table (origin: down left corner)
1170 1445 1650 1810 2000 2215 2490 2700 2975 3185 3460 3460 VBND 1150 1545 1685 1860 2565 3035 3225 3460 3460 1940 2130 2130 2130 2130 2130 2130 2130 2130 2130 2130 2130 2130 1940
VBND
Wafer diameter: Wafer thickness: size: Bond size: Passivation openings:
(390±10)m (3.73 2.37) (stepping interval) (110 110) (100 100) (4±0.5)
Polyimidpassivation:
Control #ML0039
March 2006
U630H16XS
Chip Operation U630H16 separate modes operation: SRAM mode nonvolatile mode, determined state pad. SRAM mode, memory operates standard fast static RAM. nonvolatile mode, data transferred from SRAM EEPROM (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. SRAM READ U630H16 performs READ cycle whenever while HIGH. address specified pads determines which 2048 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pads, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE WRITE cycle performed whenever HIGH. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pads will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis(W) after goes LOW. Noise Consideration U630H16 high speed memory therefore must have high frequency bypass capacitor approximately connected between using leads traces that short possible. with high speed CMOS ICs, normal carefull routing power, ground signals will help prevent noise problems. Hardware Nonvolatile STORE STORE cycle performed when while HIGH. While sequence achieve this state will initiate STORE, only initiation initiation practical without risking unintentional SRAM WRITE that would disturb SRAM data. During March 2006 Control #ML0039 STORE cycle, previous nonvolatile data erased SRAM contents then programmed into nonvolatile elements. Once STORE cycle initiated, further input output disabled pads tristated until cycle completed. HIGH cycle, READ will performed outputs will active, indicating STORE. Hardware Nonvolatile RECALL RECALL cycle performed when while HIGH. Like STORE cycle, RECALL initiated when last three clock-signals goes RECALL state. Once initiated, RECALL cycle will take ,,RECALL Cycle Time" complete, during which inputs ignored. When RECALL completes, READ WRITE state input pads will take effect. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL alters data nonvolatile cells. nonvolatile data recalled unlimited number times. Like STORE cycle, transition must occur some control pads cause RECALL, preventing inadvertend multi-triggering. Automatic Power RECALL power once exceeds sense voltage VSWITCH, RECALL cycle automatically initiated. voltage must drop below VSWITCH once risen above order RECALL operate properly. this automatic RECALL, SRAM operation cannot commence until tRESTORE after exceeds VSWITCH. U630H16 WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between system VCC. Hardware Protection U630H16 offers levels protection suppress inadvertent STORE cycles. control signals remain STORE condition STORE cycle, second STORE cycle will started. STORE RECALL) will initiated only after transition these signals required state. addition multi-trigger protection, U630H16 offers hardware protection through Sense. When VSWITCH externally initiated STORE operation will inhibited.
U630H16XS
Average Active Power U630H16 been designed draw significantly less power when (chip enabled) access cycle time longer than When HIGH chip consumes only standby current. overall average current drawn part depends following items: CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature level
information describes type component shall considered assured characteristics. Terms delivery rights change design reserved. Control #ML0039 March 2006
U630H16XS
LIFE SUPPORT POLICY products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized such purpose.
LIMITED WARRANTY information this document been carefully checked believed reliable. However Zentrum Mikroelektronik Dresden (ZMD) makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent ZMD's warranty product beyond that forth standard terms conditions sale. reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 01.11.2001 11.08.2003 20.04.2004 7.4.2005 Name Ivonne Steffens Matthias Schniebel Matthias Schniebel Stefan Change format revision release ,,Memory 2002" adding A-Type with ICC1 85mA; ICC2 7mA; ICC3 15mA; ICC(SB) 2mA; ICC(SB)1 adding ,,Leadfree Green Package" ordering information adding ,,Device Marking" changing endurance cycles 100a data retention, delete classes, change ordering code, PDIP special request, RoHS free added, limitation PDIP deleted converted into bare data sheet based version June 11th 2001 Assigned Simtek Document Control Number
7.4.2005
Steffen Buschbeck Simtek
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