HardStore nvSRAM Features Description U630H16P separate modes ope

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HardStore nvSRAM Features Description U630H16P separate modes ope

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U630H16P
HardStore nvSRAM
Features Description U630H16P separate modes operation: SRAM mode nonvolatile mode, determined state pin. SRAM mode, memory operates ordinary static RAM. nonvolatile operation, data transferred parallel from SRAM EEPROM from EEPROM SRAM. this mode SRAM functions disabled. U630H16P fast static ns), with nonvolatile electrically erasable PROM (EEPROM) element incorporated each static memory cell. SRAM read written unlimited number times, while independent nonvolatile data resides EEPROM. Data transfers from SRAM EEPROM (the STORE operation), from EEPROM SRAM (the RECALL operation) initiated through state through software sequences. U630H16P combines high performance ease fast SRAM with nonvolatile data integrity. Once STORE cycle initiated, further input output disabled until cycle completed. Because sequence addresses used STORE initiation, important that other read write accesses intervene sequence sequence will aborted. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times.
High-performance CMOS nonvolatile static 2048 bits Access Times Output Enable Access Times Hardware Software STORE Initiation (STORE Cycle Time Automatic STORE Timing STORE cycles EEPROM years data retention EEPROM Automatic RECALL Power Hardware Software RECALL Initiation (RECALL Cycle Time Unlimited RECALL cycles from EEPROM Unlimited Read Write SRAM Single Operation Operating temperature ranges: 9000 Quality Standard characterization according 883C M3015.7-HBM (classification Code Numbers) Package: PLCC32
Configuration
(VCC) n.c. n.c.
Description
Signal Name
n.c. n.c.
Signal Description Address Inputs Data In/Out Chip Enable Output Enable Write Enable Nonvolatile Enable Power Supply Voltage Ground connected Power Supply Voltage (optional)
n.c.
n.c. (VCC)
(VCC)
View March 2006
Control #ML0037
U630H16P
Block Diagram
EEPROM Array STORE Decoder SRAM Array Rows Columns
Store/ Recall Control
RECALL
Input Buffers
Column Column Decoder
Software Detect
Truth Table SRAM Operations Operating Mode Standby/not selected Internal Read Read Write Characteristics
voltages referenced (ground). characteristics valid power supply voltage range operating temperature range specified. Dynamic measurements based rise fall time measured between well input levels timing reference level input output signals with exception tdis-times ten-times, which cases transition measured from steady-state voltage.
High-Z High-Z Data Outputs Low-Z Data Inputs High-Z
Absolute Maximum Ratingsa Power Supply Voltage Input Voltage Output Voltage Power Dissipation Operating Temperature Storage Temperature C-Type K-Type
Symbol Tstg
Min. -0.5 -0.3 -0.3
Max. VCC+0.5 VCC+0.5
Unit
Stresses greater than those listed under ,,Absolute Maximum Ratings" cause permanent damage device. This stress rating only, functional operation device condition above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Control #ML0037
March 2006
U630H16P
Recommended Operating Conditions Power Supply Voltage Input Voltage Input High Voltage
Symbol
Conditions
Min.
Max. VCC+0.3
Unit
Pulse Width permitted
-0.3
C-Type Characteristics Operating Supply Currentb Symbol ICC1 Average Supply Current during STOREc ICC2 Average Supply Current (Cycling CMOS Input Levels) Standby Supply Currentd (Stable CMOS Input Levels) ICC3 Conditions Min. VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 VCC-0.2 Max.
K-Type Unit Min. Max.
Standby Supply Currentd (Cycling Input Levels)
ICC(SB)1
ICC(SB)
ICC1 ICC3 dependent output loading cycle rate. specified values obtained with outputs unloaded. current ICC1 measured WRITE/READ ratio 1/2. ICC2 average current required duration STORE cycle (STORE Cycle Time). Bringing will produce standby current levels until nonvolatile cycle progress timed out. MODE SELECTION table. current ICC(SB)1 measured WRITE/READ ratio 1/2.
March 2006
Control #ML0037
U630H16P
Symbol High Output Leakage Current High Three-State- Output Three-State- Output IOHZ IOLZ Conditions Min. Max. Unit
Characteristics
Output High Voltage Output Voltage Output High Current Output Current Input Leakage Current
SRAM Memory Operations
Switching Characteristics Read Cycle Read Cycle Timef Address Access Time Data Validg Chip Enable Access Time Data Valid Output Enable Access Time Data Valid HIGH Output High-Zh HIGH Output High-Zh Output Low-Z Output Low-Z Output Hold Time after Addr. Changeg
Symbol Alt. tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tELQX tGLQX tAXQX tELICCH tEHICCL ta(A) ta(E) ta(G) tdis(E) tdis(G) ten(E) ten(G) tv(A) Min.
Unit Max.
Chip Enable Power Activee Chip Disable Power Standbyd,
Parameter guaranteed tested. Device continuously selected with both LOW. Address valid prior coincident with transition LOW. Measured from steady state output voltage.
Control #ML0037
March 2006
U630H16P
Read Cycle Ai-controlled (during Read cycle: VIL, VIH)f
Output Previous Data Valid tv(A)
Address Valid ta(A) Output Data Valid
Read Cycle E-controlled (during Read cycle: VIH)g
Output
Address Valid ta(A) ta(E) ten(E) ta(G) ten(G) High Impedance (10) ACTIVE STANDBY Output Data Valid (11) tdis(E)
tdis(G)
Switching Characteristics Write Cycle Write Cycle Time Write Pulse Width Write Pulse Width Setup Time Address Setup Time Address Valid Write Chip Enable Setup Time Chip Enable Write Data Setup Time Write Data Hold Time after Write Address Hold after Write Output High-Zh, HIGH Output Low-Z
Symbol Alt. Alt. tAVAV tWLWH tWLEH tAVWL tAVWH tELWH tELEH tDVWH tWHDX tWHAX tWLQZ tWHQX tDVEH tEHDX tEHAX tAVEL tAVAV tw(W) tsu(W) tsu(A) Min.
Unit Max.
tAVEH tsu(A-WH) tsu(E) tw(E) tsu(D) th(D) th(A) tdis(W) ten(W)
March 2006
Control #ML0037
U630H16P
Write Cycle W-controlledj
(12)
tsu(A)
Address Valid tsu(E) (17)
th(A) (21)
tsu(A-WH) (16) tw(W) (13) tsu(D) (19) tdis(W)
(22)
Input
(15)
th(D) (20)
Output
Previous Data
Input Data Valid ten(W) (23) High Impedance
Write Cycle E-controlledj
(12)
Input ten(E) tsu(A) (15)
Address Valid tw(E) (18)
th(A) (21)
tsu(W) (14) tsu(D) (19) tdis(W) (22) th(D) (20)
Input Data Valid High Impedance
Output
undefined
H-level
L-level
when goes LOW, outputs remain high impedance state. must during address transitions.
Control #ML0037
March 2006
U630H16P
Nonvolatile Memory Operations
STORE Cycle Inhibit Automatic Power RECALL Power RECALL Durationk, Voltage Trigger Level
Symbol Min. Alt. tRESTORE VSWITCH Max. Unit
tRESTORE starts from time rises above VSWITCH.
STORE Cycle Inhibit Automatic Power RECALL VSWITCH
STORE inhibit Power RECALL
(24)
tRESTORE
Hardware Mode Selection
Mode Nonvolatile RECALL Nonvolatile STORE operation
Power Active ICC2 Active
Notes
automatic RECALL also takes place power starting when exceeds VSWITCH takes tRESTORE. must drop below VSWITCH once been exceeded RECALL function properly.
March 2006
Control #ML0037
U630H16P
STORE Cycles Symbol STORE Cycle W-controlled Alt. STORE Cycle Timem STORE Initiation Cycle Timen Output Disable Setup Fall Setup Chip Enable Setup tWLQX tWLNH tGHNL tNLWL tELWL td(W)S tw(W)S tsu(G)S tsu(N)S tsu(E)S Min. Max. Unit
STORE Cycle: W-controlledo
tsu(E)S (29)
tsu(G)S tsu(N)S
(27) (28)
tw(W)S (26)
Output td(W)S (25) High Impedance
Symbol STORE Cycle E-controlled Alt. STORE Cycle Time STORE Initiation Cycle Time Output Disable Setup Fall Setup Write Enable Setup tELQXS tELNHS tGHEL tNLEL tWLEL td(E)S tw(E)S tsu(G)S tsu(N)S tsu(W)S Min. Max. Unit
STORE Cycle: E-controlledo
tsu(N)S
Output
(33)
tsu(G)S (32) tsu(W)S (34) tw(E)S (31) td(E)S (30) High Impedance
Control #ML0037
March 2006
U630H16P
RECALL Cycles Symbol RECALL Cycle NE-controlled Alt. RECALL Cycle Timep RECALL Initiation Cycle Timeq Output Enable Setup Write Enable Setup Chip Enable Setup Fall Output Inactive tNLQX tNLNH tGLNL tWHNL tELNL tNLQZ td(N)R tw(N)R tsu(G)R tsu(W)R tsu(E)R tdis(N)R Min. Max. Unit
RECALL Cycle: NE-controlledo
tsu(G)R tw(N)R (36)
(37)
tsu(W)R
(38)
tdis(N)R (40) td(N)R (35) High Impedance
tsu(E)R (39)
Output
Symbol RECALL Cycle E-controlled Alt. RECALL Cycle Time RECALL Initiation Cycle Time Setup Output Enable Setup Write Enable Setup tELQXR tELNHR tNLEL tGLEL tWHEL td(E)R tw(E)R tsu(N)R tsu(G)R tsu(W)R Min. Max. Unit
RECALL Cycle: E-controlledo
tsu(N)R
Output
(43)
tsu(G)R (44)
tsu(W)R
(45)
tw(E)R (42) td(E)R (41)
High Impedance
March 2006
Control #ML0037
U630H16P
Symbol RECALL Cycle G-controlled Alt. RECALL Cycle Time RECALL Initiation Cycle Time Setup Write Enable Setup Chip Enable Setup tGLQXR tGLNH tNLGL tWHGL tELGL td(G)R tw(G)R tsu(N)R tsu(W)R tsu(E)R Min. Max. Unit
RECALL Cycle: G-controlledo,
tsu(N)R
(48)
tw(G)R (47)
tsu(W)R (49) tsu(E)R (50) td(G)R (46)
Output
High Impedance
Measured with both returned HIGH, returned LOW. Note that STORE cycles inhibited/aborted VSWITCH (STORE inhibit). Once tw(W)S been satisfied STORE cycle completed automatically. used terminate STORE initiation cycle. period time which HIGH while LOW, than RECALL cycle initiated. E-controlled STORE during tw(E)S have static. Measured with both HIGH, LOW. Once tw(N)R been satisfied RECALL cycle completed automatically. used terminate RECALL initiation cycle. point which both HIGH, than STORE cycle will initiated instead RECALL.
Control #ML0037
March 2006
U630H16P
Software Mode Selection (hex)
Mode Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile STORE Read SRAM Read SRAM Read SRAM Read SRAM Read SRAM Nonvolatile RECALL
Output Data Output Data Output Data Output Data Output Data Output High Output Data Output Data Output Data Output Data Output Data Output High
Power Active
Notes
ICC2 Active
consecutive addresses must order listed (000, 555, 2AA, 7FF, 0F0, 70F) Store cycle (000, 555, 2AA, 7FF, 0F0, 70E) RECALL cycle. must high during consecutive cycles. STORE cycle RECALL cycle tables diagrams further details. following six-address sequence used testing purposes should used: 000, 555, 2AA, 7FF, 0F0, 39C. state assumes that VIL. Activation nonvolatile cycles does depend state
Symbol
Min. Max. Min.
Max. Min.
Unit Max.
Software Controlled STORE/RECALL Cycles, STORE/RECALL Initiation Time Chip Enable Output Inactivev STORE Cycle Timew RECALL Cycle Timel Address Setup Chip Enablex Chip Enable Pulse Widthx, Chip Disable Address Changex
Alt.
tAVAV tELQZ tELQXS tELQXR tAVELN tELEHN tEHAXN
tdis(E)SR td(E)S td(E)R tsu(A)SR tw(E)SR th(A)SR
software sequence clocked with controlled READs. Once software controlled STORE RECALL cycle initiated, completes automatically, ignoring inputs. Note that STORE cycles (but RECALL) aborted VSWITCH (STORE inhibit). Noise trigger multiple READ cycles from same address abort address sequence. Chip Enable Pulse Width less than ta(E) (see Read Cycle) greater than equal tw(E)SR, than data valid pulse, however STORE RECALL will still initiated.
March 2006
Control #ML0037
U630H16P
Software Controlled STORE/RECALL Cyclex, HIGH after STORE initiation)
(25) ADDRESS tw(E)SR (31) th(A)SR
(30) (31)
(25)
tsu(A)SR (29)
ADDRESS tw(E)SR
(30)
tdis(E) td(E)R (28)
Output
th(A)SR High Impedance VALID
tsu(A)SR
(29)
td(E)S (27) VALID tdis(E)SR (26)
Software Controlled STORE/RECALL Cyclex, after STORE initiation)
(25)
Output
(29)
ADDRESS tw(E)SR
(30) (31) (29)
ADDRESS
(31) th(A)SR
tsu(A)SR High Impedance
th(A)SR
VALID
tsu(A)SR
td(E)S (27) td(E)R (28) VALID tdis(E)SR (26)
must HIGH when during address sequence order initiate nonvolatile cycle. either HIGH throughout. Addresses through found mode selection table. Address determines whether U630H16P performs STOREor RECALL. must used clock address sequence Software controlled STORE RECALL cycles.
Control #ML0037
March 2006
U630H16P
Test Configuration Functional Check
VCCac
Input level according
relevant test measurement
ment output pins
Simultaneous measure-
measurement tdis-times ten-times capacitance Between must connected high frequency bypass capacitor avoid disturbances.
Capacitancee Input Capacitance Output Capacitance
Conditions
Symbol
Min.
Max.
Unit
pins under test must connected with ground capacitors. Ordering Code Example Type Class blank 2000 Package PLCC32 Operating Temperature Range U630H16 Leadfree Option blank Standard Package Leadfree Green Package Access Time
Device Marking (example)
Product specification
U630H16PC 0425
Date manufacture (The first digits indicating year, last digits calendar week.) Leadfree Green Package
Internal Code
March 2006
Control #ML0037
U630H16P
Device Operation U630H16P separate modes operation: SRAM mode nonvolatile mode, determined state pin. SRAM mode, memory operates standard fast static RAM. nonvolatile mode, data transferred from SRAM EEPROM (the STORE operation) from EEPROM SRAM (the RECALL operation). this mode SRAM functions disabled. SRAM READ U630H16P performs READ cycle whenever while HIGH. address specified pins determines which 2048 data bytes will accessed. When READ initiated address transition, outputs will valid after delay tcR. READ initiated outputs will valid ta(E) ta(G), whichever later. data outputs will repeatedly respond address changes within access time without need transition control input pins, will remain valid until another address change until brought HIGH brought LOW. SRAM WRITE WRITE cycle performed whenever HIGH. address inputs must stable prior entering WRITE cycle must remain stable until either goes HIGH cycle. data pins will written into memory valid tsu(D) before controlled WRITE tsu(D) before controlled WRITE. recommended that kept HIGH during entire WRITE cycle avoid data contention common lines. left LOW, internal circuitry will turn output buffers tdis(W) after goes LOW. Noise Consideration U630H16P high speed memory therefore must have high frequency bypass capacitor approximately connected between using leads traces that short possible. with high speed CMOS ICs, normal carefull routing power, ground signals will help prevent noise problems. Hardware Nonvolatile STORE STORE cycle performed when while HIGH. While sequence achieve this state will initiate STORE, only initiation initiation practical without risking unintentional Control #ML0037 RECALL cycle performed when while HIGH. Like STORE cycle, RECALL initiated when last three clock-signals goes RECALL state. Once initiated, RECALL cycle will take ,,RECALL Cycle Time" complete, during which inputs ignored. When RECALL completes, READ WRITE state input pins will take effect. Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL alters data nonvolatile cells. nonvolatile data recalled unlimited number times. Like STORE cycle, transition must occur some control pins cause RECALL, preventing inadvertend multi-triggering. Software Nonvolatile STORE U630H16P software controlled STORE cycle initiated executing sequential READ cycles from specific address locations. relying READ cycles only, U630H16P implements nonvolatile operation while remaining compatible with standard SRAMs. During STORE cycle, erase previous nonvolatile data first performed, followed parallel programming nonvolatile elements. Once STORE cycle initiated, further inputs outputs disabled until cycle completed. Because sequence addresses used STORE initiation, important that other READ WRITE accesses intervene sequence sequence will aborted STORE RECALL will take place. initiate STORE cycle following READ sequence must performed: Read address Read address Read address Read address Read address Read address (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate STORE SRAM WRITE that would disturb SRAM data. During STORE cycle, previous nonvolatile data erased SRAM contents then programmed into nonvolatile elements. Once STORE cycle initiated, further input output disabled pins tristated until cycle completed. HIGH cycle, READ will performed outputs will active, indicating STORE. Hardware Nonvolatile RECALL
March 2006
U630H16P
Once sixth address sequence been entered, STORE cycle will commence chip will disabled. important that READ cycles WRITE cycles used sequence. necessary that sequence valid. After tSTORE cycle time been fulfilled, SRAM will again activated READ WRITE operation. Software Nonvolatile RECALL RECALL cycle EEPROM data into SRAM initiated with sequence READ operations manner similar STORE initiation. initiate RECALL cycle following sequence READ operations must performed: Read address Read address Read address Read address Read address Read address (hex) (hex) (hex) (hex) (hex) (hex) Valid READ Valid READ Valid READ Valid READ Valid READ Initiate RECALL Hardware Protection U630H16P offers levels protection suppress inadvertent STORE cycles. control signals remain STORE condition STORE cycle, second STORE cycle will started. STORE RECALL) will initiated only after transition these signals required state. addition multi-trigger protection, U630H16P offers hardware protection through Sense. When VSWITCH externally initiated STORE operation will inhibited. Average Active Power U630H16P been designed draw significantly less power when (chip enabled) access cycle time longer than When HIGH chip consumes only standby current. overall average current drawn part depends following items:
Internally, RECALL step procedure. First, SRAM data cleared second, nonvolatile information transferred into SRAM cells. RECALL operation alters data EEPROM cells. nonvolatile data recalled unlimited number times. Automatic Power RECALL power once exceeds sense voltage VSWITCH, RECALL cycle automatically initiated. voltage must drop below VSWITCH once risen above order RECALL operate properly. this automatic RECALL, SRAM operation cannot commence until tRESTORE after exceeds VSWITCH. U630H16P WRITE state power RECALL, SRAM data will corrupted. help avoid this situation, resistor should connected between system VCC.
CMOS input levels time during which chip disabled HIGH) cycle time accesses LOW) ratio READs WRITEs operating temperature level
information describes type component shall considered assured characteristics. Terms delivery rights change design reserved.
March 2006
Control #ML0037
U630H16P
LIFE SUPPORT POLICY Simtek products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Simtek product could create situation where personal injury death occur. Components used life-support devices systems must expressly authorized Simtek such purpose.
LIMITED WARRANTY information this document been carefully checked believed reliable. However, Simtek makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon information this document describes type component shall considered assured characteristics. Simtek does guarantee that information contained herein will infringe upon patent, trademark, copyright, mask work right other rights third parties, patent licence implied hereby. This document does extent Simtek's warranty product beyond that forth standard terms conditions sale. Simtek reserves terms delivery reserves right make changes products specifications, both, presented this publication time without notice.
March 2006
Change record
Date/Rev 10.05.2004 31.3.2006 Name Matthias Schniebel Troy Meester Simtek Change initial release based U630H16PA35 U630H16 integrating software controlled Store Recall U631H16) changed obsolete status Assigned Simtek Document Control Number

HardStore nvSRAM Features Description U630H16P separate modes ope

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