1.8V-3.3V PicoPLL Programmable Clock Advanced Programmable design

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1.8V-3.3V PicoPLL Programmable Clock Advanced Programmable design

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PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
Advanced Programmable design lowfrequency (KHz) input applications. selectable AC/DC Ref. Coupling. Accepts <1.0V reference signal input voltage Very Jitter Phase Noise (30-70ps Pk-Pk typical) Output frequency 133MHz 1.8V operation 166MHz 2.5V operation 200MHz 3.3V operation Offered Tiny GREEN/RoHS compliant packages 6-pin (2.0mmx1.3mmx0.6mm) 6-pin SC70 (2.3mmx2.25mmx1.0mm) 6-pin SOT23 (3.0mmx3.0mmx1.35mm) Input Frequency: 10KHz 200MHz Single 1.8V, 2.5V, 3.3V power supply Operating temperature range from 70°C
DESCRIPTION
PL611s-15 low-cost general purpose frequency synthesizer member PhaseLink's PicoPLL Factory Programmable `Quick Turn Clock (QTC)' family. Designed small SOT23, SC70, package high performance applications, PL611s-15 accepts frequency (>10KHz) Reference input generates 200MHz output with best phase noise, jitter performance, power consumption handheld devices notebook applications. Cascading PL611s-15 with other PicoPLL could result producing required system clocks with specific savings board space, power consumption, cost.
PACKAGE ASSIGNMENT
GNDA CLK0
PL611s-15
CLK0 GNDA
CLK0
PL611s-15
PL611s-15
GNDA
DFN-6L (2.0mmx1.3mmx0.6mm)
SC70-6L (2.3mmx2.25mmx1.0mm)
SOT23-6L (3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
R-Counter (7-bit) M-Counter (16-bit)
Phase Detector
Charge Pump
FVCO FRef M/R)
Programmable Function
FOut FVCO
P-Counter (4-bit) /2*P
CLK0
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page
PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
PACKAGE ASSIGNMENT
Name
GNDA CLK0
SC70
Type
connection.
Description
Ground connection Analog Circuitry. Reference input pin. Loop Filter input pin. connection Programmable Clock Output
GUIDELINES EXTERNAL COMPONENT SELECTION
optimum performance, accurate external loop filter components must selected. general guideline selecting these components based input frequency shown below table. Please contact PhaseLink more accurate component selections. Input frequency 3MHz 200MHz 300KHz 10MHz 30KHz 1.0MHz 10KHz 100KHz Capacitor Value 4.7nF 4.7nF 4.7nF 47nF Resistor Value 2.2K 6.8K
APPLICATION RECOMMENDATIONS PL611s-15
PL611s-15 accept reference input >10KHz produce clock output range, shown diagram `1', below. However, save costs consumer product system designs greater area optimization, possible XOUT crystal (32.768KHz) reference input PL611s-15, shown diagram `2', below.
REFIN
LPGND (Any Frequency
PL611s15
32.768K
ASIC
XOUT
XOUT
1.8~3.3V
REFIN
LPGND (Any Frequency)
PL611s15
1.8~3.3V
Diagram
Note: Coupling required Clock amplitude small.
Diagram
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page
PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Data Retention 85°C Storage Temperature Ambient Operating Temperature
SYMBOL
MIN.
MAX.
UNITS
Year
Exposure device under conditions beyond limits specified Maximum Ratings extended periods cause permanent damage device affect product reliability. These conditions represent stress rating only, functional operations device these other conditions above operational limits noted this specification implied.
SPECIFICATIONS
PARAMETERS
Input Frequency (FIN) Output Frequency Output Frequency Output Frequency Settling Time Input (FIN) Signal Amplitude Output Rise Time Output Fall Time Duty Cycle
CONDITIONS
Reference Clock Input Vdd=3.3V Vdd=2.5V Vdd=1.8V power-up (after increases over 1.62V) Internally coupled 15pF Load, 10/90%VDD, High Drive, 3.3V 15pF Load, 90/10%VDD, High Drive, 3.3V VDD/2
MIN.
10KHz
TYP.
MAX.
UNITS
Note: Jitter performance depends programming parameters.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page
PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Operating Voltage Output Voltage Output High Voltage Output Current, drive Output Current, Standard drive Output Current, High drive Short-circuit Current
SYMBOL
CONDITIONS
@Vdd=3.3V,30MHz, load=15pF @Vdd=2.5V,30MHz, load=15pF @Vdd=1.8V,30MHz, load=5pF
MIN.
TYP.
2.1*
MAX.
UNITS
1.62 +4mA Standard Drive -4mA Standard Drive 0.4V, 2.4V 0.4V, 2.4V 0.4V, 2.4V
3.63
Note: Please PL611s-16 datasheet lower power required.
LAYOUT CONSIDERATIONS PERFORMANCE OPTIMIZATION
following guidelines assist with performance optimized design: Keep traces PL611s-15 short possible, well keeping other traces away from possible. When reference input clock generated from crystal (see diagram above), place PL611s-15 `FIN' close possible `Xout' crystal pin. This will reduce crosstalk between reference input other signals. Place Loop Filter (LF) components close package PL611s-15 possible. Place 0.01µF~0.1µF decoupling capacitor between GND, component side PCB, close pin. recommended place this component backside PCB. Going through vias will reduce signal integrity, causing additional jitter phase noise. highly recommended keep traces short possible. When connecting long traces inch) CMOS output, important design traces transmission line `stripline', avoid reflections ringing. this case, CMOS output needs matched trace impedance. Usually `striplines' designed impedance CMOS outputs usually have lower than impedance matching achieved adding resistor series with CMOS output `stripline' trace. Please contact PhaseLink application note design outputs driving long traces Gerber files PL611s-15 layout.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page
PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6 Symbol SC70-6L Symbol DFN-6L
Dimension Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 0.35 0.55 0.95
Pin1
Dimension Min. Max. 0.80 1.00 0.00 0.09 0.80 0.91 0.15 0.30 0.08 0.25 1.85 2.25 1.15 1.35 2.00 2.30 0.21 0.41 0.65BSC
Pin1
Symbol
Dimension Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
Chamfer
Pin1
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page
PL611s-15
1.8V-3.3V PicoPLL Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
part ordering, please contact Sales Department: 47745 Fremont Blvd., Fremont, 94538, Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
order number this device combination following: Device number, Package type Operating temperature range
PL611s-XXX
PART NUMBER DIGIT Code (will assigned programming time) PACKAGE TYPE T=SOT U=SC70 G=DFN Part Number PL611s-XXX PL611s-XXX PL611s-XXX
NONE= TUBE R=TAPE REEL TEMPERATURE C=COMMERCIAL INDUSTRIAL Marking 15XXX 15XXX 15XXX Package Option 6-Pin SC70 (Tape Reel) 6-Pin SC70 (Tape Reel) 6-Pin SOT-23 (Tape Reel)
Order Number PL611s-15-XXXGC-R PL611s-15-XXXUC-R PL611s-15-XXXTC-R
Note: `XXX' designates marking identifier that could independent part number.
PhaseLink Corporation, reserves right make changes products specifications, both time without notice. information furnished Phaselink believed accurate reliable. However, PhaseLink makes guarantee warranty concerning accuracy said information shall responsible loss damage whatever nature resulting from reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products authorized critical components life support devices systems without express written approval President PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 (510) 492-0990 (510) 492-0991 www.phaselink.com 07/18/06 Page

1.8V-3.3V PicoPLL Programmable Clock Advanced Programmable design

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