MC74HC165A identical pinout LS165. device inputs compatible with stand
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MC74HC165A 8-Bit Serial Parallel-Input/ Serial-Output Shift Register
MC74HC165A identical pinout LS165. device inputs compatible with standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs. This device 8-bit shift register with complementary outputs from last stage. Data loaded into register either parallel serial form. When Serial Shift/Parallel Load input low, data loaded asynchronously parallel. When Serial Shift/Parallel Load input high, data loaded serially rising edge either Clock Clock Inhibit (see Function Table). 2-input clock used either combining independent clock sources designating clock inputs clock inhibit.
Features
MARKING DIAGRAMS
PDIP-16 SUFFIX CASE SOIC-16 SUFFIX CASE 751B HC165AG AWLYWW MC74HC165AN AWLYYWWG
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS, Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance with Requirements Defined JEDEC Standard Chip Complexity: FETs 71.5 Equivalent Gates Pb-Free Packages Available*
TSSOP-16 SUFFIX CASE 948F SOEIAJ-16 SUFFIX CASE 74HC165A ALYWG 165A ALYWG
Assembly Location Wafer Year Work Week Pb-Free Package Pb-Free Package (Note: Microdot either location)
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
Semiconductor Components Industries, LLC, 2005
June, 2005 Rev.
Publication Order Number: MC74HC165A/D
MC74HC165A
SERIAL SHIFT/ PARALLEL LOAD CLOCK CLOCK INHIBIT PARALLEL DATA INPUTS SERIAL DATA OUTPUTS
Figure Assignment
SERIAL DATA INPUT SERIAL SHIFT/ PARALLEL LOAD CLOCK CLOCK INHIBIT
Figure Logic Diagram
FUNCTION TABLE
Serial Shift/ Parallel Load Inputs Clock Inhibit Clock don't care Internal Stages Change Change Output Operation Asynchronous Parallel Load Serial Shift Clock Serial Shift Clock Inhibit Inhibited Clock Clock
Data shifted from preceding stage
ORDERING INFORMATION
Device MC74HC165AN MC74HC165ANG MC74HC165AD MC74HC165ADG MC74HC165ADR2 MC74HC165ADR2G MC74HC165ADTR2 MC74HC165ADTR2G MC74HC165AF MC74HC165AFG MC74HC165AFEL MC74HC165AFELG Package PDIP-16 PDIP-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) SOIC-16 SOIC-16 (Pb-Free) TSSOP-16* TSSOP-16* SOEIAJ-16 SOEIAJ-16 (Pb-Free) SOEIAJ-16 SOEIAJ-16 (Pb-Free) Shipping Units Rail Units Rail Units Rail Units Rail 2500 Units Reel 2500 Units Reel 2500 Units Reel 2500 Units Reel Units Rail Units Rail 2000 Units Reel 2000 Units Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free.
MC74HC165A
MAXIMUM RATINGS
Symbol Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Vout Output Voltage (Referenced GND) Input Current, Iout Output Current, Supply Current, Pins Power Dissipation Still Plastic SOIC Package TSSOP Package Tstg Storage Temperature Lead Temperature, from Case Seconds (Plastic DIP, SOIC TSSOP Package)
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Maximum ratings those values beyond which device damage occur. Maximum ratings applied device individual stress limit values (not normal operating conditions) valid simultaneously. these limits exceeded, device functional operation implied, damage occur reliability affected. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter
Unit
Supply Voltage (Referenced GND)
Vin, Vout
Input Voltage, Output Voltage (Referenced GND) Operating Temperature, Package Types Input Rise Fall Time (Figure
1000
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol
Parameter
Test Conditions
Guaranteed Limit 85_C 3.15 1.35 1.80
25_C 3.15 1.35 1.80
125_C 3.15 1.35 1.80
Unit
Minimum High-Level Input Voltage
Vout |Iout|
Maximum Low-Level Input Voltage
Vout |Iout|
Minimum High-Level Output Voltage
|Iout|
|Iout| |Iout| |Iout|
2.48 3.98 5.48
2.34 3.84 5.34
2.20 3.70 5.20
MC74HC165A
ELECTRICAL CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter Test Conditions Guaranteed Limit 85_C 25_C 125_C Unit Maximum Low-Level Output Voltage |Iout| |Iout| |Iout| |Iout| 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 Maximum Input Leakage Current Iout Maximum Quiescent Supply Current (per Package) NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
ELECTRICAL CHARACTERISTICS Input
Symbol fmax Parameter
Guaranteed Limit 85_C
25_C
125_C
Unit
Maximum Clock Frequency (50% Duty Cycle) (Figures
tPLH, tPHL
Maximum Propagation Delay, Clock Clock Inhibit) (Figures
tPLH, tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load (Figures
tPLH, tPHL
Maximum Propagation Delay, Input (Figures
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
NOTES: propagation delays with loads other than Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Package)*
Used determine no-load dynamic power consumption: VCC2 load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
TIMING REQUIREMENTS (Input
Symbol
trec
Maximum Input Rise Fall Times (Figure
Minimum Pulse width, Serial Shift/Parallel Load (Figure
Minimum Pulse Width, Clock Clock Inhibit) (Figure
Minimum Recovery Time, Clock Clock Inhibit (Figure
Minimum Hold Time, Clock Clock Inhibit) Serial Shift/Parallel Load (Figure
Minimum Hold Time, Clock Clock Inhibit) Input (Figure
Minimum Hold Time, Serial Shift/Parallel Load Parallel Data Inputs (Figure
Minimum Setup Time, Clock Clock Inhibit (Figure
Minimum Setup Time, Serial Shift/Parallel Load Clock Clock Inhibit) (Figure
Minimum Setup Time, Input Clock Clock Inhibit) (Figure
Minimum Setup Time, Parallel Data Inputs Serial Shift/Parallel Load (Figure
Parameter
MC74HC165A
25_C 1000 Guaranteed Limit 85_C 1000 125_C 1000 Unit
MC74HC165A
DESCRIPTIONS
INPUTS (Pins
applied this pin, data Parallel Data inputs asynchronously loaded into each eight internal stages.
Clock, Clock Inhibit (Pins
Parallel Data inputs. Data these inputs asynchronously entered parallel into internal flip-flops when Serial Shift/Parallel Load input low.
(Pin
Serial Data input. When Serial Shift/Parallel Load input high, data this serially entered into first stage shift register with rising edge Clock.
CONTROL INPUTS Serial Shift/Parallel Load (Pin
Clock inputs. These clock inputs function identically. Either used active-high clock inhibit. However, avoid double clocking, inhibit input should high only while clock input high. shift register completely static, allowing Clock rates down continuous intermittent mode.
OUTPUTS (Pins
Data-entry control input. When high level applied this pin, data Serial Data input (SA) shifted into register with rising edge Clock. When level
Complementary Shift Register outputs. These pins noninverted inverted outputs eighth stage shift register.
MC74HC165A
SWITCHING WAVEFORMS
CLOCK CLOCK INHIBIT 1/fmax tPLH tPHL tTLH tTHL SERIAL SHIFT/ PARALLEL LOAD tPLH tPHL
Figure Serial-Shirt Mode
Figure Parallel-Load Mode
VALID INPUT tPLH tTLH tPHL SERIAL SHIFT/ PARALLEL LOAD tTHL INPUTS
ASYNCHRONOUS PARALLEL LOAD (LEVEL SENSITIVE)
Figure Parallel-Load Mode
Figure Parallel-Load Mode
VALID INPUT CLOCK CLOCK INHIBIT
SERIAL SHIFT/ PARALLEL LOAD CLOCK CLOCK INHIBIT
Figure Serial-Shift Mode
Figure Serial-Shift Mode
TEST POINT CLOCK INHIBITED CLOCK INHIBIT CLOCK trec OUTPUT DEVICE UNDER TEST
*Includes probe capacitance
Figure Serial-Shift, Clock-Inhibit Mode
Figure Test Circuit
MC74HC165A
EXPANDED LOGIC DIAGRAM
SERIAL SHIFT/ PARALLEL LOAD SERIAL DATA INPUT
CLOCK CLOCK INHIBIT
TIMING DIAGRAM
CLOCK CLOCK INHIBIT SERIAL SHIFT/ PARALLEL LOAD PARALLEL DATA INPUTS CLOCK INHIBIT MODE PARALLEL LOAD
SERIAL-SHIFT MODE
MC74HC165A
PACKAGE DIMENSIONS
PDIP-16 SUFFIX CASE 648-08 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL.
SEATING PLANE
0.25 (0.010)
INCHES 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 0.050 0.008 0.015 0.110 0.130 0.295 0.305 0.020 0.040
MILLIMETERS 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 1.27 0.21 0.38 2.80 3.30 7.50 7.74 0.51 1.01
SOIC-16 SUFFIX CASE 751B-05 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50 INCHES 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.229 0.244 0.010 0.019
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
MC74HC165A
PACKAGE DIMENSIONS
TSSOP-16 SUFFIX CASE 948F-01 ISSUE
0.10 (0.004) 0.15 (0.006)
IDENT.
0.15 (0.006)
0.25 (0.010)
DETAIL
0.10 (0.004) SEATING
PLANE
DETAIL
SECTION
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH. PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 4.90 5.10 4.30 4.50 1.20 0.05 0.15 0.50 0.75 0.65 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 INCHES 0.193 0.200 0.169 0.177 0.047 0.002 0.006 0.020 0.030 0.026 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252
MC74HC165A
PACKAGE DIMENSIONS
SOEIAJ-16 SUFFIX CASE 966-01 ISSUE
DETAIL
VIEW
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS MEASURED PARTING LINE. MOLD FLASH PROTRUSIONS SHALL EXCEED 0.15 (0.006) SIDE. TERMINAL NUMBERS SHOWN REFERENCE ONLY. LEAD WIDTH DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS LEAD WIDTH DIMENSION MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT LOCATED LOWER RADIUS FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS ADJACENT LEAD 0.46 0.018). MILLIMETERS 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 7.40 8.20 0.50 0.85 1.10 1.50 0.70 0.90 0.78 INCHES 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 0.291 0.323 0.020 0.033 0.043 0.059 0.028 0.035 0.031
0.13 (0.005)
0.10 (0.004)
MC74HC165A
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MC74HC165A/D
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