MC74HC08A identical pinout LS08. device inputs compatible with Standar

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MC74HC08A identical pinout LS08. device inputs compatible with Standar

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MC74HC08A Quad 2-Input Gate
MC74HC08A identical pinout LS08. device inputs compatible with Standard CMOS outputs; with pullup resistors, they compatible with LSTTL outputs.
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PDIP-14 SUFFIX CASE SOIC-14 SUFFIX CASE 751A HC08AG AWLYWW
Output Drive Capability: LSTTL Loads Outputs Directly Interface CMOS, NMOS Operating Voltage Range: Input Current: High Noise Immunity Characteristic CMOS Devices Compliance With JEDEC Standard Requirements Chip Complexity: FETs Equivalent Gates Pb-Free Packages Available
LOGIC DIAGRAM
MC74HC08AN AWLYYWWG
TSSOP-14 SUFFIX CASE 948G
ALYW
Assembly Location Wafer Year Work Week Pb-Free Package (Note: Microdot either location)
FUNCTION TABLE Pinout: 14-Lead Packages (Top View)
Inputs Output
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
Semiconductor Components Industries, LLC, 2006
October, 2006 Rev.
Publication Order Number: MC74HC08A/D
MC74HC08A
MAXIMUM RATINGS
Symbol Vout Iout Parameter Value Unit Supply Voltage (Referenced GND) Input Voltage (Referenced GND) Output Voltage (Referenced GND) Input Current, Output Current, Supply Current, Pins Power Dissipation Still Air, Plastic SOIC Package TSSOP Package Tstg Storage Temperature Lead Temperature, from Case Seconds Plastic DIP, SOIC TSSOP Package
This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VCC. Unused inputs must always tied appropriate logic voltage level (e.g., either VCC). Unused outputs must left open.
Stresses exceeding Maximum Ratings damage device. Maximum Ratings stress ratings only. Functional operation above Recommended Operating Conditions implied. Extended exposure stresses above Recommended Operating Conditions affect device reliability. Derating Plastic DIP: mW/_C from 125_C SOIC Package: mW/_C from 125_C TSSOP Package: mW/_C from 125_C high frequency heavy load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
Symbol Parameter Unit Supply Voltage (Referenced GND) Input Voltage, Output Voltage (Referenced GND) Vin, Vout Operating Temperature, Package Types Input Rise Fall Time (Figure 1000
RECOMMENDED OPERATING CONDITIONS
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MC74HC08A
ORDERING INFORMATION
Device MC74HC08AN MC74HC08ANG MC74HC08AD MC74HC08ADG MC74HC08ADR2 MC74HC08ADR2G MC74HC08ADTR2 MC74HC08ADTR2G MC74HC08AFEL MC74HC08AFELG Package PDIP-14 PDIP-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14* TSSOP-14* SOEIAJ-14 SOEIAJ-14 (Pb-Free) 2000/Tape Reel 2500/Tape Reel Units Rail Units Rail Shipping
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D. *This package inherently Pb-Free.
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MC74HC08A
CHARACTERISTICS (Voltages Referenced GND)
Symbol Parameter Minimum High-Level Input Voltage Condition Vout 0.1V -0.1V |Iout| 20mA |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA |Iout| 2.4mA |Iout| 4.0mA |Iout| 5.2mA Guaranteed Limit 25°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.48 3.98 5.48 0.26 0.26 0.26 ±0.1 85°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.34 3.84 5.34 0.33 0.33 0.33 ±1.0 125°C 1.50 2.10 3.15 4.20 0.50 0.90 1.35 1.80 2.20 3.70 5.20 0.40 0.40 0.40 ±1.0 Unit
Maximum Low-Level Input Voltage
Vout 0.1V 0.1V |Iout| 20mA
Minimum High-Level Output Voltage
|Iout| 20mA =VIH
Maximum Low-Level Output Voltage
|Iout| 20mA
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
Iout
NOTE: Information typical parametric values found Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
CHARACTERISTICS 50pF, Input 6ns)
Symbol tPLH, tPHL Parameter Maximum Propagation Delay, Input Output (Figures Guaranteed Limit 25°C 85°C 125°C Unit
tTLH, tTHL
Maximum Output Transition Time, Output (Figures
Maximum Input Capacitance
NOTE: propagation delays with loads other than information typical parametric values, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D). Typical 25°C, Power Dissipation Capacitance (Per Buffer)* Used determine no-load dynamic power consumption: load considerations, Chapter Semiconductor High-Speed CMOS Data Book (DL129/D).
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MC74HC08A
INPUT tPLH OUTPUT tTLH tTHL tPHL
Figure Switching Waveforms
TEST POINT OUTPUT DEVICE UNDER TEST
*Includes probe capacitance
Figure Test Circuit
Figure Expanded Logic Diagram (1/4 Device)
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MC74HC08A
PACKAGE DIMENSIONS
PDIP-14 CASE 646-06 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: INCH. DIMENSION CENTER LEADS WHEN FORMED PARALLEL. DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL. INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.290 0.310 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.37 7.87 0.38 1.01
SEATING PLANE
0.13 (0.005)
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MC74HC08A
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE
0.25 (0.010)
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION.
SEATING PLANE
0.25 (0.010)
MILLIMETERS 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50
INCHES 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
SOLDERING FOOTPRINT*
7.04 0.58
1.52
1.27 PITCH
DIMENSIONS: MILLIMETERS
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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MC74HC08A
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE
0.10 (0.004) 0.15 (0.006)
0.25 (0.010)
IDENT.
DETAIL
0.15 (0.006)
SECTION
0.10 (0.004) SEATING
PLANE
DETAIL
SOLDERING FOOTPRINT*
7.06
0.36
1.26
*For additional information Pb-Free strategy soldering details, please download Semiconductor Soldering Mounting Techniques Reference Manual, SOLDERRM/D.
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NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS INCHES 4.90 5.10 0.193 0.200 4.30 4.50 0.169 0.177 1.20 0.047 0.05 0.15 0.002 0.006 0.50 0.75 0.020 0.030 0.65 0.026 0.50 0.60 0.020 0.024 0.09 0.20 0.004 0.008 0.09 0.16 0.004 0.006 0.19 0.30 0.007 0.012 0.19 0.25 0.007 0.010 6.40 0.252
0.65 PITCH
DIMENSIONS: MILLIMETERS
MC74HC08A
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PUBLICATION ORDERING INFORMATION
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MC74HC08A/D

MC74HC08A identical pinout LS08. device inputs compatible with Standar

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