MC33560 interface smartcard reader/writer applications. enables manage
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MC33560 Power Management Interface Smartcard Readers Couplers
MC33560 interface smartcard reader/writer applications. enables management type smart memory card through simple flexible microcontroller interface. Moreover, several couplers coupled parallel, thanks chip select input (Pin MC33560 particularly suited power portable applications because power saving features minimum external parts required. Battery life extended wide operating range quiescent current standby mode. highly sophisticated protection system guarantees timely controlled shutdown upon error conditions. 100% Compatible with 7816-3 Standard Wide Battery Supply Voltage Range: VBAT Programmable Supply Card Operation Power Management Very Quiescent Current Standby Mode max) Microprocessor Wakeup Signal Generated Upon Card Insertion Self Contained DC-DC Converter Generate using Minimum Passive Components Controlled Powerup/Down Sequence High Signal Integrity Card Signal Lines Programmable Card Clock Generator Chip Select Capability Parallel Coupler Operation High Protection Card Pins (4.0 Human Body Model) Fault Monitoring VBATlow, VCClow ICClim Card Outputs Current Limited Short Circuit Protected Tested Operating Temperature Range: -25°C +85°C Pb-Free Packages Available
MC33560DW AWLYYWWG SO-24W SUFFIX CASE 751E MC335 ALYW Assembly Location Wafer Year Work Week Pb-Free Device
TSSOP-24 SUFFIX CASE 948K
CONNECTIONS
PGND PWRON RDYMOD RESET INVOUT ASYCLKIN ILIM VBAT CRDC8 CRDCON CRDDET CRDC4 CRDCLK CRDRST CRDVCC (Top View)
SYNCLK CRDIO CRDGND
ORDERING INFORMATION
detailed ordering shipping information package dimensions section page this data sheet.
Semiconductor Components Industries, LLC, 2005
August, 2005 Rev.
Publication Order Number: MC33560/D
MC33560
VBAT
ILIM PGND
DC-DC CONVERTER
PWRON RDYMOD SYNCLK ASYCLKIN INVOUT RESET
POWER MANAGER PROGRAMMING CLOCK GENERATOR VBAT
CARD DETECTOR DELAY
CRDDET CRDCON
CRDVCC CRDIO CRDRST CRDC4 CRDC8 CRDCLK CRDGND
LEVEL TRANSLATOR
Figure Simplified Functional Block Diagram
MAXIMUM RATINGS (Note
Symbol VBAT IBAT VOUT IOUT VCard ICard VESD Battery Supply Voltage Battery Supply Current Power Supply Voltage Power Supply Current Digital Input Pins Digital Output Pins Card Interface Pins Coil Driver ILIM (Pin Power Ground (Pin Capability: (Note Standard Pins Card Interface Pins SO-24 Package: Power Dissipation 85°C Thermal Resistance Junction-to-Air TSSOP-24 Package: Power Dissipation 85°C Thermal Resistance Junction-to-Air Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note Storage Temperature Range Rating Value ±200 ±150 -0.5 VBAT +0.5 ±5.0 -0.5 VBAT +0.5 -0.5 ±200 ±100 +125 +150 Unit
°C/W °C/W
RqJAs RqJAt TJmax Tstg
Maximum ratings those values beyond which device damage occur. Maximum ratings applied device individual stress limit values (not normal operating conditions) valid simultaneously. these limits exceeded, device functional operation implied, damage occur reliability affected. Maximum electrical ratings those values beyond which damage device occur. 25°C. Human body model, 1500 Maximum thermal rating beyond which damage device occur.
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MC33560
ELECTRICAL CHARACTERISTICS These specifications written same style common standard
integrated circuits. convention considers current flowing into (sink current) positive current flowing (source current) negative. (Conditions: VBAT nom, PWRON VBAT Operating Mode, -ICC -25°C 85°C, RLIM CRDVCC capacitor unless otherwise noted.) Characteristic BATTERY POWER SUPPLY SECTION Supply Voltage Range Normal operating range extended operating range (Note MC33560 Standby Quiescent Current PWRON GND, CRDCON GND, ASYCLKIN GND, VBAT Other Logic Inputs Outputs Open Operating Current -ICC VBAT VBAT Undervoltage Detection: Upper Threshold Lower Threshold Hysteresis NOMINAL POWER SUPPLY SECTION Output Voltage VBAT -ICC VBAT -ICC (RDYMOD Output) (See Table 4.75 4.60 VT5H VT5L VHYS5 -ICClim -ICCst Vsat22 VFsat22 5.25 5.40 0.14 VBAT IoBAT Test Conditions Symbol Unit
IBATop
12.5
Card Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Peak Output Current Current limit time-out Startup Current Side Switch Saturation Voltage Rectifier Saturation Voltage Converter Switching Frequency Shutdown Current (Card access deactivated)
Internally Limited (RDYMOD +85°C -40°C 25°C PWRON GND,
NOMINAL POWER SUPPLY SECTION (VBAT -ICC Output Voltage VBAT -ICC VBAT -ICC (RDYMOD Output) (See Table 2.75 2.60 VT3H VT3L VHYS3 -ICCst 3.25 3.40
Card Undervoltage Detection: Upper Threshold Lower Threshold Switching Hysteresis Startup Current Shutdown Current (Card access deactivated)
PWRON GND,
Figures transistors lines (see Figure have Rdson loading except INVOUT clock buffer optimized power consumption hence symmetrical, clock signal duty cycle guaranteed divide divide ratio. either direction.
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MC33560
ELECTRICAL CHARACTERISTICS (continued) These specifications written same style common standard integrated circuits. convention considers current flowing into (sink current) positive current flowing (source current) negative. (Conditions: VBAT nom, PWRON VBAT Operating Mode, -ICC -25°C 85°C, RLIM CRDVCC capacitor unless otherwise noted.)
Characteristic Test Conditions Symbol Unit
APPLICATION INTERFACE SECTION (VBAT Input High Threshold Voltage (increasing) Input Threshold Voltage (decreasing) Switching Hysteresis Threshold Voltage Pulldown resistance Pullup resistance Output High Voltage Pins Pins Pins VBAT Pins -2.5 pins 20,21 -0.2 Output Mode) Pins Pins Pins 0.55*VBAT 0.3*VBAT 0.2*VBAT 0.3*VBAT 0.06*VBAT 0.5*VBAT 0.4*VBAT VBAT 0.65*VBAT 0.45*VBAT 0.40*VBAT 0.5*VBAT 0.3*VBAT 0.6*VBAT 0.6*VBAT
VHYST Rdown
Output Voltage Input Leakage Current
±Ileak
CARD INTERFACE SECTION (VBAT Output High Voltage Output Voltage Pullup Resistance, Operating Mode, PWRON Card pins security voltage (Card access deactivated) Pins Pins Pins Pins Pins PWRON GND, Pins Vsecurity
DIGITAL DYNAMIC SECTION (VBAT Normal Operating Mode) (Note Input Clock Frequency Card Clock Frequency Card Clock Duty Cycle (Note Card Clock Rise Fall Time Data Transfer Frequency Duty Cycle Rise Fall Time Transfer Time Card Signal Sequence Interval Duty Cycle VCC, 11], [21, 16], [20, (Note 11], [21, 16], [20, (Note 11], [21, 16], [20, (Note 11], [21, 16], [20, (Note VCC, Pins Powerup Powerdown fasyclk fcrdclk rclk trclk, tfclk trio, tfio tdseq
Figures transistors lines (see Figure have Rdson loading except INVOUT clock buffer optimized power consumption hence symmetrical, clock signal duty cycle guaranteed divide divide ratio. either direction.
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MC33560
ELECTRICAL CHARACTERISTICS (continued) These specifications written same style common standard integrated circuits. convention considers current flowing into (sink current) positive current flowing (source current) negative. (Conditions: VBAT nom, PWRON VBAT Operating Mode, -ICC -25°C 85°C, RLIM CRDVCC capacitor unless otherwise noted.)
Characteristic Test Conditions Symbol Unit
DIGITAL DYNAMIC SECTION (VBAT Normal Operating Mode) (Note Card Detection Filter Time: Card Insertion Card Extraction Internal Reset Delay Ready Delay Time PWRON Pulse Width RES, Powerup Powerdown tfltin tfltout tdres tdrdy twon
DIGITAL DYNAMIC SECTION (VBAT programming mode) (Note Data Setup Time RDYMOD, PWRON, RESET, Data Hold Time RDYMOD, PWRON, RESET, Pulse Width Pins tsmod thmod Pins twcs
Figures transistors lines (see Figure have Rdson loading except INVOUT clock buffer optimized power consumption hence symmetrical, clock signal duty cycle guaranteed divide divide ratio. either direction.
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MC33560
(mA) (mA) Mode Sync SYNCLK Rlim VBAT IBATop Mode Sync SYNCLK Rlim VBAT IBATop
Figure Maximum Battery Card Supply Current VBAT (VCC
Figure Maximum Battery Card Supply Current VBAT (VCC
IBATop (mA) Async/4 VBAT Rlim Async
Sync IBATop (mA) Async/2 Async/4 Async Sync VBAT Rlim
Async/2
Frequency (MHz)
Frequency (MHz)
Figure Battery Current Input Clock Frequency (ICC VBAT
Figure Battery Current Input Clock Frequency (ICC VBAT
IBATop (mA) L1=22 Rlim (ohms) L1=100 Mode Sync SYNCLK VBAT
IBATop (mA) L1=22 Rlim (ohms) L1=100 Mode Sync SYNCLK VBAT
L1=47
L1=47
Figure Maximum Battery Current RLIM (VCC VBAT
Figure Maximum Battery Current RLIM (VCC VBAT
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MC33560
(mA) Rlim (ohms) Mode Sync SYNCLK=4MHz VBAT=4V (mA) Rlim (ohms) Mode Sync SYNCLK VBAT
Figure Maximum Card Supply Current RLIM (VCC VBAT
Figure Maximum Card Supply Current RLIM (VCC VBAT
0.08 Side Switch Saturation Voltage 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00 Rectifier Saturation Voltage
0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure Side Switch Saturation Voltage Temperature
Figure Rectifier Saturation Voltage Temperature
tfltout, Filter Time tfltin, Filter Time
Ambient Temperature (°C)
Ambient Temperature (°C)
Figure Card Detection (Insertion) Filter Time Temperature
Figure Card Detection (Extraction) Filter Time Temperature
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MC33560
PULLDOWN RESISTANCE (kW)
Ambient Temperature (°C)
Figure Pulldown Resistance Temperature
Figure Transition from Card Supply
Figure Transition from Card Supply
Figure Overcurrent Shutoff
Figure Undervoltage Shutoff (VT5L
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MC33560
VBAT VBAT VBAT PWRON VBAT VBAT RDYMOD VBATOK POWER MANAGEMENT LOGIC PROGRAMMING PROGRAM CARDENABLE FAULT LOGIC CARD CRDVCC DELAY CRDCON PWRON CRDDET VBATOK
CARD PINS SEQUENCER SEQ1 SEQ2 SEQ3 SEQ4
FAULT VBAT VBAT
ON/OFF 3V/5V
DC/DC CONVERTER CRDVCC
ILIM CRDVCC
CRDVCC BIDIRECTIONAL
SEQ1 CARDENABLE VBATOK VBAT SEQ3 CARDENABLE VBATOK VBAT
CRDIO CRDVCC
BIDIRECTIONAL CRDVCC BIDIRECTIONAL VBAT CRDVCC
CRDC4
SEQ3 CARDENABLE VBATOK
CRDC8
RESET
DATA LATCH CARDENABLE
LEVEL SHIFT
CRDRST VBAT CRDVCC
LEVEL SHIFT
SEQ4
SYNCLK ASYCLKIN CLOCK GENERATOR PROGRAMMING
CRDCLK
SEQ2 PROGRAM INVOUT
Figure Functional Block Diagram
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MC33560
Table FUNCTION DESCRIPTION
Symbol Type Name/Function
CONTROLLER INTERFACE PWRON INPUT Pulldown OUTPUT Pullup This used start operation internal DC-DC converter. programming mode, this used "Output Voltage" switch. (See Table This open collector indicates change card presence circuit status. When card inserted extracted, goes logic level "0". signal reset logic level upon rising edge upon rising edge PWRON. case multislot application, more outputs connected together microcontroller poll MC33560s identify which slot detected. This bidirectional tri-state output Schmitt trigger input. When RDYMOD forced MC33560 programming mode negative transition When RDYMOD connected high impedance, MC33560 normal operating mode, RDYMOD output mode (See Tables With PWRON=H, RDYMOD indicates status DC-DC converter. With PWRON=L, RDYMOD indicates status card detector. This MC33560 chip select signal. Pins disabled when When RDYMOD MC33560 enters programming mode upon falling edge (Figure signal present this input translated (the card reset signal) when signal this latched when This also used programming mode. (See Table This connects Serial port microcontroller. bi-directional level translator adapts serial signal between smartcard microcontroller. level translator enabled when signal thispin latched when CS=H. This also used programming mode. (See Table ASYCLKIN (Pin signal buffered inverted generate output signal INVOUT. This output used multislot applications, where ASYCLKIN inputs INVOUT outputs daisy-chained. (See multislot application example Figure This connected microcontroller master clock clock signal asynchronous cards. signal internal clock selector circuit, translated CRDCLK same frequency, divided depending programming. (See Table This function used communication with synchronous cards, generally connected controller serial interface clock signal. signal internal clock selector circuit, translated CRDCLK upon appropriate programming MC33560 (See Table When selected programming, signal this latched when General purpose input/output. same behavior I/O, except programming. connected bidirectional port microcontroller. level translator enabled when signal latched whenCS (Compare with General purpose input/output. same behavior I/O, except programming. connected bidirectional port microcontroller. level translator enabled when signal latched when (Compare with
RDYMOD
Pullup
INPUT Pullup
RESET
INPUT Pulldown
INVOUT
OUTPUT INPUT high impedance
ASYCLKIN
SYNCLK
INPUT Pulldown
CARD INTERFACE CRDIO CRDRST CRDCLK OUTPUT OUTPUT This connects serial card connector. bidirectional level translator adapts serial signal between card microcontroller. (Compare with This connects RESET card connector. level translator adapts RESET signal driven microcontroller. (Compare with This connects card connector. CRDCLK signal output clock selector circuit.The clock selection programmed using Pins with RDYMOD forced "0". General purpose input/output. same behavior CRDIO. connected card connector. This connects card detection switch card connector. Card detection phase determined with This needs external pullup pulldown resistor operate properly. This connects PGND VBAT, possibly output port microcontroller. With this logic "0", presence card signalled with logic With this logic "1", presence card signalled with logic
CRDC4 CRDDET
INPUT high impedance INPUT high impedance
CRDCON
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MC33560
Table FUNCTION DESCRIPTION
Symbol Type Name/Function
CARD INTERFACE CRDC8 General purpose input/output. same behavior CRDIO. connected card connector.
CURRENT LIMIT THERMAL PROTECTION PGND POWER POWER POWER POWER POWER This return path current flowing into (L1). must connected CRDGND using appropriate grounding techniques. CRDGND CRDVCC VBAT This signal ground. must connected ground card connector. reference level analog digital signals. This connects card connector. reference level logic Pins This connects external inductance DC-DC converter. Please refer description DC-DC converter functional block. This connected supply voltage. Logic level Pins referenced VBAT. Operation MC33560 inhibited when VBAT lower than minimum value. This connected PGND pin, resistor connected PGND, left open, depending peak coil current needed supply card. ILIM POWER
PROGRAMMING STATUS FUNCTIONS MC33560 features programming interface status interface. Figure shows enter exit programming mode; Table shows which pins used access various functions.
RDYMOD (in) PWRON RESET ENTER PROGRAMMING MODE PROGRAM DATA VALUE PROGRAM DATA VALUE PROGRAM DATA VALUE LATCH EXIT PROGRAM PROGRAMMING MODE VALUE
Figure MC33560 Programming Sequence
Table PROGRAMMING STATUS FUNCTIONS
Programs CRDVCC
RDYMOD (In/Out) (In) PWRON RESET(In) I/O(In) Force rising edge Programs Input/Divide Ratio Programs Input/Divide Ratio
Select ON/OFF READ USED USED
Select Clock Input Force rising edge Programs CRDVCC
Program ASYCLKIN Divide Ratio Force rising edge Programs CRDVCC
Poll Card Status READ Hi-z USED USED
Poll CRDVCC Status READ USED USED
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MC33560
CARD CARD CLOCK PROGRAMMING CRDVCC ASYCLK programming options allow system clock frequency matched card clock frequency select CRDVCC supply. Table shows values PWRON, RESET possible options. default power reset condition state (synchronous clock CRDVCC =5.0 states latched each output variable programming mode positive transition (Figure 20).
Table CARD CARD CLOCK TRUTH TABLE
STATE# NOTE: PWRON RESET CRDVCC CRDCLK SYNCLK ASYCLKIN/4 ASYCLKIN/2 ASYCLKIN SYNCLK ASYCLKIN/4 ASYCLKIN/2 ASYCLKIN
Card clock integrity maintained during frequency commutations spikes). State default state power
DC-DC CONVERTER CARD DETECTOR STATUS MC33560 status polled when Please consult Table description input output signals.The significance status message described Table
Table RDYMOD STATUS MESSAGES
PWRON (Input) HIGH HIGH RDYMOD (Output) HIGH HIGH Message card Card present DC-DC converter overload DC-DC converter
DETAILED OPERATING DESCRIPTION
INTRODUCTION
MC33560 Smartcard interface been designed provide necessary functions safe data transfers between microcontroller smartcard memory card. card detector scans presence card generates debounced wake-up signal microcontroller. Communication control signal levels translated between digital interface card interface voltage level translator, card clock matched system clock frequency programmable card clock
generator. power management unit enables DC-DC converter card power supply, supervises powerup/down sequence card's signal lines, keeps power consumption very standby mode. card interface pins have adequate protection, fault monitoring (VBATlow, VCClow, ICClim) guarantees hazard free card reader operation. Several MC33560s operated parallel, using same control data bus, through chip select signal
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MC33560
FALLING EDGE STAND MODE PWRON RISING EDGE RDYMOD: FALLING EDGE RDYMOD: RISING EDGE PROGRAMMING MODE RDYMOD ACTIVE MODE PWRON PWRON: RISING EDGE START SEQUENCE TRANSACTION MODE PWRON STOP SEQUENCE ERROR CONDITION
IDLE MODE PWRON RDYMOD: RISING EDGE RDYMOD: FALLING EDGE PROGRAMMING MODE RDYMOD
PWRON: FALLING EDGE ERROR CONDITION
Figure MC33560 Operating Modes OPERATING MODES TRANSACTION MODE
MC33560 five operating modes: Standby Programming Active Transaction Idle transitions between these different states shown Figure above.
STANDBY MODE
transaction mode, MC33560 maintains power selected clock signal applied card, levels I/O, RESET, signals between microcontroller card translated depending supply voltages VBAT VCC. DC-DC converter status monitored RDYMOD pin.
IDLE MODE
Standby mode allows MC33560 detect card insertion monitor power supply while keeping power consumption minimum. obtained with PWRON When MC33560 detects card, asserted wake Microcontroller.
PROGRAMMING MODE
Idle mode used when maintaining card powered without communicating with When asynchronous clock used, selected clock signal applied card.
POWERDOWN OPERATION
programming mode allows user configure card card clock signal specific application. card supply, CRDVCC, programmed card clock signal defined either synchronous, asynchronous divided Programming mode obtained with RDYMOD followed negative transition programming options shown Table Programmed values latched positive transition with RDYMOD
ACTIVE MODE
Powerdown initiated controlling microprocessor, stopping DC-DC converter with PWRON while MC33560 itself when error condition been detected (CRDVCC undervoltage, overcurrent longer than typ., overtemperature, "hot" card extraction). communication session terminated given sequence defined ISO7816-3. MC33560 then goes into active mode, which status polled. Standby mode reached deselecting MC33560 FUNCTIONAL BLOCKS
CARD DETECTOR
active mode, MC33560 selected, RDYMOD becomes output, MC33560 status polled. Power applied card. microcontroller polls MC33560 asserting reading RDYMOD pin. card present, microcontroller starts DC-DC converter asserting PWRON=H. This starts automatic power sequence: when CRDVCC reaches undervoltage level (VT5H VT3H, depending programming), card sequencer validates CRDIO, CRDRST, CRDCLK, CRDC4, CRDC8 pins according ISO7816-3 sequence (Figure 26). MC33560 transaction mode, system ready data exchange three lines RESET line.
This block monitors card contact CRDDET (during insertion extraction), filters incoming waveform generates interrupt signal after each change. order identify which coupler activated line (multicoupler application) microcontroller scans both circuits reads RDYMOD pin. programming input CRDCON tells level detector which type mechanical contact implemented (normally open normally closed). Special care taken hold current consumption very this part circuit which continuously powered VBAT supply. CRDDET high impedance input, external resistor must connected pullup pulldown, depending CRDCON. This resistor chosen according maximum leakage current card connector PCB.
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MC33560
card detector internal debouncing delay. micro controller insert additional delay range) allow card contacts stabilize card connector before setting PWRON When card detector circuit detects card extraction, activates powerdown sequence stops converter, regardless PWRON signal. delay debouncer enough ensure that card signals have reached safe value before communication with card takes place.
CARD STATUS
controlling microprocessor informed MC33560 status interrupt polling. When card extracted inserted, line asserted low. interrupt cleared upon rising edge upon rising edge PWRON (INT line high state). microprocessor poll status time reading RDYMOD with proper PWRON setting (see Tables Since RDYMOD have high value pullup resistor (240 typical), their rise time long parasitic capacitance high other pullup circuitry connected.
POWER MANAGER
output voltage programmable (see Table guarantee full cross compatibility reader smartcards. wide voltage supply range, VBAT accommodates broad range coupler applications with different battery configurations (single cell multiple cells, serial parallel connections). CRDVCC current-limited short-circuit-proof. avoid excessive battery loading during card short-circuit, current integration function forces powerdown sequence (Figure 28). retry session, microprocessor works through power sequence defined power manager section.
DC-DC CONVERTER OPERATING PRINCIPLES
task power manager activate only those circuit functions which needed determined operating mode order minimize power consumption (Figure 19). standby mode (PWRON power manager keeps only "card present" detector alive. card interface pins forced ground potential. event powerup request from microcontroller (PWRON transition, power manager starts DC-DC converter. soon CRDVCC supply reaches operating voltage range, circuit activates card signals following sequence: CRDVCC, CRDIO, CRDCLK, CRDC4/C8, CRDRST transaction (PWRON reset forced card extraction, CRDVCC supply powers down card signal deactivation sequence takes place: CRDRST, CRDC4/C8, CRDCLK, CRDIO, CRDVCC When bi-directional signal lines (I/O, into high impedance state avoid signal collision with microcontroller transmission mode.
BATTERY UNDERVOLTAGE DETECTOR
task this block monitor supply voltage, allow operation DC-DC converter only with valid voltage (typically comparator been designed have stability better than temperature range.
DC-DC CONVERTER
Upon request from power manager, DC-DC converter generates CRDVCC supply smartcard.
DC-DC converter architecture used MC33560 allows step-up step-down voltage conversion done. unique regulation architecture permits automatic transition from step-up step-down, from zero full load, without affecting output characteristics. DC-DC Converter Description: converter architecture very similar boost architecture, with active rectifier place diode. switching transistor connected ground through resistor network order adjust maximum peak current (Figure 22). transistor connected converter output (CRDVCC) forces this voltage when converter operating. This prevents erratic voltage supply smartcard when use. MC33560 built oscillator; DC-DC converter requires only inductor output filtering capacitor operate. Stepup Operation: When card supply voltage lower than battery voltage, converter operates like boost converter; active rectifier behavior similar that diode. Stepdown Operation: When card supply voltage higher than battery voltage, rectifier control circuit puts power rectifying transistor conduction when voltage reaches VBAT VFSAT22. voltage across rectifying transistor higher than step-up operation. efficiency lower, similar linear regulator. Fault Detection: DC-DC converter several features that help avoid electrical overstress MC33560 smartcard, help ensure that data transmission with smartcard occurs only when supply voltage within predetermined limits. These functions are: Overtemperature Detection, Current Limitation, Card Supply Undervoltage Detection. level which current will limited defined maximum card supply current programmed with external components RLIM. undervoltage detection levels card supply preset internally MC33560.
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MC33560
VBAT FEED BACK CLOCK STOP /OFF ILIMCOMP /OFF
DIGITAL FILTER
LOGIC COUNTER
Rectifier Switch
CRDVCC Active pull-down switch
Side Switch
RECTIFIER CONTROL
/OFF
/OFF
CRDGND PGND Internal resistors ILIM RLIM (external) VBATOK CONVERTER FAULT
ERROR AMP.
3V/5V
UNDER VOLTAGE DETECTOR
OVER TEMP DETECTION
CRDGND VREF
Figure DC-DC Converter Functional Block
overcurrent undervoltage protection features complementary, will shut circuit either overcurrent high enough bring CRDVCC output below preset threshold, either after (typ.) addition, DC-DC converter will allowed start only battery supply voltage high enough allow normal operation (1.8 undervoltage comparator hysteresis delay typically ensure stable operation. current detector comparator associated with resistors: attached PGND usually connected analog ground, attached ILIM, usually connected ground through external resistor adjust maximum peak current. voltage developed across this resistor network then compared (typical) reference voltage, comparator output performs cycle-by-cycle peak current limitation switching side transistor when voltage exceeds internal ILIMCOMP signal monitored stop converter current limitation continuously detected during (typical). This allows normal operation with high filtering capacitance peak current, even converter startup. result, short circuit ground card connector continuous overcurrent reported RDYMOD (typical) after powerup. Unexpected Card Extraction: MC33560 detects card extraction runs powerdown sequence card power still when extraction occurs. active pulldown switch clamps CRDVCC within (max) after extraction detected. external capacitors will then discharged. With typical capacitor values indicated application schematic, time needed discharge CRDVCC voltage below
estimated less than total time aftercard extraction detection until CRDVCC reaches then estimated (maximum). smartcard connector contacts will deactivated before CRDVCC deactivation. This ensures that electrical damage will caused smartcard under abnormal extraction conditions. V/5.0 Programming: possible card supply voltage time, before DC-DC converter start, during converter operation. When switching from (typical) delay blanks undervoltage fault detection allow filter capacitor charging. PWM: free-running integrated oscillator working modes: Variable on-state fixed frequency (typically KHz) average heavy loads. Variable on-state variable frequency light loads. frequency load connected CRDVCC. charging current timing capacitor related VBAT supply voltage, allow better line regulation, increase stability. Filtering Capacitor: high value allows efficient filtering card current spikes. values allow startup charging current. Care must taken combine capacitor value with high current limiting, this generate high ripple. Usual values range from depending current limiting. Selecting External Components RLIM: choice inductor resistor made using Figure (5.0 card) and/or Figure (3.0 card) page
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MC33560
First, determine maximum current that application requires supply card (ICCmax, y-axis) Then, select curve that crosses selected ICCmax level. curve associated with inductance value mH). Finally, intersection curve ICCmax level find Rlim value x-axis. Good starting values Rlim Note also that, high inductance value (100 mH), filtering capacitor generally charged before inductance current reaches current limitation, while alow inductance value, current limitation activated after converter cycles. Battery Requirements: Having determined Rlim values, maximum current drawn from battery supply shown curves Figures When application powered single battery, special care taken extend lifetime. When lithium batteries approach end-of-life, their internal resistance increases, while voltage decreases. This phenomenon prevent startup DC-DC converter current limiting high, because filtering capacitor charging current. CLOCK GENERATOR primary purpose clock generator module match smartcard operating frequency system frequency. source frequency provided ASYCLKIN microcontroller itself from external oscillator circuit. programming mode (RDYMOD=L asserted low) three input variables PWRON, RESET used configure output variables CRDVCC CRDCLK described Table This circuit setup latched during positive transition Furthermore, asynchronous mode system clock frequency ASYCLKIN divided factor circuit controls frequency commutation guarantee that card clock signal remains free from spikes glitches. addition, this circuit ensures that CRDCLK signal pulses will shorter than shortest and/or longer than longest clock signals present before after programming changes.
SYNCLK SYNCHRONISATION LOGIC LATCH CARDENABLE ASYCLKIN INVOUT
INVOUT output provided drive other circuits without additional load microprocessor quartz oscillator. also used build local oscillator. This driver been optimized consumption; hysteresis, input levels symmetrical. ASYCLKIN connected sine wave, duty cycle will always INVOUT.
CLOCK GENERATOR OPERATING PRINCIPLES
Synchronous Clock: This clock used mainly memory cards. also used asynchronous (microprocessor) cards, allowing different clock sources. status SYNCLK latched CRDCLK when goes high, that data (the pin) clock always consistent card connector, whatever status When using synchronous clock, clock output becomes active only when MC33560 selected with Asynchronous Clock: This clock used mainly microprocessor cards. When applied, clock output remains active even when MC33560 selected with order keep microprocessor running avoid unwanted reset. ASYCLKIN signal buffered INVOUT pin, that several MC33560 systems same clock with load only. Depending programming, frequency directly, divided CRDCLK pin. duty cycle applied clock signal exactly symmetrical, recommended that clock signal divided four guarantee duty cycle. Clock Signal Synchronization Consistency (Figure 29). clock divider includes synchronization logic that controls switch from synchronous clock asynchronous (and vice-versa), from division ratio other ratio, during changes powerup. synchronization logic guarantees that each clock cycle CRDCLK finished before changing clock selection (and always adequate duration), regardless moment programming changed. powerup, when ASYCLKIN selected, clock signal CRDCLK entire length, according selected divide ratio, whatever ASYCLKIN signal versus internal sequencer timing.
SELECTOR
CRDVCC SYNCHRO LATCH CRDCLK SEQ3
RESET SELECTOR LATCH
PROGRAM
Figure Clock Generator Functional Block http://onsemi.com
MC33560
BIDIRECTIONAL LEVEL TRANSLATOR This module (used I/O/CRDIO, C4/CRDC4, C8/CRDC8, Figure adapts signal voltage levels control lines between micro controller (supplied VBAT) smartcard (supplied CRDVCC) When low, with CRDVCC start sequencing completed, this module transparent data, acts card directly connected reader microcontroller. core level shifter circuit defined bidirectional CRDIO, CRDC4 CRDC8 lines consists NMOS switch which driven logic state from either side (microcontroller card). both sides work transmission mode with opposite phase, then signal collision line avoidable. this case, peak current limited safe value integrated circuit smartcard. During high-to-low transitions, NMOS transistor impedance maximum) enough charge parasitic capacitance, have high enough dv/dt. high transition, NMOS transistor active above certain voltage, acceleration circuit activated ensure high dv/dt. When chip disabled with voltage supply CRDVCC still active, I/O, lines keep their last logic state. When converter off, transistor forces CRDIO, CRDC4 CRDC8 lines state, thus preventing unwanted voltage level applied data lines when card use.
VBAT CRDVCC
Card presence detector "clean" fast shutdown Consistent card signal sequencing startup
powerdown, according ISO7816, even error conditions Consistent clock signal, even when division ratio synchronization clock signal changed fly" during card session (Figure Active pulldown card pins, including CRDVCC, when normal operating mode. current limiting function overtemperature detector limiting power dissipation. PROTECTION nature smartcards, card interface pins must absorb high Electro Static Discharge (ESD) energy during card insertion. addition, control circuits attached these pins must safely withstand short circuits voltage transients during forced card extraction. Therefore, MC33560 features enhanced protection, current limitation short circuit protection smartcard interface pins, including PARALLEL OPERATION applications where more MC33560 used, digital control data lines common MC33560. Only chip select signal, requires separate line each interface. While deselected, communication pins except CRDCLK will keep their logical state card side, will high impedance mode microprocessor side. Figure shows typical application dual card reader. This arrangement chosen only illustrate parallel operation card interfaces same module. discrete capacitor components necessary provide impedance supply lines VBAT CRDVCC suppress high frequency noise DC-DC converter. load resistors external order adapt sense current "card present" switches. MINIMUM POWER CONSUMPTION CONSIDERATIONS analog blocks except VBAT comparator card presence detector disabled standby mode DC-DC converter stopped). order maintain standby current minimum value, pins with pullup resistance (CS, INT, RDYMOD) have kept high state left open, pins with pulldown resistance (RESET, SYNCLK, PWRON) have kept state left open. ASYCLKIN should connected active clock signal during standby avoid dynamic currents. This valid also SYNCLK, except that left open.
(C4) (C8) CRDIO (CRDC4) (CRDC8)
CONTROL LOGIC
SEQ1 (SEQ3) CARDENABLE
CRDGND
Figure Bidirectional Translator Functional Block
SECURITY FEATURES MC33560 number unique security functions guarantee that electrical damage will caused smartcard: Battery supply minimum voltage threshold Card supply undervoltage overcurrent detection with automatic shutdown Card overvoltage clamp CRDVCC
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MC33560
VBAT ILIM PGND CRDGND CRDIO PWRON RDYMOD RESET SYNCLK ASYCLKIN INVOUT CRDC8 CRDDET CRDC4 CRDCLK CRDRST CRDVCC
Figure Example Single Sided Layout MC33560
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MC33560
POWERUP NORMAL OPERATION POWERDOWN
CRDVCC RDYMOD (out) PWRON RESET twon
VTxH
CRDIO CRDCLK CRDC4, CRDC8 CRDRST SEQ1 SEQ4 SEQ4 SEQ1
Figure Card Signal Sequence During Powerup/Down
tfltin CRDDET RDYMOD (out) typ. INTERRUPT SERVICING
tfltout
tdrdy POLLING INTERRUPT SERVICING POLLING
Figure Interrupt Servicing Polling
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MC33560
deactivates PWRON after card extraction
poll with PWRON RDYMOD card still present PWRON CRDVCC undervoltage RDYMOD
overload time smaller than tdres (glitch scale)
card inserted
tfltin
VTxH VTxL
tfltout
CRDVCC CRDDET RDYMOD PWRON tdrdy tdres tdres card extraction
poll with PWRON RDYMOD card present
polls RDYMOD overload time greater than tdres converter stop CRDVCC pulldown
poll with PWRON RDYMOD DC-DC converter overload
Figure Card Signal Sequence During Overload Unexpected Card Extraction
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MC33560
RDYMOD RESET SYNCLK ASYCLK CRDCLK
Figure "On-the-Fly" Card Clock Selection Examples
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RDYMOD RESET SYNCLK ASYCLK CRDCLK
MC33560 MC145407 reset
7805
8.40
Connector
Card Detect
MC33560
Figure Card Reader/Writer Application
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MC68HC705C9
RESET 0SC1 OSC2 TCAP TCMP SCLK MOSI MISO PGND PWRON RDYMOD RESET INVOUT ASYCLKIN SYNCLK CRDIO CRDGND
ILIM VBAT CRDC8 CRDCON CRDDET CRDC4 CRDCLK CRDRST CRDVCC
Card Slot
XTAL 4MHz General Purpose diode kOhm C4,C5: MOhm MURATA LQH3C MOhm 7805 regulator Value depending max. card current General Purpose zener diode Card connector
VBAT
MC33560
Card Detect
VBAT
reset
PGND PWRON RDYMOD RESET INVOUT ASYCLKIN SYNCLK CRDIO CRDGND ILIM VBAT CRDC8 CRDCON CRDDET CRDC4 CRDCLK CRDRST CRDVCC
MC33560
Figure Multi Slot Card Reader/Writer Application
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MC68HC705
VBAT
MC33560
RESET 0SC1 OSC2 TCAP TCMP SCLK MOSI MISO
Card Detect
PGND PWRON RDYMOD RESET INVOUT ASYCLKIN SYNCLK CRDIO CRDGND
ILIM VBAT CRDC8 CRDCON CRDDET CRDC4 CRDCLK CRDRST CRDVCC
MC33560
ORDERING INFORMATION
Device MC33560DTB MC33560DTBR2 MC33560DTBR2G MC33560DW MC33560DWR2 MC33560DWR2G Package TSSOP-24 TSSOP-24 TSSOP-24 (Pb-Free) SO-24 SO-24 SO-24 (Pb-Free) Shipping Units Rail 2500 Tape Reel 2500 Tape Reel Units Rail 1000 Tape Reel 1000 Tape Reel
information tape reel specifications, including part orientation tape sizes, please refer Tape Reel Packaging Specifications Brochure, BRD8011/D.
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MC33560
PACKAGE DIMENSIONS
SO-24L SUFFIX PLASTIC PACKAGE CASE 751E-04 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSIONS INCLUDE MOLD PROTRUSION. MAXIMUM MOLD PROTRUSION 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.13 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. MILLIMETERS 15.25 15.54 7.40 7.60 2.35 2.65 0.35 0.49 0.41 0.90 1.27 0.23 0.32 0.13 0.29 10.05 10.55 0.25 0.75 INCHES 0.601 0.612 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 0.009 0.013 0.005 0.011 0.395 0.415 0.010 0.029
0.010 (0.25)
0.010 (0.25)
SEATING PLANE
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MC33560
PACKAGE DIMENSIONS
TSSOP-24 SUFFIX PLASTIC PACKAGE CASE 948K-01 ISSUE
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982. CONTROLLING DIMENSION: MILLIMETER. DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH GATE BURRS SHALL EXCEED 0.15 (0.006) SIDE. DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSION. INTERLEAD FLASH PROTRUSION SHALL EXCEED 0.25 (0.010) SIDE. DIMENSION DOES INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL 0.08 (0.003) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION. TERMINAL NUMBERS SHOWN REFERENCE ONLY. DIMENSION DETERMINED DATUM PLANE -W-. MILLIMETERS 7.70 7.90 5.50 5.70 1.20 0.05 0.15 0.50 0.75 0.65 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 7.60 INCHES 0.303 0.311 0.216 0.224 0.047 0.002 0.006 0.020 0.030 0.026 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.299
0.10 (0.004) 0.15 (0.006)
IDENT.
0.15 (0.006)
0.10 (0.004) SEATING
PLANE
DETAIL
0.25 (0.010)
DETAIL
SECTION
Semiconductor registered trademarks Semiconductor Components Industries, (SCILLC). SCILLC reserves right make changes without further notice products herein. SCILLC makes warranty, representation guarantee regarding suitability products particular purpose, does SCILLC assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential incidental damages. "Typical" parameters which provided SCILLC data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. SCILLC does convey license under patent rights rights others. SCILLC products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure SCILLC product could create situation where personal injury death occur. Should Buyer purchase SCILLC products such unintended unauthorized application, Buyer shall indemnify hold SCILLC officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that SCILLC negligent regarding design manufacture part. SCILLC Equal Opportunity/Affirmative Action Employer. This literature subject applicable copyright laws resale manner.
PUBLICATION ORDERING INFORMATION
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MC33560/D
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