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74HC74 Dual D Flip-Flop with Set and Reset

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74HC74 Dual D Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are compatible with standard CMOS outputs with pullup resistors, they are compatible with LSTTL outputs. This device consists of two D flip-flops with individual Set, Reset, and Clock inputs. Information at a D-input is transferred to the corresponding Q output on the next positive going edge of the clock input. Both Q and Q outputs are available from each flip-flop. The Set and Reset inputs are asynchronous.
Features
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14 SOIC-14 D SUFFIX CASE 751A 1 HC74G AWLYWW
14 14 1 TSSOP-14 DT SUFFIX CASE 948G 1 HC 74 ALYW G G
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet.
February, 2007 - Rev. 0
Publication Order Number: 74HC74 / D
74HC74
PIN ASSIGNMENT
RESET 1 DATA 1 CLOCK 1 SET 1 Q1 Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC RESET 2 DATA 2 CLOCK 2 SET 2 Q2 Q2 RESET 2 DATA 2 CLOCK 2 SET 2 RESET 1 DATA 1 CLOCK 1 SET 1
LOGIC DIAGRAM
FUNCTION TABLE
Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously.
MAXIMUM RATINGS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
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74HC74
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Maximum Low-Level Input Voltage
Minimum High-Level Output Voltage
Maximum Low-Level Output Voltage
Iin ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129 / D).
tPLH, tPHL
Maximum Propagation Delay, Clock to Q or Q (Figures 1 and 4)
tPLH, tPHL
Maximum Propagation Delay, Set or Reset to Q or Q (Figures 2 and 4)
tTLH, tTHL
Maximum Output Transition Time, Any Output (Figures 1 and 4)
Maximum Input Capacitance
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74HC74
Minimum Hold Time, Clock to Data (Figure 3)
Minimum Recovery Time, Set or Reset Inactive to Clock (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Pulse Width, Set or Reset (Figure 2)
tr, tf
Maximum Input Rise and Fall Times (Figures 1, 2, 3)
ORDERING INFORMATION
Device 74HC74D 74HC74DG 74HC74DR2 74HC74DR2G 74HC74DTR2 74HC74DTR2G Package SOIC-14 SOIC-14 (Pb-Free) SOIC-14 SOIC-14 (Pb-Free) TSSOP-14 TSSOP-14 2500 / Tape & Reel 55 Units / Rail Shipping
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011 / D. This package is inherently Pb-Free.
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74HC74
SWITCHING WAVEFORMS
VCC GND
Figure 1.
Figure 2.
TEST POINT VCC GND VCC GND Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT C L
CLOCK
Figure 3.
Figure 4.
CLOCK
6, 8 Q 1, 13 RESET
Figure 5. EXPANDED LOGIC DIAGRAM
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74HC74
PACKAGE DIMENSIONS
SOIC-14 CASE 751A-03 ISSUE H
P 7 PL 0.25 (0.010)
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
SEATING PLANE
D 14 PL 0.25 (0.010)
SOLDERING FOOTPRINT
1.27 PITCH
DIMENSIONS: MILLIMETERS
For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM / D.
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74HC74
PACKAGE DIMENSIONS
TSSOP-14 CASE 948G-01 ISSUE B
14X K REF
0.10 (0.004) 0.15 (0.006) T U
0.25 (0.010) M
PIN 1 IDENT. 1 7
0.15 (0.006) T U
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
DETAIL E
SOLDERING FOOTPRINT
For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM / D.
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0.65 PITCH
DIMENSIONS: MILLIMETERS
74HC74
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA / Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA / Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA / Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com / orderlit For additional information, please contact your local Sales Representative
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74HC74 / D