The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

Single-chip 16-bit/32-bit micro; flash, ethernet, CAN, ISP/IAP, device


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



LPC2458
Single-chip 16-bit/32-bit micro; flash, ethernet, CAN, ISP/IAP, device/host/OTG, external memory interface
Rev. July 2007 Preliminary data sheet
Semiconductors designed LPC2458 microcontroller around 16-bit/32-bit ARM7TDMI-S core with real-time debug interfaces that include both JTAG embedded trace. LPC2458 on-chip high-speed flash memory. This flash memory includes special 128-bit wide memory interface accelerator architecture that enables execute sequential instructions from flash memory maximum system clock rate. This feature available only LPC2000 microcontroller family products. LPC2458 execute both 32-bit 16-bit Thumb instructions. Support instruction sets means engineers choose optimize their application either performance code size sub-routine level. When core executes instructions Thumb state reduce code size more than with only small loss performance while executing instructions state maximizes core performance. LPC2458 microcontroller ideal multi-purpose communication applications. incorporates 10/100 Ethernet Media Access Controller (MAC), full-speed Device/Host/OTG Controller with endpoint RAM, four UARTs, Controller Area Network (CAN) channels, interface, Synchronous Serial Ports (SSP), three interfaces, interface. Supporting this collection serial communications interfaces following feature components; on-chip internal precision oscillator, total consisting local SRAM, SRAM Ethernet, SRAM general purpose DMA, battery powered SRAM, External Memory Controller (EMC). These features make this device optimally suited communication gateways protocol converters. Complementing many serial communication controllers, versatile clocking capabilities, memory features various 32-bit timers, improved 10-bit ADC, 10-bit DAC, units, four external interrupt pins, fast GPIO lines. LPC2458 connects GPIO pins hardware based Vector Interrupt Controller (VIC) that means these external inputs generate edge-triggered interrupts. these features make LPC2458 particularly suitable industrial control medical systems.
Features
ARM7TDMI-S processor, running MHz. on-chip flash program memory with In-System Programming (ISP) In-Application Programming (IAP) capabilities. Flash program memory local high performance access. on-chip SRAM includes: SRAM local high performance access. SRAM Ethernet interface. also used general purpose SRAM.
Semiconductors
LPC2458
Fast communication chip
SRAM general purpose also accessible USB. SRAM data storage powered from Real-Time Clock (RTC) power domain. Dual Advanced High-performance (AHB) system allows simultaneous Ethernet DMA, DMA, program execution from on-chip flash with contention. provides support asynchronous static memory devices such RAM, flash, well dynamic memories such Single Data Rate SDRAM. Advanced Vectored Interrupt Controller (VIC), supporting vectored interrupts. General Purpose controller (GPDMA) that used with SSP, I2S, SD/MM interface well memory-to-memory transfers. Serial Interfaces: Ethernet with MII/RMII interface associated controller. These functions reside independent bus. full-speed dual port Device/Host/OTG Controller with on-chip associated controller. Four UARTs with fractional baud rate generation, with modem control I/O, with IrDA support, with FIFO. controller with channels. controller. controllers, with FIFO multi-protocol capabilities. alternate port, sharing interrupt. SSPs used with GPDMA controller. Three I2C-bus interfaces (one with open-drain with standard port pins). (Inter-IC Sound) interface digital audio input output. used with GPDMA. Other peripherals: SD/MMC memory card interface. General purpose pins with configurable pull-up/down resistors. 10-bit with input multiplexing among pins. 10-bit DAC. Four general purpose timers/counters with capture inputs compare outputs. Each timer block external count input. PWM/timer blocks with support three-phase motor control. Each external count inputs. with separate power domain, clock source oscillator clock. SRAM powered from power pin, allowing data stored when rest chip powered off. WatchDog Timer (WDT). clocked from internal oscillator, oscillator, clock. Standard test/debug interface compatibility with existing tools. Emulation trace module supports real-time trace. Single power supply (3.0 Three reduced power modes: idle, sleep, power-down. Four external interrupt inputs configurable edge/level sensitive. pins PORT0 PORT2 used edge sensitive interrupt sources. Processor wake-up from Power-down mode interrupt able operate during Power-down mode (includes external interrupts, interrupt, activity, Ethernet wake-up interrupt, activity, PORT0/2 interrupt).
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
independent power domains allow fine tuning power consumption based needed features. Each peripheral clock divider further power saving. These dividers help reducing active power Brownout detect with separate thresholds interrupt forced reset. On-chip power-on reset. On-chip crystal oscillator with operating range MHz. internal oscillator trimmed accuracy that optionally used system clock. When used clock, does allow run. On-chip allows operation maximum rate without need high frequency crystal. from main oscillator, internal oscillator, oscillator. Boundary scan simplified board testing. Versatile function selections allow more possibilities using on-chip peripheral functions.
Applications
Industrial control Medical systems Protocol converter Communications
Ordering information
Table Ordering information Package Name Description Version Type number
LPC2458FET180 TFBGA180 plastic thin fine-pitch ball grid array package; balls; body SOT570-2
Ordering options
Table Ordering options Flash (kB) Local SRAM (kB) Ethernet buffer External Ethernet OTG/ OHC/ FIFO channels channels channels Temp range Type number
GP/USB
LPC2458FET180
Full 32-bit
Total
MII/ RMII
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Block diagram
XTAL1 VDD(3V3) XTAL2 VDDA VDD(1V8) RESET
trace signals
TRST EXTIN0 DBGEN
TEST/DEBUG INTERFACE
EMULATION TRACE MODULE
LPC2458
SRAM
FLASH
system clock
SYSTEM FUNCTIONS INTERNAL OSCILLATOR
VREF VSSA, VDD(DCDC)(3V3)
HIGH-SPEED GPI/O PINS TOTAL
INTERNAL CONTROLLERS SRAM FLASH
ARM7TDMI-S
SRAM
EXTERNAL MEMORY CONTROLLER AHB1
D[15:0] A[19:0] control lines
AHB2
BRIDGE
BRIDGE DEVICE/ HOST/OTG WITH CONTROLLER I2SRX_CLK I2STX_CLK I2SRX_WS I2STX_WS I2SRX_SDA I2STX_SDA SCK, SCK0 MOSI, MOSI0 MISO, MISO0 SSEL, SSEL1 SCK1 MOSI1 MIS01 SSEL1 MCICLK, MCIPWR MCICMD, MCIDAT[3:0] TXD0, TXD2, TXD3 RXD0, RXD2, RXD3 TXD1 RXD1 DTR1, RTS1 DSR1, CTS1, DCD1, CAN1, CAN2 RD1, TD1, SCL0, SCL1, SCL2 SDA0, SDA1, SDA2 VBUS port1 port2
MII/RMII
ETHERNET WITH
SRAM
MASTER SLAVE PORT BRIDGE PORT BRIDGE
EINT3 EINT0 CAP0/CAP1/ CAP2/CAP3 MAT2, MAT3, MAT1/MAT0 PWM0, PWM1 PCAP0, PCAP1
EXTERNAL INTERRUPTS CAPTURE/COMPARE TIMER0/TIMER1/ TIMER2/TIMER3 INTERFACE
SPI, SSP0 INTERFACE PWM0, PWM1
LEGACY GPI/O PINS TOTAL
SSP1 INTERFACE
CONVERTER
SD/MMC CARD INTERFACE
AOUT VBAT power domain RTCX1 RTCX2 ALARM
CONVERTER
UART0, UART2, UART3
BATTERY UART1
OSCILLATOR
REALTIME CLOCK
WATCHDOG TIMER I2C0, I2C1, I2C2 SYSTEM CONTROL
002aad093
LPC2458 block diagram
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Pinning information
Pinning
ball index area
LPC2458
002aad094
Transparent view
LPC2458 pinning TFBGA180 package Table P3[12]/D12 P1[1]/ENET_TXD1 P3[2]/D2 P3[8]/D8 P0[3]/RXD0 P1[10]/ENET_RXD1 P3[9]/D9 P1[15]/ ENET_REF_CLK/ ENET_RX_CLK P1[11]/ENET_RXD2/ MCIDAT2/PWM0[6] allocation table Symbol Symbol Symbol
Symbol
P1[3]/ENET_TXD3/ MCICMD/PWM0[2] P0[9]/I2STX_SDA/ MOSI1/MAT2[3] P1[0]/ENET_TXD0 P4[29]/BLS3/ MAT2[1]/RXD3 P1[5]/ENET_TX_ER/ MCIPWR/PWM0[3] P3[13]/D13 VDD(3V3) P1[17]/ENET_MDIO
VSSCORE P1[12]/ENET_RXD3/ MCIDAT3/PCAP0[0] P3[11]/D11 P1[8]/ENET_CRS_DV/ ENET_CRS P1[6]/ENET_TX_CLK/ MCIDAT0/PWM0[4] P4[13]/A13
P0[4]/I2SRX_CLK/RD2/ CAP2[0]
P3[10]/D10 P1[2]/ENET_TXD2/ MCICLK/PWM0[1] P0[5]/I2SRX_WS/TD2/ CAP2[1] VSSIO P1[16]/ENET_MDC P0[7]/I2STX_CLK/SCK1 /MAT2[1]
P1[4]/ENET_TX_EN P4[15]/A15 P4[30]/CS0 VSSIO RTCK P4[24]/OE P0[8]/I2STX_WS/ MISO1/MAT2[2]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table
allocation table .continued Symbol P2[1]/PWM1[2]/RXD1/ PIPESTAT0 P3[0]/D0 P4[28]/BLS2/ MAT2[0]/TXD3 P1[13]/ENET_RX_DV VDD(3V3) P3[1]/D1 VDD(3V3) P2[4]/PWM1[5]/ DSR1/TRACESYNC VDDA Symbol Symbol
Symbol P1[7]/ENET_COL/ MCIDAT1/PWM0[5] P0[26]/AD0[3]/ AOUT/RXD3 P0[2]/TXD0 P4[25]/WE VSSIO P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] DBGEN VDD(DCDC)(3V3) P2[3]/PWM1[4]/ DCD1/PIPESTAT2 P3[14]/D14 P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0]
P3[4]/D4 P1[9]/ENET_RXD0 P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] P3[5]/D5 P4[31]/CS1 P2[2]/PWM1[3]/ CTS1/PIPESTAT1 TRST P1[14]/ENET_RX_ER P2[0]/PWM1[1]/TXD1/ TRACECLK P0[25]/AD0[2]/ I2SRX_SDA/TXD3 P4[14]/A14 VDD(3V3)
P2[6]/PCAP1[0]/ RI1/TRACEPKT1 VDD(DCDC)(3V3) P3[3]/D3 P4[12]/A12 P4[27]/BLS1 P4[11]/A11 VSSA P2[5]/PWM1[6]/ DTR1/TRACEPKT0 P3[6]/D6
VSSIO P2[8]/TD2/ TXD2/TRACEPKT3 RSTOUT P4[5]/A5 VREF P2[7]/RD2/ RTS1/TRACEPKT2 P3[7]/D7 P4[10]/A10 P3[15]/D15
ALARM P2[9]/ USB_CONNECT1/ RXD2/EXTIN0 VSSCORE P4[9]/A9 VSSIO
P0[15]/TXD1/ SCK0/SCK RESET
P0[16]/RXD1/ SSEL0/SSEL RTCX1
RTCX2 P0[12]/USB_PPWR2/ MISO1/AD0[6]
P0[13]/USB_UP_LED2/ MOSI1/AD0[7]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table
allocation table .continued Symbol P0[19]/DSR1/ MCICLK/SDA1 VDD(3V3) Symbol P4[8]/A8 Symbol P0[17]/CTS1/ MISO0/MISO
Symbol
P0[18]/DCD1/ MOSI0/MOSI VBAT P0[29]/USB_D+1 P4[3]/A3 P4[26]/BLS0
P1[31]/USB_OVRCR2/ SCK1/AD0[5] P1[20]/USB_TX_DP1/ PWM1[2]/SCK0 P4[6]/A6 P0[20]/DTR1/ MCICMD/SCL1 XTAL1 P4[0]/A0 P0[10]/TXD2/SDA2/ MAT3[0] P0[22]/RTS1/ MCIDAT0/TD1 P2[28]/DQMOUT0 P1[22]/USB_RCV1/ USB_PWRD1/MAT1[0] P0[0]/RD1/TXD3/SDA1 P4[19]/A19 USB_D-2 P1[21]/USB_TX_DM1/ PWM1[3]/SSEL0 P1[29]/USB_SDA1/ PCAP1[1]/MAT0[1] P2[12]/EINT2/ MCIDAT2/I2STX_WS P2[25]/CKEOUT1 P2[20]/DYCS0 P1[28]/USB_SCL1/ PCAP1[0]/MAT0[0] P4[18]/A18 P1[30]/USB_PWRD2/ VBUS/AD0[4] P3[26]/D26/ MAT0[1]/PWM1[3] P0[21]/RI1/ MCIPWR/RD1 XTAL2 VDD(3V3) P4[7]/A7
P2[29]/DQMOUT1 P0[27]/SDA0 VDD(3V3) VSSCORE P1[18]/USB_UP_LED1/ PWM1[1]/CAP1[0] VSSIO VSSIO P1[25]/USB_LS1/ USB_HSTEN1/MAT1[1] VDD(3V3)
P0[28]/SCL0 P0[14]/USB_HSTEN2/ USB_CONNECT2/ SSEL1 P3[25]/D25/ MAT0[0]/PWM1[2] P4[1]/A1 P3[23]/D23/ CAP0[0]/PCAP1[0] P4[2]/A2
P1[27]/USB_INT1/ USB_OVRCR1/CAP0[1] P2[10]/EINT0 P0[31]/USB_D+2 P2[19]/CLKOUT1 VDD(DCDC)(3V3) P4[17]/A17
P2[13]/EINT3/ MCIDAT3/I2STX_SDA P3[24]/D24/ CAP0[1]/PWM1[1] P1[23]/USB_RX_DP1/ PWM1[4]/MISO0 P0[1]/TD1/RXD3/SCL1
P2[11]/EINT1/ MCIDAT1/I2STX_CLK P0[30]/USB_D-1 P2[21]/DYCS1 P4[16]/A16
P2[24]/CKEOUT0 P1[19]/USB_TX_E1/ USB_PPWR1/CAP1[1] P2[16]/CAS P4[4]/A4 P2[18]/CLKOUT0 P1[24]/USB_RX_DM1/ PWM1[5]/MOSI0 P2[17]/RAS VSSIO P1[26]/USB_SSPND1/ PWM1[6]/CAP0[0] P0[11]/RXD2/SCL2/ MAT3[1] B.V. 2007. rights reserved.
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
description
Table Symbol P0[0] P0[31] description Ball Type Description Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P0[0] General purpose digital input/output pin. CAN1 receiver input. TXD3 Transmitter output UART3. SDA1 I2C1 data input/output (this open-drain pin). P0[1] General purpose digital input/output pin. CAN1 transmitter output. RXD3 Receiver input UART3. SCL1 I2C1 clock input/output (this open-drain pin). P0[2] General purpose digital input/output pin. TXD0 Transmitter output UART0. P0[3] General purpose digital input/output pin. RXD0 Receiver input UART0. P0[4] General purpose digital input/output pin. I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAN2 receiver input. CAP2[0] Capture input Timer channel P0[5] General purpose digital input/output pin. I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAN2 transmitter output. CAP2[1] Capture input Timer channel P0[6] General purpose digital input/output pin. I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. SSEL1 Slave Select SSP1. MAT2[0] Match output Timer channel P0[7] General purpose digital input/output pin. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. SCK1 Serial Clock SSP1. MAT2[1] Match output Timer channel P0[8] General purpose digital input/output pin. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. MISO1 Master Slave SSP1. MAT2[2] Match output Timer channel
P0[0]/RD1/ TXD3/SDA1
M10[1]
P0[1]/TD1/RXD3/ SCL1
N11[1]
P0[2]/TXD0 P0[3]/RXD0 P0[4]/ I2SRX_CLK/ RD2/CAP2[0]
D5[1] A3[1] A11[1]
P0[5]/ I2SRX_WS/ TD2/CAP2[1]
B11[1]
P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0]
D11[1]
P0[7]/ I2STX_CLK/ SCK1/MAT2[1]
B12[1]
P0[8]/ I2STX_WS/ MISO1/MAT2[2]
C12[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball A13[1] Type Description P0[9] General purpose digital input/output pin. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. MOSI1 Master Slave SSP1. MAT2[3] Match output Timer channel P0[10] General purpose digital input/output pin. TXD2 Transmitter output UART2. SDA2 I2C2 data input/output (this open-drain pin). MAT3[0] Match output Timer channel P0[11] General purpose digital input/output pin. RXD2 Receiver input UART2. SCL2 I2C2 clock input/output (this open-drain pin). MAT3[1] Match output Timer channel P0[12] General purpose digital input/output pin. USB_PPWR2 Port Power enable signal port MISO1 Master Slave SSP1. AD0[6] converter input P0[13] General purpose digital input/output pin. USB_UP_LED2 port GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. MOSI1 Master Slave SSP1. AD0[7] converter input P0[14] General purpose digital input/output pin. USB_HSTEN2 Host Enabled status port USB_CONNECT2 SoftConnect control port Signal used switch external resistor under software control. Used with SoftConnect feature. SSEL1 Slave Select SSP1. P0[15] General purpose digital input/output pin. TXD1 Transmitter output UART1. SCK0 Serial clock SSP0. Serial clock SPI. [16] General purpose digital input/output pin. RXD1 Receiver input UART1. SSEL0 Slave Select SSP0. SSEL Slave Select SPI. P0[17] General purpose digital input/output pin. CTS1 Clear Send input UART1. MISO0 Master Slave SSP0. MISO Master Slave SPI.
P0[9]/ I2STX_SDA/ MOSI1/MAT2[3]
P0[10]/TXD2/ SDA2/MAT3[0]
L10[1]
P0[11]/RXD2/ SCL2/MAT3[1]
P12[1]
P0[12]/ USB_PPWR2/ MISO1/AD0[6]
J4[2]
P0[13]/ USB_UP_LED2/ MOSI1/AD0[7]
J5[2]
M5[1] P0[14]/ USB_HSTEN2/ USB_CONNECT2/S SEL1
P0[15]/TXD1/ SCK0/SCK H13[1] P0[16]/RXD1/ SSEL0/SSEL H14[1] P0[17]/CTS1/ MISO0/MISO J12[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball J13[1] Type Description P0[18] General purpose digital input/output pin. DCD1 Data Carrier Detect input UART1. MOSI0 Master Slave SSP0. MOSI Master Slave SPI. P0[19] General purpose digital input/output pin. DSR1 Data Ready input UART1. MCICLK Clock output line SD/MMC interface. SDA1 I2C1 data input/output (this open-drain pin). P0[20] General purpose digital input/output pin. DTR1 Data Terminal Ready output UART1. MCICMD Command line SD/MMC interface. SCL1 I2C1 clock input/output (this open-drain pin). P0[21] General purpose digital input/output pin. Ring Indicator input UART1. MCIPWR Power Supply Enable external SD/MMC power supply. CAN1 receiver input. P0[22] General purpose digital input/output pin. RTS1 Request Send output UART1. MCIDAT0 Data line SD/MMC interface. CAN1 transmitter output. P0[23] General purpose digital input/output pin. AD0[0] converter input I2SRX_CLK Receive Clock. driven master received slave. Corresponds signal I2S-bus specification. CAP3[0] Capture input Timer channel P0[24] General purpose digital input/output pin. AD0[1] converter input I2SRX_WS Receive Word Select. driven master received slave. Corresponds signal I2S-bus specification. CAP3[1] Capture input Timer channel P0[25] General purpose digital input/output pin. AD0[2] converter input I2SRX_SDA Receive data. driven transmitter read receiver. Corresponds signal I2S-bus specification. TXD3 Transmitter output UART3. P0[26] General purpose digital input/output pin. AD0[3] converter input AOUT converter output. RXD3 Receiver input UART3. P0[27] General purpose digital input/output pin. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance).
P0[18]/DCD1/ MOSI0/MOSI
P0[19]/DSR1/ MCICLK/SDA1
J10[1]
P0[20]/DTR1/ MCICMD/SCL1
K14[1]
P0[21]/RI1/ MCIPWR/RD1
K11[1]
P0[22]/RTS1/ MCIDAT0/TD1
L14[1]
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
F5[2]
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
E1[2]
P0[25]/AD0[2]/ I2SRX_SDA/ TXD3
E4[2]
P0[26]/AD0[3]/ AOUT/RXD3
D1[2][3]
P0[27]/SDA0
L3[4]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball M1[4] K5[5] N4[5] N1[5] Type Description P0[28] General purpose digital input/output pin. SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29] General purpose digital input/output pin. USB_D+1 port bidirectional line. P0[30] General purpose digital input/output pin. USB_D-1 port 1bidirectional line. P0[31] General purpose digital input/output pin. USB_D+2 port bidirectional line. Port Port port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P1[0] General purpose digital input/output pin. ENET_TXD0 Ethernet transmit data (RMII/MII interface). P1[1] General purpose digital input/output pin. ENET_TXD1 Ethernet transmit data (RMII/MII interface). P1[2] General purpose digital input/output pin. ENET_TXD2 Ethernet transmit data (MII interface). MCICLK Clock output line SD/MMC interface. PWM0[1] Pulse Width Modulator output P1[3] General purpose digital input/output pin. ENET_TXD3 Ethernet transmit data (MII interface). MCICMD Command line SD/MMC interface. PWM0[2] Pulse Width Modulator output P1[4] General purpose digital input/output pin. ENET_TX_EN Ethernet transmit data enable (RMII/MII interface). P1[5] General purpose digital input/output pin. ENET_TX_ER Ethernet Trensmit Error (MII interface). MCIPWR Power Supply Enable external SD/MMC power supply. PWM0[3] Pulse Width Modulator output P1[6] General purpose digital input/output pin. ENET_TX_CLK Ethernet Transmit Clock (MII interface). MCIDAT0 Data line SD/MMC interface. PWM0[4] Pulse Width Modulator output P1[7] General purpose digital input/output pin. ENET_COL Ethernet Collision detect (MII interface). MCIDAT1 Data line SD/MMC interface. PWM0[5] Pulse Width Modulator output P1[8] General purpose digital input/output pin. ENET_CRS_DV/ENET_CRS Ethernet Carrier Sense/Data Valid (RMII interface)/ Ethernet Carrier Sense (MII interface). P1[9] General purpose digital input/output pin. ENET_RXD0 Ethernet receive data (RMII/MII interface).
B.V. 2007. rights reserved.
P0[28]/SCL0 P0[29]/USB_D+1 P0[30]/USB_D-1 P0[31]/USB_D+2 P1[0] P1[31]
P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[2]/ ENET_TXD2/ MCICLK/ PWM0[1] P1[3]/ ENET_TXD3/ MCICMD/ PWM0[2] P1[4]/ ENET_TX_EN P1[5]/ ENET_TX_ER/ MCIPWR/ PWM0[3] P1[6]/ ENET_TX_CLK/ MCIDAT0/ PWM0[4] P1[7]/ ENET_COL/ MCIDAT1/ PWM0[5] P1[8]/ ENET_CRS_DV/ ENET_CRS P1[9]/ ENET_RXD0
LPC2468_1
B5[1] A5[1] B7[1]
A9[1]
C6[1] B13[1]
B10[1]
C13[1]
B6[1]
D7[1]
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball A7[1] A12[1] Type A14[1] D14[1] D8[1] A8[1] B8[1] C9[1] L5[1] Description P1[10] General purpose digital input/output pin. ENET_RXD1 Ethernet receive data (RMII/MII interface). P1[11] General purpose digital input/output pin. ENET_RXD2 Ethernet Receive Data (MII interface). MCIDAT2 Data line SD/MMC interface. PWM0[6] Pulse Width Modulator output P1[12] General purpose digital input/output pin. ENET_RXD3 Ethernet Receive Data (MII interface). MCIDAT3 Data line SD/MMC interface. PCAP0[0] Capture input PWM0, channel P1[13] General purpose digital input/output pin. ENET_RX_DV Ethernet Receive Data Valid (MII interface). P1[14] General purpose digital input/output pin. ENET_RX_ER Ethernet receive error (RMII/MII interface). P1[15] General purpose digital input/output pin. ENET_REF_CLK/ENET_RX_CLK Ethernet Reference Clock (RMII interface)/ Ethernet Receive Clock (MII interface). P1[16] General purpose digital input/output pin. ENET_MDC Ethernet MIIM clock. P1[17] General purpose digital input/output pin. ENET_MDIO Ethernet data input output. P1[18] General purpose digital input/output pin. USB_UP_LED1 port GoodLink indicator. when device configured (non-control endpoints enabled). HIGH when device configured during global suspend. PWM1[1] Pulse Width Modulator channel output. CAP1[0] Capture input Timer channel P1[19] General purpose digital input/output pin. USB_TX_E1 Transmit Enable signal port (OTG transceiver). USB_PPWR1 Port Power enable signal port CAP1[1] Capture input Timer channel P1[20] General purpose digital input/output pin. USB_TX_DP1 transmit data port (OTG transceiver). PWM1[2] Pulse Width Modulator channel output. SCK0 Serial clock SSP0. P1[21] General purpose digital input/output pin. USB_TX_DM1 transmit data port (OTG transceiver). PWM1[3] Pulse Width Modulator channel output. SSEL0 Slave Select SSP0.
P1[10]/ ENET_RXD1 P1[11]/ ENET_RXD2/ MCIDAT2/ PWM0[6] P1[12]/ ENET_RXD3/ MCIDAT3/ PCAP0[0] P1[13]/ ENET_RX_DV P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK/E NET_RX_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED1/ PWM1[1]/ CAP1[0]
P1[19]/ USB_TX_E1/ USB_PPWR1/ CAP1[1] P1[20]/ USB_TX_DP1/ PWM1[2]/SCK0 P5[1] K6[1] P1[21]/ USB_TX_DM1/ PWM1[3]/SSEL0 N6[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball M6[1] Type N7[1] P7[1] L7[1] P8[1] M9[1] P10[1] N10[1] K3[2] Description P1[22] General purpose digital input/output pin. USB_RCV1 Differential receive data port (OTG transceiver). USB_PWRD1 Power Status port (host power switch). MAT1[0] Match output Timer channel P1[23] General purpose digital input/output pin. USB_RX_DP1 receive data port (OTG transceiver). PWM1[4] Pulse Width Modulator channel output. MISO0 Master Slave SSP0. P1[24] General purpose digital input/output pin. USB_RX_DM1 receive data port (OTG transceiver). PWM1[5] Pulse Width Modulator channel output. MOSI0 Master Slave SSP0. P1[25] General purpose digital input/output pin. USB_LS1 Low-speed status port (OTG transceiver). USB_HSTEN1 Host Enabled status port MAT1[1] Match output Timer channel P1[26] General purpose digital input/output pin. USB_SSPND1 port Suspend status (OTG transciever). PWM1[6] Pulse Width Modulator channel output. CAP0[0] Capture input Timer channel P1[27] General purpose digital input/output pin. USB_INT1 port interrupt (OTG transceiver). USB_OVRCR1 port Over-Current status. CAP0[1] Capture input Timer channel P1[28] General purpose digital input/output pin. USB_SCL1 port serial clock (OTG transciever). PCAP1[0] Capture input PWM1, channel MAT0[0] Match output Timer channel P1[29] General purpose digital input/output pin. USB_SDA1 port serial data (OTG transciever). PCAP1[1] Capture input PWM1, channel MAT0[1] Match output Timer channel P1[30] General purpose digital input/output pin. USB_PWRD2 Power Status port VBUS Indicates presence power. Note: This signal must HIGH reset occur. AD0[4] converter input P1[31] General purpose digital input/output pin. USB_OVRCR2 Over-Current status port SCK1 Serial Clock SSP1. AD0[5] converter input
B.V. 2007. rights reserved.
P1[22]/ USB_RCV1/ USB_PWRD1/ MAT1[0] P1[23]/ USB_RX_DP1/ PWM1[4]/MISO0
P1[24]/ USB_RX_DM1/ PWM1[5]/MOSI0
P1[25]/ USB_LS1/ USB_HSTEN1/ MAT1[1] P1[26]/ USB_SSPND1/ PWM1[6]/ CAP0[0] P1[27]/ USB_INT1/ USB_OVRCR1/ CAP0[1] P1[28]/ USB_SCL1/ PCAP1[0]/ MAT0[0] P1[29]/ USB_SDA1/ PCAP1[1]/ MAT0[1] P1[30]/ USB_PWRD2/ VBUS/AD0[4]
P1[31]/ USB_OVRCR2/ SCK1/AD0[5]
K2[2]
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball Type Description Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P2[0] General purpose digital input/output pin. PWM1[1] Pulse Width Modulator channel output. TXD1 Transmitter output UART1. TRACECLK Trace Clock. P2[1] General purpose digital input/output pin. PWM1[2] Pulse Width Modulator channel output. RXD1 Receiver input UART1. PIPESTAT0 Pipeline Status, P2[2] General purpose digital input/output pin. PWM1[3] Pulse Width Modulator channel output. CTS1 Clear Send input UART1. PIPESTAT1 Pipeline Status, P2[3] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator channel output. DCD1 Data Carrier Detect input UART1. PIPESTAT2 Pipeline Status, P2[4] General purpose digital input/output pin. PWM1[5] Pulse Width Modulator channel output. DSR1 Data Ready input UART1. TRACESYNC Trace Synchronization. P2[5] General purpose digital input/output pin. PWM1[6] Pulse Width Modulator channel output. DTR1 Data Terminal Ready output UART1. TRACEPKT0 Trace Packet, P2[6] General purpose digital input/output pin. PCAP1[0] Capture input PWM1, channel Ring Indicator input UART1. TRACEPKT1 Trace Packet, P2[7] General purpose digital input/output pin. CAN2 receiver input. RTS1 Request Send output UART1. TRACEPKT2 Trace Packet, P2[8] General purpose digital input/output pin. CAN2 transmitter output. TXD2 Transmitter output UART2. TRACEPKT3 Trace Packet,
P2[0] P2[31]
P2[0]/PWM1[1]/ TXD1/ TRACECLK
D12[1]
P2[1]/PWM1[2]/ RXD1/ PIPESTAT0
C14[1]
P2[2]/PWM1[3]/ CTS1/ PIPESTAT1
E11[1]
P2[3]/PWM1[4]/ DCD1/ PIPESTAT2
E13[1]
P2[4]/PWM1[5]/ DSR1/ TRACESYNC
E14[1]
P2[5]/PWM1[6]/ DTR1/ TRACEPKT0
F12[1]
P2[6]/PCAP1[0]/RI1/ F13[1] TRACEPKT1
P2[7]/RD2/ RTS1/ TRACEPKT2
G11[1]
P2[8]/TD2/ TXD2/ TRACEPKT3
G14[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball H11[1] Type Description P2[9] General purpose digital input/output pin. USB_CONNECT1 USB1 SoftConnect control. Signal used switch external resistor under software control. Used with SoftConnect feature. RXD2 Receiver input UART2. EXTIN0 External Trigger Input. P2[10] General purpose digital input/output pin. Note: this while RESET forces on-chip bootloader take over control part after reset. EINT0 External interrupt input. P2[11] General purpose digital input/output pin. EINT1 External interrupt input. MCIDAT1 Data line SD/MMC interface. I2STX_CLK Transmit Clock. driven master received slave. Corresponds signal I2S-bus specification. P2[12] General purpose digital input/output pin. EINT2 External interrupt input. MCIDAT2 Data line SD/MMC interface. I2STX_WS Transmit Word Select. driven master received slave. Corresponds signal I2S-bus specification. P2[13] General purpose digital input/output pin. EINT3 External interrupt input. MCIDAT3 Data line SD/MMC interface. I2STX_SDA Transmit data. driven transmitter read receiver. Corresponds signal I2S-bus specification. P2[16] General purpose digital input/output pin. active SDRAM Column Address Strobe. P2[17] General purpose digital input/output pin. active SDRAM Address Strobe. P2[18] General purpose digital input/output pin. CLKOUT0 SDRAM clock P2[19] General purpose digital input/output pin. CLKOUT1 SDRAM clock P2[20] General purpose digital input/output pin. DYCS0 SDRAM chip select P2[21] General purpose digital input/output pin. DYCS1 SDRAM chip select P2[24] General purpose digital input/output pin. CKEOUT0 SDRAM clock enable P2[25] General purpose digital input/output pin. CKEOUT1 SDRAM clock enable
P2[9]/ USB_CONNECT1/ RXD2/ EXTIN0
P2[10]/EINT0 M13[6]
P2[11]/EINT1/ MCIDAT1/ I2STX_CLK
M12[6]
P2[12]/EINT2/ MCIDAT2/ I2STX_WS
N14[6]
P2[13]/EINT3/ MCIDAT3/ I2STX_SDA
M11[6]
P2[16]/CAS P2[17]/RAS P2[18]/ CLKOUT0 P2[19]/ CLKOUT1 P2[20]/DYCS0 P2[21]/DYCS1 P2[24]/ CKEOUT0 P2[25]/ CKEOUT1
P9[1] P11[1] P3[1] N5[1] P6[1] N8[1] P1[1] P2[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol P2[28]/ DQMOUT0 P2[29]/ DQMOUT1
description .continued Ball M2[1] L1[1] Type Description P2[28] General purpose digital input/output pin. DQMOUT0 Data mask used with SDRAM static devices. P2[29] General purpose digital input/output pin. DQMOUT1 Data mask used with SDRAM static devices. Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P3[0] General purpose digital input/output pin. External memory data line P3[1] General purpose digital input/output pin. External memory data line P3[2] General purpose digital input/output pin. External memory data line P3[3] General purpose digital input/output pin. External memory data line P3[4] General purpose digital input/output pin. External memory data line P3[5] General purpose digital input/output pin. External memory data line P3[6] General purpose digital input/output pin. External memory data line P3[7] General purpose digital input/output pin. External memory data line P3[8] General purpose digital input/output pin. External memory data line P3[9] General purpose digital input/output pin. External memory data line P3[10] General purpose digital input/output pin. External memory data line P3[11] General purpose digital input/output pin. External memory data line P3[12] General purpose digital input/output pin. External memory data line P3[13] General purpose digital input/output pin. External memory data line P3[14] General purpose digital input/output pin. External memory data line P3[15] General purpose digital input/output pin. External memory data line
P3[0] P3[31]
P3[0]/D0 P3[1]/D1 P3[2]/D2 P3[3]/D3 P3[4]/D4 P3[5]/D5 P3[6]/D6 P3[7]/D7 P3[8]/D8 P3[9]/D9 P3[10]/D10 P3[11]/D11 P3[12]/D12 P3[13]/D13 P3[14]/D14 P3[15]/D15
D6[1] E6[1] A2[1] G5[1] D3[1] E3[1] F4[1] G3[1] A6[1] A4[1] B3[1] B2[1] A1[1] C1[1] F1[1] G4[1]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol
description .continued Ball M4[1] Type N3[1] M3[1] K7[1] Description P3[23] General purpose digital input/output pin. External memory data line CAP0[0] Capture input Timer channel PCAP1[0] Capture input PWM1, channel P3[24] General purpose digital input/output pin. External memory data line CAP0[1] Capture input Timer channel PWM1[1] Pulse Width Modulator output P3[25] General purpose digital input/output pin. External memory data line MAT0[0] Match output Timer channel PWM1[2] Pulse Width Modulator output P3[26] General purpose digital input/output pin. External memory data line MAT0[1] Match output Timer channel PWM1[3] Pulse Width Modulator output Port Port 32-bit port with individual direction controls each bit. operation port pins depends upon function selected Connect block. P4[0] ]General purpose digital input/output pin. External memory address line P4[1] General purpose digital input/output pin. External memory address line P4[2] General purpose digital input/output pin. External memory address line P4[3] General purpose digital input/output pin. External memory address line P4[4] General purpose digital input/output pin. External memory address line P4[5] General purpose digital input/output pin. External memory address line P4[6] General purpose digital input/output pin. External memory address line P4[7] General purpose digital input/output pin. External memory address line P4[8] General purpose digital input/output pin. External memory address line P4[9] General purpose digital input/output pin. External memory address line P4[10] General purpose digital input/output pin. External memory address line
B.V. 2007. rights reserved.
P3[23]/D23/ CAP0[0]/ PCAP1[0]
P3[24]/D24/ CAP0[1]/ PWM1[1]
P3[25]/D25/ MAT0[0]/ PWM1[2]
P3[26]/D26/ MAT0[1]/ PWM1[3]
P4[0] P4[31]
P4[0]/A0 P4[1]/A1 P4[2]/A2 P4[3]/A3 P4[4]/A4 P4[5]/A5 P4[6]/A6 P4[7]/A7 P4[8]/A8 P4[9]/A9 P4[10]/A10
L6[1] M7[1] M8[1] K9[1] P13[1] H10[1] K10[1] K12[1] J11[1] H12[1] G12[1]
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol P4[11]/A11 P4[12]/A12 P4[13]/A13 P4[14]/A14 P4[15]/A15 P4[16]/A16 P4[17]/A17 P4[18]/A18 P4[19]/A19 P4[24]/OE P4[25]/WE
description .continued Ball F11[1] F10[1] B14[1] E8[1] C10[1] N12[1] N13[1] P14[1] M14[1] C8[1] D9[1] K13[1] F14[1] D10[1] Type Description P4[11] General purpose digital input/output pin. External memory address line P4[12] General purpose digital input/output pin. External memory address line P4[13] General purpose digital input/output pin. External memory address line P4[14] General purpose digital input/output pin. External memory address line P4[15] General purpose digital input/output pin. External memory address line P4[16] General purpose digital input/output pin. External memory address line P4[17] General purpose digital input/output pin. External memory address line P4[18] General purpose digital input/output pin. External memory address line P4[19] General purpose digital input/output pin. External memory address line P4[24] General purpose digital input/output pin. active Output Enable signal. P4[25] General purpose digital input/output pin. active Write Enable signal. P4[26] General purpose digital input/output pin. BLS0 active Byte Lane select signal P4[27] General purpose digital input/output pin. BLS1 active Byte Lane select signal [28] General purpose digital input/output pin. BLS2 active Byte Lane select signal MAT2[0] Match output Timer channel TXD3 Transmitter output UART3. P4[29] General purpose digital input/output pin. BLS3 active Byte Lane select signal MAT2[1] Match output Timer channel RXD3 Receiver input UART3. P4[30] General purpose digital input/output pin. active Chip Select signal. P4[31] General purpose digital input/output pin. active Chip Select signal. ALARM controlled output. This pin. goes HIGH when alarm generated. USB_D-2 port bidirectional line.
B.V. 2007. rights reserved.
P4[26]/BLS0 P4[27]/BLS1 P4[28]/BLS2/ MAT2[0]/TXD3
P4[29]/BLS3/ MAT2[1]/RXD3
B9[1]
P4[30]/CS0 P4[31]/CS1 ALARM USB_D-2
LPC2468_1
C7[1] E7[1] H5[8]
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Symbol DBGEN TRST RTCK
description .continued Ball E5[1] B1[1] C3[1] C2[1] D4[1] D2[1] C4[1] Type Description DBGEN JTAG interface control signal. Also used boundary scanning. Test Data JTAG interface. Test Data JTAG interface. Test Mode Select JTAG interface. TRST Test Reset JTAG interface. Test Clock JTAG interface. RTCK JTAG interface control signal. Note: this while RESET enables Epins (P2[9:0]) operate Trace port after reset.
RSTOUT RESET
H2[1] J1[7]
RSTOUT this indicates LPC2458 being Reset state. external reset input: this resets device, causing ports peripherals take their default states, processor execution begin address with hysteresis, tolerant. VBAT must powered with RESET detect external signal existence and/or activity.
XTAL1 XTAL2 RTCX1 RTCX2 VSSIO
L2[8] K4[8] J2[8] J3[8]
Input oscillator circuit internal clock generator circuits. Output from oscillator amplifier. Input oscillator circuit. Output from oscillator circuit. ground: reference digital pins.
P4,L9, L13, G13,D13 C11, B4[9] A10[9] F3[10]
VSSCORE VSSA VDD(3V3)
ground: reference core. analog ground: reference. This should nominally same voltage VSS, should isolated minimize noise error. supply voltage: This power supply voltage ports.
E2,L4,K8 ,L11,J14, E12, E10,C5[1
VDD(DCDC)(3V3) VDDA
L12, G10[12] E9[13] F2[14]
Connected pins: These pins must left unconnected (floating). DC-to-DC converter supply voltage: This power supply on-chip DC-to-DC converter. analog supply voltage: This should nominally same voltage VDD(3V3) should isolated minimize noise error. This voltage used power DAC. reference: This should nominally same voltage VDD(3V3) should isolated minimize noise error. level this used reference DAC. RESET power supply: this supplies power peripheral RESET logic.
VREF
G2[14]
VBAT
K1[14]
tolerant providing digital functions with levels hysteresis.
B.V. 2007. rights reserved.
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
tolerant providing digital functions (with levels hysteresis) analog input. When configured input, digital section disabled. tolerant providing digital with levels hysteresis analog output function. When configured output, digital section disabled. Open-drain tolerant digital I2C-bus specification compatible pad. requires external pull-up provide output functionality. When power switched off, this connected I2C-bus floating does disturb lines. provides digital functions. designed accordance with specification, revision (Full-speed Low-speed mode only). tolerant with glitch filter providing digital functions with levels hysteresis. tolerant with glitch filter providing digital function with levels hysteresis. provides special analog functionality. provides special analog functionality.
[10] provides special analog functionality. [11] provides special analog functionality. [12] provides special analog functionality. [13] provides special analog functionality. [14] provides special analog functionality.
Functional description
Architectural overview
LPC2458 microcontroller consists ARM7TDMI-S with emulation support, ARM7 local closely coupled, high-speed access majority on-chip memory, AMBA interfacing high-speed on-chip peripherals external memory, AMBA connection other on-chip peripheral functions. microcontroller permanently configures ARM7TDMI-S processor little-endian byte order. LPC2458 implements buses order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, includes VIC, GPDMA controller, EMC. second AHB, referred AHB2, includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into off-chip memory unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block. peripherals allocated range addresses very memory space. Each peripheral allocated address space within address space. Lower speed peripheral functions connected bus. bridge interfaces bus. peripherals also allocated range addresses, beginning address point. Each peripheral allocated address space within address space. ARM7TDMI-S processor general purpose 32-bit microprocessor, which offers high performance very power consumption. architecture based Reduced Instruction Computer (RISC) principles, instruction related
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
decode mechanism much simpler than those microprogrammed complex instruction computers. This simplicity results high instruction throughput impressive real-time interrupt response from small cost-effective processor core. Pipeline techniques employed that parts processing memory systems operate continuously. Typically, while instruction being executed, successor being decoded, third instruction being fetched from memory. ARM7TDMI-S processor also employs unique architectural strategy known Thumb, which makes ideally suited high-volume applications with memory restrictions, applications where code density issue. idea behind Thumb that super-reduced instruction set. Essentially, ARM7TDMI-S processor instruction sets:
standard 32-bit 16-bit Thumb
Thumb set's 16-bit instruction length allows approach higher density compared standard code while retaining most ARM's performance.
On-chip flash programming memory
LPC2458 incorporates flash memory system. This memory used both code data storage. Programming flash memory accomplished several ways. programmed System serial port (UART0). application program also erase and/or program flash while application running, allowing great degree flexibility data storage field firmware upgrades. flash memory bits wide includes pre-fetching buffering techniques allow operate speeds MHz. LPC2458 provides minimum 100000 write/erase cycles years data retention.
On-chip SRAM
LPC2458 includes SRAM memory reserved processor exclusive use. This used code and/or data storage accessed bits, bits, bits. SRAM block serving buffer Ethernet controller SRAM associated with second used both data code storage, too. Remaining SRAM such FIFO SRAM used data storage only. SRAM battery powered retains content absence main power supply.
Memory
LPC2458 memory incorporates several distinct regions shown Table Figure addition, interrupt vectors remapped allow them reside either flash memory (default), boot ROM, SRAM (see Section 7.26.6).
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
LPC2458 memory usage details Address range details description flash Memory (512 Fast GPIO registers
Table
Address range General
0x0000 0000 On-chip 0x0000 0000 0x0007 FFFF 0x3FFF FFFF non-volatile 0x3FFF C000 0x3FFF FFFF memory Fast 0x4000 0000 On-chip 0x7FFF FFFF 0x4000 0000 0x4000 FFFF 0x7FE0 0000 0x7FE0 3FFF 0x7FD0 0000 0x7FD0 3FFF 0x8000 0000 Off-Chip Memory 0xDFFF FFFF 0x8000 0000 0x80FF FFFF 0x8100 0000 0x81FF FFFF 0x8200 0000 0x82FF FFFF 0x8300 0000 0x83FF FFFF
Ethernet Static memory bank Static memory bank Static memory bank Static memory bank
Four static memory banks, each
Four dynamic memory banks, each 0xA000 0000 0xAFFF FFFF 0xB000 0000 0xBFFF FFFF 0xC000 0000 0xCFFF FFFF 0xD000 0000 0xDFFF FFFF 0xE000 0000 Peripherals 0xEFFF FFFF 0xF000 0000 peripherals 0xFFFF FFFF peripheral blocks, each Dynamic memory bank Dynamic memory bank Dynamic memory bank Dynamic memory bank
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
PERIPHERALS 3.75 PERIPHERALS
0xFFFF FFFF 0xF000 0000
0xE000 0000
RESERVED ADDRESS SPACE 0xC000 0000 0xDFFF FFFF EXTERNAL STATIC DYNAMIC MEMORY
BOOT BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH)
0x8000 0000 0x7FFF FFFF
RESERVED ADDRESS SPACE
ON-CHIP STATIC SPECIAL REGISTERS
0x4000 0000 0x3FFF FFFF 0x3FFF 8000
RESERVED ADDRESS SPACE
ON-CHIP NON-VOLATILE MEMORY
002aac736
0x0000 0000
LPC2458 memory
Interrupt controller
processor core interrupt inputs called Interrupt Request (IRQ) Fast Interrupt Request (FIQ). takes interrupt request inputs which programmed vectored types. programmable assignment scheme means that priorities interrupts from various peripherals dynamically assigned adjusted. FIQs have highest priority. more than request assigned FIQ, requests produce signal processor. fastest possible latency achieved when only request classified FIQ, because then
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
service routine simply start dealing with that device. more than request assigned class, service routine read word from that identifies which source(s) (are) requesting interrupt. Vectored IRQs, which include interrupt requests that classified FIQs, have programmable interrupt priority. When more than interrupt assigned same priority occur simultaneously, connected lowest numbered channel will serviced first. requests from vectored IRQs produce signal processor. service routine start reading register from jumping address supplied that register.
7.5.1 Interrupt sources
Each peripheral device interrupt line connected have several interrupt flags. Individual interrupt flags also represent more than interrupt source. PORT0 PORT2 (total pins) regardless selected function, programmed generate interrupt rising edge, falling edge, both. Such interrupt request coming from PORT0 and/or PORT2 will combined with EINT3 interrupt requests.
connect block
connect block allows selected pins microcontroller have more than function. Configuration registers control multiplexers allow connection between chip peripherals. Peripherals should connected appropriate pins prior being activated prior related interrupt(s) being enabled. Activity enabled peripheral function that mapped related should considered undefined.
External memory controller
LPC2458 PrimeCell MultiPort Memory Controller peripheral offering support asynchronous static memory devices such RAM, ROM, flash. addition, used interface with off-chip memory-mapped devices peripherals. Advanced Microcontroller Architecture (AMBA) compliant peripheral.
7.7.1 Features
Dynamic memory interface support including Single Data Rate SDRAM Asynchronous static memory device support including RAM, ROM, flash, with
without asynchronous page mode
LPC2468_1
transaction latency Read write buffers reduce latency improve performance 8/16 data address lines wide static memory support wide chip select SDRAM memory support Static memory features include:
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Asynchronous page mode read Programmable Wait States turnaround delay Output enable write enable delays Extended wait
chip selects synchronous memory chip selects static memory
devices
Power-saving modes dynamically control CLKOUT SDRAMs Dynamic memory self-refresh mode controlled software Controller supports address synchronous memory parts. That
typical parts, with data bits device
Separate reset domains allow auto-refresh through chip reset desired
Note: Synchronous static memory devices (synchronous burst mode) supported.
General purpose controller
GPDMA AMBA compliant peripheral allowing selected LPC2458 peripherals have support. GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, memory-to-memory transactions. Each stream provides unidirectional serial transfers single source destination. example, bidirectional port requires stream transmit receive. source destination areas each either memory region peripheral, accessed through master.
7.8.1 Features
channels. Each channel support unidirectional transfer. GPDMA transfer data between SRAM, external memory,
peripherals such SD/MMC, SSPs, interface.
Single burst request signals. Each peripheral connected
GPDMA assert either burst request single request. burst size programming GPDMA.
Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral transfers.
Scatter gather supported through linked lists. This means that
source destination areas have occupy contiguous areas memory.
Hardware channel priority. Each channel specific hardware priority.
channel highest priority channel lowest priority. requests from channels become active same time, channel with highest priority serviced first.
slave programming interface. GPDMA programmed writing
control registers over slave interface.
master transferring data. This interface transfers data when
request goes active.
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
32-bit master width. Incrementing non-incrementing addressing source destination. Programmable burst size. burst size programmed more
efficiently transfer data. Usually burst size half size FIFO peripheral.
Internal four-word FIFO channel. Supports 8-bit, 16-bit, 32-bit wide transactions. interrupt processor generated completion when
error occurred.
Interrupt masking. error terminal count interrupt requests
masked.
interrupt status. error count interrupt status read
prior masking.
Fast general purpose parallel
Device pins that connected specific peripheral function controlled GPIO registers. Pins dynamically configured inputs outputs. Separate registers allow setting clearing number outputs simultaneously. value output register read back well current state port pins. LPC2458 accelerated GPIO functions:
GPIO registers relocated local that fastest possible
timing achieved.
Mask registers allow treating sets port bits group, leaving other bits
unchanged.
GPIO registers byte half-word addressable. Entire port value written instruction.
Additionally, PORT0 PORT2 (total pins) that configured analog input/output programmed generate interrupt rising edge, falling edge, both. edge detection asynchronous, operate when clocks present such during Power-down mode. Each enabled interrupt used wake chip from Power-down mode.
7.9.1 Features
level clear registers allow single instruction clear number
bits port.
Direction control individual bits. default inputs after reset. Backward compatibility with other earlier devices maintained with legacy PORT0
PORT1 registers appearing original addresses bus.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.10 Ethernet
Ethernet block contains full featured Mbit/s Mbit/s Ethernet designed provide optimized performance through hardware acceleration. Features include generous suite control registers, half full duplex operation, flow control, control frames, hardware acceleration transmit retry, receive packet filtering wake-up activity. Automatic frame transmission reception with scatter-gather off-loads many operations from CPU. Ethernet block share dedicated subsystem that used access Ethernet SRAM Ethernet data, control, status information. other traffic LPC2458 takes place different subsystem, effectively separating Ethernet activity from rest system. Ethernet also access off-chip memory EMC, well SRAM located another AHB. However, using memory other than Ethernet SRAM, especially off-chip memory, will slow Ethernet access memory increase loading AHB. Ethernet block interfaces between off-chip Ethernet using Media Independent Interface (MII) Reduced (RMII) protocol on-chip Media Independent Interface Management (MIIM) serial bus.
7.10.1 Features
Ethernet standards support:
Supports Mbit/s Mbit/s devices including Base-T, Base-TX, Base-FX, Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x Full Duplex Flow Control Half Duplex back pressure. Flexible transmit receive frame options. Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit receive buffers memory mapped shared SRAM. managers with scatter/gather arrays frame descriptors. Memory traffic optimized buffering pre-fetching.
Enhanced Ethernet features:
Receive filtering. Multicast broadcast frame support both transmit receive. Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) transmit. Selectable automatic transmit frame padding. Over-length frame support both transmit receive allows length frames. Promiscuous receive mode. Automatic collision back-off frame retransmission. Includes power management clock switching.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Wake-on-LAN power management support allows system wake-up: using receive filters magic frame detection filter.
Physical interface:
Attachment external chip through standard RMII interface. register access available MIIM interface.
7.11 interface
Universal Serial (USB) 4-wire that supports communication between host more 127) peripherals. Host Controller allocates bandwidth attached devices through token-based protocol. supports plugging dynamic configuration devices. transactions initiated Host Controller. LPC2458 interface includes Device, Host, Controller. Details typical interfacing solutions found Section 11.1 "Suggested interface solutions" page
7.11.1 Device Controller
Device Controller enables Mbit/s data exchange with Host Controller. consists register interface, serial interface engine, endpoint buffer memory, controller. serial interface engine decodes data stream writes data appropriate endpoint buffer. status completed transfer error condition indicated status registers. interrupt also generated enabled. When enabled, controller transfers data between endpoint buffer RAM. 7.11.1.1 Features
Fully compliant with specification (full speed). Supports physical logical) endpoints with endpoint buffer RAM. Supports Control, Bulk, Interrupt Isochronous endpoints. Scalable realization endpoints time. Endpoint Maximum packet size selection maximum specification) software time.
Supports SoftConnect GoodLink features. While Suspend mode, LPC2458 enter reduced power
modes wake activity.
Supports transfers with non-control endpoints. Allows dynamic switching between CPU-controlled modes. Double buffer implementation Bulk Isochronous endpoints.
7.11.2 Host Controller
Host Controller enables full- low-speed data exchange with devices attached bus. consists register interface, serial interface engine controller. register interface complies with OHCI specification.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.11.2.1
Features
OHCI compliant. downstream ports. Supports per-port power switching.
7.11.3 Controller
(On-The-Go) supplement specification that augments capability existing mobile devices peripherals adding host functionality connection peripherals. Controller integrates Host Controller, device controller, master-only interface implement dual-role device functionality. dedicated interface controls external transceiver. 7.11.3.1 Features
Fully compliant with On-The-Go supplement Specification, Revision
1.0a.
Hardware support Host Negotiation Protocol (HNP). Includes programmable timer required Session Request Protocol
(SRP).
Supports transceiver compliant with Transceiver Specification
(CEA-2011), Rev. 1.0.
7.12 controller acceptance filters
Controller Area Network (CAN) serial communications protocol which efficiently supports distributed real-time control with very high level security. domain application ranges from high-speed networks cost multiplex wiring. block intended support multiple buses simultaneously, allowing device used gateway, switch, router between buses industrial automotive applications. Each controller register structure similar SJA1000 PeliCAN Library block, 8-bit registers those devices have been combined 32-bit words allow simultaneous access environment. main operational difference that recognition received Identifiers, known terminology Acceptance Filtering, been removed from controllers centralized global Acceptance Filter.
7.12.1 Features
controllers buses. Data rates Mbit/s each bus. 32-bit register access. Compatible with specification 2.0B, 11898-1. Global Acceptance Filter recognizes 11-bit 29-bit receive identifiers buses.
B.V. 2007. rights reserved.
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Acceptance Filter provide FullCAN-style automatic reception selected
Standard Identifiers.
Full messages generate interrupts. 7.13 10-bit
LPC2458 contains ADC. single 10-bit successive approximation with eight channels.
7.13.1 Features
10-bit successive approximation Input multiplexing among pins Power-down mode Measurement range Vi(VREF) 10-bit conversion time 2.44 Burst conversion mode single multiple inputs Optional conversion transition input Timer Match signal Individual result registers each channel reduce interrupt overhead
7.14 10-bit
allows LPC2458 generate variable analog output. maximum output value Vi(VREF).
7.14.1 Features
10-bit Resistor string architecture Buffered output Power-down mode Selectable output drive
7.15 UARTs
LPC2458 contains four UARTs. addition standard transmit receive data lines, UART1 also provides full modem control handshake interface. UARTs include fractional baud rate generator. Standard baud rates such 115200 achieved with crystal frequency above MHz.
7.15.1 Features
Receive Transmit FIFOs. Register locations conform 16C550 industry standard. Receiver FIFO trigger points Built-in fractional baud rate generator covering wide range baud rates without need external crystals particular values.
B.V. 2007. rights reserved.
LPC2468_1
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Fractional divider baud rate control, auto baud capabilities FIFO control
mechanism that enables software flow control implementation.
UART1 equipped with standard modem interface signals. This module also provides
full support hardware flow control (auto-CTS/RTS).
UART3 includes IrDA mode support infrared communication. 7.16 serial controller
LPC2458 contains controller. full duplex serial interface designed handle multiple masters slaves connected given bus. Only single master single slave communicate interface during given data transfer. During data transfer master always sends bits bits data slave, slave always sends bits bits data master.
7.16.1 Features
Compliant with specification Synchronous, Serial, Full Duplex Communication Combined master slave Maximum data rate eighth input clock rate bits bits transfer
7.17 serial controller
LPC2458 contains controllers. controller capable operation SPI, 4-wire SSI, Microwire bus. interact with multiple masters slaves bus. Only single master single slave communicate during given data transfer. supports full duplex transfers, with frames bits bits data flowing from master slave from slave master. practice, often only these data flows carries meaningful data.
7.17.1 Features
Compatible with Motorola SPI, 4-wire SSI, National Semiconductor Microwire
buses
Synchronous serial communication Master slave operation 8-frame FIFOs both transmit receive 4-bit 16-bit frame Maximum data rate half (Master mode) twelfth (Slave mode) input clock rate
transfers supported GPDMA 7.18 SD/MMC card interface
Secure Digital Multimedia Card Interface (MCI) allows access external memory cards. card interface conforms Multimedia Card Specification Version 2.11.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.18.1 Features
interface provides functions specific SD/MMC memory card. These
include clock generation unit, power management control, command data transfer.
Conforms Multimedia Card Specification v2.11. Conforms Secure Digital Memory Card Physical Layer Specification, v0.96. used multimedia card secure digital memory card host.
SD/MMC connected several multimedia cards single secure digital memory card.
supported through GPDMA controller. 7.19 I2C-bus serial controller
LPC2458 contains three I2C-bus controllers. I2C-bus bidirectional, inter-IC control using only wires: serial clock line (SCL), serial data line (SDA). Each device recognized unique address operate either receiver-only device (e.g., driver) transmitter with capability both receive send information (such memory). Transmitters and/or receivers operate either master slave mode, depending whether chip initiate data transfer only addressed. I2C-bus multi-master controlled more than master connected I2C-bus implemented LPC2458 supports rates kbit/s (Fast I2C-bus).
7.19.1 Features
I2C0 standard compliant interface with open-drain pins. I2C1 I2C2 standard pins support powering individual
devices connected same lines.
Easy configure master, slave, master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters slaves. Multi-master central master). Arbitration between simultaneously transmitting masters without corruption serial data bus. serial bus.
Serial clock synchronization allows devices with different rates communicate Serial clock synchronization used handshake mechanism suspend
resume serial transfer.
I2C-bus used test diagnostic purposes. 7.20 I2S-bus serial controllers
I2S-bus provides standard communication interface digital audio applications.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
I2S-bus specification defines 3-wire serial using data line, clock line, word select signal. basic connection master, which always master, slave. interface LPC2458 provides separate transmit receive channel, each which operate either master slave.
7.20.1 Features
interface separate input/output channels each which operate master
slave mode.
Capable handling 8-bit, 16-bit, 32-bit word sizes. Mono stereo audio data supported. sampling frequency range from (16, 22.05, 44.1,
kHz.
Configurable word select period master mode (separately input output). word FIFO data buffers provided, transmit receive. Generates interrupt requests when buffer levels cross programmable boundary. requests, controlled programmable buffer levels. These connected GPDMA block.
Controls include reset, stop mute options separately input output. 7.21 General purpose 32-bit timers/external event counters
LPC2458 includes four 32-bit Timer/Counters. Timer/Counter designed count cycles system derived clock externally-supplied clock. optionally generate interrupts perform other actions specified timer values, based four match registers. Timer/Counter also includes four capture inputs trap timer value when input signal transitions, optionally generating interrupt.
7.21.1 Features
32-bit Timer/Counter with programmable 32-bit prescaler. Counter Timer operation. four 32-bit capture channels timer, that take snapshot timer
value when input signal transitions. capture event also optionally generate interrupt.
Four 32-bit match registers that allow:
Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
four external outputs corresponding match registers, with following
capabilities: match. HIGH match. Toggle match. nothing match.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.22 Pulse width modulator
based standard Timer block inherits features, although only function pinned LPC2458. Timer designed count cycles system derived clock optionally switch pins, generate interrupts perform other actions when specified timer values occur, based seven match registers. function addition these features based match register events. ability separately control rising falling edge locations allows used more applications. instance, multi-phase motor control typically requires three non-overlapping outputs with individual control three pulse widths positions. match registers used provide single edge controlled output. dedicated match register controls cycle rate, resetting count upon match. other match register controls edge position. Additional single edge controlled outputs require only match register each, since repetition rate same outputs. Multiple single edge controlled outputs will have rising edge beginning each cycle, when PWMMR0 match occurs. Three match registers used provide output with both edges controlled. Again, dedicated match register controls cycle rate. other match registers control edge positions. Additional double edge controlled outputs require only match registers each, since repetition rate same outputs. With double edge controlled outputs, specific match registers control rising falling edge output. This allows both positive going pulses (when rising edge occurs prior falling edge), negative going pulses (when falling edge occurs prior rising edge).
7.22.1 Features
LPC2458 PWMs with same operational features. These operated
synchronized fashion setting them both same rate, then enabling both simultaneously. PWM0 acts master PWM1 slave this use.
Counter Timer operation (may peripheral clock capture inputs
clock source).
Seven match registers allow single edge controlled double edge
controlled outputs, both types. match registers also allow: Continuous operation with optional interrupt generation match. Stop timer match with optional interrupt generation. Reset timer match with optional interrupt generation.
Supports single edge controlled and/or double edge controlled outputs. Single
edge controlled outputs high beginning each cycle unless output constant low. Double edge controlled outputs have either edge occur position within cycle. This allows both positive going negative going pulses.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Pulse period width number timer counts. This allows complete
flexibility trade-off between resolution repetition rate. outputs will occur same repetition rate.
Double edge controlled outputs programmed either positive going
negative going pulses.
Match register updates synchronized with pulse outputs prevent generation
erroneous pulses. Software must `release' match values before they become effective.
used standard timer mode enabled. 32-bit Timer/Counter with programmable 32-bit Prescaler. 7.23 Watchdog timer (WDT)
purpose watchdog reset microcontroller within reasonable amount time enters erroneous state. When enabled, watchdog will generate system reset user program fails `feed' reload) watchdog within predetermined amount time.
7.23.1 Features
Internally resets chip periodically reloaded. Debug mode. Enabled software requires hardware reset watchdog reset/interrupt
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt enabled. Flag indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) (Tcy(WDCLK) multiples Tcy(WDCLK) Internal oscillator (IRC), peripheral clock. This gives wide range potential timing choices Watchdog operation under different power reduction conditions. also provides ability from entirely internal source that dependent external crystal associated components wiring, increased reliability.
Watchdog Clock (WDCLK) source selected from clock,
7.24 battery
counters measuring time when system power optionally when off. uses little power Power-down mode. LPC2458, clocked separate 32.768 oscillator programmable prescale divider based clock. Also, powered power supply pin, VBAT, which connected battery same supply used rest device. VBAT supplies power only Battery RAM. These functions require minimum power operate, which supplied external battery. When rest chip functions stopped power removed, supply alarm output that used external hardware restore chip power resume operation.
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.24.1 Features
Measures passage time maintain calendar clock. Ultra power design support battery powered systems. Provides Seconds, Minutes, Hours, Month, Month, Year, Week,
Year.
Dedicated oscillator programmable prescaler from clock. Dedicated power supply connected battery main alarm output included assist waking when chip power
removed functions except Battery RAM.
Periodic interrupts generated from increments field time registers,
selected fractional second values. This enhancement enables used System Timer.
data SRAM powered VBAT. Battery power supply isolated from rest chip. 7.25 Clocking power control
7.25.1 Crystal oscillators
LPC2458 includes three independent oscillators. These Main Oscillator, Internal oscillator, oscillator. Each oscillator used more than purpose required particular application. three clock sources chosen software drive ultimately CPU. Following reset, LPC2458 will operate from Internal oscillator until switched software. This allows systems operate without external crystal bootloader code operate known frequency. 7.25.1.1 Internal oscillator used clock source WDT, and/or clock that drives subsequently CPU. nominal frequency MHz. trimmed accuracy. Upon power-up chip reset, LPC2458 uses clock source. Software later switch other available clock sources. 7.25.1.2 Main oscillator main oscillator used clock source CPU, with without using PLL. main oscillator operates frequencies MHz. This frequency boosted higher frequency, maximum operating frequency, PLL. clock selected input PLLCLKIN. processor clock frequency referred CCLK elsewhere this document. frequencies PLLCLKIN CCLK same value unless active connected. clock frequency each peripheral selected individually referred PCLK. Refer Section 7.25.2 additional information.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.25.1.3
oscillator oscillator used clock source and/or WDT. Also, oscillator used drive CPU.
7.25.2
accepts input clock frequency range MHz. input frequency multiplied high frequency, then divided down provide actual clock used block. input, range MHz, initially divided down value `N', which range 256. This input division provides wide range output frequencies from same input frequency. Following input divider multiplier. This multiply input divider output through Current Controlled Oscillator (CCO) value `M', range through 32768. resulting frequency must range MHz. multiplier works dividing output value then using phase-frequency detector compare divided output multiplier input. error value used adjust frequency. turned bypassed following chip Reset entering Power-down mode. enabled software only. program must configure activate PLL, wait lock, then connect clock source.
7.25.3 Wake-up timer
LPC2458 begins operation power-up when awakened from Power-down mode using oscillator clock source. This allows chip operation resume quickly. main oscillator needed application, software will need enable these features wait them stabilize before they used clock source. When main oscillator initially activated, wake-up timer allows software ensure that main oscillator fully functional before processor uses clock source starts execute instructions. This important power types Reset, whenever aforementioned functions turned reason. Since oscillator other functions turned during Power-down mode, wake-up processor from Power-down mode makes wake-up Timer. Wake-up Timer monitors crystal oscillator check whether safe begin code execution. When power applied chip, when some event caused chip exit Power-down mode, some time required oscillator produce signal sufficient amplitude drive clock logic. amount time depends many factors, including rate VDD(3V3) ramp case power on), type crystal electrical characteristics quartz crystal used), well other external circuitry (e.g., capacitors), characteristics oscillator itself under existing ambient conditions.
7.25.4 Power control
LPC2458 supports variety power control features. There three special modes processor power reduction: Idle mode, Sleep mode, Power-down mode. clock rate also controlled needed changing clock sources, reconfiguring
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
values, and/or altering clock divider value. This allows trade-off power versus processing speed based application requirements. addition, Peripheral power control allows shutting down clocks individual on-chip peripherals, allowing fine tuning power consumption eliminating dynamic power peripherals that required application. Each peripherals clock divider which provides even better power control. LPC2458 also implements separate power domain order allow turning power bulk device while maintaining operation small SRAM, referred Battery RAM. 7.25.4.1 Idle mode Idle mode, execution instructions suspended until either Reset interrupt occurs. Peripheral functions continue operation during Idle mode generate interrupts cause processor resume execution. Idle mode eliminates dynamic power used processor itself, memory systems related controllers, internal buses. 7.25.4.2 Sleep mode Sleep mode, oscillator shut down chip receives internal clocks. processor state registers, peripheral registers, internal SRAM values preserved throughout Sleep mode logic levels chip pins remain static. output disabled powered down fast wake-up later. oscillator stopped because interrupts used wake-up source. automatically turned disconnected. CCLK clock dividers automatically reset zero. Sleep mode terminated normal operation resumed either Reset certain specific interrupts that able function without clocks. Since dynamic operation chip suspended, Sleep mode reduces chip power consumption very value. flash memory left Sleep mode, allowing very quick wake-up. wake-up from Sleep mode, used before entering Sleep mode, code execution peripherals activities will resume after cycles expire. main external oscillator used, code execution will resume when 4096 cycles expire. customers need reconfigure clock dividers accordingly. 7.25.4.3 Power-down mode Power-down mode does everything that Sleep mode does, also turns oscillator flash memory. This saves more power, requires waiting resumption flash operation before execution code data access flash memory accomplished. wake-up from Power-down mode, used before entering Power-down mode, will take start-up. After this cycles will expire before code execution then resumed code running from SRAM. meantime, flash wake-up timer then counts clock cycles make flash start-up time. When times out, access flash will allowed. customers need reconfigure clock dividers accordingly.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.25.4.4
Power domains LPC2458 provides independent power domains that allow bulk device have power removed while maintaining operation Battery RAM. LPC2458, pads powered (VDD(3V3)) pins, while VDD(DCDC)(3V3) pins power on-chip DC-to-DC converter which turn provides power most peripherals. Although both ring core require supply, different powering schemes used depending actual application requirements. first option assumes that power consumption concern design ties VDD(3V3) VDD(DCDC)(3V3) pins together. This approach requires only power supply both pads, CPU, peripherals. While this solution simple, does support powering down ring fly" while keeping peripherals alive. second option uses power supplies; supply pads (VDD(3V3)) dedicated supply (VDD(DCDC)(3V3)). Having on-chip DC-DC converter powered independently from ring enables shutting down power supply fly", while peripherals stay active. VBAT supplies power only Battery RAM. These functions require minimum power operate, which supplied external battery. When rest chip functions stopped power removed, supply alarm output that used external hardware restore chip power resume operation.
7.26 System control
7.26.1 Reset
Reset four sources LPC2458: RESET pin, Watchdog reset, power-on reset, BrownOut Detection (BOD) circuit. RESET Schmitt trigger input pin. Assertion chip Reset source, once operating voltage attains usable level, starts Wake-up timer (see description Section 7.25.3 "Wake-up timer"), causing reset remain asserted until external Reset de-asserted, oscillator running, fixed number clocks have passed, flash controller completed initialization. When internal Reset removed, processor begins executing address which initially Reset vector mapped from Boot Block. that point, processor peripheral registers have been initialized predetermined values.
7.26.2 Brownout detection
LPC2458 includes 2-stage monitoring voltage VDD(3V3) pins. this voltage falls below 2.95 asserts interrupt signal Vectored Interrupt Controller. This signal enabled interrupt Interrupt Enable Register order cause interrupt; not, software monitor signal reading dedicated status register.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
second stage low-voltage detection asserts Reset inactivate LPC2458 when voltage VDD(3V3) pins falls below 2.65 This Reset prevents alteration flash operation various elements chip would otherwise become unreliable voltage. circuit maintains this reset down below which point power-on reset circuitry maintains overall Reset. Both 2.95 2.65 thresholds include some hysteresis. normal operation, this hysteresis allows 2.95 detection reliably interrupt, regularly-executed event loop sense condition.
7.26.3 Code security (Code Read Protection CRP)
This feature LPC2458 allows user enable different levels security system that access on-chip flash JTAG restricted. When needed, invoked programming specific pattern into dedicated flash location. commands affected CRP. There three levels Code Read Protection. CRP1 disables access chip JTAG allows partial flash update (excluding flash sector using limited commands. This mode useful when required flash field updates needed sectors erased. CRP2 disables access chip JTAG only allows full flash erase update using reduced commands. Running application with level CRP3 selected fully disables access chip JTAG pins ISP. This mode effectively disables overide using P2[10] pin, too. user's application provide needed) flash update mechanism using calls call reinvoke command enable flash update UART0.
CAUTION level three Code Read Protection (CRP3) selected, future factory testing performed device.
7.26.4
LPC2458 implements buses order allow Ethernet block operate without interference caused other system activity. primary AHB, referred AHB1, includes Vectored Interrupt Controller, GPDMA controller, interface, SRAM. second AHB, referred AHB2, includes only Ethernet block associated SRAM. addition, bridge provided that allows secondary master AHB1, allowing expansion Ethernet buffer space into off-chip memory unused space memory residing AHB1. summary, masters with access AHB1 ARM7 itself, block, GPDMA function, Ethernet block (via bridge from AHB2). masters with access AHB2 ARM7 Ethernet block.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
7.26.5 External interrupt inputs
LPC2458 includes edge sensitive interrupt inputs combined with four level sensitive external interrupt inputs selectable functions. external interrupt inputs optionally used wake processor from Power-down mode.
7.26.6 Memory mapping control
memory mapping control alters mapping interrupt vectors that appear beginning address 0x0000 0000. Vectors mapped bottom Boot ROM, SRAM, external memory. This allows code running different memory spaces have control interrupts.
7.27 Emulation debugging
LPC2458 support emulation debugging JTAG serial port. trace port allows tracing program execution. Debugging trace functions multiplexed only with GPIOs P2[0] P2[9]. This means that communication, timer, interface peripherals residing other pins available during development debugging phase they when application embedded system itself.
7.27.1 EmbeddedICE
EmbeddedICE logic provides on-chip debug support. debugging target system requires host computer running debugger software EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts Remote Debug Protocol commands JTAG data needed access ARM7TDMI-S core present target system. core Debug Communication Channel (DCC) function built-in. allows program running target communicate with host debugger another separate host without stopping program flow even entering debug state. accessed coprocessor program running ARM7TDMI-S core. allows JTAG port used sending receiving data without affecting normal program flow. data control registers mapped addresses EmbeddedICE logic.
7.27.2 Embedded trace
Since LPC2458 have significant amounts on-chip memories, possible determine processor core operating simply observing external pins. Eprovides real-time trace capability deeply embedded processor cores. outputs information about processor execution trace port. software debugger allows configuration Eusing JTAG interface displays trace information that been captured. connected directly core main AMBA system bus. compresses trace information exports through narrow trace port. external Trace Port Analyzer captures trace information under software debugger control. trace port broadcast Instruction trace information. Instruction trace trace) shows flow execution processor provides list instructions that were executed. Instruction trace significantly compressed only broadcasting branch addresses well status signals that indicate pipeline status cycle cycle basis. Trace information generation controlled selecting trigger resource. Trigger resources include address comparators, counters sequencers.
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Since trace information compressed software debugger requires static image code being executed. Self-modifying code traced because this restriction.
7.27.3 RealMonitor
RealMonitor configurable software module, developed Inc., which enables real-time debug. lightweight debug monitor that runs background while users debug their foreground application. communicates with host using DCC, which present EmbeddedICE logic. LPC2458 contain specific configuration RealMonitor software programmed into on-chip memory.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) Parameter supply voltage (3.3 Conditions core external rail -0.5 related pins tolerant pins; only valid when VDD(3V3) supply voltage present other pins Tstg Ptot(pack) supply current ground current storage temperature total power dissipation (per package) based package heat transfer, device power consumption human body model; pins
+4.6 +4.6 +4.6 +5.1 +6.0
Unit
VDD(DCDC)(3V3) DC-to-DC converter supply voltage (3.3 VDDA Vi(VBAT) Vi(VREF) analog supply voltage input voltage VBAT input voltage VREF analog input voltage input voltage
-0.5 -0.5 -0.5 -0.5
[2][3]
-0.5
VDD(3V3) +150
supply ground
Vesd
electrostatic discharge voltage
-2000
+2000
following applies Limiting values: This product includes circuitry specifically designed protection internal devices from damaging effects excessive static charge. Nonetheless, suggested that conventional precautions taken avoid applying greater than rated maximum. Parameters valid over operating temperature range unless otherwise specified. voltages with respect unless otherwise noted.
Including voltage outputs 3-state mode. exceed peak current limited times corresponding maximum current. Dependent package type. Human body model: equivalent discharging capacitor through series resistor.
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Static characteristics
Table Static characteristics Tamb commercial applications, unless otherwise specified. Symbol VDD(3V3) VDD(DCDC)(3V3) VDDA Vi(VBAT) Vi(VREF) Parameter supply voltage (3.3 DC-to-DC converter supply voltage (3.3 analog supply voltage input voltage VBAT input voltage VREF LOW-level input current HIGH-level input current OFF-state output current latch-up current pull-up VDD(3V3); pull-down VDD(3V3); pull-up/down -(0.5VDD(3V3)) (1.5VDD(3V3)); Vhys IOHS input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current HIGH-level short-circuit output current VDD(3V3)
Conditions core external rail
Typ[1]
VDDA
Unit
Standard port pins, RESET, RTCK Ilatch
configured provide digital function output active
[3][4][5]
VDD(3V3)
VDD(3V3)
IOLS
LOW-level short-circuit VDDA output current pull-down current pull-up current VDD(3V3)
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Parameter Conditions Typ[1] Unit IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) converter supply Tamb code current (3.3 while(1){} executed from flash; peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK peripherals enabled; PCLK CCLK CCLK CCLK IDD(DCDC)pd(3V3) power-down mode DC-to-DC converter supply current (3.3 active mode battery supply current VDD(DCDC)(3V3) Tamb DC-to-DC converter DC-to-DC converter
IBATact
I2C-bus pins (P0[27] P0[28]) Vhys Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) pins VBUS
LPC2468_1
HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current IOLS VDD(3V3) input voltage XTAL1 output voltage XTAL2 input voltage RTCX1 output voltage RTCX2 OFF-state output current supply voltage
0.7VDD(3V3) 0.5VDD(3V)
0.3VDD(3V3)
[10]
5.25
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table Static characteristics .continued Tamb commercial applications, unless otherwise specified. Symbol Vth(rs)se Parameter differential input sensitivity differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage low-/full-speed HIGH-level output voltage (driven) low-/full-speed transceiver capacitance driver output impedance driver which high-speed capable pull-up resistance Conditions |(D+) (D-)| includes range Typ[1] Unit
0.18
Ctrans ZDRV
with series resistor; steady state drive
[11]
44.1
SoftConnect
Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages typically fails when Vi(VBAT) drops below Including voltage outputs 3-state mode. VDD(3V3) supply voltages must present. 3-state outputs into 3-state mode when VDD(3V3) grounded. Accounts voltage drop supply lines. Only allowed short time period. Minimum condition maximum condition VBAT.
[10] VSS. [11] Includes external resistors
Table static characteristics VDDA Tamb unless otherwise specified; frequency MHz. Symbol EL(adj) Rvsi Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance
[1][2][3] [1][4] [1][5] [1][6] [1][7]
Conditions
VDDA ±0.5
Unit
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Conditions: VSSA VDDA monotonic, there missing codes. differential linearity error (ED) difference between actual step width ideal step width. Figure integral non-linearity (EL(adj)) peak difference between center steps actual ideal transfer curve after appropriate adjustment gain offset errors. Figure offset error (EO) absolute difference between straight line which fits actual curve straight line which fits ideal curve. Figure gain error (EG) relative difference percent between straight line fitting actual transfer curve after removing offset error, straight line which fits ideal transfer curve. Figure absolute error (ET) maximum difference between center steps actual transfer curve non-calibrated ideal transfer curve. Figure Figure
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
offset error 1023
gain error
1022
1021
1020
1019
1018
code
(ideal) 1018 1019 1020 1021 1022 1023 1024
offset error (LSBideal)
VDDA VSSA 1024
002aab136
Example actual transfer curve. ideal transfer curve. Differential linearity error (ED). Integral non-linearity (EL(adj)). Center step actual transfer curve.
characteristics
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
LPC2XXX
AD0[y]SAMPLE
AD0[y]
Rvsi
VEXT
002aac733
Suggested interface LPC2458 AD0[y]
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Dynamic characteristics
Table Dynamic characteristics pins (full-speed) VDD(3V3),unless otherwise specified. Symbol tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise fall time matching output signal crossover voltage source interval source jitter differential transition transition receiver jitter next transition receiver jitter paired transitions width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
13.8 13.7 +18.5
Unit
Figure Figure
-18.5
tEOPR2
width receiver
Characterized implemented production test. Guaranteed design.
Table Dynamic characteristics Tamb commercial applications; VDD(3V3) over specified ranges.[1] Symbol External clock fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL I2C-bus tf(o)
Parameter oscillator frequency clock cycle time clock HIGH time clock time clock rise time clock fall time pins (P0[27] P0[28]) output fall time
Conditions
Tcy(clk) Tcy(clk)
Typ[2]
Unit
Cb[3]
Parameters valid over operating temperature range unless otherwise specified. Typical ratings guaranteed. values listed room temperature °C), nominal supply voltages. capacitance from
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table External memory interface dynamic characteristics Tamb Symbol tCHAV tCHCSL tCHCSH tCHANV Parameter XCLK HIGH address valid time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH address invalid time address valid time address valid time time memory access time memory access time (initial burst-ROM) memory access time (subsequent burst-ROM) data hold time HIGH HIGH time HIGH address invalid time XCLK HIGH time XCLK HIGH HIGH time address valid time data valid time time time data valid time data valid time HIGH time HIGH time HIGH address invalid time HIGH data invalid time HIGH address invalid time
[2][3]
Conditions
Unit
Common read write cycles
Read cycle parameters tCSLAV tOELAV tCSLOEL tam(ibr) tam(sbr) th(D) tCSHOEH tOEHANV tCHOEL tCHOEH (Tcy(CCLK) WST1)) (-20) (Tcy(CCLK) WST1)) (-20) Tcy(CCLK) (-20)
[2][3]
[2][4]
Write cycle parameters tAVCSL tCSLDV tCSLWEL tCSLBLSL tWELDV tCSLDV tWELWEH tBLSLBLSH tWEHANV tWEHDNV tBLSHANV Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK) Tcy(CCLK)) Tcy(CCLK) Tcy(CCLK) WST2) Tcy(CCLK) WST2) Tcy(CCLK)
Tcy(CCLK)) Tcy(CCLK)
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Table External memory interface dynamic characteristics .continued Tamb Symbol tBLSHDNV tCHDV tCHWEL tCHBLSL tCHWEH tCHBLSH tCHDNV Parameter HIGH data invalid time XCLK HIGH data valid time XCLK HIGH time XCLK HIGH time XCLK HIGH HIGH time XCLK HIGH HIGH time XCLK HIGH data invalid time Conditions
Tcy(CCLK))
Unit
Tcy(CCLK))
Except initial access, which case address Tcy(CCLK) earlier. Tcy(CCLK) 1/CCLK. Latest address valid, LOW, data valid. Address valid data valid. Earliest HIGH, HIGH, address change data invalid.
Table
Standard read access specifications frequency setting round integer Memory access time requirement
Access cycle
standard read
WST1 WST2 WRITE WST1 INIT
WST1 CCLK WRITE WST2 CCLK INIT WST1 CCLK
CCLK WST1 WRITE CCLK WST2 INIT CCLK WST1 CCLK
standard write
burst read initial
burst read subsequent
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
10.1 Timing
XCLK tCSLAV tCSHOEH
addr data tCSLOEL tOELAV tCHOEL tCHOEH
002aaa749
th(D)
tOEHANV
External memory read access
XCLK tCSLDV
tAVCSL tWELWEH tBLSLBLSH tWEHANV tCSLBLSL tWELDV tBLSHANV
tCSLWEL BLS/WE
addr tCSLDV data tWEHDNV tBLSHDNV
002aaa750
External memory write access
continued
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
0.45
0.2VDD 0.2VDD tCHCL tCLCX Tcy(clk)
002aaa907
tCHCX tCLCH
External clock timing
tPERIOD crossover point differential data lines
crossover point extended
source width: tFEOPT differential data SEO/EOP skew tPERIOD tFDEOP
receiver width: tEOPR1, tEOPR2
002aab561
Differential data-to-EOP transition skew width
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Application information
11.1 Suggested interface solutions
VDD(3V3)
USB_UP_LED USB_CONNECT
LPC24XX
soft-connect switch
VBUS USB_D+ USB_D-
002aac737
USB-B connector
LPC2458 interface self-powered device
VDD(3V3)
LPC24XX
USB_UP_LED VBUS USB_D+ USB_D-
USB-B connector
002aac738
LPC2458 interface bus-powered device
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
RSTOUT
RESET_N ADR/PSW OE_N/INT_N SPEED SUSPEND
VBUS
Mini-AB connector
ISP1301
USB_SCL1 USB_SDA1 USB_INT1 USB_D+1 USB_D-1 USB_UP_LED1
INT_N
LPC24XX
USB_PPWR2 USB_OVRCR2
LM3526-L
OUTA FLAGA
USB_PWRD2 USB_D+2 USB_D-2
VBUS USB-A connector
USB_UP_LED2
002aac708
LPC2458 port configuration: port dual-role device, port host
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
RSTOUT USB_TX_E1 USB_TX_DP1 USB_TX_DM1 USB_RCV1 USB_RX_DP1 USB_RX_DM1
RESET_N OE_N/INT_N DAT_VP SE0_VM VBUS
ISP1301 LPC24XX
ADR/PSW SPEED SUSPEND
MINI-AB connector
USB_SCL1 USB_SDA1 USB_INT1 USB_UP_LED1
INT_N
002aac711
LPC2458 port configuration: VP_VM mode
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
USB_UP_LED1 USB_D+1 USB_D-1
USB-A connect
USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA
VBUS
LM3526-L
OUTA
LPC24XX
USB_UP_LED2
USB_CONNECT2
USB_D+2 USB_D-2 VBUS
VBUS USB-B connect
002aac710
LPC2458 port configuration: port device, port host
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
USB_UP_LED1 USB_D+1 USB_D-1
USB-A connecto
USB_PWRD1 USB_OVRCR1 USB_PPWR1 FLAGA OUTA
VBUS
LPC24XX
LM3526-L
OUTB FLAGB
USB_PPWR2 USB_OVRCR2 USB_PWRD2
VBUS
USB_D+2 USB_D-2
USB-A connecto
USB_UP_LED2
002aac709
LPC2458 port configuration: port host, port host
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Package outline
TFBGA180: thin fine-pitch ball grid array package; balls; body SOT570-2
ball index area
detail
ball index area
scale
DIMENSIONS original dimensions) UNIT max. 0.35 0.25 0.85 0.75 12.2 11.8 12.2 11.8 10.4 10.4 0.15 0.08 0.12
OUTLINE VERSION SOT570-2
REFERENCES JEDEC JEITA
EUROPEAN PROJECTION
ISSUE DATE 03-03-03 06-03-14
Package outline SOT570-2 (TFBGA180)
LPC2468_1 B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Abbreviations
Table Acronym AMBA EGPIO JTAG RMII SD/MMC UART Acronym list Description Analog-to-Digital Converter Advanced High-performance Advanced Microcontroller Architecture Advanced Peripheral Analog Transceiver Byte Lane Select BrownOut Detection Controller Area Network Digital-to-Analog Converter Debug Communication Channel Direct Memory Access Digital Signal Processing Packet Embedded Trace Macrocell General Purpose Input/Output Joint Test Action Group Media Independent Interface Physical Layer Phase-Locked Loop Pulse Width Modulator Reduced Media Independent Interface Secure Digital/MultiMediaCard Single Ended Zero Serial Peripheral Interface Synchronous Serial Interface Synchronous Serial Port Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Revision history
Table Revision history Release date <tbd> Data sheet status Preliminary data sheet Change notice Supersedes Document LPC2458_1
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Legal information
15.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
Product status[3] Development Qualification Production
Definition This document contains data from objective specification product development. This document contains data from preliminary specification. This document contains product specification.
Please consult most recently issued document before initiating completing design. term `short data sheet' explained section "Definitions". product status device(s) described this document have changed since this document published differ case multiple devices. latest product status information available Internet http://www.nxp.com.
15.2 Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Short data sheet short data sheet extract from full data sheet with same product type number(s) title. short data sheet intended quick reference only should relied upon contain detailed full information. detailed full information relevant full data sheet, which available request local Semiconductors sales office. case inconsistency conflict with short data sheet, full data sheet shall prevail.
Semiconductors accepts liability inclusion and/or Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Limiting values Stress above more limiting values defined Absolute Maximum Ratings System 60134) cause permanent damage device. Limiting values stress ratings only operation device these other conditions above those given Characteristics sections this document implied. Exposure limiting values extended periods affect device reliability. Terms conditions sale Semiconductors products sold subject general terms conditions commercial sale, published including those pertaining warranty, intellectual property rights infringement limitation liability, unless explicitly otherwise agreed writing Semiconductors. case inconsistency conflict between information this document such terms conditions, latter will prevail. offer sell license Nothing this document interpreted construed offer sell products that open acceptance grant, conveyance implication license under copyrights, patents other industrial intellectual property rights.
15.3 Disclaimers
General Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable medical, military, aircraft, space life support equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage.
15.4 Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners. I2C-bus logo trademark B.V. SoftConnect trademark B.V. GoodLink trademark B.V.
Contact information
additional information, please visit: http://www.nxp.com sales office addresses, send email salesaddresses@nxp.com
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
Contents
General description Features Applications Ordering information Ordering options Block diagram Pinning information Pinning description Functional description Architectural overview On-chip flash programming memory On-chip SRAM Memory map. Interrupt controller 7.5.1 Interrupt sources. connect block External memory controller. 7.7.1 Features General purpose controller 7.8.1 Features Fast general purpose parallel 7.9.1 Features 7.10 Ethernet 7.10.1 Features 7.11 interface 7.11.1 Device Controller 7.11.1.1 Features 7.11.2 Host Controller 7.11.2.1 Features 7.11.3 Controller 7.11.3.1 Features 7.12 controller acceptance filters 7.12.1 Features 7.13 10-bit 7.13.1 Features 7.14 10-bit 7.14.1 Features 7.15 UARTs. 7.15.1 Features 7.16 serial controller. 7.16.1 Features 7.17 serial controller 7.17.1 Features 7.18 SD/MMC card interface 7.18.1 Features 7.19 I2C-bus serial controller 7.19.1 7.20 7.20.1 7.21 Features. I2S-bus serial controllers Features. General purpose 32-bit timers/external event counters 7.21.1 Features. 7.22 Pulse width modulator 7.22.1 Features. 7.23 Watchdog timer (WDT) 7.23.1 Features. 7.24 battery 7.24.1 Features. 7.25 Clocking power control 7.25.1 Crystal oscillators 7.25.1.1 Internal oscillator 7.25.1.2 Main oscillator 7.25.1.3 oscillator 7.25.2 PLL. 7.25.3 Wake-up timer 7.25.4 Power control 7.25.4.1 Idle mode 7.25.4.2 Sleep mode 7.25.4.3 Power-down mode 7.25.4.4 Power domains 7.26 System control 7.26.1 Reset 7.26.2 Brownout detection 7.26.3 Code security (Code Read Protection CRP) 7.26.4 bus. 7.26.5 External interrupt inputs 7.26.6 Memory mapping control 7.27 Emulation debugging 7.27.1 EmbeddedICE 7.27.2 Embedded trace. 7.27.3 RealMonitor Limiting values Static characteristics Dynamic characteristics. 10.1 Timing Application information 11.1 Suggested interface solutions Package outline. Abbreviations Revision history Legal information 15.1 Data sheet status
continued
LPC2468_1
B.V. 2007. rights reserved.
Preliminary data sheet
Rev. July 2007
Semiconductors
LPC2458
Fast communication chip
15.2 15.3 15.4
Definitions Disclaimers Trademarks. Contact information. Contents
Please aware that important notices concerning this document product(s) described herein, have been included section `Legal information'.
B.V. 2007.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send email salesaddresses@nxp.com Date release: July 2007 Document identifier: LPC2468_1

Other recent searches


REJ03B0167-0100 - REJ03B0167-0100   REJ03B0167-0100 Datasheet
FYT-5632 - FYT-5632   FYT-5632 Datasheet
CY7C1302CV25 - CY7C1302CV25   CY7C1302CV25 Datasheet
BSS84PW - BSS84PW   BSS84PW Datasheet
ADuC7000 - ADuC7000   ADuC7000 Datasheet
A8498 - A8498   A8498 Datasheet
2SK4016 - 2SK4016   2SK4016 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive