8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash A
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8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny24/44/84 Preliminary Summary
Rev. 8006FS-AVR-02/07
Configurations
Figure 1-1. Pinout ATtiny24/44/84
PDIP/SOIC
(PCINT8/XTAL1/CLKI) (PCINT9/XTAL2) (PCINT11/RESET/dW) (PCINT10/INT0/OC0A/CKOUT) (PCINT7/ICP/OC0B/ADC7) (PCINT6/OC1A/SDA/MOSI/ADC6) (ADC0/AREF/PCINT0) (ADC1/AIN0/PCINT1) (ADC2/AIN1/PCINT2) (ADC3/T0/PCINT3) (ADC4/USCK/SCL/T1/PCINT4) (ADC5/DO/MISO/OC1B/PCINT5)
QFN/MLF
(PCINT6/OC1A/SDA/MOSI/ADC6) (ADC5/DO/MISO/OC1B/PCINT5) (PCINT7/ICP/OC0B/ADC7) (PCINT10/INT0/OC0A/CKOUT) (PCINT11/RESET/dW) (PCINT9/XTAL2) (PCINT8/XTAL1/CLKI) NOTE Bottom should soldered ground. DNC: Connect
Disclaimer
Typical values contained this data sheet based simulations characterization other microcontrollers manufactured same process technology. values will available after device characterized.
ATtiny24/44/84
8006FS-AVR-02/07
(ADC4/USCK/SCL/T1/PCINT4) (ADC3/T0/PCINT3) (ADC2/AIN1/PCINT2) (ADC1/AIN0/PCINT1) (ADC0/AREF/PCINT0)
ATtiny24/44/84
Overview
ATtiny24/44/84 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATtiny24/44/84 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed.
Block Diagram
Figure 2-1.
8-BIT DATABUS INTERNAL OSCILLATOR
PROGRAM COUNTER STACK POINTER
Block Diagram
INTERNAL CALIBRATED OSCILLATOR
WATCHDOG TIMER CONTROL REGISTER
TIMING CONTROL
PROGRAM FLASH
SRAM
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1
INSTRUCTION DECODER
CONTROL LINES
STATUS REGISTER
INTERRUPT UNIT
PROGRAMMING LOGIC
INTERFACE
EEPROM
OSCILLATORS
ANALOG COMPARATOR
DATA REGISTER PORT
DATA DIR. REG.PORT
DATA REGISTER PORT
DATA DIR. REG.PORT
PORT DRIVERS
PORT DRIVERS
PA7-PA0
PB3-PB0
core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent
8006FS-AVR-02/07
registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATtiny24/44/84 provides following features: 2/4/8K byte In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, general purpose lines, general purpose working registers, 8-bit Timer/Counter with channels, 16-bit timer/counter with channels, Internal External Interrupts, 8-channel 10-bit ADC, programmable gain stage (1x, 20x) differential channel pairs, programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, three software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counter, ADC, Analog Comparator, Interrupt system continue functioning. Power-down mode saves register contents, disabling chip functions until next Interrupt Hardware Reset. Noise Reduction mode stops modules except ADC, minimize switching noise during conversions. Standby mode, crystal/resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with power consumption. device manufactured Atmel's high density non-volatile memory technology. Onchip Flash allows Program memory re-programmed In-System through serial interface, conventional non-volatile memory programmer On-chip boot code running core. ATtiny24/44/84 supported with full suite program system development tools including: Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, Evaluation kits.
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
2.2.1
Descriptions
Supply voltage.
2.2.2
Ground.
2.2.3
Port (PB3.PB0) Port 4-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability except which RESET capability. pin, instead RESET pin, program (`0') RSTDISBL fuse. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATtiny24/44/84 listed Section 12.3 "Alternate Port Functions" page
2.2.4
RESET Reset input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given Table 22-3 page 183. Shorter pulses guaranteed generate reset.
2.2.5
Port (PA7.PA0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port alternate functions analog inputs ADC, analog comparator, timer/counter, change interrupt described "Alternate Port Functions" page
Resources
comprehensive development tools, drivers application notes, datasheets available download http://www.atmel.com/avr.
8006FS-AVR-02/07
Register Summary
Address
0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C) 0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31)) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
Name
SREG OCR0B GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL TCCR0A TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL DWDR CLKPR ICR1H ICR1L GTCCR TCCR1C WDTCSR PCMSK1 EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB GPIOR2 GPIOR1 GPIOR0 PCMSK0 Reserved USIBR USIDR USISR USICR TIMSK1 TIFR1 Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved DIDR0
FOC0A CAL7 COM0A1 COM1A1 ICNC1
INT0 INTF0 FOC0B CAL6 COM0A0 COM1A0 ICES1
OCIE0A OCF0A PGERS ISC01 EXTRF CS01 CAL1 WGM01 WGM11
TOIE0 TOV0 SPMEN ISC00 PORF CS00 CAL0 WGM00 WGM10 CS10
Page
Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page
Timer/Counter0 Output Compare Register PCIE1 PCIF1 PCIE0 PCIF0 OCIE0B OCF0B
CTPB RFLB PGWRT Timer/Counter0 Output Compare Register CAL4 COM0B0 COM1B0 WGM13 WDRF WGM02 CAL3 WGM12 CS12 BORF CS02 CAL2
CAL5 COM0B1 COM1B1
Timer/Counter0
CS11
Timer/Counter1 Counter Register High Byte Timer/Counter1 Counter Register Byte Timer/Counter1 Compare Register High Byte Timer/Counter1 Compare Register Byte Timer/Counter1 Compare Register High Byte Timer/Counter1 Compare Register Byte DWDR[7:0] CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPS0 Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte FOC1A WDIF EEAR7 PORTA7 DDA7 PINA7 FOC1B WDIE EEAR6 PORTA6 DDA6 PINA6 WDP3 EEAR5 EEPM1 PORTA5 DDA5 PINA5 WDCE EEAR4 EEPM0 PORTA4 DDA4 PINA4 PCINT11 EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 WDP2 PCINT10 EEAR2 EEMPE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 WDP1 PCINT9 EEAR1 EEPE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PSR10 WDP0 PCINT8 EEAR8 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0
Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page
EEPROM Data Register
General Purpose Register General Purpose Register General Purpose Register PCINT7 PCINT6 PCINT5 PCINT4 Buffer Register Data Register USISIF USISIE USIOIF USIOIE USIPF USIWM1 ICIE1 ICF1 USIDC USIWM0 REFS1 ADEN ACBG REFS0 ADSC MUX5 ADATE MUX4 ADIF ACIE MUX3 ADIE ACIC MUX2 ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 USICNT3 USICS1 USICNT2 USICS0 OCIE1B OCF1B USICNT1 USICLK OCIE1A OCF1A USICNT0 USITC TOIE1 TOV1 PCINT3 PCINT2 PCINT1 PCINT0
Page Page Page Page Page Page Page
Page Page Page Page Page
Data Register High Byte Data Register Byte ADC7D ACME ADC6D ADC5D ADLAR ADC4D ADC3D PRTIM1 ADC2D PRTIM0 ADC1D PRUSI ADC0D PRADC ADTS2 ADTS1 ADTS0
Page Page 138,Page Page
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
Note: compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Registers within address range 0x00 0x1F directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Some Status Flags cleared writing logical them. Note that, unlike most other AVRs, instructions will only operation specified bit, therefore used registers containing such Status Flags. instructions work with registers 0x00 0x1F only.
8006FS-AVR-02/07
Instruction Summary
Mnemonics
ADIW SUBI SBCI SBIW ANDI RJMP IJMP RCALL ICALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K
Operands
Rdl,K Rdl,K Rd,K Rd,K Registers
Description
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V
#Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Relative Jump Indirect Jump Relative Subroutine Call Indirect Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Register Clear Register Logical Shift Left Logical Shift Right Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl 0xFF 0x00 (0xFF 0xFF STACK STACK (Rr(b)=0) (Rr(b)=1) (P(b)=0) (P(b)=1) (SREG(s) then PCPC+k (SREG(s) then PCPC+k then then then then then then then then then then then then then then then then then then I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7)
BRANCH INSTRUCTIONS
BIT-TEST INSTRUCTIONS
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
Mnemonics
SWAP BSET BCLR DATA TRANSFER INSTRUCTIONS MOVW PUSH SLEEP BREAK Rd,Y+q Y+q,Rr Z+q,Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Load Program Memory Post-Inc Store Program Memory Port Port Push Register Stack Register from Stack Operation Sleep Watchdog Reset Break (see specific descr. Sleep function) (see specific descr. WDR/Timer) On-chip Debug Only Rd+1:Rd Rr+1:Rr (X), (Y), (Z), (Z), R1:R0 STACK STACK None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
Operands
Description
Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Flag Clear Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG Clear Half Carry Flag SREG
Operation
Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0.6 Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b)
Flags
Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None
#Clocks
CONTROL INSTRUCTIONS
8006FS-AVR-02/07
Ordering Information
ATtiny24
Speed (MHz) Power Supply 5.5V Ordering Code(1) ATtiny24V-10SSU ATtiny24V-10PU ATtiny24V-10MU ATtiny24-20SSU ATtiny24-20PU ATtiny24-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40°C 85°C)
Notes:
5.5V
Industrial (-40°C 85°C)
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
ATtiny44
Speed (MHz) Power Supply 5.5V Ordering Code(1) ATtiny44V-10SSU ATtiny44V-10PU ATtiny44V-10MU ATtiny44-20SSU ATtiny44-20PU ATtiny44-20MU Package(2) 14S1 14P3 20M1 14S1 14P3 20M1 Operational Range Industrial (-40°C 85°C)
Notes:
5.5V
Industrial (-40°C 85°C)
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
8006FS-AVR-02/07
ATtiny84
Speed (MHz) Power Supply 5.5V 5.5V Ordering Code(1) ATtiny84V-10PU ATtiny84V-10MU ATtiny84-20PU ATtiny84-20MU Package(2) 14P3 20M1 14P3 20M1 Operational Range Industrial (-40°C 85°C) Industrial (-40°C 85°C)
Notes:
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free packaging, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green.
Package Type 14S1 14P3 20M1 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 20-pad, Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
Packaging Information
20M1
SIDE VIEW
VIEW
Notch (0.20
0.08
SYMBOL
COMMON DIMENSIONS (Unit Measure 0.70 0.75 0.01 0.20 0.18 0.23 4.00 2.45 2.60 4.00 2.45 2.60 0.50 0.35 0.40 0.55 2.75 2.75 0.30 0.80 0.05 NOTE
BOTTOM VIEW
Note:
Reference JEDEC Standard MO-220, Fig. (SAW Singulation) WGGD-5.
10/27/04 2325 Orchard Parkway Jose, 95131 TITLE 20M1, 20-pad, Body, Lead Pitch 0.50 Exposed Pad, Micro Lead Frame Package (MLF) DRAWING 20M1 REV.
8006FS-AVR-02/07
14P3
SEATING PLANE
SYMBOL Notes: This package conforms JEDEC reference MS-001, Variation Dimensions include mold Flash Protrusion. Mold Flash Protrusion shall exceed 0.25 (0.010").
COMMON DIMENSIONS (Unit Measure 0.381 18.669 7.620 6.096 0.356 1.143 2.921 0.203 0.000 5.334 19.685 8.255 7.112 0.559 1.778 3.810 0.356 10.922 1.524 Note Note NOTE
2.540
11/02/05 2325 Orchard Parkway Jose, 95131 TITLE 14P3, 14-lead (0.300"/7.62 Wide) Plastic Dual Inline Package (PDIP) DRAWING 14P3 REV.
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
14S1
View
View
SYMBOL
COMMON DIMENSIONS (Unit Measure mm/inches) NOTE
1.35/0.0532 0.1/.0040 0.33/0.0130 8.55/0.3367 3.8/0.1497 5.8/0.2284 0.41/0.0160
1.27/0.050
1.75/0.0688 0.25/0.0098 0.5/0.0200 8.74/0.3444 3.99/0.1574 6.19/0.2440 1.27/0.0500
Side View
Notes:
This drawing general information only; refer JEDEC Drawing MS-012, Variation additional information. Dimension does include mold Flash, protrusions gate burrs. Mold Flash, protrusion gate burrs shall exceed 0.15 (0.006") side. Dimension does include inter-lead Flash protrusion. Inter-lead flash protrusions shall exceed 0.25 (0.010") side. length terminal soldering substrate. lead width measured 0.36 (0.014") greater above seating plane, shall exceed maximum value 0.61 (0.024") side.
2/5/02 TITLE
DRAWING 14S1, 14-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) 14S1
2325 Orchard Parkway Jose, 95131
REV.
8006FS-AVR-02/07
Errata
revision letter this section refers revision ATtiny24/44/84 device.
8.1.1
ATtiny24
Rev. known errata.
8.1.2
Rev. Reading EEPROM when system clock frequency below work Reading EEPROM when system clock frequency below work Reading data from EEPROM system clock frequency below result wrong data read. Problem Fix/Work around Avoid using EEPROM clock frequency below kHz.
8.1.3
Rev. EEPROM read from application code does work Lock Mode Reading EEPROM when system clock frequency below work EEPROM read from application code does work Lock Mode When Memory Lock Bits programmed mode EEPROM read does work from application code. Problem Fix/Work around Lock Protection Mode when application code needs read from EEPROM. Reading EEPROM when system clock frequency below work Reading data from EEPROM system clock frequency below result wrong data read. Problem Fix/Work around Avoid using EEPROM clock frequency below kHz.
8.1.4
Rev. sampled.
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
8.2.1
ATtiny44
Rev. known errata.
8.2.2
Rev. Reading EEPROM when system clock frequency below work Reading EEPROM when system clock frequency below work Reading data from EEPROM system clock frequency below result wrong data read. Problem Fix/Work around Avoid using EEPROM clock frequency below kHz.
8006FS-AVR-02/07
8.3.1
ATtiny84
Rev. known errata.
ATtiny24/44/84
8006FS-AVR-02/07
ATtiny24/44/84
Datasheet Revision History
02/07
Updated Figure page Figure page Figure 22-5 page 187. Updated Table 10-1 page Table 12-7 page Table 13-2 page Table 13-3 page Table 13-5 page Table 13-6 page Table 13-7 page Table 13-8 page Table 22-6 page 185, Table 22-8 page 187. Updated table references "TCCR0A Timer/Counter Control Register page Updated Port functions "Alternate Functions Port page Updated WDTCR name WDTCSR assembly code examples. Updated bit5 name Section 14.11.9 page 120. Updated bit5 Section 14.11.9 page 120. Updated "SPI Master Operation Example" page 126. Updated step "Enter High-voltage Serial Programming Mode" page 174.
09/06
characterization data moved "Electrical Characteristics" page 180. Register Descriptions gathered separate sections each chapter. Updated "System Control Reset" page Updated Table 13-3 page Table 13-6 page Table 13-8 page Table 14-2 page Table 14-4 page 116. Updated "Fast Mode" page 105. Updated Figure 14-7 page Figure 18-1 page 140. Updated "Analog Comparator Multiplexed Input" page 135. Added note Table 21-11 page 171. Updated "Electrical Characteristics" page 180. Updated "Typical Characteristics Preliminary Data" page 188.
08/06
Updated "Calibrated Internal Oscillator" page Updated "Oscillator Calibration Register OSCCAL" page Added Table 22-1 page 182. Updated code examples "SPI Master Operation Example" page 126. Updated code examples "SPI Slave Operation Example" page 127. Updated "Signature Bytes" page 167.
8006FS-AVR-02/07
07/06
Updated Features "USI Universal Serial Interface" page 123. Added "Clock speed considerations" page 130. Updated description "ADMUX Multiplexer Selection Register" page 151. Added note Table 20-1 page 163.
05/06
Updated "Default Clock Source" page Updated "Power Reduction Register" page Updated Table 22-3 page 183, Table page Table 18-3 page 151, Table 21-5 page 167, Table 21-11 page 171, Table 21-15 page 177, Table 22-6 page 185. Updated Features "Analog Digital Converter" page 139. Updated Operation "Analog Digital Converter" page 139. Updated "Temperature Measurement" page 150. Updated Characteristics "Electrical Characteristics" page 180. Updated "Typical Characteristics Preliminary Data" page 188. Updated "Errata" page 223.
12/05
Initial revision.
ATtiny24/44/84
8006FS-AVR-02/07
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8006FS-AVR-02/07
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