8-bit Microcontroller with Bytes In-System Programmable Flash ATtiny13

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8-bit Microcontroller with Bytes In-System Programmable Flash ATtiny13

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8-bit Microcontroller with Bytes In-System Programmable Flash ATtiny13V ATtiny13 Summary
Rev. 2535GS-AVR-01/07
Configurations
Figure Pinout ATtiny13
PDIP/SOIC
(PCINT5/RESET/ADC0/dW) (PCINT3/CLKI/ADC3) (PCINT4/ADC2) (SCK/ADC1/T0/PCINT2) (MISO/AIN1/OC0B/INT0/PCINT1) (MOSI/AIN0/OC0A/PCINT0)
QFN/MLF
(PCINT5/RESET/ADC0/dW) (PCINT3/CLKI/ADC3) (PCINT4/ADC2)
NOTE: Bottom should soldered ground. DNC: Connect
Overview
ATtiny13 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATtiny13 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed.
ATtiny13
2535GS-AVR-01/07
(SCK/ADC1/T0/PCINT2) (MISO/AIN1/OC0B/INT0/PCINT1) (MOSI/AIN0/OC0A/PCINT0)
ATtiny13
Block Diagram
Figure Block Diagram
8-BIT DATABUS
STACK POINTER
WATCHDOG OSCILLATOR
CALIBRATED INTERNAL OSCILLATOR
SRAM
WATCHDOG TIMER CONTROL REGISTER STATUS REGISTER TIMER/ COUNTER0
TIMING CONTROL
PROGRAM COUNTER PROGRAM FLASH
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
INTERRUPT UNIT PROGRAMMING LOGIC
INSTRUCTION DECODER
CONTROL LINES
DATA EEPROM
STATUS REGISTER
ANALOG COMPARATOR
DATA REGISTER PORT
DATA DIR. REG.PORT
PORT DRIVERS
RESET CLKI
PB0-PB5
2535GS-AVR-01/07
core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATtiny13 provides following features: byte In-System Programmable Flash, bytes EEPROM, bytes SRAM, general purpose lines, general purpose working registers, 8-bit Timer/Counter with compare modes, Internal External Interrupts, 4-channel, 10-bit ADC, programmable Watchdog Timer with internal Oscillator, three software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counter, ADC, Analog Comparator, Interrupt system continue functioning. Power-down mode saves register contents, disabling chip functions until next Interrupt Hardware Reset. Noise Reduction mode stops modules except ADC, minimize switching noise during conversions. device manufactured using Atmel's high density non-volatile memory technology. On-chip Flash allows Program memory re-programmed In-System through serial interface, conventional non-volatile memory programmer On-chip boot code running core. ATtiny13 supported with full suite program system development tools including: Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, Evaluation kits.
Descriptions
Port (PB5.PB0) Digital supply voltage. Ground. Port 6-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATtiny13 listed page RESET Reset input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given Table page Shorter pulses guaranteed generate reset.
ATtiny13
2535GS-AVR-01/07
ATtiny13
Register Summary
Address
0x3F 0x3E 0x3D 0x3C 0x3B 0x3A 0x39 0x38 0x37 0x36 0x35 0x34 0x33 0x32 0x31 0x30 0x2F 0x2E 0x2D 0x2C 0x2B 0x2A 0x29 0x28 0x27 0x26 0x25 0x24 0x23 0x22 0x21 0x20 0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10 0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
Name
SREG Reserved Reserved GIMSK GIFR TIMSK0 TIFR0 SPMCSR OCR0A MCUCR MCUSR TCCR0B TCNT0 OSCCAL Reserved TCCR0A DWDR Reserved Reserved Reserved Reserved OCR0B GTCCR Reserved CLKPR Reserved Reserved Reserved Reserved WDTCR Reserved Reserved EEARL EEDR EECR Reserved Reserved Reserved PORTB DDRB PINB PCMSK DIDR0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACSR ADMUX ADCSRA ADCH ADCL ADCSRB Reserved Reserved Reserved
SP[7:0]
Page
page page
FOC0A
INT0 INTF0 FOC0B
PCIE PCIF
CTPB
OCIE0B OCF0B RFLB WDRF WGM02
OCIE0A OCF0A PGWRT BORF CS02
TOIE0 TOV0 PGERS ISC01 EXTRF CS01
SELFPRGEN
page page page page page page page page page page page
Timer/Counter Output Compare Register ISC00 PORF CS00
Timer/Counter (8-bit) Oscillator Calibration Register COM0A1 COM0A0 COM0B1 COM0B0 DWDR[7:0] Timer/Counter Output Compare Register CLKPCE WDTIF WDTIE WDP3 WDCE EEPM1 EEPM0 PORTB5 DDB5 PINB5 PCINT5 ADC0D PORTB4 DDB4 PINB4 PCINT4 ADC2D ADEN ACBG REFS0 ADSC ADLAR ADATE ADIF ACIE ADIE ADPS2 ACIS1 MUX1 ADPS1 ACIS0 MUX0 ADPS0 PORTB3 DDB3 PINB3 PCINT3 ADC3D PORTB2 DDB2 PINB2 PCINT2 ADC1D PORTB1 DDB1 PINB1 PCINT1 AIN1D PORTB0 DDB0 PINB0 PCINT0 AIN0D EEPROM Address Register EEPROM Data Register EERIE EEMPE EEPE EERE WDP2 WDP1 WDP0 CLKPS3 CLKPS2 CLKPS1 CLKPS0 PSR10 WGM01 WGM00
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Data Register High Byte Data Register Byte ACME ADTS2 ADTS1 ADTS0
page
2535GS-AVR-01/07
Note:
compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Registers within address range 0x00 0x1F directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Some Status Flags cleared writing logical them. Note that, unlike most other AVRs, instructions will only operation specified bit, therefore used registers containing such Status Flags. instructions work with registers 0x00 0x1F only.
ATtiny13
2535GS-AVR-01/07
ATtiny13
Instruction Summary
Mnemonics
ADIW SUBI SBCI SBIW ANDI RJMP IJMP RCALL ICALL RETI CPSE SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd,Rr Rd,Rr Rd,Rr Rd,K
Operands
Rdl,K Rdl,K Rd,K Rd,K Registers
Description
Operation
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None None N,V,C,H N,V,C,H N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V
#Clocks
1/2/3 1/2/3 1/2/3 1/2/3 1/2/3
ARITHMETIC LOGIC INSTRUCTIONS with Carry Registers Immediate Word Subtract Registers Subtract Constant from Register Subtract with Carry Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical Registers Logical Register Constant Logical Registers Logical Register Constant Exclusive Registers One's Complement Two's Complement Bit(s) Register Clear Bit(s) Register Increment Decrement Test Zero Minus Clear Register Register Relative Jump Indirect Jump Relative Subroutine Call Indirect Call Subroutine Return Interrupt Return Compare, Skip Equal Compare Compare with Carry Compare Register with Immediate Skip Register Cleared Skip Register Skip Register Cleared Skip Register Branch Status Flag Branch Status Flag Cleared Branch Equal Branch Equal Branch Carry Branch Carry Cleared Branch Same Higher Branch Lower Branch Minus Branch Plus Branch Greater Equal, Signed Branch Less Than Zero, Signed Branch Half Carry Flag Branch Half Carry Flag Cleared Branch Flag Branch Flag Cleared Branch Overflow Flag Branch Overflow Flag Cleared Branch Interrupt Enabled Branch Interrupt Disabled Register Clear Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rdh:Rdl Rdh:Rdl Rdh:Rdl Rdh:Rdl 0xFF 0x00 (0xFF 0xFF STACK STACK (Rr(b)=0) (Rr(b)=1) (P(b)=0) (P(b)=1) (SREG(s) then PCPC+k (SREG(s) then PCPC+k then then then then then then then then then then then then then then then then then then I/O(P,b) I/O(P,b) Rd(n+1) Rd(n), Rd(0) Rd(n) Rd(n+1), Rd(7) Rd(0)C,Rd(n+1) Rd(n),CRd(7)
BRANCH INSTRUCTIONS
BIT-TEST INSTRUCTIONS
2535GS-AVR-01/07
Mnemonics
SWAP BSET BCLR
Operands
Arithmetic Shift Right Swap Nibbles Flag Flag Clear
Description
Rotate Right Through Carry
Operation
Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0.6 Rd(3.0)Rd(7.4),Rd(7.4)Rd(3.0) SREG(s) SREG(s) Rr(b) Rd(b) Rd+1:Rd Rr+1:Rr (X), (Y), (Z), (Z), R1:R0 STACK STACK
Flags
Z,C,N,V Z,C,N,V None SREG(s) SREG(s) None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
Store from Register load from Register Carry Clear Carry Negative Flag Clear Negative Flag Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Signed Test Flag Clear Signed Test Flag Twos Complement Overflow. Clear Twos Complement Overflow SREG Clear SREG Half Carry Flag SREG Clear Half Carry Flag SREG
DATA TRANSFER INSTRUCTIONS MOVW PUSH SLEEP BREAK Rd,Y+q Y+q,Rr Z+q,Rr Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect Post-Inc. Load Indirect Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect Post-Inc. Store Indirect Pre-Dec. Store Indirect with Displacement Store Direct SRAM Load Program Memory Load Program Memory Load Program Memory Post-Inc Store Program Memory Port Port Push Register Stack Register from Stack Operation Sleep Watchdog Reset Break (see specific descr. Sleep function) (see specific descr. WDR/Timer) On-chip Debug Only
CONTROL INSTRUCTIONS None None None
ATtiny13
2535GS-AVR-01/07
ATtiny13
Ordering Information
Speed (MHz)(3) Power Supply Ordering Code ATtiny13V-10PI ATtiny13V-10PU(2) ATtiny13V-10SI ATtiny13V-10SU(2) ATtiny13V-10SSI ATtiny13V-10SSU(2)I ATtiny13V-10MU(2) ATtiny13-20PI ATtiny13-20PU(2) ATtiny13-20SI ATtiny13-20SU(2) ATtiny13-20SSI ATtiny13-20SSU(2) ATtiny13-20MU(2) Package(1) S8S1 S8S1 20M1 S8S1 S8S1 20M1 Operation Range
Industrial (-40°C 85°C)
Industrial (-40°C 85°C)
Notes:
This device also supplied wafer form. Please contact your local Atmel sales office detailed ordering information minimum quantities. Pb-free packaging alternative, complies European Directive Restriction Hazardous Substances (RoHS directive). Also Halide free fully Green Speed VCC, "Maximum Speed VCC" page 122.
Package Type S8S1 20M1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.209" Wide, Plastic Small Outline Package (EIAJ SOIC) 8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC) 20-pad, Body, Lead Pitch 0.50 Micro Lead Frame Package (MLF)
2535GS-AVR-01/07
Packaging Information
View
View
SYMBOL
COMMON DIMENSIONS (Unit Measure inches) NOTE
0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 0.300 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
PLCS
0.325 0.280
Side View
0.150
Notes:
This drawing general information only; refer JEDEC Drawing MS-001, Variation additional information. Dimensions measured with package seated JEDEC seating plane Gauge GS-3. dimensions include mold Flash protrusions. Mold Flash protrusions shall exceed 0.010 inch. measured with leads constrained perpendicular datum. Pointed rounded lead tips preferred ease insertion. maximum dimensions include Dambar protrusions. Dambar protrusions shall exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway Jose, 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING REV.
ATtiny13
2535GS-AVR-01/07
ATtiny13
VIEW
VIEW
SYMBOL
COMMON DIMENSIONS (Unit Measure NOTE
1.70 0.05 0.35 0.15 5.13 5.18 7.70 0.51 1.27
2.16 0.25 0.48 0.35 5.35 5.40 8.26 0.85
SIDE VIEW
Notes:
This drawing general information only; refer EIAJ Drawing EDR-7320 additional information. Mismatch upper lower dies resin burrs included. recommended that upper lower cavities equal. they different, larger dimension shall regarded. Determines true geometric position. Values apply plated terminal. standard thickness plating layer shall measure between 0.007 .021
4/7/06 TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) DRAWING REV.
2325 Orchard Parkway Jose, 95131
2535GS-AVR-01/07
S8S1
View
SYMBOL COMMON DIMENSIONS (Unit Measure NOTE
5.79 3.81 1.35 4.80 0.17 0.31 1.27
6.20 3.99 1.75 0.25 4.98 0.25 0.51 1.27
Side View
View
Notes: This drawing general information only; refer JEDEC Drawing MS-012 proper dimensions, tolerances, datums,etc.
7/28/03 TITLE S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING REV.
2325 Orchard Parkway Jose, 95131
S8S1
ATtiny13
2535GS-AVR-01/07
ATtiny13
20M1
SIDE VIEW
VIEW
Notch (0.20
0.08
SYMBOL
COMMON DIMENSIONS (Unit Measure 0.70 0.75 0.01 0.20 0.18 0.23 4.00 2.45 2.60 4.00 2.45 2.60 0.50 0.35 0.40 0.55 2.75 2.75 0.30 0.80 0.05 NOTE
BOTTOM VIEW
Note:
Reference JEDEC Standard MO-220, Fig. (SAW Singulation) WGGD-5.
10/27/04 2325 Orchard Parkway Jose, 95131 TITLE 20M1, 20-pad, Body, Lead Pitch 0.50 Exposed Pad, Micro Lead Frame Package (MLF) DRAWING 20M1 REV.
2535GS-AVR-01/07
Errata
ATtiny13 Rev.
revision letter this section refers revision ATtiny13 device. EEPROM written below Volt EEPROM written below Volt Writing EEPROM below volts might fail. Problem Fix/Workaround write EEPROM when below volts.
ATtiny13 Rev.
Wrong values read after Erase Only operation High Voltage Serial Programming Flash, EEPROM, Fuse Lock Bits fail Device lock further programming debugWIRE communication blocked lock-bits Watchdog Timer Interrupt disabled EEPROM written below Volt
Wrong values read after Erase Only operation supply voltages below EEPROM location that erased Erase Only operation read programmed (0x00). Problem Fix/Workaround necessary read EEPROM location after Erase Only, Atomic Write operation with 0xFF data order erase location. case, Write Only operation used intended. Thus special considerations needed long erased location read before programmed. High Voltage Serial Programming Flash, EEPROM, Fuse Lock Bits fail Writing these locations bits some occasions fail. Problem Fix/Workaround After writing been initiated, always observe RDY/BSY signal. writing should fail, rewrite until RDY/BSY verifies correct writing. This will fixed revision Device lock further programming Special combinations fuse bits will lock device further programming effectively turning into device. following combinations settings/fuse bits will cause this effect: internal oscillator (CKSEL[1.0] 11), shortest start-up time (SUT[1.0] 00), Debugwire enabled (DWEN Reset disabled RSTDISBL internal oscillator (CKSEL[1.0] 10), shortest start-up time (SUT[1.0] 00), Debugwire enabled (DWEN Reset disabled RSTDISBL internal oscillator (CKSEL[1.0] 01), shortest start-up time (SUT[1.0] 00), Debugwire enabled (DWEN Reset disabled RSTDISBL
Problem fix/ Workaround Avoid above fuse combinations. Selecting longer start-up time will eliminate problem.
ATtiny13
2535GS-AVR-01/07
ATtiny13
debugWIRE communication blocked lock-bits When debugWIRE on-chip debug enabled (DWEN contents program memory EEPROM data memory read even lock-bits block further reading device. Problem fix/ Workaround ship products with on-chip debug tiny13 enabled. Watchdog Timer Interrupt disabled watchdog timer interrupt flag cleared before timeout occurs, watchdog will disabled, interrupt flag will automatically cleared. This only applicable interrupt only mode. Watchdog configured reset device watchdog time-out following interrupt, device works correctly. Problem Workaround Make sure there enough time always service first timeout event before watchdog timeout occurs. This done selecting long enough time-out period. EEPROM written below Volt Writing EEPROM below volts might fail. Problem Fix/Workaround write EEPROM when below volts.
ATtiny13 Rev.
Revision been sampled.
2535GS-AVR-01/07
Datasheet Revision History
Changes from Rev. 2535F-04/06 Rev. 2535G-01/07
Please note that referring page numbers this section referring this document. referring revision this section referring document revision.
Removed Preliminary. Updated Table page Table page 39,Table page 111. Removed Note from Table page Updated "Bit ACBG: Analog Comparator Bandgap Select" page Updated "Prescaling Conversion Timing" page Updated Figure page 111. Updated Characteristics" page 120. Updated "Ordering Information" page 163. Updated "Packaging Information" page 164.
Changes from Rev. 2535E-10/04 Rev. 2535F-04/06 Changes from Rev. 2535C-02/04 Rev. 2535D-04/04
Revision published.
Maximum Speed Grades changed 12MHz 10MHz 24MHz 20MHz Updated "Serial Programming Instruction Set" page 109. Updated "Maximum Speed VCC" page Updated "Ordering Information" page
Changes from Rev. 2535B-01/04 Rev. 2535C-02/04
C-code examples updated legal syntax. Replaced occurrences WDIF with WDTIF WDIE with WDTIE. Updated "Stack Pointer" page Updated "Calibrated Internal Oscillator" page Updated "Oscillator Calibration Register OSCCAL" page Updated typo introduction "Watchdog Timer" page Updated "ADC Conversion Time" page Updated "Serial Downloading" page 106. Updated "Electrical Characteristics" page 119. Updated "Ordering Information" page Removed rev. from "Errata" page
Changes from Rev. 2535A-06/03 Rev. 2535B-01/04
Updated Figure page Updated Table page Table page Table page Table page 121. Updated "Calibrated Internal Oscillator" page Updated whole "Watchdog Timer" page Updated Figure page Figure page 111.
ATtiny13
2535GS-AVR-01/07
ATtiny13
Updated registers "MCU Control Register MCUCR" page "Timer/Counter Control Register TCCR0B" page "Digital Input Disable Register DIDR0" page Updated Absolute Maximum Ratings Characteristics "Electrical Characteristics" page 119. Added "Maximum Speed VCC" page Updated "ADC Characteristics" page 123. Updated "Typical Characteristics" page 124. Updated "Ordering Information" page Updated "Packaging Information" page Updated "Errata" page Changed instances EEAR EEARL.
2535GS-AVR-01/07
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2535GS-AVR-01/07

8-bit Microcontroller with Bytes In-System Programmable Flash ATtiny13

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