8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable
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8-bit Microcontroller with 64K/128K/256K Bytes In-System Programmable Flash ATmega640/V ATmega1280/V ATmega1281/V ATmega2560/V ATmega2561/V Preliminary
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Configurations
Figure TQFP-pinout ATmega640/1280/2560
(ADC10/PCINT18) (ADC11/PCINT19) (ADC12/PCINT20) (ADC13/PCINT21) (ADC14/PCINT22) (ADC5/TMS) (ADC6/TDO) (ADC4/TCK) (ADC7/TDI) (ADC15/PCINT23) (ADC8/PCINT16) (ADC9/PCINT17)
(ADC1)
(ADC2)
(ADC0)
(ADC3)
(AD0)
(AD1)
(OC0B) (RXD0/PCINT8) (TXD0) (XCK0/AIN0) (OC3A/AIN1) (OC3B/INT4) (OC3C/INT5) (T3/INT6) (CLKO/ICP3/INT7) (RXD2) (TXD2) (XCK2) (OC4A) (OC4B) (OC4C) (OC2B) (SS/PCINT0) (SCK/PCINT1) (MOSI/PCINT2) (MISO/PCINT3) (OC2A/PCINT4) (OC1A/PCINT5) (OC1B/PCINT6)
(OC0A/OC1C/PCINT7)
(AD2)
AVCC
AREF
(AD3) (AD4) (AD5) (AD6) (AD7) (ALE) (PCINT15) (PCINT14) (PCINT13) (PCINT12) (XCK3/PCINT11) (TXD3/PCINT10) (RXD3/PCINT9) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (RD) (WR)
INDEX CORNER
ATmega640/1280/2560
(T4)
(TOSC2)
(TOSC1)
RESET
XTAL2
XTAL1
(ICP4)
(ICP5)
(T5)
(OC5A)
(OC5B)
(OC5C)
(SCL/INT0)
(SDA/INT1)
(RXD1/INT2)
(TXD1/INT3)
(ICP1)
(XCK1)
(T1)
(T0)
ATmega640/1280/1281/2560/2561
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ATmega640/1280/1281/2560/2561
Figure CBGA-pinout ATmega640/1280/2560
view
Bottom view
Table CBGA-pinout ATmega640/1280/2560.
AVCC AREF RESET XTAL2 XTAL1
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Figure Pinout ATmega1281/2561
(ADC6/TDO) (ADC4/TCK) (ADC5/TMS) (ADC7/TDI) (ADC0) (ADC1) (ADC2) (ADC3)
(AD0)
(AD1)
(OC0B) (RXD0/PCINT8/PDI) (TXD0/PDO) (XCK0/AIN0) (OC3A/AIN1) (OC3B/INT4) (OC3C/INT5) (T3/INT6) (ICP3/CLKO/INT7) (SS/PCINT0) (SCK/ PCINT1) (MOSI/ PCINT2) (MISO/ PCINT3) (OC2A/ PCINT4) (OC1A/PCINT5) (OC1B/PCINT6)
INDEX CORNER
(AD2)
AVCC
AREF
(AD3) (AD4) (AD5) (AD6) (AD7) (ALE) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (RD) (WR)
ATmega1281/2561
(T1)
(RXD1/INT2)
(SCL/INT0)
(TXD1/INT3)
(OC0A/OC1C/PCINT7)
(XCK1)
(ICP1)
Note:
large center underneath QFN/MLF package made metal internally connected GND. should soldered glued board ensure good mechanical stability. center left unconnected, package might loosen from board.
Disclaimer
Typical values contained this datasheet based simulations characterization other microcontrollers manufactured same process technology. Min. values will available after device characterized.
ATmega640/1280/1281/2560/2561
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(SDA/INT1)
(TOSC2)
(TOSC1)
(T0)
XTAL2
RESET
XTAL1
ATmega640/1280/1281/2560/2561
Overview
ATmega640/1280/1281/2560/2561 low-power CMOS 8-bit microcontroller based enhanced RISC architecture. executing powerful instructions single clock cycle, ATmega640/1280/1281/2560/2561 achieves throughputs approaching MIPS allowing system designer optimize power consumption versus processing speed.
Block Diagram
Figure Block Diagram
PF7.0
PK7.0
PJ7.0
PE7.0
RESET
Power Supervision RESET
PORT
PORT
PORT
PORT
Watchdog Timer
Watchdog Oscillator
JTAG
Converter
Analog Comparator
USART
XTAL1
Oscillator Circuits Clock Generation
EEPROM
Internal Bandgap reference
16bit
XTAL2
16bit
USART
PA7.0
PORT
16bit USART
PG5.0
PORT
XRAM
FLASH
SRAM
16bit
PC7.0
PORT
8bit
8bit
USART
NOTE: Shaded parts only available 100-pin version. Complete functionality ADC, T/C4, T/C5 only available 100-pin version.
PORT PORT PORT PORT
PD7.0
PB7.0
PH7.0
PL7.0
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core combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega640/1280/1281/2560/2561 provides following features: 64K/128K/256K bytes In-System Programmable Flash with Read-While-Write capabilities, bytes EEPROM, bytes SRAM, 54/86 general purpose lines, general purpose working registers, Real Time Counter (RTC), flexible Timer/Counters with compare modes PWM, USARTs, byte oriented 2-wire Serial Interface, 16-channel, 10bit with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, serial port, IEEE std. 1149.1 compliant JTAG test interface, also used accessing On-chip Debug system programming software selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counters, port, interrupt system continue functioning. Power-down mode saves register contents freezes Oscillator, disabling other chip functions until next interrupt Hardware Reset. Power-save mode, asynchronous timer continues run, allowing user maintain timer base while rest device sleeping. Noise Reduction mode stops modules except Asynchronous Timer ADC, minimize switching noise during conversions. Standby mode, Crystal/Resonator Oscillator running while rest device sleeping. This allows very fast start-up combined with power consumption. Extended Standby mode, both main Oscillator Asynchronous Timer continue run. device manufactured using Atmel's high-density nonvolatile memory technology. On-chip Flash allows program memory reprogrammed in-system through serial interface, conventional nonvolatile memory programmer, On-chip Boot program running core. boot program interface download application program application Flash memory. Software Boot Flash section will continue while Application Flash section updated, providing true Read-While-Write operation. combining 8-bit RISC with In-System Self-Program mable Flash monolithic Atmel ATmega640/1280/1281/2560/2561 powerful microcontroller that provides highly flexible cost effective solution many embedded control applications. ATmega640/1280/1281/2560/2561 supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, in-circuit emulators, evaluation kits.
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ATmega640/1280/1281/2560/2561
Comparison Between ATmega1281/2561 ATmega640/1280/2560
Each device ATmega640/1280/1281/2560/2561 family differs only memory size number pins. Table summarizes different configurations devices. Table Configuration Summary
Device ATmega640 ATmega1280 ATmega1281 ATmega2560 ATmega2561 Flash 64KB 128KB 128KB 256KB 256KB EEPROM General Purpose pins bits resolution channels Serial USARTs Channels
Descriptions
Port (PA7.PA0) Digital supply voltage. Ground. Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/1281/2560/2561 listed page Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port better driving capabilities than other ports. Port also serves functions various special features ATmega640/1280/1281/2560/2561 listed page Port (PC7.PC0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions special ATmega640/1280/1281/2560/2561 listed page Port (PD7.PD0) features
Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source
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current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/1281/2560/2561 listed page Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/1281/2560/2561 listed page Port (PF7.PF0) Port serves analog inputs Converter. Port also serves 8-bit bi-directional port, Converter used. Port pins provide internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. JTAG interface enabled, pull-up resistors pins PF7(TDI), PF5(TMS), PF4(TCK) will activated even reset occurs. Port also serves functions JTAG interface. Port (PG5.PG0) Port 6-bit port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/1281/2560/2561 listed page 105. Port (PH7.PH0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 107. Port (PJ7.PJ0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 109. Port (PK7.PK0) Port serves analog inputs Converter.
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ATmega640/1280/1281/2560/2561
Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 111. Port (PL7.PL0) Port 8-bit bi-directional port with internal pull-up resistors (selected each bit). Port output buffers have symmetrical drive characteristics with both high sink source capability. inputs, Port pins that externally pulled will source current pull-up resistors activated. Port pins tri-stated when reset condition becomes active, even clock running. Port also serves functions various special features ATmega640/1280/2560 listed page 113. RESET Reset input. level this longer than minimum pulse length will generate reset, even clock running. minimum pulse length given Table page Shorter pulses guaranteed generate reset. Input inverting Oscillator amplifier input internal clock operating circuit. Output from inverting Oscillator amplifier. AVCC supply voltage Port Converter. should externally connected VCC, even used. used, should connected through low-pass filter. This analog reference Converter.
XTAL1 XTAL2 AVCC
AREF
Resources
comprehensive development tools application notes, datasheets available download http://www.atmel.com/avr.
About Code Examples
This documentation contains simple code examples that briefly show various parts device. aware that compiler vendors include definitions header files interrupt handling compiler dependent. Please confirm with compiler documentation more details. These code examples assume that part specific header file included before compilation. registers located extended map, "IN", "OUT", "SBIS", "SBIC", "CBI", "SBI" instructions must replaced with instructions that allow access extended I/O. Typically "LDS" "STS" combined with "SBRS", "SBRC", "SBR", "CBR".
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Core
Introduction
This section discusses core architecture general. main function core ensure correct program execution. must therefore able access memories, perform calculations, control peripherals, handle interrupts. Figure Block Diagram Architecture
Architectural Overview
Data 8-bit
Flash Program Memory
Program Counter
Status Control
Instruction Register
General Purpose Registrers
Interrupt Unit Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
Control Lines
Analog Comparator
Module1
Data SRAM
Module
Module EEPROM
Lines
order maximize performance parallelism, uses Harvard architecture with separate memories buses program data. Instructions program memory executed with single level pipelining. While instruction being executed, next instruction pre-fetched from program memory. This concept enables instructions executed every clock cycle. program memory InSystem Reprogrammable Flash memory. fast-access Register File contains 8-bit general purpose working registers with single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. typical operation, operands output from Register File,
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operation executed, result stored back Register File clock cycle. registers used three 16-bit indirect address register pointers Data Space addressing enabling efficient address calculations. these address pointers also used address pointer look tables Flash program memory. These added function registers 16-bit Z-register, described later this section. supports arithmetic logic operations between registers between constant register. Single register operations also executed ALU. After arithmetic operation, Status Register updated reflect information about result operation. Program flow provided conditional unconditional jump call instructions, able directly address whole address space. Most instructions have single 16-bit word format. Every program memory address contains 32-bit instruction. Program Flash memory space divided sections, Boot Program section Application Program section. Both sections have dedicated Lock bits write read/write protection. instruction that writes into Application Flash memory section must reside Boot Program section. During interrupts subroutine calls, return address Program Counter (PC) stored Stack. Stack effectively allocated general data SRAM, consequently Stack size only limited total SRAM size usage SRAM. user programs must initialize Reset routine (before subroutines interrupts executed). Stack Pointer (SP) read/write accessible space. data SRAM easily accessed through five different addressing modes supported architecture. memory spaces architecture linear regular memory maps. flexible interrupt module control registers space with additional Global Interrupt Enable Status Register. interrupts have separate Interrupt Vector Interrupt Vector table. interrupts have priority accordance with their Interrupt Vector position. lower Interrupt Vector address, higher priority. memory space contains addresses peripheral functions Control Registers, SPI, other functions. Memory accessed directly, Data Space locations following those Register File, 0x20 0x5F. addition, ATmega640/1280/1281/2560/2561 Extended space from 0x60 0x1FF SRAM where only ST/STS/STD LD/LDS/LDD instructions used.
Arithmetic Logic Unit
high-performance operates direct connection with general purpose working registers. Within single clock cycle, arithmetic operations between general purpose registers between register immediate executed. operations divided into three main categories arithmetic, logical, bit-functions. Some implementations architecture also provide powerful multiplier supporting both signed/unsigned multiplication fractional format. "Instruction Set" section detailed description. Status Register contains information about result most recently executed arithmetic instruction. This information used altering program flow order perform conditional operations. Note that Status Register updated after operations, specified Instruction Reference. This will many cases
Status Register
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remove need using dedicated compare instructions, resulting faster more compact code. Status Register automatically stored when entering interrupt routine restored when returning from interrupt. This must handled software. SREG Status Register Status Register SREG defined
0x3F (0x5F) Read/Write Initial Value SREG
Global Interrupt Enable Global Interrupt Enable must interrupts enabled. individual interrupt enable control then performed separate control registers. Global Interrupt Enable Register cleared, none interrupts enabled independent individual interrupt enable settings. I-bit cleared hardware after interrupt occurred, RETI instruction enable subsequent interrupts. Ibit also cleared application with instructions, described instruction reference. Copy Storage Copy instructions (Bit LoaD) (Bit STore) T-bit source destination operated bit. from register Register File copied into instruction, copied into register Register File instruction. Half Carry Flag Half Carry Flag indicates Half Carry some arithmetic operations. Half Carry useful arithmetic. "Instruction Description" detailed information. Sign Bit,
S-bit always exclusive between Negative Flag Two's Complement Overflow Flag "Instruction Description" detailed information. Two's Complement Overflow Flag Two's Complement Overflow Flag supports two's complement arithmetics. "Instruction Description" detailed information. Negative Flag Negative Flag indicates negative result arithmetic logic operation. "Instruction Description" detailed information. Zero Flag Zero Flag indicates zero result arithmetic logic operation. "Instruction Description" detailed information. Carry Flag Carry Flag indicates carry arithmetic logic operation. "Instruction Description" detailed information.
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ATmega640/1280/1281/2560/2561
General Purpose Register File
Register File optimized Enhanced RISC instruction set. order achieve required performance flexibility, following input/output schemes supported Register File: 8-bit output operand 8-bit result input 8-bit output operands 8-bit result input 8-bit output operands 16-bit result input 16-bit output operand 16-bit result input
Figure shows structure general purpose working registers CPU. Figure General Purpose Working Registers
General Purpose Working Registers 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Byte X-register High Byte Y-register Byte Y-register High Byte Z-register Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 Addr. 0x00 0x01 0x02
Most instructions operating Register File have direct access registers, most them single cycle instructions. shown Figure page each register also assigned data memory address, mapping them directly into first locations user Data Space. Although being physically implemented SRAM locations, this memory organization provides great flexibility access registers, Z-pointer registers index register file.
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X-register, Y-register, Z-register
registers R26.R31 have some added functions their general purpose usage. These registers 16-bit address pointers indirect addressing data space. three indirect address registers defined described Figure Figure Z-registers
X-register (0x1B) (0x1A)
Y-register (0x1D) Z-register (0x1F)
(0x1C) (0x1E)
different addressing modes these address registers have functions fixed displacement, automatic increment, automatic decrement (see instruction reference details).
Stack Pointer
Stack mainly used storing temporary data, storing local variables storing return addresses after interrupts subroutine calls. Stack Pointer Register always points Stack. Note that Stack implemented growing from higher memory locations lower memory locations. This implies that Stack PUSH command decreases Stack Pointer. Stack Pointer points data SRAM Stack area where Subroutine Interrupt Stacks located. This Stack space data SRAM must defined program before subroutine calls executed interrupts enabled. Stack Pointer must point above 0x0200. initial value stack pointer last address internal SRAM. Stack Pointer decremented when data pushed onto Stack with PUSH instruction, decremented ATmega640/1280/1281 three ATmega2560/2561 when return address pushed onto Stack with subroutine call interrupt. Stack Pointer incremented when data popped from Stack with instruction, incremented ATmega640/1280/1281 three ATmega2560/2561 when data popped from Stack with return from subroutine return from interrupt RETI. Stack Pointer implemented 8-bit registers space. number bits actually used implementation dependent. Note that data space some implementations architecture small that only needed. this case, Register will present.
0x3E (0x5E) 0x3D (0x5D) SP15 Read/Write Initial Value SP14 SP13 SP12 SP11 SP10
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ATmega640/1280/1281/2560/2561
RAMPZ Extended Z-pointer Register ELPM/SPM
0x3B (0x5B) Read/Write Initial Value
RAMPZ7
RAMPZ6
RAMPZ5
RAMPZ4
RAMPZ3
RAMPZ2
RAMPZ1
RAMPZ0
RAMPZ
ELPM/SPM instructions, Z-pointer concatenation RAMPZ, shown Figure Note that affected RAMPZ setting. Figure Z-pointer used ELPM
Individually)
RAMPZ
(Z-pointer)
actual number bits implementation dependent. Unused bits implementation will always read zero. compatibility with future devices, sure write these bits zero. EIND Extended Indirect Register
0x3C (0x5C) Read/Write Initial Value
EIND7
EIND6
EIND5
EIND4
EIND3
EIND2
EIND1
EIND0 EIND
EICALL/EIJMP instructions, Indirect-pointer subroutine/routine concatenation EIND, shown Figure Note that ICALL IJMP affected EIND setting. Figure Indirect-pointer used EICALL EIJMP
(Individually)
EIND
(Indirectpointer)
actual number bits implementation dependent. Unused bits implementation will always read zero. compatibility with future devices, sure write these bits zero.
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Instruction Execution Timing
This section describes general access timing concepts instruction execution. driven clock clkCPU, directly generated from selected clock source chip. internal clock division used. Figure shows parallel instruction fetches instruction executions enabled Harvard architecture fast-access Register File concept. This basic pipelining concept obtain MIPS with corresponding unique results functions cost, functions clocks, functions power-unit. Figure Parallel Instruction Fetches Instruction Executions
clkCPU Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch
Figure shows internal timing concept Register File. single clock cycle operation using register operands executed, result stored back destination register. Figure Single Cycle Operation
clkCPU Total Execution Time Register Operands Fetch Operation Execute Result Write Back
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ATmega640/1280/1281/2560/2561
Reset Interrupt Handling
provides several different interrupt sources. These interrupts separate Reset Vector each have separate program vector program memory space. interrupts assigned individual enable bits which must written logic together with Global Interrupt Enable Status Register order enable interrupt. Depending Program Counter value, interrupts automatically disabled when Boot Lock bits BLB02 BLB12 programmed. This feature improves software security. section "Memory Programming" page details. lowest addresses program memory space default defined Reset Interrupt Vectors. complete list vectors shown "Interrupts" page list also determines priority levels different interrupts. lower address higher priority level. RESET highest priority, next INT0 External Interrupt Request Interrupt Vectors moved start Boot Flash section setting IVSEL Control Register (MCUCR). Refer "Interrupts" page more information. Reset Vector also moved start Boot Flash section programming BOOTRST Fuse, "Memory Programming" page 342. When interrupt occurs, Global Interrupt Enable I-bit cleared interrupts disabled. user software write logic I-bit enable nested interrupts. enabled interrupts then interrupt current interrupt routine. I-bit automatically when Return from Interrupt instruction RETI executed. There basically types interrupts. first type triggered event that sets Interrupt Flag. these interrupts, Program Counter vectored actual Interrupt Vector order execute interrupt handling routine, hardware clears corresponding Interrupt Flag. Interrupt Flags also cleared writing logic flag position(s) cleared. interrupt condition occurs while corresponding interrupt enable cleared, Interrupt Flag will remembered until interrupt enabled, flag cleared software. Similarly, more interrupt conditions occur while Global Interrupt Enable cleared, corresponding Interrupt Flag(s) will remembered until Global Interrupt Enable set, will then executed order priority. second type interrupts will trigger long interrupt condition present. These interrupts necessarily have Interrupt Flags. interrupt condition disappears before interrupt enabled, interrupt will triggered. When exits from interrupt, will always return main program execute more instruction before pending interrupt served. Note that Status Register automatically stored when entering interrupt routine, restored when returning from interrupt routine. This must handled software. When using instruction disable interrupts, interrupts will immediately disabled. interrupt will executed after instruction, even occurs simulta-
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neously with instruction. following example shows this used avoid interrupts during timed EEPROM write sequence. Assembly Code Example
r16, SREG store SREG value start EEPROM write restore SREG value (I-bit) disable interrupts during timed sequence
EECR, EEMPE EECR, EEPE SREG,
Code Example
char cSREG; cSREG SREG; store SREG value disable interrupts during timed sequence _disable_interrupt(); EECR (1<<EEMPE); start EEPROM write EECR (1<<EEPE); SREG cSREG; restore SREG value (I-bit)
When using instruction enable interrupts, instruction following will executed before pending interrupts, shown this example. Assembly Code Example
Global Interrupt Enable sleep enter sleep, waiting interrupt note: will enter sleep before pending interrupt(s)
Code Example
_enable_interrupt(); Global Interrupt Enable _sleep(); enter sleep, waiting interrupt note: will enter sleep before pending interrupt(s)
Interrupt Response Time
interrupt execution response enabled interrupts five clock cycles minimum. After five clock cycles program vector address actual interrupt handling routine executed. During these five clock cycle period, Program Counter pushed onto Stack. vector normally jump interrupt routine, this jump takes three clock cycles. interrupt occurs during execution multi-cycle instruction, this instruction completed before interrupt served. interrupt occurs when sleep mode, interrupt execution response time increased five clock cycles. This increase comes addition start-up time from selected sleep mode. return from interrupt handling routine takes five clock cycles. During these five clock cycles, Program Counter (three bytes) popped back from Stack, Stack Pointer incremented three, I-bit SREG set.
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Memories
This section describes different memories ATmega640/1280/1281/2560/2561. architecture main memory spaces, Data Memory Program Memory space. addition, ATmega640/1280/1281/2560/2561 features EEPROM Memory data storage. three memory spaces linear regular.
In-System Reprogrammable Flash Program Memory
ATmega640/1280/1281/2560/2561 contains 64K/128K/256K bytes On-chip In-System Reprogrammable Flash memory program storage, Table page Since instructions bits wide, Flash organized 32K/64K/128K software security, Flash Program memory space divided into sections, Boot Program section Application Program section. Flash memory endurance least 10,000 write/erase cycles. ATmega640/1280/1281/2560/2561 Program Counter (PC) 15/16/17 bits wide, thus addressing 32K/64K/128K program memory locations. operation Boot Program section associated Boot Lock bits software protection described detail "Boot Loader Support Read-While-Write Self-Programming" page 323. "Memory Programming" page contains detailed description Flash data serial downloading using pins JTAG interface. Constant tables allocated within entire program memory address space (see Load Program Memory instruction description ELPM Extended Load Program Memory instruction description). Timing diagrams instruction fetch execution presented "Instruction Execution Timing" page Table Program Flash Memory
Address (HEX) Application Flash Section
Boot Flash Section 0x7FFF/0xFFFF/0x1FFFF
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SRAM Data Memory
Table page shows ATmega640/1280/1281/2560/2561 SRAM Memory organized. ATmega640/1280/1281/2560/2561 complex microcontroller with more peripheral units than supported within location reserved Opcode instructions. Extended space from $060 $1FF SRAM, only ST/STS/STD LD/LDS/LDD instructions used. first 4,608/8,704 Data Memory locations address both Register File, Memory, Extended Memory, internal data SRAM. first locations address Register file, next location standard Memory, then locations Extended memory next 8,192 locations address internal data SRAM. optional external data SRAM used with ATmega640/1280/1281/2560/2561. This SRAM will occupy area remaining address locations address space. This area starts address following internal SRAM. Register file, I/O, Extended Internal SRAM occupies lowest 4,608/8,704 bytes, when using 64KB (65,536 bytes) External Memory, 60,478/56,832 Bytes External Memory available. "External Memory Interface" page details take advantage external memory map. When addresses accessing SRAM memory space exceeds internal data memory locations, external data SRAM accessed using same instructions internal data memory access. When internal data memories accessed, read write strobe pins (PG0 PG1) inactive during whole access cycle. External SRAM operation enabled setting XMCRA Register. Accessing external SRAM takes additional clock cycle byte compared access internal SRAM. This means that commands LDS, STS, LDD, STD, PUSH, take additional clock cycle. Stack placed external SRAM, interrupts, subroutine calls returns take three clock cycles extra because three-byte program counter pushed popped, external memory access does take advantage internal pipe-line memory access. When external SRAM interface used with wait-state, one-byte external access takes two, three, four additional clock cycles one, two, three wait-states respectively. Interrupts, subroutine calls returns will need five, seven, nine clock cycles more than specified instruction manual one, two, three wait-states. five different addressing modes data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, Indirect with Post-increment. Register file, registers feature indirect addressing pointer registers. direct addressing reaches entire data space. Indirect with Displacement mode reaches address locations from base address given Z-register. When using register indirect addressing modes with automatic pre-decrement postincrement, address registers decremented incremented. general purpose working registers, registers, 4,196/8,192 bytes internal data SRAM ATmega640/1280/1281/2560/2561 accessible through
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these addressing modes. Register File described "General Purpose Register File" page Table Data Memory
Address (HEX) 21FF 2200 Registers Registers External Registers Internal SRAM (8192 External SRAM
FFFF
Data Memory Access Times
This section describes general access timing concepts internal memory access. internal data SRAM access performed clkCPU cycles described Figure Figure On-chip Data SRAM Access Cycles
clkCPU Address Data Data
Compute Address Address valid
Memory Access Instruction
Next Instruction
Read
Write
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EEPROM Data Memory
ATmega640/1280/1281/2560/2561 contains bytes data EEPROM memory. organized separate data space, which single bytes read written. EEPROM endurance least 100,000 write/erase cycles. access between EEPROM described following, specifying EEPROM Address Registers, EEPROM Data Register, EEPROM Control Register. detailed description SPI, JTAG Parallel data downloading EEPROM, "Serial Downloading" page 356, "Programming JTAG Interface" page 361, "Programming EEPROM" page respectively.
EEPROM Read/Write Access
EEPROM Access Registers accessible space, "Register Description" page write access time EEPROM given Table page self-timing function, however, lets user software detect when next byte written. user code contains instructions that write EEPROM, some precautions must taken. heavily filtered power supplies, likely rise fall slowly powerup/down. This causes device some period time voltage lower than specified minimum clock frequency used. "Preventing EEPROM Corruption" page details avoid problems these situations. order prevent unintentional EEPROM writes, specific write procedure must followed. description EEPROM Control Register details this, "Register Description" page When EEPROM read, halted four clock cycles before next instruction executed. When EEPROM written, halted clock cycles before next instruction executed. calibrated Oscillator used time EEPROM accesses. Table lists typical programming time EEPROM access from CPU. Table EEPROM Programming Time
Symbol EEPROM write (from CPU) Number Calibrated Oscillator Cycles 26,368 Programming Time
following code examples show assembly function writing EEPROM. examples assume that interrupts controlled (e.g. disabling interrupts globally) that interrupts will occur during execution these functions. examples also assume that Flash Boot Loader present software. such code present, EEPROM write function must also wait ongoing command finish.
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Assembly Code Example()
EEPROM_write: Wait completion previous write sbic EECR,EEPE rjmp EEPROM_write address (r18:r17) address register EEARH, EEARL, EEDR,r16 EECR,EEMPE EECR,EEPE
Write data (r16) Data Register Write logical EEMPE Start eeprom write setting EEPE
Code Example(1)
void EEPROM_write(unsigned uiAddress, unsigned char ucData) Wait completion previous write while(EECR (1<<EEPE)) address Data Registers EEAR uiAddress; EEDR ucData; Write logical EEMPE EECR (1<<EEMPE); Start eeprom write setting EEPE EECR (1<<EEPE);
Note:
"About Code Examples" page
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next code examples show assembly functions reading EEPROM. examples assume that interrupts controlled that interrupts will occur during execution these functions. Assembly Code Example(1)
EEPROM_read: Wait completion previous write sbic EECR,EEPE rjmp EEPROM_read address (r18:r17) address register EEARH, EEARL, EECR,EERE r16,EEDR
Start eeprom read writing EERE Read data from Data Register
Code Example(1)
unsigned char EEPROM_read(unsigned uiAddress) Wait completion previous write while(EECR (1<<EEPE)) address register EEAR uiAddress; Start eeprom read writing EERE EECR (1<<EERE); Return data from Data Register return EEDR;
Note:
"About Code Examples" page
Preventing EEPROM Corruption
During periods VCC, EEPROM data corrupted because supply voltage EEPROM operate properly. These issues same board level systems using EEPROM, same design solutions should applied. EEPROM data corruption caused situations when voltage low. First, regular write sequence EEPROM requires minimum voltage operate correctly. Secondly, itself execute instructions incorrectly, supply voltage low. EEPROM data corruption easily avoided following this design recommendation: Keep RESET active (low) during periods insufficient power supply voltage. This done enabling internal Brown-out Detector (BOD). detection level internal does match needed detection level, external reset Protection circuit used. reset occurs while write operation progress, write operation will completed provided that power supply voltage sufficient.
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Memory
space definition ATmega640/1280/1281/2560/2561 shown "Register Summary" page 416. ATmega640/1280/1281/2560/2561 I/Os peripherals placed space. locations accessed LD/LDS/LDD ST/STS/STD instructions, transferring data between general purpose working registers space. Registers within address range 0x00 0x1F directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Refer instruction section more details. When using specific commands OUT, addresses 0x00 0x3F must used. When addressing Registers data space using instructions, 0x20 must added these addresses. ATmega640/1280/1281/2560/2561 complex microcontroller with more peripheral units than supported within location reserved Opcode instructions. Extended space from 0x60 0x1FF SRAM, only ST/STS/STD LD/LDS/LDD instructions used. compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Some Status Flags cleared writing logical them. Note that, unlike most other AVRs, instructions will only operate specified bit, therefore used registers containing such Status Flags. instructions work with registers 0x00 0x1F only. peripherals control registers explained later sections. General Purpose Registers ATmega640/1280/1281/2560/2561 contains three General Purpose Registers. These registers used storing information, they particularly useful storing global variables Status Flags. General Purpose Registers within address range 0x00 0x1F directly bit-accessible using SBI, CBI, SBIS, SBIC instructions. "Register Description" page
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External Memory Interface
With features External Memory Interface provides, well suited operate interface memory devices such External SRAM Flash, peripherals such LCD-display, A/D, D/A. main features are: Four different wait-state settings (including wait-state). Independent wait-state setting different External Memory sectors (configurable sector
size)
number bits dedicated address high byte selectable keepers data lines minimize current consumption (optional) Overview When eXternal MEMory (XMEM) enabled, address space outside internal SRAM becomes available using dedicated External Memory pins (see Figure page Table page Table page Table page 105). memory configuration shown Figure Figure External Memory with Sector Select
Memory Configuration 0x0000
Internal memory
0x21FF 0x2200 Lower sector SRW01 SRW00
SRL[2.0] External Memory (0-60K Upper sector
SRW11 SRW10
0xFFFF
Using External Memory Interface
interface consists AD7:0: Multiplexed low-order address data bus. A15:8: High-order address (configurable number bits). ALE: Address latch enable. Read strobe. Write strobe.
control bits External Memory Interface located registers, External Memory Control Register XMCRA, External Memory Control Register XMCRB. When XMEM interface enabled, XMEM interface will override setting data direction registers that corresponds ports dedicated XMEM interface.
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details about port override, alternate functions section "I/O-Ports" page XMEM interface will auto-detect whether access internal external. access external, XMEM interface will output address, data, control signals ports according Figure (this figure shows wave forms without wait-states). When goes from high-to-low, there valid address AD7:0. during data transfer. When XMEM interface enabled, also internal access will cause activity address, data ports, strobes will toggle during internal access. When External Memory Interface disabled, normal data direction settings used. Note that when XMEM interface disabled, address space above internal SRAM boundary mapped into internal SRAM. Figure illustrates connect external SRAM using octal latch (typically 573" equivalent) which transparent when high. Address Latch Requirements high-speed operation XRAM interface, address latch must selected with care system frequencies above 2.7V. When operating conditions above these frequencies, typical style 74HC series latch becomes inadequate. External Memory Interface designed compliance 74AHC series latch. However, most latches used long they comply with main timing parameters. main parameters address latch are: propagation delay (tPD). Data setup time before (tSU). Data (address) hold time after (TH).
External Memory Interface designed guaranty minimum address hold time after asserted Refer tLAXX_LD/tLLAXX_ST "External Data Memory Timing" Tables through Tables pages 387. D-to-Q propagation delay (tPD) must taken into consideration when calculating access time requirement external component. data setup time before must exceed address valid (tAVLLC) minus wiring delay (dependent capacitive load). Figure External SRAM Connected
SRAM
D[7:0]
AD7:0
A[7:0]
A15:8
A[15:8]
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Pull-up Bus-keeper
pull-ups AD7:0 ports activated corresponding Port register written one. reduce power consumption sleep mode, recommended disable pull-ups writing Port register zero before entering sleep. XMEM interface also provides bus-keeper AD7:0 lines. bus-keeper disabled enabled software described "XMCRB External Memory Control Register page When enabled, bus-keeper will keep previous value AD7:0 while these lines tri-stated XMEM interface.
Timing
External Memory devices have different timing requirements. meet these requirements, XMEM interface provides four different wait-states shown Table important consider timing specification External Memory device before selecting wait-state. most important parameters access time external memory compared set-up requirement. access time External Memory defined time from receiving chip select/address until data this address actually driven bus. access time cannot exceed time from pulse must asserted until data stable during read sequence (See tLLRL+ tRLRH tDVRH Tables through Tables pages 387). different wait-states software. additional feature, possible divide external memory space sectors with individual wait-state settings. This makes possible connect different memory devices with different timing requirements same XMEM interface. XMEM interface timing details, please refer Table Table Figure Figure "External Data Memory Timing" page 385. Note that XMEM interface asynchronous that waveforms following figures related internal system clock. skew between internal external clock (XTAL1) guarantied (varies between devices temperature, supply voltage). Consequently, XMEM interface suited synchronous operation. Figure External Data Memory Cycles without Wait-state (SRWn1=0 SRWn0=0)
System Clock (CLKCPU
A15:8
Prev. addr.
Address
DA7:0 (XMBK
Prev. data
Address
Data
Read
DA7:0 (XMBK
Prev. data
Address
XXXXX
Data
XXXXXXXX
Note:
SRWn1 SRW11 (upper sector) SRW01 (lower sector), SRWn0 SRW10 (upper sector) SRW00 (lower sector). pulse period only present next instruction accesses (internal external).
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Write
DA7:0
Prev. data
Address
Data
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Figure External Data Memory Cycles with SRWn1 SRWn0 1(1)
System Clock (CLKCPU
A15:8
Prev. addr.
Address
DA7:0 (XMBK
Prev. data
Address
Data
DA7:0 (XMBK
Prev. data
Address
Data
Note:
SRWn1 SRW11 (upper sector) SRW01 (lower sector), SRWn0 SRW10 (upper sector) SRW00 (lower sector). pulse period only present next instruction accesses (internal external).
Figure External Data Memory Cycles with SRWn1 SRWn0 0(1)
System Clock (CLKCPU
A15:8
Prev. addr.
Address
DA7:0 (XMBK
Prev. data
Address
Data
DA7:0 (XMBK
Prev. data
Address
Data
Note:
SRWn1 SRW11 (upper sector) SRW01 (lower sector), SRWn0 SRW10 (upper sector) SRW00 (lower sector). pulse period only present next instruction accesses (internal external).
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Read
Write
DA7:0
Prev. data
Address
Data
Read
Write
DA7:0
Prev. data
Address
Data
Figure External Data Memory Cycles with SRWn1 SRWn0 1(1)
System Clock (CLKCPU
A15:8
Prev. addr.
Address
DA7:0
Prev. data
Address
Data
DA7:0 (XMBK
Prev. data
Address
Data
DA7:0 (XMBK
Prev. data
Address
Data
Note:
SRWn1 SRW11 (upper sector) SRW01 (lower sector), SRWn0 SRW10 (upper sector) SRW00 (lower sector). pulse period only present next instruction accesses (internal external).
Using Locations External Memory Smaller than
Since external memory mapped after internal memory shown Figure external memory addressed when addressing first 8,704 bytes data space. appear that first 8,704 bytes external memory inaccessible (external memory addresses 0x0000 0x21FF). However, when connecting external memory smaller than example these locations easily accessed simply addressing from address 0x8000 0xA1FF. Since External Memory Address connected external memory, addresses 0x8000 0xA1FF will appear addresses 0x0000 0x21FF external memory. Addressing above address 0xA1FF recommended, since this will address external memory location that already accessed another (lower) address. Application software, external memory will appear linear address space from 0x2200 0xA1FF. This illustrated Figure Figure Address with External Memory
Memory External SRAM
0x0000 Internal Memory 0x21FF 0x2200
0x0000
0x7FFF 0x8000
External Memory
0x7FFF
0x90FF 0x9100
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Read
Write
ATmega640/1280/1281/2560/2561
Using 64KB Locations External Memory Since External Memory mapped after Internal Memory shown Figure only 56KB External Memory available default (address space 0x0000 0x21FF reserved internal memory). However, possible take advantage entire External Memory masking higher address bits zero. This done using XMMn bits control software most significant bits address. setting Port output 0x00, releasing most significant bits normal Port operation, Memory Interface will address 0x0000 0x2FFF. following code examples. Care must exercised using this option most memory masked away. Assembly Code Example(1)
OFFSET defined 0x4000 ensure external memory access Configure Port (address high byte) output 0x00 when pins released normal Port operation
r16, 0xFF DDRC, r16, 0x00 PORTC, release PC7:6 r16, (1<<XMM1) XMCRB, write 0xAA address 0x0001 external memory r16, 0xaa 0x0001+OFFSET, re-enable PC7:6 external memory r16, (0<<XMM1) XMCRB, store 0x55 address (OFFSET external memory r16, 0x55 0x0001+OFFSET,
Code Example(1)
#define OFFSET 0x4000 void XRAM_example(void) unsigned char (unsigned char (OFFSET DDRC 0xFF; PORTC 0x00; XMCRB (1<<XMM1); 0xaa; XMCRB 0x00; 0x55;
Note:
"About Code Examples" page
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Register Description
EEPROM registers EEARH EEARL EEPROM Address Register
0x22 (0x42) 0x21 (0x41)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR11 EEAR3
EEAR10 EEAR2
EEAR9 EEAR1
EEAR8 EEAR0 EEARH EEARL
Read/Write
Initial Value
Bits 15:12 Res: Reserved Bits These bits reserved bits will always read zero. Bits 11:0 EEAR8:0: EEPROM Address EEPROM Address Registers EEARH EEARL specify EEPROM address bytes EEPROM space. EEPROM data bytes addressed linearly between 4096. initial value EEAR undefined. proper value must written before EEPROM accessed. EEDR EEPROM Data Register
0x20 (0x40) Read/Write Initial Value
EEDR
Bits EEDR7:0: EEPROM Data EEPROM write operation, EEDR Register contains data written EEPROM address given EEAR Register. EEPROM read operation, EEDR contains data read from EEPROM address given EEAR. EECR EEPROM Control Register
0x1F (0x3F) Read/Write Initial Value
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE EECR
Bits Res: Reserved Bits These bits reserved bits will always read zero. Bits EEPM1 EEPM0: EEPROM Programming Mode Bits EEPROM Programming mode setting defines which programming action that will triggered when writing EEPE. possible program data atomic operation (erase value program value) split Erase Write operations different operations. Programming times different modes shown Table While EEPE set, write EEPMn will ignored. During reset, EEPMn bits will reset 0b00 unless EEPROM busy programming.
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Table EEPROM Mode Bits
EEPM1 EEPM0 Programming Time Operation Erase Write operation (Atomic Operation) Erase Only Write Only Reserved future
EERIE: EEPROM Ready Interrupt Enable Writing EERIE enables EEPROM Ready Interrupt SREG set. Writing EERIE zero disables interrupt. EEPROM Ready interrupt generates constant interrupt when EEPE cleared. EEMPE: EEPROM Master Programming Enable EEMPE determines whether setting EEPE causes EEPROM written. When EEMPE set, setting EEPE within four clock cycles will write data EEPROM selected address EEMPE zero, setting EEPE will have effect. When EEMPE been written software, hardware clears zero after four clock cycles. description EEPE EEPROM write procedure. EEPE: EEPROM Programming Enable EEPROM Write Enable Signal EEPE write strobe EEPROM. When address data correctly EEPE must written write value into EEPROM. EEMPE must written before logical written EEPE, otherwise EEPROM write takes place. following procedure should followed when writing EEPROM (the order steps essential): Wait until EEPE becomes zero. Wait until SPMEN SPMCSR becomes zero. Write EEPROM address EEAR (optional). Write EEPROM data EEDR (optional). Write logical EEMPE while writing zero EEPE EECR. Within four clock cycles after setting EEMPE, write logical EEPE. EEPROM programmed during write Flash memory. software must check that Flash programming completed before initiating EEPROM write. Step only relevant software contains Boot Loader allowing program Flash. Flash never being updated CPU, step omitted. "Memory Programming" page details about Boot programming. Caution: interrupt between step step will make write cycle fail, since EEPROM Master Write Enable will time-out. interrupt routine accessing EEPROM interrupting another EEPROM access, EEAR EEDR Register will modified, causing interrupted EEPROM access fail. recommended have Global Interrupt Flag cleared during steps avoid these problems. When write access time elapsed, EEPE cleared hardware. user software poll this wait zero before writing next byte. When EEPE been set, halted cycles before next instruction executed.
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EERE: EEPROM Read Enable EEPROM Read Enable Signal EERE read strobe EEPROM. When correct address EEAR Register, EERE must written logic trigger EEPROM read. EEPROM read access takes instruction, requested data available immediately. When EEPROM read, halted four cycles before next instruction executed. user should poll EEPE before starting read operation. write operation progress, neither possible read EEPROM, change EEAR Register. General Purpose registers GPIOR2 General Purpose Register
0x2B (0x4B) Read/Write Initial Value
GPIOR2
GPIOR1 General Purpose Register
0x2A (0x4A) Read/Write Initial Value
GPIOR1
GPIOR0 General Purpose Register
0x1E (0x3E) Read/Write Initial Value
GPIOR0
External Memory registers XMCRA External Memory Control Register
"(0x74)" Read/Write Initial Value
SRL2
SRL1
SRL0
SRW11
SRW10
SRW01
SRW00 XMCRA
SRE: External SRAM/XMEM Enable Writing enables External Memory Interface.The functions AD7:0, A15:8, ALE, activated alternate functions. overrides direction settings respective data direction registers. Writing zero, disables External Memory Interface normal data direction settings used. SRL2:0: Wait-state Sector Limit possible configure different wait-states different External Memory addresses. external memory address space divided sectors that have separate wait-state bits. SRL2, SRL1, SRL0 bits select split sectors, Table Figure default, SRL2, SRL1, SRL0 bits zero entire external memory address space treated sector. When entire SRAM
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address space configured sector, wait-states configured SRW11 SRW10 bits. Table Sector limits with different settings SRL2:0
SRL2 SRL1 SRL0 Sector Limits Lower sector Upper sector 0x2200 0xFFFF Lower sector 0x2200 0x3FFF Upper sector 0x4000 0xFFFF Lower sector 0x2200 0x5FFF Upper sector 0x6000 0xFFFF Lower sector 0x2200 0x7FFF Upper sector 0x8000 0xFFFF Lower sector 0x2200 0x9FFF Upper sector 0xA000 0xFFFF Lower sector 0x2200 0xBFFF Upper sector 0xC000 0xFFFF Lower sector 0x2200 0xDFFF Upper sector 0xE000 0xFFFF
SRW11, SRW10: Wait-state Select Bits Upper Sector SRW11 SRW10 bits control number wait-states upper sector external memory address space, Table SRW01, SRW00: Wait-state Select Bits Lower Sector SRW01 SRW00 bits control number wait-states lower sector external memory address space, Table Table Wait States(1)
SRWn1 Note: SRWn0 Wait States wait-states Wait cycle during read/write strobe Wait cycles during read/write strobe
Wait cycles during read/write wait cycle before driving address (lower/upper sector). further details timing wait-states External Memory Interface, Figures through Figures setting bits affects timing.
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XMCRB External Memory Control Register
(0x75) Read/Write Initial Value
XMBK
XMM2
XMM1
XMM0 XMCRB
XMBK: External Memory Bus-keeper Enable Writing XMBK enables keeper AD7:0 lines. When keeper enabled, AD7:0 will keep last driven value lines even XMEM interface tri-stated lines. Writing XMBK zero disables keeper. XMBK qualified with SRE, even XMEM interface disabled, keepers still activated long XMBK one. Res: Reserved Bits These bits reserved will always read zero. When writing this address location, write these bits zero compatibility with future devices. XMM2, XMM1, XMM0: External Memory High Mask When External Memory enabled, Port pins default used high address byte. full 60KB address space required access External Memory, some, all, Port pins released normal Port function described Table described "Using 64KB Locations External Memory" page possible XMMn bits access 64KB locations External Memory. Table Port Pins Released Normal Port Pins when External Memory Enabled
XMM2 XMM1 XMM0 Bits External Memory Address (Full 56KB space) Address high bits Released Port Pins None Full Port
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System Clock Clock Options
Overview
This section describes clock options microcontroller.
Figure presents principal clock systems their distribution. clocks need active given time. order reduce power consumption, clocks modules being used halted using different sleep modes, described "Power Management Sleep Modes" page clock systems detailed below. Figure Clock Distribution
Asynchronous Timer/Counter General Modules Core Flash EEPROM
clkADC clkI/O clkASY clkCPU clkFLASH
Clock Control Unit
Reset Logic
Watchdog Timer
Source clock System Clock Prescaler
Watchdog clock Watchdog Oscillator
Clock Multiplexer
Timer/Counter Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated Oscillator
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Clock Systems their Distribution
Clock clkCPU clock routed parts system concerned with operation core. Examples such modules General Purpose Register File, Status Register data memory holding Stack Pointer. Halting clock inhibits core from performing general operations calculations. clock used majority modules, like Timer/Counters, SPI, USART. clock also used External Interrupt module, note that some external interrupts detected asynchronous logic, allowing such interrupts detected even clock halted. Also note that start condition detection module carried asynchronously when clkI/O halted, address recognition sleep modes. Flash clock controls operation Flash interface. Flash clock usually active simultaneously with clock. Asynchronous Timer clock allows Asynchronous Timer/Counter clocked directly from external clock external clock crystal. dedicated clock domain allows using this Timer/Counter real-time counter even when device sleep mode. provided with dedicated clock domain. This allows halting clocks order reduce noise generated digital circuitry. This gives more accurate conversion results.
Clock clkI/O
Flash Clock clkFLASH
Asynchronous Timer Clock clkASY
Clock clkADC
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Clock Sources
device following clock source options, selectable Flash Fuse bits shown below. clock from selected source input clock generator, routed appropriate modules. Table Device Clocking Options Select(1)
Device Clocking Option Power Crystal Oscillator Full Swing Crystal Oscillator Frequency Crystal Oscillator Internal Oscillator Calibrated Internal Oscillator External Clock Reserved Note: CKSEL3:0 1111 1000 0111 0110 0101 0100 0011 0010 0000 0001
fuses means unprogrammed while means programmed.
Default Clock Source
device shipped with internal oscillator with fuse CKDIV8 programmed, resulting system clock. startup time maximum time-out period enabled. (CKSEL "0010", "10", CKDIV8 "0"). default setting ensures that users make their desired clock source setting using available programming interface. clock source needs sufficient start oscillating minimum number oscillating cycles before considered stable. ensure sufficient VCC, device issues internal reset with time-out delay (tTOUT) after device reset released other reset sources. "On-chip Debug System" page describes start conditions internal reset. delay (tTOUT) timed from Watchdog Oscillator number cycles delay SUTx CKSELx fuse bits. selectable delays shown Table frequency Watchdog Oscillator voltage dependent shown "Typical Characteristics" page 390. Table Number Watchdog Oscillator Cycles
Time-out (VCC 5.0V) Time-out (VCC 3.0V) Number Cycles (8,192)
Clock Start-up Sequence
Main purpose delay keep reset until supplied with minimum Vcc. delay will monitor actual voltage will required select delay longer than rise time. this possible, internal external Brown-Out Detection circuit should used. circuit will ensure sufficient before releases reset, time-out delay disabled. Disabling time-out delay without utilizing Brown-Out Detection circuit recommended. oscillator required oscillate minimum number cycles before clock considered stable. internal ripple counter monitors oscillator output clock, keeps internal reset active given number clock cycles. reset then released device will start execute. recommended oscillator start-up time
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dependent clock type, varies from cycles externally applied clock cycles frequency crystal. start-up sequence clock includes both time-out delay start-up time when device starts from reset. When starting from Power-save Powerdown mode, assumed sufficient level only start-up time included.
Power Crystal Oscillator
Pins XTAL1 XTAL2 input output, respectively, inverting amplifier which configured On-chip Oscillator, shown Figure Either quartz crystal ceramic resonator used. This Crystal Oscillator power oscillator, with reduced voltage swing XTAL2 output. gives lowest power consumption, capable driving other clock inputs, more susceptible noise noisy environments. these cases, refer "Full Swing Crystal Oscillator" page should always equal both crystals resonators. optimal value capacitors depends crystal resonator use, amount stray capacitance, electromagnetic noise environment. Some initial guidelines choosing capacitors with crystals given Table ceramic resonators, capacitor values given manufacturer should used. Figure Crystal Oscillator Connections
XTAL2 XTAL1
Power Oscillator operate three different modes, each optimized specific frequency range. operating mode selected fuses CKSEL3:1 shown Table Table Power Crystal Oscillator Operating Modes(3)
Frequency Range(1) (MHz) 16.0(4) Notes: CKSEL3:1 100(2) Recommended Range Capacitors (pF)
frequency ranges preliminary values. Actual values TBD. This option should used with crystals, only with ceramic resonators. frequency exceeds specification device (depends VCC), CKDIV8 Fuse programmed order divide internal frequency must ensured that resulting divided clock meets frequency specification device.
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frequency when using ceramic oscillator MHz.
CKSEL0 Fuse together with SUT1:0 Fuses select start-up times shown Table Table Start-up Times Power Crystal Oscillator Clock Selection
Oscillator Source Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: Start-up Time from Power-down Power-save Additional Delay from Reset (VCC 5.0V) 14CK ms(1) 14CK ms(1) 14CK(2) 14CK ms(2) 14CK ms(2) 14CK 14CK 14CK
CKSEL0
SUT1:0
These options should only used when operating close maximum frequency device, only frequency stability start-up important application. These options suitable crystals. These options intended with ceramic resonators will ensure frequency stability start-up. They also used with crystals when operating close maximum frequency device, frequency stability start-up important application.
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Full Swing Crystal Oscillator
Pins XTAL1 XTAL2 input output, respectively, inverting amplifier which configured On-chip Oscillator, shown Figure Either quartz crystal ceramic resonator used. This Crystal Oscillator full swing oscillator, with rail-to-rail swing XTAL2 output. This useful driving other clock inputs noisy environments. current consumption higher than "Low Power Crystal Oscillator" page Note that Full Swing Crystal Oscillator will only operate volts. should always equal both crystals resonators. optimal value capacitors depends crystal resonator use, amount stray capacitance, electromagnetic noise environment. Some initial guidelines choosing capacitors with crystals given Table ceramic resonators, capacitor values given manufacturer should used. operating mode selected fuses CKSEL3:1 shown Table Table Full Swing Crystal Oscillator operating modes(2)
Frequency Range(1) (MHz) Notes: CKSEL3:1 Recommended Range Capacitors (pF)
frequency ranges preliminary values. Actual values TBD. frequency exceeds specification device (depends VCC), CKDIV8 Fuse programmed order divide internal frequency must ensured that resulting divided clock meets frequency specification device.
Figure Crystal Oscillator Connections
XTAL2 XTAL1
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Table Start-up Times Full Swing Crystal Oscillator Clock Selection
Oscillator Source Power Conditions Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Ceramic resonator, enabled Ceramic resonator, fast rising power Ceramic resonator, slowly rising power Crystal Oscillator, enabled Crystal Oscillator, fast rising power Crystal Oscillator, slowly rising power Notes: Start-up Time from Power-down Power-save Additional Delay from Reset (VCC 5.0V) 14CK
CKSEL0
SUT1:0
14CK ms(1) 14CK(2) 14CK ms(2) 14CK ms(2) 14CK 14CK 14CK
These options should only used when operating close maximum frequency device, only frequency stability start-up important application. These options suitable crystals. These options intended with ceramic resonators will ensure frequency stability start-up. They also used with crystals when operating close maximum frequency device, frequency stability start-up important application.
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Frequency Crystal Oscillator
device utilize 32.768 watch crystal clock source dedicated Frequency Crystal Oscillator. crystal should connected shown Figure When this Oscillator selected, start-up times determined Fuses CKSEL0 shown Table Table Start-up Times Frequency Crystal Oscillator Clock Selection
Start-up Time from Power-down Power-save Reserved enabled Fast rising power Slowly rising power Reserved Note: 14CK 14CK 14CK Additional Delay from Reset (VCC 5.0V) 14CK
Power Conditions enabled Fast rising power Slowly rising power
CKSEL0
SUT1:0
14CK ms(1) 14CK
These options should only used frequency stability start-up important application.
Calibrated Internal Oscillator
defaylt, Internal Oscillator provides approximate clock. Though voltage temperature dependent, this clock very accurately calibrated user. Table page "Internal Oscillator Speed" page more details. device shipped with CKDIV8 Fuse programmed. "System Clock Prescaler" page more details. This clock selected system clock programming CKSEL Fuses shown Table selected, will operate with external components. During reset, hardware loads pre-programmed calibration value into OSCCAL Register thereby automatically calibrates Oscillator. accuracy this calibration shown Factory calibration Table page 384. changing OSCCAL register from "OSCCAL Oscillator Calibration Register" page possible higher calibration accuracy than using factory calibration. accuracy this calibration shown User calibration Table page 384. When this Oscillator used chip clock, Watchdog Oscillator will still used Watchdog Timer Reset Time-out. more information preprogrammed calibration value, section "Calibration Byte" page 345. Table Internal Calibrated Oscillator Operating Modes(1)(3)
Frequency Range(2) (MHz) Notes: CKSEL3:0 0010
device shipped with this option selected. frequency ranges preliminary values. Actual values TBD. frequency exceeds specification device (depends VCC), CKDIV8 Fuse programmed order divide internal frequency
When this Oscillator selected, start-up times determined Fuses shown Table page
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Table Start-up times internal calibrated Oscillator clock selection
Power Conditions enabled Fast rising power Slowly rising power Start-up Time from Powerdown Power-save Reserved Note: device shipped with this option selected. Additional Delay from Reset (VCC 5.0V) 14CK 14CK 14CK ms(1) SUT1:0
Internal Oscillator
internal Oscillator power Oscillator providing clock kHz. frequency nominal 25°C. This clock select system clock programming CKSEL Fuses "11" shown Table Table Internal Oscillator Operating Modes
Nominal Frequency Note: frequency preliminary value. Actual value TBD. CKSEL3:0 0011
When this clock source selected, start-up times determined Fuses shown Table Table Start-up Times Internal Oscillator
Power Conditions enabled Fast rising power Slowly rising power Start-up Time from Powerdown Power-save Reserved Additional Delay from Reset 14CK 14CK 14CK SUT1:0
External Clock
drive device from external clock source, XTAL1 should driven shown Figure device external clock, CKSEL Fuses must programmed "0000". Figure External Clock Drive Configuration
XTAL2
EXTERNAL CLOCK SIGNAL
XTAL1
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When this clock source selected, start-up times determined Fuses shown Table Table Crystal Oscillator Clock Frequency
Nominal Frequency CKSEL3:0 0000
Table Start-up Times External Clock Selection
Power Conditions enabled Fast rising power Slowly rising power Start-up Time from Powerdown Power-save Reserved Additional Delay from Reset (VCC 5.0V) 14CK 14CK 14CK SUT1:0
When applying external clock, required avoid sudden changes applied clock frequency ensure stable operation MCU. variation frequency more than from clock cycle next lead unpredictable behavior. changes more than required, ensure that kept Reset during changes. Note that System Clock Prescaler used implement run-time changes internal clock frequency while still ensuring stable operation. Refer "System Clock Prescaler" page details.
Clock Output Buffer
device output system clock CLKO pin. enable output, CKOUT Fuse programmed. This mode suitable when chip clock used drive other circuits system. clock also will output during reset, normal operation will overridden when fuse programmed. clock source, including internal Oscillator, selected when clock output CLKO. System Clock Prescaler used, divided system clock that output. device operate Timer/Counter2 from external 32.768 watch crystal external clock source. Figure page crystal connection. Applying external clock source TOSC1 requires EXCLK ASSR Register written logic one. "Asynchronous Operation Timer/Counter2" page further description selecting external clock input instead crystal.
Timer/Counter Oscillator
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System Clock Prescaler
ATmega640/1280/1281/2560/2561 system clock prescaler, system clock divided setting "CLKPR Clock Prescale Register" page This feature used decrease system clock frequency power consumption when requirement processing power low. This used with clock source options, will affect clock frequency synchronous peripherals. clkI/O, clkADC, clkCPU, clkFLASH divided factor shown Table When switching between prescaler settings, System Clock Prescaler ensures that glitches occurs clock system. also ensures that intermediate frequency higher than neither clock frequency corresponding previous setting, clock frequency corresponding setting. ripple counter that implements prescaler runs frequency undivided clock, which faster than CPU's clock frequency. Hence, possible determine state prescaler even were readable, exact time takes switch from clock division other cannot exactly predicted. From time CLKPS values written, takes between before clock frequency active. this interval, active clock edges produced. Here, previous clock period, period corresponding prescaler setting. avoid unintentional changes clock frequency, special write procedure must followed change CLKPS bits: Write Clock Prescaler Change Enable (CLKPCE) other bits CLKPR zero. Within four cycles, write desired value CLKPS while writing zero CLKPCE. Interrupts must disabled when changing prescaler setting make sure write procedure interrupted.
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Register Description
OSCCAL Oscillator Calibration Register
(0x66) Read/Write Initial Value CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL
Device Specific Calibration Value
Bits CAL7:0: Oscillator Calibration Value Oscillator Calibration Register used trim Calibrated Internal Oscillator remove process variations from oscillator frequency. pre-programmed calibration value automatically written this register during chip reset, giving Factory calibrated frequency specified Table page 384. application software write this register change oscillator frequency. oscillator calibrated frequencies specified Table page 384. Calibration outside that range guaranteed. Note that this oscillator used time EEPROM Flash write accesses, these write times will affected accordingly. EEPROM Flash written, calibrate more than MHz. Otherwise, EEPROM Flash write fail. CAL7 determines range operation oscillator. Setting this gives lowest frequency range, setting this gives highest frequency range. frequency ranges overlapping, other words setting OSCCAL 0x7F gives higher frequency than OSCCAL 0x80. CAL6.0 bits used tune frequency within selected range. setting 0x00 gives lowest frequency that range, setting 0x7F gives highest frequency range. CLKPR Clock Prescale Register
(0x61) Read/Write Initial Value
CLKPCE
CLKPS3
CLKPS2
CLKPS1
CLKPS0 CLKPR
Description
CLKPCE: Clock Prescaler Change Enable CLKPCE must written logic enable change CLKPS bits. CLKPCE only updated when other bits CLKPR simultaneously written zero. CLKPCE cleared hardware four cycles after written when CLKPS bits written. Rewriting CLKPCE within this time-out period does neither extend time-out period, clear CLKPCE bit. Bits CLKPS3:0: Clock Prescaler Select Bits These bits define division factor between selected clock source internal system clock. These bits written run-time vary clock frequency suit application requirements. divider divides master clock input MCU, speed synchronous peripherals reduced when division factor used. division factors given Table CKDIV8 Fuse determines initial value CLKPS bits. CKDIV8 unprogrammed, CLKPS bits will reset "0000". CKDIV8 programmed, CLKPS bits reset "0011", giving division factor start This feature should used selected clock source higher frequency than maximum frequency
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device present operating conditions. Note that value written CLKPS bits regardless CKDIV8 Fuse setting. Application software must ensure that sufficient division factor chosen selected clock source higher frequency than maximum frequency device present operating conditions. device shipped with CKDIV8 Fuse programmed.
Table Clock Prescaler Select
CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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Power Management Sleep Modes
Sleep Modes
Sleep modes enable application shut down unused modules MCU, thereby saving power. provides various sleep modes allowing user tailor power consumption application's requirements. Figure page presents different clock systems ATmega640/1280/1281/2560/2561, their distribution. figure helpful selecting appropriate sleep mode. Table shows different sleep modes their wake-up sources.
Table Active Clock Domains Wake-up Sources Different Sleep Modes.
Active Clock Domains Oscillators
Address Match INT7:0 Change
Wake-up Sources
SPM/ EEPROM Ready Interrupt
Main Clock Source Enabled
Timer Enabled
Sleep Mode Idle ADCNRM Power-down Power-save Standby
X(2)
X(3)
X(2)
X(3)
Extended Standby Notes: Only recommended with external crystal resonator selected clock source. Timer/Counter2 running asynchronous mode. INT7:4, only level interrupt.
enter sleep modes, "SMCR Sleep Mode Control Register" page must written logic SLEEP instruction must executed. SM2, SM1, bits SMCR Register select which sleep mode will activated SLEEP instruction. Table page summary. enabled interrupt occurs while sleep mode, wakes then halted four cycles addition start-up time, executes interrupt routine, resumes execution from instruction following SLEEP. contents Register File SRAM unaltered when device wakes from sleep. reset occurs during sleep mode, wakes executes from Reset Vector.
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Other
clkFLASH
Timer2
clkADC
clkCPU
clkASY
clkIO
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Idle Mode
When SM2:0 bits written 000, SLEEP instruction makes enter Idle mode, stopping allowing SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, interrupt system continue operating. This sleep mode basically halts clkCPU clkFLASH, while allowing other clocks run. Idle mode enables wake from external triggered interrupts well internal ones like Timer Overflow USART Transmit Complete interrupts. wake-up from Analog Comparator interrupt required, Analog Comparator powered down setting Analog Comparator Control Status Register ACSR. This will reduce power consumption Idle mode. enabled, conversion starts automatically when this mode entered.
Noise Reduction Mode
When SM2:0 bits written 001, SLEEP instruction makes enter Noise Reduction mode, stopping allowing ADC, external interrupts, 2-wire Serial Interface address match, Timer/Counter2 Watchdog continue operating enabled). This sleep mode basically halts clkI/O, clkCPU, clkFLASH, while allowing other clocks run. This improves noise environment ADC, enabling higher resolution measurements. enabled, conversion starts automatically when this mode entered. Apart form Conversion Complete interrupt, only External Reset, Watchdog System Reset, Watchdog interrupt, Brown-out Reset, 2-wire serial interface interrupt, Timer/Counter2 interrupt, SPM/EEPROM ready interrupt, external level interrupt INT7:4 change interrupt wakeup from Noise Reduction mode.
Power-down Mode
When SM2:0 bits written 010, SLEEP instruction makes enter Power-down mode. this mode, external Oscillator stopped, while external interrupts, 2-wire Serial Interface, Watchdog continue operating enabled). Only External Reset, Watchdog Reset, Brown-out Reset, 2-wire Serial Interface address match, external level interrupt INT7:4, external interrupt INT3:0, change interrupt wake MCU. This sleep mode basically halts generated clocks, allowing operation asynchronous modules only. Note that level triggered interrupt used wake-up from Power-down mode, changed level must held some time wake MCU. Refer "External Interrupts" page details. When waking from Power-down mode, there delay from wake-up condition occurs until wake-up becomes effective. This allows clock restart become stable after having been stopped. wake-up period defined same CKSEL Fuses that define Reset Time-out period, described "Clock Sources" page
Power-save Mode
When SM2:0 bits written 011, SLEEP instruction makes enter Power-save mode. This mode identical Power-down, with exception: Timer/Counter2 enabled, will keep running during sleep. device wake from either Timer Overflow Output Compare event from Timer/Counter2 corresponding Timer/Counter2 interrupt enable bits TIMSK2, Global Interrupt Enable SREG set. Timer/Counter2 running, Power-down mode recommended instead Powersave mode.
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Timer/Counter2 clocked both synchronously asynchronously Powersave mode. Timer/Counter2 using asynchronous clock, Timer/Counter Oscillator stopped during sleep. Timer/Counter2 using synchronous clock, clock source stopped during sleep. Note that even synchronous clock running Power-save, this clock only available Timer/Counter2.
Standby Mode
When SM2:0 bits external crystal/resonator clock option selected, SLEEP instruction makes enter Standby mode. This mode identical Power-down with exception that Oscillator kept running. From Standby mode, device wakes clock cycles.
Extended Standby Mode
When SM2:0 bits external crystal/resonator clock option selected, SLEEP instruction makes enter Extended Standby mode. This mode identical Power-save mode with exception that Oscillator kept running. From Extended Standby mode, device wakes clock cycles.Power Reduction Register Power Reduction Register (PRR), "PRR0 Power Reduction Register page "PRR1 Power Reduction Register page provides method stop clock individual peripherals reduce power consumption. current state peripheral frozen registers read written. Resources used peripheral when stopping clock will remain occupied, hence peripheral should most cases disabled before stopping clock. Waking module, which done clearing PRR, puts module same state before shutdown. Module shutdown used Idle mode Active mode significantly reduce overall power consumption. "Supply Current modules" page examples. other sleep modes, clock already stopped.
Minimizing Power Consumption
There several issues consider when trying minimize power consumption controlled system. general, sleep modes should used much possible, sleep mode should selected that possible device's functions operating. functions needed should disabled. particular, following modules need special consideration when trying achieve lowest possible power consumption. enabled, will enabled sleep modes. save power, should disabled before entering sleep mode. When turned again, next conversion will extended conversion. Refer "ADC Analog Digital Converter" page details operation. When entering Idle mode, Analog Comparator should disabled used. When entering Noise Reduction mode, Analog Comparator should disabled. other sleep modes, Analog Comparator automatically disabled. However, Analog Comparator Internal Voltage Reference input, Analog Comparator should disabled sleep modes. Otherwise, Internal Voltage Reference will enabled, independent sleep mode. Refer Analog Comparator" page details configure Analog Comparator.
Analog Digital Converter
Analog Comparator
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Brown-out Detector Brown-out Detector needed application, this module should turned off. Brown-out Detector enabled BODLEVEL Fuses, will enabled sleep modes, hence, always consume power. deeper sleep modes, this will contribute significantly total current consumption. Refer "Brown-out Detection" page details configure Brown-out Detector. Internal Voltage Reference will enabled when needed Brown-out Detection, Analog Comparator ADC. these modules disabled described sections above, internal voltage reference will disabled will consuming power. When turned again, user must allow reference start before output used. reference kept sleep mode, output used immediately. Refer "Internal Voltage Reference" page details start-up time. Watchdog Timer needed application, module should turned off. Watchdog Timer enabled, will enabled sleep modes, hence, always consume power. deeper sleep modes, this will contribute significantly total current consumption. Refer "Interrupts" page details configure Watchdog Timer. When entering sleep mode, port pins should configured minimum power. most important then ensure that pins drive resistive loads. sleep modes where both clock (clkI/O) clock (clkADC) stopped, input buffers device will disabled. This ensures that power consumed input logic when needed. some cases, input logic needed detecting wake-up conditions, will then enabled. Refer section "Digital Input Enable Sleep Modes" page details which pins enabled. input buffer enabled input signal left floating have analog signal level close VCC/2, input buffer will excessive power. analog input pins, digital input buffer should disabled times. analog signal level close VCC/2 input cause significant current even active mode. Digital input buffers disabled writing Digital Input Disable Registers (DIDR2, DIDR1 DIDR0). Refer "DIDR2 Digital Input Disable Register page 300, "DIDR1 Digital Input Disable Register page "DIDR0 Digital Input Disable Register page details. On-chip Debug System On-chip debug system enabled OCDEN Fuse chip enters sleep mode, main clock source enabled, hence, always consumes power. deeper sleep modes, this will contribute significantly total current consumption. There three alternative ways disable system: Disable OCDEN Fuse. Disable JTAGEN Fuse. Write MCUCR.
Internal Voltage Reference
Watchdog Timer
Port Pins
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Register Description
SMCR Sleep Mode Control Register Sleep Mode Control Register contains control bits power management.
0x33 (0x53) Read/Write Initial Value SMCR
Bits SM2:0: Sleep Mode Select Bits These bits select between five available sleep modes shown Table Table Sleep Mode Select
Note: Sleep Mode Idle Noise Reduction Power-down Power-save Reserved Reserved Standby(1) Extended Standby(1)
Standby modes only recommended with external crystals resonators.
Sleep Enable must written logic make enter sleep mode when SLEEP instruction executed. avoid entering sleep mode unless programmer's purpose, recommended write Sleep Enable (SE) just before execution SLEEP instruction clear immediately after waking
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PRR0 Power Reduction Register
(0x64) Read/Write Initial Value
PRTWI
PRTIM2
PRTIM0
PRTIM1
PRSPI
PRUSART0
PRADC PRR0
PRTWI: Power Reduction Writing logic this shuts down stopping clock module. When waking again, should initialized ensure proper operation. PRTIM2: Power Reduction Timer/Counter2 Writing logic this shuts down Timer/Counter2 module synchronous mode (AS2 When Timer/Counter2 enabled, operation will continue like before shutdown. PRTIM0: Power Reduction Timer/Counter0 Writing logic this shuts down Timer/Counter0 module. When Timer/Counter0 enabled, operation will continue like before shutdown. Res: Reserved This reserved will always read zero. PRTIM1: Power Reduction Timer/Counter1 Writing logic this shuts down Timer/Counter1 module. When Timer/Counter1 enabled, operation will continue like before shutdown. PRSPI: Power Reduction Serial Peripheral Interface Writing logic this shuts down Serial Peripheral Interface stopping clock module. When waking again, should initialized ensure proper operation. PRUSART0: Power Reduction USART0 Writing logic this shuts down USART0 stopping clock module. When waking USART0 again, USART0 should initialized ensure proper operation. PRADC: Power Reduction Writing logic this shuts down ADC. must disabled before shut down. analog comparator cannot input when shut down.
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PRR1 Power Reduction Register
(0x65) Read/Write Initial Value
PRTIM5
PRTIM4
PRTIM3
PRUSART3
PRUSART2
PRUSART1 PRR1
Res: Reserved bits These bits reserved will always read zero. PRTIM5: Power Reduction Timer/Counter5 Writing logic this shuts down Timer/Counter5 module. When Timer/Counter5 enabled, operation will continue like before shutdown. PRTIM4: Power Reduction Timer/Counter4 Writing logic this shuts down Timer/Counter4 module. When Timer/Counter4 enabled, operation will continue like before shutdown. PRTIM3: Power Reduction Timer/Counter3 Writing logic this shuts down Timer/Counter3 module. When Timer/Counter3 enabled, operation will continue like before shutdown. PRUSART3: Power Reduction USART3 Writing logic this shuts down USART3 stopping clock module. When waking USART3 again, USART3 should initialized ensure proper operation. PRUSART2: Power Reduction USART2 Writing logic this shuts down USART2 stopping clock module. When waking USART2 again, USART2 should initialized ensure proper operation. PRUSART1: Power Reduction USART1 Writing logic this shuts down USART1 stopping clock module. When waking USART1 again, USART1 should initialized ensure proper operation.
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System Control Reset
Resetting During reset, Registers their initial values, program starts execution from Reset Vector. instruction placed Reset Vector must Absolute Jump instruction reset handling routine. program never enables interrupt source, Interrupt Vectors used, regular program code placed these locations. This also case Reset Vector Application section while Interrupt Vectors Boot section vice versa. circuit diagram Figure shows reset logic. Table defines electrical parameters reset circuitry. ports immediately reset their initial state when reset source goes active. This does require clock source running. After reset sources have gone inactive, delay counter invoked, stretching internal reset. This allows power reach stable level before normal operation starts. time-out period delay counter defined user through CKSEL Fuses. different selections delay period presented "Clock Sources" page Reset Sources ATmega640/1280/1281/2560/2561 five sources reset: Power-on Reset. reset when supply voltage below Power-on Reset threshold (VPOT). External Reset. reset when level present RESET longer than minimum pulse length. Watchdog Reset. reset when Watchdog Timer period expires Watchdog enabled. Brown-out Reset. reset when supply voltage below Brown-out Reset threshold (VBOT) Brown-out Detector enabled. JTAG Reset. reset long there logic Reset Register, scan chains JTAG system. Refer section "IEEE 1149.1 (JTAG) Boundary-scan" page details.
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Figure Reset Logic
DATA
Status Register (MCUSR)
PORF BORF EXTRF WDRF JTRF
Power-on Reset Circuit
BODLEVEL [2.0] Pull-up Resistor
SPIKE FILTER
Brown-out Reset Circuit
JTAG Reset Register
Watchdog Oscillator
Clock Generator
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
Table Reset Characteristics(1)
Symbol Parameter Power-on Reset Threshold Voltage (rising) VPOT Power-on Reset Threshold Voltage (falling)(2) RESET Threshold Voltage Minimum pulse width RESET Condition Units
VRST tRST Notes:
Values guidelines only. Actual values TBD. Power-on Reset will work unless supply voltage been below VPOT (falling)
Power-on Reset
Power-on Reset (POR) pulse generated On-chip detection circuit. detection level defined Table activated whenever below detection level. circuit used trigger start-up Reset, well detect failure supply voltage. Power-on Reset (POR) circuit ensures that device reset from Power-on. Reaching Power-on Reset threshold voltage invokes delay counter, which determines long device kept RESET after rise. RESET signal activated again, without delay, when decreases below detection level.
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Figure Start-up, RESET Tied
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure Start-up, RESET Extended Externally
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
External Reset
External Reset generated level RESET pin. Reset pulses longer than minimum pulse width (see Table will generate reset, even clock running. Shorter pulses guaranteed generate reset. When applied signal reaches Reset Threshold Voltage VRST positive edge, delay counter starts after Time-out period tTOUT expired. Figure External Reset During Operation
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Brown-out Detection
ATmega640/1280/1281/2560/2561 On-chip Brown-out Detection (BOD) circuit monitoring level during operation comparing fixed trigger level. trigger level selected BODLEVEL Fuses. trigger level hysteresis ensure spike free Brown-out Detection. hysteresis detection level should interpreted VBOT+ VBOT VHYST/2 VBOT- VBOT VHYST/2. Table BODLEVEL Fuse Coding(1)
BODLEVEL Fuses Reserved Note: VBOT below nominal minimum operating voltage some devices. devices where this case, device tested down VBOT during production test. This guarantees that Brown-Out Reset will occur before drops voltage where correct operation microcontroller longer guaranteed. test performed using BODLEVEL operation BODLEVEL operation ATmega640/1280/1281, BODLEVEL operation ATmega640/1280/1281/2560/2561. VBOT VBOT VBOT Units
Disabled
Table Brown-out Characteristics
Symbol VHYST tBOD Parameter Brown-out Detector Hysteresis Pulse Width Brown-out Reset Units
When enabled, decreases value below trigger level (VBOTin Figure 28), Brown-out Reset immediately activated. When increases above trigger level (VBOT+ Figure 28), delay counter starts after Timeout period tTOUT expired. circuit will only detect drop voltage stays below trigger level longer than tBOD given Table Figure Brown-out Reset During Operation
VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
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Watchdog Reset When Watchdog times out, will generate short reset pulse cycle duration. falling edge this pulse, delay timer starts counting Time-out period tTOUT. "Watchdog Timer" page details operation Watchdog Timer. Figure Watchdog Reset During Operation
Internal Voltage Reference
Voltage Reference Enable Signals Start-up Time
ATmega640/1280/1281/2560/2561 features internal bandgap reference. This reference used Brown-out Detection, used input Analog Comparator ADC. voltage reference start-up time that influence should used. start-up time given Table save power, reference always turned reference during following situations: When enabled programming BODLEVEL [2:0] Fuse). When bandgap reference connected Analog Comparator setting ACBG ACSR). When enabled. Thus, when enabled, after setting ACBG enabling ADC, user must always allow reference start before output from Analog Comparator used. reduce power consumption Power-down mode, user avoid three conditions above ensure that reference turned before entering Power-down mode. Table Internal Voltage Reference Characteristics(1)
Symbol Note: Parameter Bandgap reference voltage Bandgap reference start-up time Bandgap reference current consumption Condition Units
Values guidelines only. Actual values TBD.
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Watchdog Timer
ATmega640/1280/1281/2560/2561 Enhanced Watchdog Timer (WDT). main features are: Clocked from separate On-chip Oscillator Operating modes
Interrupt System Reset Interrupt System Reset Selectable Time-out period from 16ms Possible Hardware fuse Watchdog always (WDTON) fail-safe mode
Figure Watchdog Timer
128kHz OSCILLATOR
OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K
WATCHDOG RESET
WDP0 WDP1 WDP2 WDP3
RESET
WDIF INTERRUPT
WDIE
Watchdog Timer (WDT) timer counting cycles separate on-chip oscillator. gives interrupt system reset when counter reaches given time-out value. normal operation mode, required that system uses Watchdog Timer Reset instruction restart counter before time-out value reached. system doesn't restart counter, interrupt system reset will issued. Interrupt mode, gives interrupt when timer expires. This interrupt used wake device from sleep-modes, also general system timer. example limit maximum time allowed certain operations, giving interrupt when operation longer than expected. System Reset mode, gives reset when timer expires. This typically used prevent system hang-up case runaway code. third mode, Interrupt System Reset mode, combines other modes first giving interrupt then switch System Reset mode. This mode will instance allow safe shutdown saving critical parameters before system reset. Watchdog always (WDTON) fuse, programmed, will force Watchdog Timer System Reset mode. With fuse programmed System Reset mode (WDE) Interrupt mode (WDIE) locked respectively. further ensure program security, alterations Watchdog set-up must follow timed sequences. sequence clearing changing time-out configuration follows:
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same operation, write logic Watchdog change enable (WDCE) WDE. logic must written regardless previous value bit. Within next four clock cycles, write Watchdog prescaler bits (WDP) desired, with WDCE cleared. This must done operation. following code example shows assembly function turning Watchdog Timer. example assumes that interrupts controlled (e.g. disabling interrupts globally) that interrupts will occur during execution these functions.
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Assembly Code Example(1)
WDT_off: Turn global interrupt Reset Watchdog Timer Clear WDRF MCUSR andi r16, MCUSR r16, (0xff (0<<WDRF)) MCUSR,
Write logical WDCE Keep prescaler setting prevent unintentional time-out r16, WDTCSR r16, (1<<WDCE) (1<<WDE) WDTCSR, Turn r16, (0<<WDE) WDTCSR, Turn global interrupt
Code Example(1)
void WDT_off(void) _disable_interrupt(); _watchdog_reset(); Clear WDRF MCUSR MCUSR ~(1<<WDRF); Write logical WDCE Keep prescaler setting prevent unintentional time-out WDTCSR (1<<WDCE) (1<<WDE); Turn WDTCSR 0x00; _enable_interrupt(); Note: example code assumes that part specific header file included.
Note: Watchdog accidentally enabled, example runaway pointer brown-out condition, device will reset Watchdog Timer will stay enabled. code handle Watchdog, this might lead eternal loop time-out resets. avoid this situation, application software should always clear Watchdog System Reset Flag (WDRF) control initialisation routine, even Watchdog use.
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following code example shows assembly function changing time-out value Watchdog Timer. Assembly Code Example(1)
WDT_Prescaler_Change: Turn global interrupt Reset Watchdog Timer Start timed sequence -ldi -sei r16, WDTCSR r16, (1<<WDCE) (1<<WDE) WDTCSR, four cycles values from here r16, (1<<WDE) (1<<WDP2) (1<<WDP0) WDTCSR, Finished setting values, used cycles
prescaler(time-out) value cycles (~0.5
Turn global interrupt
Code Example(1)
void WDT_Prescaler_Change(void) _disable_interrupt(); _watchdog_reset(); Start timed equence WDTCSR (1<<WDCE) (1<<WDE); prescaler(time-out) value cycles (~0.5 WDTCSR Note: example code assumes that part specific header file included. (1<<WDE) (1<<WDP2) (1<<WDP0); _enable_interrupt();
Note: Watchdog Timer should reset before change bits, since change bits result time-out when switching shorter time-out period.
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Register Description
MCUSR Status Register Status Register provides information which reset source caused reset.
0x35 (0x55) Read/Write Initial Value JTRF WDRF BORF Description EXTRF PORF MCUSR
JTRF: JTAG Reset Flag This reset being caused logic JTAG Reset Register selected JTAG instruction AVR_RESET. This reset Power-on Reset, writing logic zero flag. WDRF: Watchdog Reset Flag This Watchdog Reset occurs. reset Power-on Reset, writing logic zero flag. BORF: Brown-out Reset Flag This Brown-out Reset occurs. reset Power-on Reset, writing logic zero flag. EXTRF: External Reset Flag This External Reset occurs. reset Power-on Reset, writing logic zero flag. PORF: Power-on Reset Flag This Power-on Reset occurs. reset only writing logic zero flag. make Reset Flags identify reset condition, user should read then Reset MCUSR early possible program. register cleared before another reset occurs, source reset found examining Reset Flags. WDTCSR Watchdog Timer Control Register
(0x60) Read/Write Initial Value
WDIF
WDIE
WDP3
WDCE
WDP2
WDP1
WDP0 WDTCSR
WDIF: Watchdog Interrupt Flag This when time-out occurs Watchdog Timer Watchdog Timer configured interrupt. WDIF cleared hardware when executing corresponding interrupt handling vector. Alternatively, WDIF cleared writing logic flag. When I-bit SREG WDIE set, Watchdog Time-out Interrupt executed. WDIE: Watchdog Interrupt Enable When this written I-bit Status Register set, Watchdog Interrupt enabled. cleared combination with this setting, Watchdog
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Timer Interrupt Mode, corresponding interrupt executed time-out Watchdog Timer occurs. set, Watchdog Timer Interrupt System Reset Mode. first time-out Watchdog Timer will WDIF. Executing corresponding interrupt vector will clear WDIE WDIF automatically hardware (the Watchdog goes System Reset Mode). This useful keeping Watchdog Timer security while using interrupt. stay Interrupt System Reset Mode, WDIE must after each interrupt. This should however done within interrupt service routine itself, this might compromise safety-function Watchdog System Reset mode. interrupt executed before next time-out, System Reset will applied. Table Watchdog Timer Configuration
WDTON(1) Note: WDIE Mode Stopped Interrupt Mode System Reset Mode Interrupt System Reset Mode System Reset Mode Action Time-out None Interrupt Reset Interrupt, then System Reset Mode Reset
WDTON Fuse means programmed means unprogrammed.
WDCE: Watchdog Change Enable This used timed sequences changing prescaler bits. clear bit, and/or change prescaler bits, WDCE must set. Once written one, hardware will clear WDCE after four clock cycles. WDE: Watchdog System Reset Enable overridden WDRF MCUSR. This means that always when WDRF set. clear WDE, WDRF must cleared first. This feature ensures multiple resets during conditions causing failure, safe start-up after failure. WDP3:0: Watchdog Timer Prescaler WDP3:0 bits determine Watchdog Timer prescaling when Watchdog Timer running. different prescaling values their corresponding time-out periods shown Table page
2549K-AVR-01/07
Table Watchdog Timer Prescale Select
WDP3 WDP2 WDP1 WDP0 Reserved Number Oscillator Cycles (2048) cycles (4096) cycles (8192) cycles (16384) cycles (32768) cycles (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles Typical Time-out 5.0V 0.125 0.25
ATmega640/1280/1281/2560/2561
2549K-AVR-01/07
ATmega640/1280/1281/2560/2561
Interrupts
This section describes specifics interrupt handling performed ATmega640/1280/1281/2560/2561. general explanation interrupt handling, refer "Reset Interrupt Handling" page
Interrupt Vectors ATmega640/1280/1281/2560/2561
Table Reset Interrupt Vectors
Vector Program Address(2) $0000(1) $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E $0030 $0032 $0034 $0036 $0038 $003A $003C
Source RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 PCINT0 PCINT1 PCINT2 TIMER2 COMPA TIMER2 COMPB TIMER2 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 COMPC TIMER1 TIMER0 COMPA TIMER0 COMPB TIMER0 SPI, USART0 USART0 UDRE USART0 ANALOG COMP READY
Interrupt Definition External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, JTAG Reset External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request Change Interrupt Request Change Interrupt Request Change Interrupt Request Watchdog Time-out Interrupt Timer/Counter2 Compare Match Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match Timer/Counter1 Compare Match Timer/Counter1 Compare Match Timer/Counter1 Overflow Timer/Counter0 Compare Match Timer/Counter0 Compare match Timer/Counter0 Overflow Serial Transfer Complete USART0 Complete USART0 Data Register Empty USART0 Complete Analog Comparator Conversion Complete EEPROM Ready
2549K-AVR-01/07
Table Reset Interrupt Vectors (Continued)
Vector Notes: Program Address(2) $003E $0040 $0042 $0044 $0046 $0048 $004A $004C $004E $0050 $0052
Source TIMER3 CAPT TIMER3 COMPA TIMER3 COMPB TIMER3 COMPC TIMER3 USART1 USART1 UDRE USART1 READY TIMER4 CAPT TIMER4 COMPA TIMER4 COMPB TIMER4 COMPC TIMER4
Interrupt Definition Timer/Counter3 Capture Event Timer/Counter3 Compare Match Timer/Counter3 Compare Match Timer/Counter3 Compare Match Timer/Counter3 Overflow USART1 Complete USART1 Data Register Empty USART1 Complete 2-wire Serial Interface Store Program Memory Ready Timer/Counter4 Capture Event Timer/Counter4 Compare Match Timer/Counter4 Compare Match Timer/Counter4 Compare Match Timer/Counter4 Overflow Timer/Counter5 Capture Event Timer/Counter5 Compare Match Timer/Counter5 Compare Match Timer/Counter5 Compare Match Timer/Counter5 Overflow USART2 Complete USART2 Data Register Empty USART2 Complete USART3 Complete USART3 Data Register Empty USART3 Complete
$0054 $0056 $0058 $005A $005C $005E $0060 $0062 $0064 $0066(3) $0068(3) $006A
TIMER5 CAPT TIMER5 COMPA TIMER5 COMPB TIMER5 COMPC TIMER5 USART2 USART2 UDRE USART2 USART3 USART3 UDRE USART3
$006C
$006E(3)) $0070
When BOOTRST Fuse programmed, device will jump Boot Loader address reset, "Memory Programming" page 342. When IVSEL MCUCR set, Interrupt Vectors will moved start Boot Flash Section. address each Interrupt Vector will then address this table added start address Boot Flash Section. Only available ATmega640/1280/2560
ATmega640/1280/1281/2560/2561
2549K-AVR-01/07
ATmega640/1280/1281/2560/2561
Reset Interrupt Vector placement
Table page shows Reset Interrupt Vectors placement various combinations BOOTRST IVSEL settings. program never enables interrupt source, Interrupt Vectors used, regular program code placed these locations. This also case Reset Vector Application section while Interrupt Vectors Boot section vice versa. Table Reset Interrupt Vectors Placement(1)
BOOTRST Note: IVSEL Reset Address 0x0000 0x0000 Boot Reset Address Boot Reset Address Interrupt Vectors Start Address 0x0002 Boot Reset Address 0x0002 0x0002 Boot Reset Address 0x0002
Boot Reset Address shown Table page through Table page 339. BOOTRST Fuse means unprogrammed while means programmed.
most typical general program setup Reset Interrupt Vector Addresses ATmega640/1280/1281/2560/2561
Address 0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0X0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C 0x002E 0x0030 0x0032 0x0034 0x0036 0x0038 0x003A 0x003C 0x003E Labels Code RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 PCINT0 PCINT1 PCINT2 TIM2_COMPA TIM2_COMPB TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_COMPC TIM1_OVF TIM0_COMPA TIM0_COMPB TIM0_OVF SPI_STC USART0_RXC USART0_UDRE USART0_TXC ANA_COMP EE_RDY TIM3_CAPT Comments Reset Handler IRQ0 Handler IRQ1 Handler IRQ2 Handler IRQ3 Handler IRQ4 Handler IRQ5 Handler IRQ6 Handler IRQ7 Handler PCINT0 Handler PCINT1 Handler PCINT2 Handler Watchdog Timeout Handler Timer2 CompareA Handler Timer2 CompareB Handler Timer2 Overflow Handler Timer1 Capture Handler Timer1 CompareA Handler Timer1 CompareB Handler Timer1 CompareC Handler Timer1 Overflow Handler Timer0 CompareA Handler Timer0 CompareB Handler Timer0 Overflow Handler Transfer Complete Handler USART0 Complete Handler USART0,UDR Empty Handler USART0 Complete Handler Analog Comparator Handler Conversion Complete Handler EEPROM Ready Handler Timer3 Capture Handler
2549K-AVR-01/07
0x0040 0x0042 0x0044 0x0046 0x0048 0x004A 0x004C 0x004E 0x0050 0x0052 0x0054 0x0056 0x0058 0x005A 0x005C 0x005E 0x0060 0x0062 0x0064 0x0066 0x0068 0x006A 0x006C 0x006E 0x0070 0x0072 0x0073 0x0074 0x0075 0x0076 0x0077 RESET:
TIM3_COMPA TIM3_COMPB TIM3_COMPC TIM3_OVF USART1_RXC USART1_UDRE USART1_TXC SPM_RDY TIM4_CAPT TIM4_COMPA TIM4_COMPB TIM4_COMPC TIM4_OVF TIM5_CAPT TIM5_COMPA TIM5_COMPB TIM5_COMPC TIM5_OVF USART2_RXC USART2_UDRE USART2_TXC USART3_RXC USART3_UDRE USART3_TXC r16, high(RAMEND) SPH,r16 r16, low(RAMEND)
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