8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATm
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8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega103 ATmega103L
Note:
recommended designs.
Rev. 0945I-AVR-02/07
Configuration
(AD3) (AD4) (AD5) (AD6) (AD7) (A15)
TQFP
(A14) (A13) (A12) (A11) (A10) (A9) (A8)
(AD2) (AD1) (AD0)
(ADC7) (ADC6) (ADC5) (ADC4) (ADC3) (ADC2) (ADC1) (ADC0) AREF AGND AVCC
(T2) (T1) (IC1) (INT3) (INT2) (INT1) (INT0) XTAL1 XTAL2 RESET TOSC1 TOSC2 (OC2/PWM2) (OC1B/PWM1B)
INDEX CORNER
(PDI/RXD)
(PDO/TXD)
(AC+)
(AC-)
(INT4)
(INT5)
(INT6)
(INT7)
(MOSI) (MISO) (OC0/PWM0) (SCK) (OC1A/PWM1A) (SS)
ATmega103(L)
0945I-AVR-02/07
ATmega103(L)
Description
ATmega103(L) low-power, CMOS, 8-bit microcontroller based RISC architecture. executing powerful instructions single clock cycle, ATmega103(L) achieves throughputs approaching MIPS MHz, allowing system designer optimize power consumption versus processing speed. core based enhanced RISC architecture that combines rich instruction with general purpose working registers. registers directly connected Arithmetic Logic Unit (ALU), allowing independent registers accessed single instruction executed clock cycle. resulting architecture more code efficient while achieving throughputs times faster than conventional CISC microcontrollers. ATmega103(L) provides following features: 128K bytes In-System Programmable Flash, bytes EEPROM, bytes SRAM, general purpose lines, input lines, output lines, general purpose working registers, Real Time Counter (RTC), flexible Timer/Counters with compare modes PWM, UART, programmable Watchdog Timer with internal Oscillator, serial port software-selectable power saving modes. Idle mode stops while allowing SRAM, Timer/Counters, port interrupt system continue functioning. Power-down mode saves register contents freezes Oscillator, disabling other chip functions until next Interrupt Hardware Reset. Power-save mode, Timer Oscillator continues run, allowing user maintain timer base while rest device sleeping. device manufactured using Atmel's high-density nonvolatile memory technology. On-chip Flash allows Program memory reprogrammed In-System through serial interface conventional nonvolatile memory programmer. combining 8-bit RISC with large array Flash monolithic chip, Atmel ATmega103(L) powerful microcontroller that provides highly flexible cost-effective solution many embedded control applications. ATmega103(L) supported with full suite program system development tools including: compilers, macro assemblers, program debugger/simulators, InCircuit Emulators evaluation kits.
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Block Diagram
Figure ATmega103(L) Block Diagram
PORTF BUFFERS AVCC DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC 8-BIT DATA PORTA DRIVER/BUFFERS PORTC DRIVERS
ANALOG
AGND AREF INTERNAL OSCILLATOR OSCILLATOR
XTAL1
XTAL1 PROGRAM COUNTER STACK POINTER WATCHDOG TIMER OSCILLATOR TOSC2
PROGRAM FLASH
SRAM
CONTROL REGISTER
TIMING CONTROL
TOSC1
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
TIMER/ COUNTERS
RESET
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
UART
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
PORTE DRIVER/BUFFERS PORTB DRIVER/BUFFERS PORTD DRIVER/BUFFERS
ATmega103(L)
0945I-AVR-02/07
ATmega103(L)
Descriptions
Port (PA7.PA0) Supply voltage. Ground. Port 8-bit bi-directional port. Port pins provide internal pull-up resistors (selected each bit). Port output buffers sink drive displays directly. When pins used inputs externally pulled low, they will source current internal pull-up resistors activated. Port serves Multiplexed Address/Data when using external SRAM. Port pins tri-stated when reset condition becomes active, even clock running. Port (PB7.PB0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled low, will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running. Port (PC7.PC0) Port 8-bit output port. Port output buffers sink Port also serves Address output when using external SRAM. Since Port output only port, Port pins tri-stated when reset condition becomes active. Port (PD7.PD0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running. Port (PE7.PE0) Port 8-bit bi-directional port with internal pull-up resistors. Port output buffers sink inputs, Port pins that externally pulled will source current pull-up resistors activated. Port also serves functions various special features. Port pins tri-stated when reset condition becomes active, even clock running Port (PF7.PF0) RESET Port 8-bit input port. Port also serves analog inputs ADC. Reset input. external reset generated level RESET pin. Reset pulses longer than will generate reset, even clock running. Shorter pulses guaranteed generate reset. Input inverting Oscillator amplifier input internal clock operating circuit. Output from inverting Oscillator amplifier.
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XTAL1 XTAL2
TOSC1 TOSC2
Input inverting Timer/Counter Oscillator amplifier. Output from inverting Timer/Counter Oscillator amplifier. External SRAM write strobe External SRAM read strobe Address Latch Enable used when External Memory enabled. strobe used latch low-order address bits) into address latch during first access cycle, pins used data during second access cycle. Supply voltage Port including ADC. must connected when used ADC. "ADC Noise Canceling Techniques" page details when using ADC. AREF analog reference input converter. operations, voltage range AGND AVCC must applied this pin. board separate analog ground plane, this should connected this ground plane. Otherwise, connect GND. programming enable Serial Programming mode. holding this during Power-on Reset, device will enter Serial Programming mode. function during normal operation.
AVCC
AREF
AGND
Clock Options
Crystal Oscillator XTAL1 XTAL2 input output, respectively, inverting amplifier, which configured on-chip Oscillator, shown Figure Either quartz crystal ceramic resonator used. Figure Oscillator Connections
BUFFER
XTAL2 XTAL1
Note:
When using Oscillator clock external device, buffer should connected indicated figure.
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ATmega103(L)
External Clock drive device from external clock source, XTAL2 should left unconnected while XTAL1 driven shown Figure Figure External Clock Drive Configuration
EXTERNAL OSCILLATOR SIGNAL XTAL2 XTAL1
Timer Oscillator
Timer Oscillator pins, TOSC1 TOSC2, crystal connected directly between pins. external capacitors needed. Oscillator optimized with 32,768 watch crystal. Applying external clock source TOSC1 recommended.
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Architectural Overview
Figure ATmega103(L) RISC Architecture
ATmega103(L) Architecture
Data 8-bit
Program Memory
Program Counter
Status Test
Instruction Register
General Purpose Registers Peripherals Indirect Addressing Direct Addressing
Instruction Decoder
Control Lines
Data SRAM
EEPROM
uses Harvard architecture concept with separate memories buses program data. Program memory accessed with single-level pipeline. While instruction being executed, next instruction pre-fetched from Program memory. This concept enables instructions executed every clock cycle. Program memory In-System Programmable Flash memory. With exceptions, instructions have single 16-bit word format, meaning that every Program memory address contains single 16-bit instruction. During interrupts subroutine calls, return address Program Counter (PC) stored Stack. Stack effectively allocated general data SRAM and, consequently, Stack size only limited total SRAM size usage SRAM. user programs must initialize reset routine (before subroutines interrupts executed). 16-bit Stack Pointer (SP) read/write accessible space. 4000 bytes data SRAM easily accessed through five different addressing modes supported architecture. flexible interrupt module control registers space with additional Global Interrupt Enable Status Register. different interrupts have sep-
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ATmega103(L)
arate Interrupt Vector Interrupt Vector table beginning Program memory. different interrupts have priority accordance with their Interrupt Vector position. lower Interrupt Vector address, higher priority. memory spaces architecture linear regular memory maps.
General Purpose Register File
Figure shows structure general purpose working registers CPU. Figure General Purpose Working Registers
General Purpose Working Registers X-register Byte X-register High Byte Y-register Byte Y-register High Byte Z-register Byte Z-register High Byte Addr.
register operating instructions instruction have direct single-cycle access registers. only exception five constant arithmetic logic instructions SBCI, SUBI, CPI, ANDI between constant register instruction load immediate constant data. These instructions apply second half registers Register File R16.R31. general SBC, SUB, other operations between registers single register apply entire Register File. shown Figure each register also assigned Data memory address, mapping them directly into first locations user Data Space. Although being physically implemented SRAM locations, this memory organization provides great flexibility access registers, Z-registers index register file. bytes SRAM available general data implemented addresses $0060 $0FFF.
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X-register, Y-register Zregister
registers R26.R31 have some added functions their general purpose usage. These registers address pointers indirect addressing SRAM. three indirect address registers defined Figure Z-registers
X-register ($1B) ($1A)
Y-register ($1D) Z-register ($1F) ($1E) ($1C)
different addressing modes these address registers have functions fixed displacement, automatic increment decrement (see descriptions different instructions).
Arithmetic Logic Unit
high-performance operates direct connection with general purpose working registers. Within single clock cycle, operations between registers Register File executed. operations divided into three main categories: arithmetic, logical functions. ATmega103(L) contains 128K bytes On-chip In-System Programmable Flash memory program storage. Since instructions single double 16-bit words, Flash organized Flash memory endurance least 1000 write/erase cycles. Constant tables allocated entire Program memory space (see Load Program Memory ELPM Extended Load Program Memory instruction descriptions).
Flash Program Memory
SRAM Data Memory
ATmega103(L) supports different configurations SRAM Data memory listed Table Table Memory Configurations
Configuration Note: Internal SRAM Data Memory 4000 4000 External SRAM Data Memory None
When using external SRAM, will available.
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ATmega103(L)
Figure Memory Configurations
Memory Configuration
Program Memory
$0000
Data Memory
Registers Registers Internal SRAM (4000 $0FFF $0000 $001F $0020 $005F $0060
Program Flash (32K/64K
$7FFF/$FFFF
Memory Configuration
Program Memory
$0000
Data Memory
Registers Registers Internal SRAM (4000 $0000 $001F $0020 $005F $0060 $0FFF $1000
Program Flash (32K/64K External SRAM
$7FFF/ $FFFF
$FFFF
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4096 first Data memory locations address both Register File, memory internal Data SRAM. first locations address Register File memory, next 4000 locations address internal Data SRAM. optional external Data SRAM used with ATmega103(L). This SRAM will occupy area remaining address locations address space. This area starts address following internal SRAM. external SRAM used, external memory lost addresses occupied internal memory. When addresses accessing SRAM memory space exceeds internal Data memory locations, external Data SRAM accessed using same instructions internal Data memory access. When internal Data memories accessed, read write strobe pins inactive during whole access cycle. External SRAM operation enabled setting MCUCR Register. Accessing external SRAM takes additional clock cycle byte compared access internal SRAM. This means that commands LDS, STS, PUSH take additional clock cycle. Stack placed external SRAM, interrupts, subroutine calls returns take clock cycles extra because 2-byte Program Counter pushed popped. When external SRAM interface used with wait state, additional clock cycles used byte. This following effect: Data transfer instructions take extra clock cycles, whereas interrupt, subroutine calls returns will need four clock cycles more than specified "Instruction Summary" page 135. five different addressing modes Data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement Indirect with Post-increment. Register File, registers feature indirect addressing pointer registers. Indirect with Displacement mode features address locations reached from base address given Z-register. When using register indirect addressing modes with automatic Pre-decrement Postincrement, address registers decremented incremented. entire Data address space including general purpose working registers Registers accessible through these addressing modes. next section detailed description different addressing modes.
Program Data Addressing Modes
ATmega103(L) RISC microcontroller supports powerful efficient addressing modes access Program memory (Flash) Data memory (SRAM, Register File memory). This section describes different addressing modes supported architecture. figures, means operation code part instruction word. simplify, figures show exact location addressing bits.
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ATmega103(L)
Register Direct, Single Register Figure Direct Single Register Addressing
REGISTER FILE
operand contained register (Rd). Register Direct, Registers Figure Direct Register Addressing, Registers
REGISTER FILE
Operands contained registers (Rr) (Rd). result stored register (Rd). Direct Figure Direct Addressing
MEMORY
Operand address contained bits instruction word. destination source register address.
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Data Direct
Figure Direct Data Addressing
Data Space LSBs Rr/Rd $0000
$FFFF
16-bit Data address contained LSBs 2-word instruction. Rd/Rr specify destination source register. Data Indirect with Displacement Figure Data Indirect with Displacement
Data Space $0000 Z-REGISTER
$FFFF
Operand address result Z-register contents added address contained bits instruction word. Data Indirect Figure Data Indirect Addressing
Data Space $0000 Z-REGISTER
$FFFF
Operand address contents Z-register.
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ATmega103(L)
Data Indirect with Predecrement Figure Data Indirect Addressing with Pre-decrement
Data Space $0000 Z-REGISTER
$FFFF
Z-register decremented before operation. Operand address decremented contents Z-register. Data Indirect with Postincrement Figure Data Indirect Addressing with Post-increment
Data Space $0000 Z-REGISTER
$FFFF
Z-register incremented after operation. Operand address contents Z-register prior incrementing. Constant Addressing Using ELPM Instructions Figure Code Memory Constant Addressing
PROGRAM MEMORY $0000 Z-REGISTER
$7FFF/$FFFF
Constant byte address specified Z-register contents. MSBs select word address 32K), selects Byte cleared (LSB High Byte (LSB
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ELPM used, Page register (RAMPZ) used select high memory page (RAMPZ0 Page, RAMPZ0 High Page). Direct Program Address, CALL Figure Direct Program Memory Addressing
PROGRAM MEMORY $0000 LSBs
$7FFF/$FFFF
Program execution continues address immediate instruction words. Indirect Program Addressing, IJMP ICALL Figure Indirect Program Memory Addressing
PROGRAM MEMORY $0000 Z-REGISTER
$7FFF/$FFFF
Program execution continues address contained Z-register (i.e., loaded with contents Z-register). Relative Program Addressing, RJMP RCALL Figure Relative Program Memory Addressing
PROGRAM MEMORY $0000
$7FFF/$FFFF
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ATmega103(L)
Program execution continues address relative address -2048 2047.
EEPROM Data Memory
EEPROM memory organized separate Data space which single bytes read written. EEPROM endurance least 100,000 write/erase cycles. access between EEPROM described page specifying EEPROM Address Register, EEPROM Data Register EEPROM Control Register. This section describes general access timing concepts instruction execution internal memory access. driven System Clock directly generated from external clock crystal chip. internal clock division used. Figure shows parallel instruction fetches instruction executions enabled Harvard architecture fast-access Register File concept. This basic pipelining concept obtain MIPS with corresponding unique results functions cost, functions clocks functions power unit. Figure Parallel Instruction Fetches Instruction Executions
Memory Access Times Instruction Execution Timing
System Clock Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch Instruction Execute Instruction Fetch
Figure shows internal timing concept Register File. single clock cycle, operation using register operands executed result stored back destination register. Figure Single Cycle Operation
System Clock Total Execution Time Register Operands Fetch Operation Execute Result Write Back
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internal Data SRAM access performed System Clock cycles described Figure Figure On-chip Data SRAM Access Cycles
System Clock Address Data Data
Prev. Address Address
"Interface External SRAM" page description access external SRAM.
Memory
space definition ATmega103(L) shown Table Table ATmega103(L) Space
Address (SRAM Address) ($5F) ($5E) ($5D) ($5C) ($5B) ($5A) ($59) ($58) ($57) ($56) ($55) ($54) ($53) ($52) ($51) ($50) ($4F) ($4E) Name SREG XDIV RAMPZ EICR EIMSK EIFR TIMSK TIFR MCUCR MCUSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B Function Status REGister Stack Pointer High Stack Pointer XTAL Divide Control Register Page Select Register External Interrupt Control Register External Interrupt MaSK Register External Interrupt Flag Register Timer/Counter Interrupt MaSK Register Timer/Counter Interrupt Flag Register General Control Register Status Register Timer/Counter0 Control Register Timer/Counter0 (8-bit) Timer/Counter0 Output Compare Register Asynchronous Mode Status Register Timer/Counter1 Control Register Timer/Counter1 Control Register
ATmega103(L)
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Read
Write
ATmega103(L)
Table ATmega103(L) Space (Continued)
Address (SRAM Address) ($4D) ($4C) ($4B) ($4A) ($49) ($48) ($47) ($46) ($45) ($44) ($43) ($41) ($3F) ($3E) ($3D) ($3C) ($3B) ($3A) ($39) ($38) ($37) ($36) ($35) ($32) ($31) ($30) ($2F) ($2E) ($2D) ($2C) ($2B) ($2A) ($29) ($28) ($27) Name TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 WDTCR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC PORTD DDRD PIND SPDR SPSR SPCR UBRR ACSR ADMUX Function Timer/Counter1 High Byte Timer/Counter1 Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Output Compare Register High Byte Timer/Counter1 Output Compare Register Byte Timer/Counter1 Input Capture Register High Byte Timer/Counter1 Input Capture Register Byte Timer/Counter2 Control Register Timer/Counter2 (8-bit) Timer/Counter2 Output Compare Register Watchdog Timer Control Register EEPROM Address Register High EERPOM Address Register EEPROM Data Register EEPROM Control Register Data Register, Port Data Direction Register, Port Input Pins, Port Data Register, Port Data Direction Register, Port Input Pins, Port Data Register, Port Data Register, Port Data Direction Register, Port Input Pins, Port Data Register Status Register Control Register UART Data Register UART Status Register UART Control Register UART Baud Rate Register Analog Comparator Control Status Register Multiplexer Select Register
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Table ATmega103(L) Space (Continued)
Address (SRAM Address) ($26) ($25) ($24) ($23) ($22) ($21) Note: Name ADCSR ADCH ADCL PORTE DDRE PINE Function Control Status Register Data Register High Data Register Data Register, Port Data Direction Register, Port Input Pins, Port
($20) PINF Input Pins, Port Reserved unused locations shown table.
different ATmega103(L) I/Os peripherals placed space. different locations directly accessed instructions transferring data between general purpose working registers space. Registers within address range directly bit-accessible using instructions. these registers, value single bits checked using SBIS SBIC instructions. Refer "Instruction Summary" page more details. When using specific instructions OUT, Register address used. When addressing Registers SRAM, must added this address. Register addresses throughout this document shown with SRAM address parentheses. compatibility with future devices, reserved bits should written zero accessed. Reserved memory addresses should never written. Some Status Flags cleared writing logical them. Note that instructions will operate bits Register, writing back into flag read set, thus clearing flag. instructions work with registers only. different peripherals control registers explained following sections. Status Register SREG Status Register (SREG) space location ($5F) defined
($5F) Read/Write Initial Value SREG
Global Interrupt Enable Global Interrupt Enable must (one) interrupts enabled. individual interrupt enable control then performed separate control registers. Global Interrupt Enable Register cleared (zero), none interrupts enabled independent individual interrupt enable settings. I-bit cleared hardware after interrupt occurred RETI instruction enable subsequent interrupts. Copy Storage Copy instructions (Bit LoaD) (Bit STore) T-bit source destination operated bit. from register Register File cop-
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into instruction copied into register register file instruction. Half-carry Flag Half-carry Flag indicates Half-carry some arithmetic operations. instruction description page detailed information. Sign Bit, S-bit always exclusive between Negative Flag Two's Complement Overflow Flag instruction description page detailed information. Two's Complement Overflow Flag Two's Complement Overflow Flag supports two's complement arithmetics. instruction description page detailed information. Negative Flag Negative Flag indicates negative result from arithmetical logical operation. Instruction description page detailed information. Zero Flag Zero Flag indicates zero result from arithmetical logical operation. instruction description page detailed information. Carry Flag Carry Flag indicates carry arithmetical logical operation. instruction description page detailed information. Note that Status Register automatically stored when entering interrupt routine restored when returning from interrupt routine. This must handled software. Stack Pointer general 16-bit Stack Pointer effectively built 8-bit registers space locations ($5E) ($5D). ATmega103(L) supports bytes memory, bits used.
($5E) ($5D) SP15 Read/Write Initial Value SP14 SP13 SP12 SP11 SP10
Stack Pointer points Data SRAM Stack area where Subroutine Interrupt Stacks located. This Stack space Data SRAM must defined program before subroutine calls executed interrupts enabled. Stack Pointer must point above $60. Stack Pointer decremented when data pushed onto Stack with PUSH instruction decremented when address pushed onto Stack with subroutine calls interrupts. Stack Pointer incremented when data popped from Stack with
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instruction incremented when address popped from Stack with return from subroutine return from interrupt RETI. Page Select Register RAMPZ
($5B) Read/Write Initial Value
RAMPZ0 RAMPZ
RAMPZ Register normally used select which page accessed pointer. ATmega103(L) does support more than SRAM memory, this register used only select which page Program memory accessed when ELPM instruction used. different settings RAMPZ0 have following effects: RAMPZ0 RAMPZ0 Program memory address $0000 $7FFF (lower bytes) accessed ELPM Program memory address $8000 $FFFF (higher bytes) accessed ELPM
Note that affected RAMPZ setting. Control Register MCUCR Control Register contains control bits general functions.
($55) Read/Write Initial Value MCUCR
SRE: External SRAM Enable When (one), external Data SRAM enabled, functions (Port (Port activated alternate functions. Then overrides direction settings respective Data Direction Registers. When cleared (zero), external Data SRAM disabled normal data direction settings used. SRW: External SRAM Wait State When (one), one-cycle wait state inserted external Data SRAM access cycle. When cleared (zero), external Data SRAM access executed with three-cycle scheme. Figure page Figure page Sleep Enable must (one) make enter sleep mode when SLEEP instruction executed. avoid entering sleep mode unless programmer's purpose, recommended Sleep Enable (SE) just before execution SLEEP instruction.
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ATmega103(L)
Bits SM1/SM0: Sleep Mode Select Bits This selects between three available sleep modes shown Table Table Sleep Mode Select
Sleep Mode Idle mode Reserved Power-down Power-save
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. XTAL Divide Control Register XDIV XTAL Divide Control Register used divide XTAL clock frequency number range 129. This feature used decrease power consumption when requirement processing power low.
($5C) Read/Write Initial Value XDIVEN XDIV6 XDIV5 XDIV4 XDIV3 XDIV2 XDIV1 XDIV0 XDIV
XDIVEN: XTAL Divide Enable When XDIVEN (one), clock frequency peripherals divided factor defined setting XDIV6 XDIV0. This cleared run-time vary clock frequency suitable application. Bits XDIV6.XDIV0: XTAL Divide Select Bits These bits define division factor that applies when XDIVEN (one). value these bits denoted following formula defines resulting clock frequency fclk: XTAL -129 value these bits only changed when XDIVEN zero. When XDIVEN one, value written simultaneously into XDIV6.XDIV0 taken division factor. When XDIVEN cleared zero, value written simultaneously into XDIV6.XDIV0 rejected. divider divides Master Clock Input MCU, speed peripherals reduced when division factor used.
Reset Interrupt Handling
ATmega103(L) provides different interrupt sources. These interrupts separate Reset Vector each have separate Program Vector Program memory space. interrupts assigned individual enable bits that must (one) together with I-bit Status Register order enable interrupt. lowest addresses Program memory space automatically defined Reset Interrupt Vectors. complete list vectors shown Table list also determines priority levels different interrupts. lower address,
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higher priority level. RESET highest priority next INT0 (the External Interrupt Request etc. Table Reset Interrupt Vectors
Vector Program Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E Source RESET INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 TIMER2 COMP TIMER2 TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 TIMER0 COMP TIMER0 SPI, UART, UART, UDRE UART, READY ANALOG COMP Interrupt Definition Hardware Pin, Power-on Reset Watchdog Reset External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request External Interrupt Request Timer/Counter2 Compare Match Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match Timer/Counter1 Compare Match Timer/Counter1 Overflow Timer/Counter0 Compare Match Timer/Counter0 Overflow Serial Transfer Complete UART, Complete UART Data Register Empty UART, Complete Conversion Complete EEPROM Ready Analog Comparator
most typical program setup Reset Interrupt vector addresses are:
Address Labels Code $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 RESET EXT_INT0 EXT_INT1 EXT_INT2 EXT_INT3 EXT_INT4 EXT_INT5 EXT_INT6 EXT_INT7 Comments Reset Handler IRQ0 Handler IRQ1 Handler IRQ2 Handler IRQ3 Handler IRQ4 Handler IRQ5 Handler IRQ6 Handler IRQ7 Handler
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$0012 $0014 $0016 $0018 $001A $001C $001E $0020 $0022 $0024 $0026 $0028 $002A $002C $002E $0030 $0031 $0032 $0033 $0034 MAIN: <instr> r16, high(RAMEND); Main program start SPH,r16 r16, low(RAMEND) SPL,r16 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC UART_RXC UART_DRE UART_TXC EE_RDY ANA_COMP Timer2 Compare Handler Timer2 Overflow Handler Timer1 Capture Handler Timer1 Compare Handler Timer1 Compare Handler Timer1 Overflow Handler Timer0 Compare Handler Timer0 Overflow Handler Transfer Complete Handler UART Complete Handler Empty Handler UART Complete Handler Conversion Complete Handler EEPROM Ready Handler Analog Comparator Handler
Reset Sources
ATmega103(L) three sources reset: Power-on Reset. reset when supply voltage below Power-on Reset threshold (VPOT). External Reset. reset when level present RESET more than Watchdog Reset. reset when Watchdog Timer period expires Watchdog enabled.
During reset, Registers except Status Register then their initial values program starts execution from address $0000. instruction placed address $0000 must (absolute jump) instruction reset handling routine. program never enables interrupt source, Interrupt Vectors used regular program code placed these locations. circuit diagram Figure shows reset logic. Table defines timing electrical parameters reset circuitry.
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Figure Reset Logic
Power-on Reset Circuit
RESET
100-500K
10-50K
Reset Circuit
COUNTER RESET
Watchdog Timer
SUT0 SUT1
On-chip Oscillator
14-stage Ripple Counter
XTAL1
Delay Unit
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INTERNAL RESET
ATmega103(L)
Table Reset Characteristics (VCC 5.0V)
Symbol Parameter Power-on Reset Threshold (rising) Power-on Reset Threshold (falling) RESET Threshold Voltage TTOUT Reset Delay Time-out Period 12.8 Condition VCC/2 16.0 19.2 Units cycles
VPOT(1)
VRST
Note:
Power-on Reset will work unless supply voltage been below VPOT (falling).
Power-on Reset
Power-on Reset (POR) circuit ensures that device Reset from Power-on. shown Figure internal timer clocked from Watchdog Timer Oscillator prevents from starting until after certain period after reached Poweron Threshold voltage (VPOT), regardless rise time (see Figure 24). Fuse bits SUT1 SUT0 used select start-up time indicated Table table indicates that fuse programmed. user select start-up time according typical Oscillator start-up time. number Oscillator cycles used each Time-out except shown Table frequency Watchdog Oscillator voltage-dependent shown "Typical Characteristics" page 123. Table Number Watchdog Oscillator Cycles
Time-out 16.0 Number Cycles
setting starts after clock cycles, used when external clock signal applied XTAL1 pin. This setting does Oscillator enables very fast start-up from sleep modes Power-down Power-save clock signal present during sleep. details, refer programming specification starting page 104. built-in start-up delay sufficient, RESET connected directly external pull-up resistor. holding period after been applied, Power-on Reset period extended. Refer Figure timing example this.
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Figure Start-up, RESET Tied VCC.
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure Start-up, RESET Controlled Externally
VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
External Reset
external reset generated level RESET pin. Reset pulses longer than will generate reset even clock running. Shorter pulses guaranteed generate reset. When applied signal reaches Reset Threshold Voltage (VRST) positive edge, delay timer starts after Time-out period tTOUT expired. Figure External Reset during Operation
RESET VRST
TIME-OUT
tTOUT
INTERNAL RESET
ATmega103(L)
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ATmega103(L)
Watchdog Reset When Watchdog times out, will generate short reset pulse XTAL cycle duration. falling edge this pulse, delay timer starts counting Time-out period tTOUT. Refer page details operation Watchdog. Figure Watchdog Reset during Operation
RESET
TIME-OUT
XTAL Cycle
RESET TIME-OUT INTERNAL RESET
tTOUT
Status Register MCUSR
Status Register provides information which reset source caused reset.
($54) Read/Write Initial Value EXTRF PORF MCUSR
description
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. EXTRF: External Reset Flag After Power-on Reset, this undefined (X). will external reset. Watchdog reset will leave this unchanged. PORF: Power-on Reset Flag This Power-on Reset. Watchdog Reset External Reset will leave this unchanged. summarize, Table shows value these bits after three modes reset: Table PORF EXTRF Values after Reset
Reset Source Power-on Reset External Reset Watchdog Reset EXTRF undefined unchanged PORF unchanged unchanged
make these bits identify reset condition, user software should clear both PORF EXTRF bits early possible program. Checking PORF EXTRF values done before bits cleared. cleared before
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external Watchdog reset occurs, source reset found using following truth table, Table Table Reset Source Identification
Reset Source Watchdog Reset Power-on Reset External Reset Power-on Reset EXTRF PORF
Interrupt Handling
ATmega103(L) dedicated 8-bit Interrupt Mask Control Registers; EIMSK (External Interrupt Mask Register) TIMSK (Timer/Counter Interrupt Mask Register). addition, other enable mask bits found peripheral control registers. When interrupt occurs, Global Interrupt Enable I-bit cleared (zero) interrupts disabled. user software (one) I-bit enable nested interrupts. I-bit (one) when Return from Interrupt instruction (RETI) executed. When Program Counter vectored actual Interrupt Vector order execute interrupt handling routine, hardware clears corresponding flag that generated interrupt. Some Interrupt Flags also cleared writing logical flag position(s) cleared. interrupt condition occurs when corresponding interrupt enable cleared (zero), Interrupt Flag will remembered until interrupt enabled flag cleared software. more interrupt conditions occur when Global Interrupt Enable cleared (zero), corresponding Interrupt Flag(s) will remembered until Global Interrupt Enable (one), will executed order priority. Note that external level interrupt does have flag will only remembered long interrupt condition active. Note that Status Register automatically stored when entering interrupt routine restored when returning from interrupt routine. This must handled software.
External Interrupt Mask Register EIMSK
($59) Read/Write Initial Value
INT7
INT6
INT5
INT4
INT3
INT2
INT1
INT0 EIMSK
Bits INT7 INT4: External Interrupt Request Enable When INT7 INT4 (one) I-bit Status Register (SREG) (one), corresponding external interrupt enabled. Interrupt Sense Control bits External Interrupt Control Register (EICR) define whether external interrupt activated rising falling edge level-sensed. Activity these pins will trigger interrupt request even enabled output. This provides generating software interrupt.
ATmega103(L)
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ATmega103(L)
Bits INT3 INT0: External Interrupt Request Enable When INT3 INT0 (one) I-bit Status Register (SREG) (one), corresponding external interrupt enabled. external interrupts always low-level triggered interrupts. Activity these pins will trigger interrupt request even enabled output. This provides generating software interrupt. When enabled, level-triggered interrupt will generate interrupt request long held low. External Interrupt Flag Register EIFR
($58) Read/Write Initial Value
INTF7
INTF6
INTF5
INTF4
EIFR
Bits INTF7 INTF4: External Interrupt Flags When edge INT7 INT4 pins triggers interrupt request, corresponding Interrupt Flag, INTF7 INTF4, becomes (one). I-bit SREG corresponding interrupt enable bit, INT7 INT4 EIMSK, (one), will jump Interrupt Vector. flag cleared when corresponding interrupt routine executed. Alternatively, flag cleared writing logical These flags always cleared when INTF7 INFT4 configured level interrupts. Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. External Interrupt Control Register EICR
($5A) Read/Write Initial Value
ISC71
ISC70
ISC61
ISC60
ISC51
ISC50
ISC41
ISC40 EICR
Bits ISCX1, ISCX0: External Interrupt Sense Control Bits External Interrupts activated external pins INT7 INT4 SREG I-flag corresponding interrupt mask EIMSK set. level edges external pins that activate interrupts defined Table Table Interrupt Sense Control
ISCX1 ISCX0 Description level INTX generates interrupt request. Reserved falling edge INTX generates interrupt request. rising edge INTX generates interrupt request.
value INTX sampled before detecting edges. edge interrupt selected, pulses that last longer than clock period will generate interrupt. Shorter pulses guaranteed generate interrupt. Observe that clock frequency lower than XTAL frequency XTAL divider enabled. low-level interrupt selected, level must held until completion currently exe-
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cuting instruction generate interrupt. enabled, level-triggered interrupt will generate interrupt request long held low.
ATmega103(L)
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ATmega103(L)
Timer/Counter Interrupt Mask Register TIMSK
($57) Read/Write Initial Value
OCIE2
TOIE2
TICIE1
OCIE1A
OCIE1B
TOIE1
OCIE0
TOIE0 TIMSK
OCIE2: Timer/Counter2 Output Compare Interrupt Enable When OCIE2 (one) I-bit Status Register (one), Timer/Counter2 Compare Match interrupt enabled. corresponding interrupt vector $0012) executed compare match Timer/Counter2 occurs, i.e., when OCF2 Timer/Counter Interrupt Flag Register (TIFR). TOIE2: Timer/Counter2 Overflow Interrupt Enable When TOIE2 (one) I-bit Status Register (one), Timer/Counter2 Overflow interrupt enabled. corresponding interrupt vector $0014) executed overflow Timer/Counter2 occurs, i.e., when TOV2 Timer/Counter Interrupt Flag Register (TIFR). TICIE1: Timer/Counter1 Input Capture Interrupt Enable When TICIE1 (one) I-bit Status Register (one), Timer/Counter1 Input Capture Event interrupt enabled. corresponding interrupt vector $0016) executed capture-triggering event occurs PD4(IC1), i.e., when ICF1 Timer/Counter Interrupt Flag Register. OCE1A: Timer/Counter1 Output Compare Match Interrupt Enable When OCIE1A (one) I-bit Status Register (one), Timer/Counter1 Compare Match interrupt enabled. corresponding interrupt vector $0018) executed Compare Match Timer/Counter1 occurs, i.e., when OCF1A Timer/Counter Interrupt Flag Register. OCIE1B: Timer/Counter1 Output Compare Match Interrupt Enable When OCIE1B (one) I-bit Status Register (one), Timer/Counter1 Compare Match interrupt enabled. corresponding interrupt vector $001A) executed Compare Match Timer/Counter1 occurs, i.e., when OCF1B Timer/Counter Interrupt Flag Register. TOIE1: Timer/Counter1 Overflow Interrupt Enable When TOIE1 (one) I-bit Status Register (one), Timer/Counter1 Overflow interrupt enabled. corresponding interrupt vector $001C) executed overflow Timer/Counter1 occurs, i.e., when TOV1 Timer/Counter Interrupt Flag Register. OCIE0: Timer/Counter0 Output Compare Interrupt Enable When OCIE0 (one) I-bit Status Register (one), Timer/Counter0 Compare Match interrupt enabled. corresponding interrupt vector $001E) executed compare match Timer/Counter0 occurs, i.e., when OCF0 Timer/Counter Interrupt Flag Register.
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TOIE0: Timer/Counter0 Overflow Interrupt Enable When TOIE0 (one) I-bit Status Register (one), Timer/Counter0 Overflow interrupt enabled. corresponding interrupt vector $0020) executed overflow Timer/Counter0 occurs, i.e., when TOV0 Timer/Counter Interrupt Flag Register.
ATmega103(L)
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ATmega103(L)
Timer/Counter Interrupt Flag Register TIFR
($56) Read/Write Initial Value
OCF2
TOV2
ICF1
OCF1A
OCF1B
TOV1
OCF0
TOV0 TIFR
OCF2: Output Compare Flag OCF2 (one) when compare match occurs between Timer/Counter2 data OCR2 Output Compare Register OCF2 cleared hardware when executing corresponding interrupt handling vector. Alternatively, OCF2 cleared writing logical flag. When I-bit SREG, OCIE2 (Timer/Counter2 Compare Interrupt Enable) OCF2 (one), Timer/Counter2 Output Compare interrupt executed. TOV2: Timer/Counter2 Overflow Flag TOV2 (one) when overflow occurs Timer/Counter2. TOV2 cleared hardware when executing corresponding interrupt handling vector. Alternatively, TOV2 cleared writing logical flag. When I-bit SREG, TOIE2 (Tim er/Co ter1 rflow Inte rrup able) Timer/Counter2 Overflow interrupt executed. mode, this when Timer/Counter2 advances from $00. ICF1: Input Capture Flag ICF1 (one) flag Input Capture event, indicating that Timer/Counter1 value been transferred Input Capture Register (ICR1). ICF1 cleared hardware when executing corresponding interrupt handling vector. Alternatively, ICF1 cleared writing logical flag. When SREG I-bit, TICIE1 (Timer/Counter1 Input Capture Interrupt Enable) ICF1 (one), Timer/Counter1 Capture interrupt executed. OCF1A: Output Compare Flag OCF1A (one) when compare match occurs between Timer/Counter1 data OCR1A Output Compare Register OCF1A cleared hardware when executing corresponding interrupt handling vector. Alternatively, OCF1A cleared writing logical flag. When I-bit SREG OCIE1A (Timer/Counter1 Compare Interrupt Enable) OCF1A (one), Timer/Counter1 Compare Match interrupt executed. OCF1B: Output Compare Flag OCF1B (one) when compare match occurs between Timer/Counter1 data OCR1B Output Compare Register OCF1B cleared hardware when executing corresponding interrupt handling vector. Alternatively, OCF1B cleared writing logical flag. When I-bit SREG OCIE1B (Timer/Counter1 Compare Match Interrupt Enable) OCF1B (one), Timer/Counter1 Compare Match interrupt executed. TOV1: Timer/Counter1 Overflow Flag TOV1 (one) when overflow occurs Timer/Counter1. TOV1 cleared hardware when executing corresponding interrupt handling vector. Alternatively, TOV1 cleared writing logical flag. When I-bit SREG TOIE1
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(Tim er/Co ter1 rflow Inte rrup able) Timer/Counter1 Overflow interrupt executed. mode, this when Timer/Counter1 advances from $0000. OCF0: Output Compare Flag OCF0 (one) when compare match occurs between Timer/Counter0 data OCR0 Output Compare Register OCF0 cleared hardware when executing corresponding interrupt handling vector. Alternatively, OCF0 cleared writing logical flag. When I-bit SREG OCIE0 (Timer/Counter2 Compare Interrupt Enable) OCF0 (one), Timer/Counter0 Output Compare interrupt executed. TOV0: Timer/Counter0 Overflow Flag TOV0 (one) when overflow occurs Timer/Counter0. TOV0 cleared hardware when executing corresponding interrupt handling vector. Alternatively, TOV0 cleared writing logical flag. When SREG I-bit TOIE0 (Tim er/Co ter0 rflow Inte rrup able) Timer/Counter0 Overflow interrupt executed. mode, this when Timer/Counter0 advances from $00. Interrupt Response Time interrupt execution response enabled interrupts four clock cycles minimum. Four clock cycles after Interrupt Flag been set, Program Vector address actual interrupt handling routine executed. During this four-clock-cycle period, Program Counter bytes) pushed onto Stack, Stack Pointer decremented vector normally jump interrupt routine, this jump takes three clock cycles. interrupt occurs during execution multi-cycle instruction, this instruction completed before interrupt served. return from interrupt handling routine (same subroutine call routine) takes four clock cycles. During these four clock cycles, Program Counter bytes) popped back from Stack, Stack Pointer incremented When exits from interrupt, will always return main program execute more instruction before pending interrupt served.
Sleep Modes
enter three sleep modes, MCUCR must (one) SLEEP instruction must executed. bits MCUCR Register select which sleep mode (Idle, Power-down, Power-save) will activated SLEEP instruction, Table page enabled interrupt occurs while sleep mode, awakes, executes interrupt routine resumes execution from instruction following SLEEP. contents Register File, SRAM, memory unaltered. reset occurs during sleep mode, wakes executes from Reset Vector.
Idle Mode
When SM1/SM0 bits SLEEP instruction makes enter Idle mode, stopping allowing SPI, UART, Analog Comparator, ADC, Timer/Counters, Watchdog interrupt system continue operating. This enables wake from external triggered interrupts well internal ones like Timer Overflow UART Receive Complete interrupts. wake-up from Analog Comparator interrupt required, Analog Comparator powered down setting ACD-bit Analog Comparator Control Status Register (ACSR). This will reduce power consumption Idle mode. When wakes from Idle mode, starts program execution immediately.
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ATmega103(L)
Power-down Mode When SM1/SM0 bits SLEEP instruction makes enter Power-down mode. this mode, external Oscillator stopped while external interrupts Watchdog enabled) continue operating. Only External Reset, Watchdog Reset enabled), external level interrupt wake MCU. Note that level-triggered interrupt used wake-up from Power-down mode, changed level must held some time wake MCU. This makes less sensitive noise. changed level sampled twice Watchdog Oscillator clock input required level during this time, will wake period Watchdog Oscillator (nominal) 5.0V 25°C. frequency Watchdog Oscillator voltage-dependent, shown "Typical Characteristics" page 123. When waking from Power-down mode, delay from wake-up condition occurs until wake-up becomes effective. This allows clock restart become stable after having been stopped. wake-up period defined same fuses that define Reset Time-out period. wake-up period equal clock reset period, shown Table page wake-up condition disappears before wakes starts execute, e.g., low-level held long enough, interrupt causing wake-up will executed. Power-save Mode When SM1/SM0 bits SLEEP instruction makes enter Power-save mode. This mode identical Power-down, with exception: Timer/Counter0 clocked asynchronously, i.e., ASSR set, Timer/Counter0 will during sleep. addition Power-down wake-up sources, device also wake from either Timer Overflow Output Compare event from Timer/Counter0 corresponding Timer/Counter0 interrupt enable bits TIMSK. ensure that part executes interrupt routine when waking also Global Interrupt Enable SREG. When waking from Power-save mode external interrupt, instruction cycles executed before Interrupt Flags updated. When waking asynchronous timer, three instruction cycles executed before flags updated. During these cycles, processor executes instructions, interrupt condition readable interrupt routine started yet. asynchronous timer clocked asynchronously, Power-down mode recommended instead Power-save mode because contents registers asynchronous timer should considered undefined after wake-up Power-save mode
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Timer/Counters
ATmega103(L) provides three general purpose Timer/Counters 8-bit T/Cs 16-bit T/C. Timer/Counter0 optionally asynchronously clocked from external Oscillator. This Oscillator optimized with 32.768 crystal, enabling Timer/Counter0 Real Time Clock (RTC). Timer/Counter0 prescaler. Timer/Counters have individual prescaling selection from same 10-bit prescaling timer. These Timer/Counters either used Timer with internal clock time base counter with external connection that triggers counting. Figure Prescaler Timer/Counter1 Timer/Counter2
10-BIT PRESCALER
Timer/Counter Prescalers
CK/256
CK/64
CS20 CS21 CS22
CS10 CS11 CS12
TIMER/COUNTER2 CLOCK SOURCE TCK2
TIMER/COUNTER1 CLOCK SOURCE TCK1
Timer/Counters CK/256 CK/1024, where lower than XTAL Timer/Counters added selected clock sources.
four different prescaled selections are: CK/8, CK/64, clock. Observe that clock frequency frequency XTAL divider enabled. selections external source stop
Figure Timer/Counter0 Prescaler
TOSC1 PCK0 10-BIT PRESCALER
PCK0/32 PCK0/128 PCK0/8 PCK0/64 PCK0/256 PCK0/1024
CS00 CS01 CS02
TIMER/COUNTER0 CLOCK SOURCE PCK0
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CK/1024
CK/8
ATmega103(L)
clock source Timer/Counter0 prescaler named PCK0. PCK0 default connected main system clock Observe that clock frequency lower than XTAL frequency XTAL divider enabled. setting ASSR, Timer/Counter0 prescaler asynchronously clocked from TOSC1 pin. This enables Timer/Counter0 Real Time Clock (RTC). crystal connected between TOSC1 TOSC2 pins serve independent clock source Timer/Counter0. This Oscillator optimized with 32.768 crystal.
8-bit Timer/Counters T/C0 T/C2
Figure shows block diagram Timer/Counter0. Figure shows block diagram Timer/Counter2. Figure Timer/Counter0 Block Diagram
T/C0 OVER- T/C0 COMPARE FLOW MATCH
8-BIT DATA 8-BIT ASYNCH T/C0 DATA
OCIE1B TICIE1 OCIE2 OCIE1A OCIE0 TOIE2 TOIE1 TOIE0 OCF0 TOV0
TIMER INT. MASK REGISTER (TIMSK)
OCF2
TIMER INT. FLAG REGISTER (TIFR)
ICF1 OCF2B OCF2A OCF0 TOV2 TOV1 TOV0
T/C0 CONTROL REGISTER (TCCR0)
CS02 CS01 COM01 COM00 PWM0 CTC0 CS00
TIMER/COUNTER0 (TCNT0)
CLEAR SOURCE UP/DOWN
CONTROL LOGIC
PCK0
8-BIT COMPARATOR
OUTPUT COMPARE REGISTER0 (OCR0)
ASYNCH. STATUS REGISTER (ASSR)
OCR0UB ICR0UB TC0UB
TCK0
SYNCH UNIT
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Figure Timer/Counter2 Block Diagram
T/C2 OVER- T/C2 COMPARE FLOW MATCH
8-BIT DATA
TICIE1
OCIE1B
OCIE1A
OCIE2
OCIE0
TOIE2
TOIE1
TOIE0
OCF2
TIMER INT. MASK REGISTER (TIMSK)
OCF2
TOV2
TIMER INT. FLAG REGISTER (TIFR)
ICF1 OCF2B OCF2A OCF0 TOV2 TOV1 TOV0
T/C2 CONTROL REGISTER (TCCR2)
CS22 CS21 COM21 COM20 PWM2 CTC2 CS20
TIMER/COUNTER2 (TCNT2)
CLEAR SOURCE UP/DOWN
CONTROL LOGIC
8-BIT COMPARATOR
OUTPUT COMPARE REGISTER2 (OCR2)
8-bit Timer/Counter0 select clock source from PCK0 prescaled PCK0. 8bit Timer/Counter2 select clock source from prescaled external pin. Both Timer/Counters stopped described specification Timer/Counter Control Registers TCCR0 TCCR2. different Status Flags (Overflow, Compare Match Capture Event) found Timer/Counter Interrupt Flag Register (TIFR). Control signals found Timer/Counter Control Registers TCCR0 TCCR2. interrupt enable/disable settings found Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter2 externally clocked, external signal synchronized with Oscillator frequency CPU. assure proper sampling external clock, minimum time between external clock transitions must least internal clock period. external clock signal sampled rising edge internal clock. 8-bit Timer/Counters feature high-resolution high-accuracy usage with lower prescaling opportunities. Similarly, high prescaling opportunities make these units useful lower speed functions exact timing functions with infrequent actions. Both Timer/Counters support Output Compare functions using Output Compare Registers (OCR0 OCR2) data source compared Timer/Counter contents. Output Compare functions include optional clearing counter compare match action Output Compare pins PB4(OC0/PWM0) PB7(OC2/PWM2) compare match. Timer/Counters also used 8-bit Pulse Width Modulators. this mode Timer/Counter Output Compare Register serve glitch-free, stand-alone with centered pulses. Refer page detailed description this function.
ATmega103(L)
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ATmega103(L)
Timer/Counter0 Control Register TCCR0
($53) Read/Write Initial Value
PWM0
COM01
COM00
CTC0
CS02
CS01
CS00 TCCR0
Timer/Counter2 Control Register TCCR2
($45) Read/Write Initial Value
PWM2
COM21
COM20
CTC2
CS22
CS21
CS20 TCCR2
Res: Reserved This reserved ATmega103(L) always reads zero. PWM0/PWM2: Pulse Width Modulator Enable When (one), this enables mode Timer/Counter0 Timer/Counter2. This mode described page Bits COM01, COM00/COM21, COM20: Compare Output Mode, Bits COMn1 COMn0 control bits determine output action following compare match Timer/Counter2. output actions affect pins (OC0/PWM0) (OC2/PWM2). Since this alternative function port, corresponding direction control must (one) control output pin. control configuration shown Table Table Compare Mode Select
COMn1 Note: COMn0 Description Timer/Counter disconnected from output OCn/PWMn Toggle OCn/PWMn output line. Clear OCn/PWMn output line zero). OCn/PWMn output line one).
mode, these bits have different function. Refer Table detailed description.
CTC0/CTC2: Clear Timer/Counter Compare Match When CTC0 CTC2 control (one), Timer/Counter reset clock cycle after compare match. control cleared, Timer continues counting unaffected compare match. Since compare match detected clock cycle following match, this function will behave differently when prescaling higher than used Timer. When prescaling used Compare Register Timer will count follows CTC0/2 set: When prescaler divide Timer will count like this: C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-1, C-1, C-1, C-1, C-1, C-1, C-1,
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mode, this effect. Bits CS02, CS01, CS00/CS22, CS21, CS20: Clock Select Bits Clock Select2 bits define prescaling source Timer/Counter. Table Timer/Counter0 Prescale Select
CS02 CS01 CS00 Description Timer/Counter0 stopped. PCK0 PCK0/8 PCK0/32 PCK0/64 PCK0/128 PCK0/256 PCK0/1024
Table Timer/Counter2 Prescale Select
CS22 CS21 CS20 Description Timer/Counter2 stopped. CK/8 CK/64 CK/256 CK/1024 External PD7(T2), falling edge External PD7(T2), rising edge
Stop condition provides Timer Enable/Disable function. down divided modes scaled directly from clock. external modes used Timer/Counter2, transitions PD7/(T2) will clock counter even configured output. This feature give user software control counting. Timer/Counter0 TCNT0
($42) Read/Write Initial Value TCNT0
Timer/Counter2 TCNT2
($44) Read/Write Initial Value TCNT2
ATmega103(L)
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ATmega103(L)
These 8-bit registers contain value Timer/Counters. Both Timer/Counters realized up/down mode) counters with read write access. Timer/Counter written clock source selected, continues counting timer clock cycle after preset with written value. Timer/Counter0 Output Compare Register OCR0
($51) Read/Write Initial Value
OCR0
Timer/Counter2 Output Compare Register OCR2
($43) Read/Write Initial Value
OCR2
Output Compare Registers 8-bit read/write registers. Timer/Counter Output Compare Registers contain data continuously compared with Timer/Counter. Actions compare matches specified TCCR0 TCCR2. compare match does only occur Timer/Counter counts value. software write that sets Timer/Counter Output Compare Register same value does generate compare match. compare match will Compare Interrupt Flag clock cycle following compare event. Timer/Counters Mode When mode selected, Timer/Counter Output Compare Register (OCR0 OCR2) form 8-bit, free-running, glitch-free phase correct with outputs PB4(OC0/PWM0) PB7(OC2/PWM2) pin. Timer/Counter acts up/down counter, counting from $FF, where turns counts down again zero before cycle repeated. When counter value matches contents Output Compare Register, PB4(OC0/PWM0) PB7(OC2/PWM2) cleared according settings COM01/COM00 COM21/COM20 bits Timer/Counter Control Registers TCCR0 TCCR2. Refer Table details. Table Compare Mode Select Mode
COMn1 Note: COMn0 Effect Compare/PWM connected connected Cleared compare match, up-counting. compare match, downcounting (non-inverted PWM). Cleared compare match, down-counting. compare match, upcounting (inverted PWM).
Note that mode, Output Compare Register transferred temporary location when written. value latched when Timer/Counter reaches $FF. This prevents occurrence odd-length pulses (glitches) event unsynchronized OCR0 OCR2 write. Figure example.
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Figure Effects Unsynchronized Latching
Compare Value changes
Counter Value Compare Value Output Synchronized Latch
Compare Value changes
Counter Value Compare Value Output Unsynchronized Latch
Glitch
During time between write latch operation, read from OCR0 OCR2 will read contents temporary location. This means that most recently written value always will read OCR0/2. When Register (not temporary register) updated $FF, output changes high immediately according settings COM21/COM20 COM11/COM10. This shown Table Table Outputs OCRn
COMn1 Note: COMn0 OCRn Output PWMn
mode, Timer Overflow Flag, TOV0 TOV2, when counter advances from $00. Timer Overflow Interrupts operate exactly normal Timer/Counter mode, i.e., executed when TOV0 TOV2 set, provided that Timer Overflow interrupt Global Interrupts enabled. This also applies Timer Output Compare Flags interrupts. frequency will Timer Clock Frequency divided 510. Asynchronous Status Register ASSR
($50) Read/Write Initial Value
TCN0UB
OCR0UB
TCR0UB ASSR
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero.
ATmega103(L)
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ATmega103(L)
AS0: Asynchronous Timer/Counter0 When (one), Timer/Counter0 clocked from TOSC1 pin. When cleared (zero), Timer/Counter0 clocked from internal system clock, When value this changed, contents TCNT0 might corrupted. TCN0UB: Timer/Counter0 Update Busy When Timer/Counter0 operates asynchronously TCNT0 written, this becomes (one). When TCNT0 been updated from temporary storage register, this cleared (zero) hardware. logical this indicates that TCNT0 ready updated with value. OCR0UB: Output Compare Register0 Update Busy When Timer/Counter0 operates asynchronously OCR0 written, this becomes (one). When OCR0 been updated from temporary storage register, this cleared (zero) hardware. logical this indicates that OCR0 ready updated with value. TCR0UB: Timer/Counter Control Register0 Update Busy When Timer/Counter0 operates asynchronously TCCR0 written, this becomes (one). When TCCR0 been updated from temporary storage register, this cleared (zero) hardware. logical this indicates that TCCR0 ready updated with value. write performed three Timer/Counter0 Registers while update busy flag (one), updated value might corrupted cause unintentional interrupt occur. When reading TCNT0, OCR0 TCCR0, there difference result. When reading TCNT0, actual timer value read. When reading OCR0 TCCR0, value temporary storage register read. Asynchronous Operation Timer/Counter0 When Timer/Counter0 operates synchronously, operations timing identical Timer/Counter2. During asynchronous operation, however, some considerations must taken. WARNING: When switching between asynchronous synchronous clocking Timer/Counter0, Timer Registers TCNT0, OCR0 TCCR0 might corrupted. following safe procedure switching clock source: Disable Timer0 interrupts OCIE0 TOIE0. Select clock source setting appropriate. Write values TCNT0, OCR0 TCCR0. switching asynchronous operation, wait TCNT0UB, OCR0UB TCR0UB cleared. Clear Timer/Counter0 Interrupt Flags. Enable interrupts needed. Oscillator optimized with 32,768 watch crystal. external clock signal applied this goes through same amplifier having bandwidth kHz. external clock signal should therefore interval kHz. frequency clock signal applied TOSC1 must lower than fourth main clock frequency. Observe that clock frequency lower than XTAL frequency XTAL divider enabled.
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When writing registers TCNT0, OCR0 TCCR0, value transferred temporary register latched after positive edges TOSC1. user should write value before contents temporary register have been transferred destination. Each three mentioned registers have their individual temporary register, which means that e.g., writing TCNT0 does disturb OCR0 write progress. detect that transfer destination register taken place, Asynchronous Status Register (ASSR) been implemented. When entering Power-save mode after having written TCNT0, OCR0 TCCR0, user must wait until written register been updated Timer/Counter0 used wake device. Otherwise, will sleep before changes have effect. This extremely important Output Compare0 interrupt used wake device; Output Compare disabled during write OCR0 TCNT0. write cycle finished (i.e., user goes sleep before OCR0UB returns zero), device will never compare match will wake Timer/Counter0 used wake device from Power-save mode, precautions must taken user wants reenter Power-save mode: interrupt logic needs TOSC1 cycle reset. time between wake-up reentering Power-save mode less than TOSC1 cycle, interrupt will occur device will fail wake user doubt whether time before re-entering Power-save sufficient, following algorithm used ensure that TOSC1 cycle elapsed: Write value TCCR0, TCNT0 OCR0. Wait until corresponding Update Busy Flag ASSR returns zero. Enter Power-save mode.
When asynchronous operation selected, Oscillator Timer/Counter0 always running, except Power-down mode. After Power-up Reset wake-up from Power-down, user should aware fact that this Oscillator might take long second stabilize. user advised wait least second before using Timer/Counter0 after Power-up wake-up from Power-down. content Timer/Counter0 Registers must considered lost after wakeup from Power-down unstable clock signal upon start-up, matter whether Oscillator clock signal applied TOSC pin. Description wake-up from Power-save mode when Timer clocked asynchronously: When interrupt condition met, wake-up process started following cycle Timer clock, that Timer always advanced least before processor read counter value. execute corresponding Timer/Counter0 interrupt routine, Global Interrupt SREG must have been set. Otherwise, part will still wake from Power-down, continues execute Sleep command. Interrupt Flags updated three processor cycles after processor clock started. During these cycles, processor executes instructions, interrupt condition readable interrupt routine started yet. During asynchronous operation, synchronization Interrupt Flags asynchronous Timer takes three processor cycles plus timer cycle. Timer therefore advanced least before processor read Timer value causing setting Interrupt Flag. Output Compare changed Timer clock, synchronized processor clock. After waking from Power-save mode with asynchronous Timer enabled, there will short interval which TCNT0 will read same value before Power-
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ATmega103(L)
save mode entered. After edge asynchronous clock, TCNT0 will read correctly. (The compare overflow functions Timer affected this behavior.) Safe procedure ensure correct value read: Write value either registers OCR0 TCCR0 Wait corresponding Update Busy Flag cleared Read TCNT0 Note that OCR0 TCCR0 never modified hardware, will always read correctly.
16-bit Timer/Counter1
Figure shows block diagram Timer/Counter1. 16-bit Timer/Counter1 select clock source from prescaled external pin. addition, stopped described specification Timer/Counter1 Control Register (TCCR1B). different Status Flags (Overflow, Compare Match Capture Event) found Timer/Counter Interrupt Flag Register (TIFR). Control signals found Timer/Counter1 Control Registers TCCR1A TCCR1B. interrupt enable/disable settings Timer/Counter1 found Timer/Counter Interrupt Mask Register (TIMSK). When Timer/Counter1 externally clocked, external signal synchronized with Oscillator frequency CPU. assure proper sampling external clock, minimum time between external clock transitions must least internal clock period. external clock signal sampled rising edge internal clock. 16-bit Timer/Counter1 features both high-resolution high-accuracy usage with lower prescaling opportunities. Similarly, high prescaling opportunities makes Timer/Counter1 useful lower speed functions exact timing functions with infrequent actions. Timer/Counter1 supports Output Compare functions using Output Compare Registers (OCR1A OCR1B) data sources compared Timer/Counter1 contents. Output Compare functions include optional clearing counter Compare Match, actions Output Compare pins both compare matches.
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Figure Timer/Counter1 Block Diagram
T/C1 OVERFLOW T/C1 COMPARE MATCHA T/C1 COMPARE T/C1 INPUT MATCHB CAPTURE
8-BIT DATA
OCIE1B
OCIE1A
OCF1B
OCF1A
TICIE1
OCIE2
TOIE2
TOIE1
OCIE0
TOIE0
OCF2
OCF0
TOV2
TIMER INT. MASK REGISTER (TIMSK)
TIMER INT. FLAG REGISTER (TIFR)
OCF1B OCF1A ICF1 TOV1
TOV1
ICF1
TOV0
T/C1 CONTROL REGISTER (TCCR1A)
PWM11 COM1A1 COM1B1 PWM10 COM1A0 COM1B0
T/C1 CONTROL REGISTER (TCCR1B)
CS12 ICNC1 CTC1 ICES1 CS10 CS11
T/C1 INPUT CAPTURE REGISTER (ICR1)
CONTROL LOGIC
CAPTURE TRIGGER
TIMER/COUNTER1 (TCNT1)
CLEAR CLOCK SOURCE UP/DOWN
16-BIT COMPARATOR
16-BIT COMPARATOR
TIMER/COUNTER1 OUTPUT COMPARE REGISTER
TIMER/COUNTER1 OUTPUT COMPARE REGISTER
Timer/Counter1 also used 10-bit Pulse Width Modulator. this mode counter OCR1A/OCR1B Registers serve dual glitch-free standalone with centered pulses. Refer page detailed description this function. Input Capture function Timer/Counter1 provides capture Timer/Counter1 contents Input Capture Register (ICR1), triggered external event Input Capture PD4/(IC1). actual capture event settings defined Timer/Counter1 Control Register (TCCR1B). addition, Analog Comparator trigger Input Capture. Refer "Analog Comparator" page details this. logic shown Figure Figure Schematic Diagram
ATmega103(L)
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ATmega103(L)
Noise Canceler function enabled, actual trigger condition capture event monitored over four samples, four must equal activate capture flag. Timer/Counter1 Control Register TCCR1A
($4F) Read/Write Initial Value
COM1A1
COM1A0
COM1B1
COM1B0
PWM11
PWM10 TCCR1A
Bits COM1A1, COM1A0: Compare Output Mode1A, Bits COM1A1 COM1A0 control bits determine output action following compare match Timer/Counter1. output actions affect OC1A Output Compare This alternative function port, corresponding direction control must (one) control output pin. control configuration shown Table Bits COM1B1, COM1B0: Compare Output Mode1B, Bits COM1B1 COM1B0 control bits determine output action following compare match Timer/Counter1. output actions affect OC1B Output Compare Since this alternative function port, corresponding direction control must (one) control output pin. control configuration given Table Table Compare1 Mode Select
COM1X1 Note: COM1X0 Description Timer/Counter1 disconnected from output OC1X Toggle OC1X output line. Clear OC1X output line zero). OC1X output line one).
mode, these bits have different function. Refer Table detailed description.
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. Bits PWM11, PWM10: Pulse Width Modulator Select Bits These bits select operation Timer/Counter1 specified Table page This mode described page Table Mode Select
PWM11 PWM10 Description operation Timer/Counter1 disabled.
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Table Mode Select
PWM11 PWM10 Description Timer/Counter1 8-bit PWM. Timer/Counter1 9-bit PWM. Timer/Counter1 10-bit PWM.
Timer/Counter1 Control Register TCCR1B
($4E) Read/Write Initial Value
ICNC1
ICES1
CTC1
CS12
CS11
CS10 TCCR1B
ICNC1: Input Capture1 Noise Canceler CKs) When ICNC1 cleared (zero), Input Capture Trigger Noise Canceler function disabled. Input Capture triggered first rising/falling edge sampled Input Capture PD4(IC1) specified. When ICNC1 (one), four successive samples measured PD4(IC1), samples must high/low according Input Capture trigger specification ICES1 bit. actual sampling frequency XTAL clock frequency. ICES1: Input Capture1 Edge Select While ICES1 cleared (zero), Timer/Counter1 contents transferred Input Capture Register (ICR1) falling edge Input Capture PD4(IC1). While ICES1 (one), Timer/Counter1 contents transferred Input Capture Register rising edge Input Capture PD4(IC1). Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. CTC1: Clear Timer/Counter1 Compare Match When CTC1 control (one), Timer/Counter1 reset $0000 clock cycle after Compare Match. CTC1 control cleared, Timer/Counter1 continues counting unaffected compare match. Since compare match detected clock cycle following match, this function will behave differently when prescaling higher than used Timer. When prescaling used Compare Register Timer will count follows CTC1 set: When prescaler divide Timer will count like this: C-2, C-2, C-2, C-2, C-2, C-2, C-2, C-1, C-1, C-1, C-1, C-1, C-1, C-1, mode, this effect.
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ATmega103(L)
Bits CS12, CS11, CS10: Clock Select1, Bits lock Select1 bits define prescaling source Timer/Counter1. Table Clock1 Prescale Select
CS12 CS11 CS10 Description Stop, Timer/Counter1 stopped. CK/8 CK/64 CK/256 CK/1024 External falling edge External rising edge
Stop condition provides Timer Enable/Disable function. down divided modes scaled directly from clock. external modes used Timer/Counter1, transitions PD6/(T1) will clock counter even configured output. This feature give user software control counting. Timer/Counter1 TCNT1H TCNT1L
($4D) ($4C)
TCNT1H TCNT1L
Read/Write Initial Value
This 16-bit register contains prescaled value 16-bit Timer/Counter1. ensure that both high bytes read written simultaneously when accesses these registers, access performed using 8-bit temporary register (TEMP). This temporary register also used when accessing OCR1A, OCR1B ICR1. main program interrupt routines perform access registers using TEMP, interrupts must disabled during access from main program (and from interrupt routines interrupts allowed from within interrupt routines). TCNT1 Timer/Counter1 Write: When writes High Byte TCNT1H, written data placed TEMP Register. Next, when writes Byte TCNT1L, this byte data combined with byte data TEMP Register, bits written TCNT1 Timer/Counter1 Register simultaneously. Consequently, High Byte TCNT1H must accessed first full 16-bit register write operation. When using Timer/Counter1 8-bit Timer, sufficient write Byte only. TCNT1 Timer/Counter1 Read: When reads Byte TCNT1L, data TCNT1L sent data High Byte TCNT1H placed TEMP Register. When reads data High Byte TCNT1H, receives data TEMP Register. Consequently, Byte TCNT1L must accessed first
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full 16-bit register read operation. When using Timer/Counter1 8-bit Timer, sufficient read Byte only. Timer/Counter1 realized up/down mode) counter with read write access. Timer/Counter1 written clock source selected, Timer/Counter1 continues counting clock cycle after preset with written value. Timer/Counter1 Output Compare Register OCR1AH OCR1AL
OCR1AH OCR1AL
Read/Write Initial Value
Timer/Counter1 Output Compare Register OCR1BH OCR1BL
OCR1BH OCR1BL
Read/Write Initial Value
Output Compare Registers 16-bit read/write registers. Timer/Counter1 Output Compare Registers contain data continuously compared with Timer/Counter1. Actions compare matches specified Timer/Counter1 Control Status Registers. compare match occurs only Timer/Counter1 counts value. software write that sets TCNT1 OCR1A OCR1B same value does generate compare match. compare match will Compare Interrupt Flag clock cycle following compare event. Since Output Compare Registers (OCR1A OCR1B) 16-bit registers, temporary register TEMP used when OCR1A/B written ensure that both bytes updated simultaneously. When writes High Byte, OCR1AH OCR1BH, data temporarily stored TEMP Register. When writes Byte, OCR1AL OCR1BL, TEMP Register simultaneously written OCR1AH OCR1BH. Consequently, High Byte OCR1AH OCR1BH must written first full 16-bit register write operation. TEMP Register also used when accessing TCNT1 ICR1. main program interrupt routines perform access registers using TEMP, interrupts must disabled during access from main program. Timer/Counter1 Input Capture Register ICR1H ICR1L
($37) ($36)
ICR1H ICR1L
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Read/Write Initial Value
Input Capture Register 16-bit read-only register. When rising falling edge (according Input Capture edge setting (ICES1)) signal Input Capture PD4(IC1) detected, current value Timer/Counter1 transferred Input Capture Register (ICR1). same time, Input Capture Flag (ICF1) (one). Since Input Capture Register (ICR1) 16-bit register, temporary register TEMP used when ICR1 read ensure that both bytes read simultaneously. When reads Byte ICR1L, data sent data High Byte ICR1H placed TEMP Register. When reads data High Byte ICR1H, receives data TEMP Register. Consequently, Byte ICR1L must accessed first full 16-bit register read operation. TEMP Register also used when accessing TCNT1, OCR1A OCR1B. main program interrupt routines perform access registers using TEMP, interrupts must disabled during access from main program. Timer/Counter1 Mode When mode selected, Timer/Counter1, Output Compare Register1A (OCR1A) Output Compare Register1B (OCR1B) form dual 10-bit, free-running, glitch-free phase-correct with outputs PB5(OC1A) PB6(OC1B) pins. Timer/Counter1 acts up/down counter, counting from $0000 (see Table 16), where turns counts down again zero before cycle repeated. When counter value matches contents least significant bits OCR1A OCR1B, PB5(OC1A)/PB6(OC1B) pins cleared according settings COM1A1/COM1A0 COM1B1/COM1B0 bits Timer/Counter1 Control Register, TCCR1A. Refer Table details. Table Timer Values Frequency
Resolution 8-bit 9-bit 10-bit Timer value $00FF (255) $01FF (511) $03FF (1023) Frequency fTCK1/510 fTCK1/1022 fTCK1/2046
Table Compare1 Mode Select Mode
COM1X1 Note: COM1X0 Effect OCX1 connected connected Cleared compare match, up-counting. compare match, down-counting (non-inverted PWM). Cleared compare match, down-counting. compare match, up-counting (inverted PWM).
Note that mode, least significant OCR1A/OCR1B bits, when written, transferred temporary location. They latched when Timer/Counter1 reaches
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value TOP. This prevents occurrence odd-length pulses (glitches) event unsynchronized OCR1A/OCR1B write. Figure example. Figure Effects Unsynchronized OCR1 Latching
Compare Value changes
Counter Value Compare Value Output OC1X Synchronized
Compare Value changes
OCR1X Latch Counter Value Compare Value Output OC1X
Unsynchronized
Note:
OCR1X Latch
Glitch
During time between write latch operation, read from OCR1A OCR1B will read contents temporary location. This means that most recently written value always will read OCR1A/B. When OCR1A/OCR1B contains $0000 TOP, output OC1A/OC1B updated high next compare match according settings COM1A1/COM1A0 COM1B1/COM1B0. This shown Table
Note: Compare Register contains value prescaler (CS12.CS10 001), output will produce pulse all, because upcounting down-counting value reached simultaneously. When prescaler (CS12.CS10 000), output goes active when counter reaches value, down-counting compare match interpreted reached before next time counter reaches value, making one-period pulse.
Table Outputs OCR1X $0000
COM1X1 Note: COM1X0 OCR1X $0000 $0000 Output OC1X
mode, Timer Overflow Flag1, TOV1, when counter advances from $0000. Timer Overflow Interrupt1 operates exactly normal Timer/Counter mode, i.e., executed when TOV1 provided that Timer Overflow Interrupt1 Global Interrupts enabled. This does also apply Timer Output Compare1 flags interrupts.
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ATmega103(L)
Watchdog Timer
Watchdog Timer clocked from separate On-chip Oscillator. controlling Watchdog Timer prescaler, Watchdog Reset interval adjusted shown Table characterization data typical values other levels. (Watchdog Reset) instruction resets Watchdog Timer. From Watchdog Reset, eight different clock cycle periods selected determine reset period. reset period expires without another Watchdog Reset, ATmega103(L) resets executes from Reset Vector. timing details Watchdog Reset, refer page prevent unintentional disabling Watchdog, special turn-off procedure must followed when Watchdog disabled. Refer description Watchdog Timer Control Register details. Figure Watchdog Timer
Oscillator
Watchdog Timer Control Register WDTCR
($41) Read/Write Initial Value
WDTOE
WDP2
WDP1
WDP0 WDTCR
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) will always read zero. WDTOE: Watchdog Turn-off Enable This must (one) when cleared, Otherwise, Watchdog will disabled. Once set, hardware will clear this zero after four clock cycles. Refer description Watchdog disable procedure. WDE: Watchdog Enable When (one), Watchdog Timer enabled cleared (zero), Watchdog Timer function disabled. only cleared WDTOE (one). disable enabled Watchdog Timer, following procedure must followed:
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same operation, write logical WDTOE WDE. logical must written even though before disable operation starts. Within next four clock cycles, write logical WDE. This disables Watchdog. Bits WDP2, WDP1, WDP0: Watchdog Timer Prescaler WDP2, WDP1 WDP0 bits determine Watchdog Timer prescaling when Watchdog Timer enabled. different prescaling values their corresponding Time-out periods shown Table Table Watchdog Timer Prescale Select
WDP2 Note: WDP1 WDP0 Number Oscillator Cycles cycles cycles cycles 128K cycles 256K cycles 512K cycles 1,024K cycles 2,048K cycles Typical Time-out 3.0V 0.19 0.38 0.75 Typical Time-out 5.0V 0.12 0,24 0.49 0.97
frequency Watchdog Oscillator voltage-dependent shown Electrical Characteristics section. (Watchdog Reset) instruction should always executed before Watchdog Timer enabled. This ensures that reset period will accordance with Watchdog Timer prescale settings. Watchdog Timer enabled without reset, Watchdog Timer start counting from zero. avoid unintentional Reset, Watchdog Timer should disabled reset before changing Watchdog Timer Prescale Select.
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ATmega103(L)
EEPROM Read/Write Access
EEPROM Access Registers accessible space. write access time range depending voltages. self-timing function lets user software detect when next byte written. special EEPROM Ready interrupt trigger when EEPROM ready accept data. order prevent unintentional EEPROM writes, specific write procedure must followed. Refer description EEPROM Control Register details this. When EEPROM written, halted clock cycles before next instruction executed. When read, halted four clock cycles. EEPROM Address Register EEARH, EEARL
($3F) ($3E)
EEAR7
EEAR6
EEAR5
EEAR4
EEAR11 EEAR3
EEAR10 EEAR2
EEAR9 EEAR1
EEAR8 EEAR0 EEARH EEARL
Read/Write
Initial Value
EEPROM Address Registers (EEARH EEARL) specify EEPROM address EEPROM space. EEPROM Data bytes addressed linearly between 4095. EEPROM Data Register EEDR
($3D) Read/Write Initial Value
EEDR
Bits EEDR7.0: EEPROM Data: EEPROM write operation, EEDR Register contains data written EEPROM address given EEAR Register. EEPROM read operation, EEDR contains data read from EEPROM address given EEAR. EEPROM Control Register EECR
($3C) Read/Write Initial Value
EERIE
EEMWE
EEWE
EERE EECR
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) will always read zero. EERIE: EEPROM Ready Interrupt Enable When I-bit SREG EERIE (one), EEPROM Ready interrupt enabled. When cleared (zero), interrupt disabled. EEPROM Ready interrupt constantly generates interrupt request when EEWE cleared (zero).
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EEMWE: EEPROM Master Write Enable EEMWE determines whether setting EEWE causes EEPROM written. When EEMWE (one), setting EEWE will write data EEPROM selected address. EEMWE zero, setting EEWE will have effect. When EEMWE been (one) software, hardware clears zero after four clock cycles. description EEWE EEPROM write procedure. EEWE: EEPROM Write Enable EEPROM Write Enable signal (EEWE) write strobe EEPROM. When address data correctly EEWE must write value into EEPROM. EEMWE must when logical written EEWE, otherwise EEPROM write takes place. following procedure should followed when writing EEPROM (the order steps unessential): Wait until EEWE becomes zero. Write EEPROM address EEAR (optional). Write EEPROM Data EEDR (optional). Write logical EEMWE EECR able write logical EEMWE bit, EEWE must written zero same cycle). Within four clock cycles after setting EEMWE, write logical EEWE. Caution: interrupt between step step will make write cycle fail, since EEPROM Master Write Enable will time-out. interrupt routine accessing EEPROM interrupting another EEPROM access, EEAR EEDR Registers will modified, causing interrupted EEPROM access fail. recommended have Global Interrupt Flag cleared during four last steps avoid these problems. When write access time (typically 2.7V) elapsed, EEWE cleared (zero) hardware. user software poll this wait zero before writing next byte. When EEWE been set, halted cycles before next instruction executed. EERE: EEPROM Read Enable EEPROM Read Enable signal (EERE) read strobe EEPROM. When correct address EEAR Register, EERE must set. When EERE cleared (zero) hardware, requested data found EEDR Register. EEPROM read access takes instruction there need poll EERE bit. When EERE been set, halted four cycles before next instruction executed. user should poll EEWE before starting read operation. write operation progress when data address written EEPROM Registers, write operation will interrupted result undefined.
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Prevent EEPROM Corruption
During periods VCC, EEPROM Data corrupted because supply voltage EEPROM operate properly. These issues same board-level systems using EEPROM same design solutions should applied. EEPROM Data corruption caused situations when voltage low. First, regular write sequence EEPROM requires minimum voltage operate correctly. Second, itself execute instructions incorrectly supply voltage executing instructions low. EEPROM Data corruption easily avoided following these design recommendations (one sufficient): Keep RESET active (low) during periods insufficient power supply voltage. This best done external Reset Protection circuit, often referred Brown-out Detector (BOD). Please refer application note "AVR 180" design considerations regarding Power-on Reset low-voltage detection. Keep core Power-down sleep mode during periods VCC. This will prevent from attempting decode execute instructions, effectively protecting EEPROM Registers from unintentional writes. Store constants Flash memory ability change memory contents from software required. Flash memory cannot updated will subject corruption.
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Serial Peripheral Interface
Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between ATmega103(L) peripheral devices between several devices. ATmega103(L) features include following: Full-duplex, Three-wire Synchronous Data Transfer Master Slave Operation First First Data Transfer Four Programmable Rates End-of-Transmission Interrupt Flag Write Collision Flag Protection Wake-up from Idle Mode (Slave Mode only)
Figure Block Diagram
interconnection between Master Slave CPUs with shown Figure (SCK) clock output Master mode clock input Slave mode. Writing Data Register Master starts clock generator, data written shifts (MOSI) into (MOSI) Slave CPU. After shifting byte, clock generator stops, setting End-of-Transmission Flag (SPIF). interrupt enable (SPIE) SPCR Register set, interrupt requested. Slave Select input, PB0(SS), select individual Slave device. Shift Registers Master Slave considered distributed 16-bit circular Shift Register. This shown Figure When data shifted from Master Slave, data also shifted opposite direction, simultaneously. This means that during shift cycle, data Master Slave interchanged.
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ATmega103(L)
Figure Master-Slave Interconnection
MASTER
MISO MISO
SLAVE
8-BIT SHIFT REGISTER
MOSI MOSI
8-BIT SHIFT REGISTER
CLOCK GENERATOR
system single-buffered transmit direction double-buffered receive direction. This means that characters transmitted cannot written Data Register before entire shift cycle completed. When receiving data, however, received byte must read from Data Register before next byte been completely shifted Otherwise, first byte lost. When enabled, data direction MOSI, MISO, pins overridden according following table: Table Overrides
MOSI MISO Note: Direction, Master User Defined Input User Defined User Defined Direction, Slave Input User Defined Input Input
"Alternate Functions Port page detailed description define direction user-defined pins.
Functionality
When configured Master (MSTR SPCR set), user determine direction pin. configured output, general output that does affect system. configured input, must held high ensure Master operation. driven peripheral circuitry when configured Master with defined input, system interprets this another Master selecting Slave starts send data avoid contention, system takes following actions: MSTR SPCR cleared system becomes Slave. result becoming Slave, MOSI pins become inputs. SPIF Flag SPSR set, interrupt enabled I-bit SREG set, interrupt routine will executed. Thus, when interrupt-driven transmittal used Master mode there exists possibility that driven low, interrupt should always check that MSTR still set. Once MSTR been cleared Slave Select, must user re-enable Master mode. When configured Slave, always input. When held low, activated MISO becomes output configured user. other pins inputs. When driven high, pins inputs passive, which means that will receive incoming data. Note that logic will reset once
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brought high. brought high during transmission, will stop sending receiving immediately both data received data sent must considered lost.
Data Modes
There four combinations phase polarity with respect serial data that determined control bits CPHA CPOL. data transfer formats shown Figure Figure Figure Transfer Format with CPHA DORD
CYCLE (FOR REFERENCE) (CPOL=0) (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SLAVE) SAMPLE
defined normally character just received.
Figure Transfer Format with CPHA DORD
CYCLE (FOR REFERENCE) (CPOL=0) (CPOL=1) MOSI (FROM MASTER) MISO (FROM SLAVE) SLAVE)
SAMPLE
defined normally previously transmitted character.
Control Register SPCR
($2D) Read/Write Initial Value SPIE DORD MSTR CPOL CPHA SPR1 SPR0 SPCR
SPIE: Interrupt Enable This causes interrupt executed SPIF SPSR Register Global Interrupts enabled. SPE: Enable When (one), enabled MOSI, MISO connected pins PB0, PB1, PB3.
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ATmega103(L)
DORD: Data Order When DORD (one), data word transmitted first. When DORD cleared (zero), data word transmitted first. MSTR: Master/Slave Select This selects Master mode when (one), Slave mode when cleared (zero). configured input driven while MSTR set, MSTR will cleared SPIF SPSR will become set. user will then have MSTR reenable Master mode. CPOL: Clock Polarity When this (one), high when idle. When CPOL cleared (zero), when idle. Refer Figure Figure additional information. CPHA: Clock Phase Refer Figure Figure functionality this bit. Bits SPR1, SPR0: Clock Rate Select These bits control rate device configured Master. SPR1 SPR0 have effect Slave. relationship between Clock frequency (fcl) shown Table Table Relationship between Oscillator Frequency
SPR1 Note: SPR0 Frequency
fcl/4 fcl/16 fcl/64 fcl/128
Observe that clock frequency lower than XTAL frequency XTAL divider enabled.
Status Register SPSR
Read/Write Initial Value SPIF WCOL SPSR
SPIF: Interrupt Flag When serial transfer complete, SPIF (one) interrupt generated SPIE SPCR (one) Global Interrupts enabled. SPIF cleared hardware when executing corresponding interrupt handling vector. Alternatively, SPIF cleared first reading Status Register with SPIF (one), then accessing Data Register (SPDR). WCOL: Write Collision Flag WCOL Data Register (SPDR) written during data transfer. WCOL (and SPIF bit) cleared (zero) first reading Status Register with WCOL (one), then accessing Data Register.
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Bits Res: Reserved Bits These bits reserved bits ATmega103(L) will always read zero.
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ATmega103(L)
Data Register SPDR
($2F) Read/Write Initial Value Undefined SPDR
Data Register read/write register used data transfer between Register File Shift Register. Writing register initiates data transmission. Reading register causes Shift Register Receive buffer read.
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UART
ATmega103(L) features full duplex (separate Receive Transmit Registers) Universal Asynchronous Receiver Transmitter (UART). main features are: Baud Rate Generator that Generate large Number Baud Rates (bps) High Baud Rates XTAL Frequencies Bits Data Noise Filtering OverRun Detection Framing Error Detection False Start Detection Three separate Interrupts Complete, Data Register Empty Complete block schematic UART Transmitter shown Figure Data transmission initiated writing data transmitted UART Data Register, UDR. Data transferred from Transmit Shift Register when: character been written after stop from previous character been shifted out. Shift Register loaded immediately. character been written before stop from previous character been shifted out. Shift Register loaded when stop character currently being transmitted been shifted out.
Data Transmission
10(11)-bit Transmit Shift Register empty, data transferred from Shift Register. this time UDRE (UART Data Register Empty) UART Status Register, USR, set. When this (one), UART ready receive next character. Writing clears UDRE. same time data transferred from 10(11)-bit Shift Register, Shift Register cleared (start bit) (stop bit). 9-bit data word selected (the CHR9 UART Control Register, set), TXB8 transferred Transmit Shift Register.
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ATmega103(L)
Figure UART Transmitter
DATA
XTAL
BAUD RATE GENERATOR
BAUD
UART DATA REGISTER (UDR)
STORE SHIFT ENABLE
CONTROL LOGIC CONTROL LOGIC
IDLE BAUD
10(11)-BIT SHIFT REGISTER
UART CONTROL REGISTER (UCR)
RXCIE TXCIE UDRIE
RXEN TXEN CHR9 RXB8 TXB8
DATA
UDRE
baud rate clock following transfer operation Shift Register, start shifted pin, followed data, first. When stop been shifted out, Shift Register loaded data been written during transmission. During loading, UDRE set. there data Register send when stop shifted out, UDRE Flag will remain set. this case, after stop been present length, Complete Flag (TXC) set. TXEN enables UART Transmitter when (one). When this cleared (zero), used general I/O. When TXEN set, UART Transmitter will connected PE1, which forced output regardless setting DDE1 DDRE.
UDRE
UART STATUS REGISTER (USR)
UDRE
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Data Reception
Figure UART Receiver
DATA
XTAL
BAUD RATE GENERATOR
BAUD
BAUD
UART DATA REGISTER (UDR)
STORE
CONTROL LOGIC DATA RECOVERY LOGIC 10(11)-BIT SHIFT REGISTER
UART CONTROL REGISTER (UCR)
RXCIE TXCIE UDRIE
DATA
Receiver front-end logic samples signal frequency times baud rate. While line idle, single sample logical will interpreted falling edge start bit, start detection sequence initiated. sample denote first zero-sample. Following 1-to-0 transition, Receiver samples samples more these three samples found logical "1"s, start rejected noise spike Receiver starts looking next 1-to-0 transition. however, valid start detected, sampling data bits following start performed. These bits also sampled samples logical value found least three samples taken value. bits shifted into Transmitter Shift Register they sampled. Sampling incoming character shown Figure
ATmega103(L)
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UDRE
RXEN TXEN CHR9 RXB8 TXB8
UART STATUS REGISTER (USR)
ATmega103(L)
Figure Sampling Received Data
START RECEIVER SAMPLING STOP
When stop enters Receiver, majority three samples must accept stop bit. more samples logical "0"s, Framing Error (FE) Flag UART Status Register (USR) when received byte transferred UDR. Before reading Register, user should always check detect Framing Errors. cleared when read. Whether valid stop detected character reception cycle, data transferred Flag set. fact physically separate registers, transmitted data received data. When read, Receive Data Register accessed, when written, Transmit Data Register accessed. 9-bit data word selected (the CHR9 UART Control Register, set), RXB8 loaded with Transmit Shift Register when data transferred UDR. after having received character, Register been accessed since last receive, OverRun (OR) flag set. This means that data transferred Shift Register could transferred lost. buffered, available when valid data byte been read. user should always check after reading from Register order detect OverRuns baud rate high load high. When RXEN Register cleared (zero), Receiver disabled. This means that used general pin. When RXEN set, UART Receiver will connected PE0, which forced input regardless setting DDE0 DDRE. When forced input UART, PORTE0 still used control pull-up resistor pin. When CHR9 Register set, transmitted received characters bits long plus start stop bits. data transmitted TXB8 Register. This must wanted value before transmission initated writing Register.
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UART Control
UART Data Register
($2C) Read/Write Initial Value
Register actually physically separate registers sharing same address. When writing register, UART Transmit Data Register written. When reading from UDR, UART Receive Data Register read. UART Status Register
($2B) Read/Write Initial Value UDRE
Register read-only register providing information UART Status. RXC: UART Receive Complete This (one) when received character transferred from Receiver Shift Register UDR. regardless detected framing errors. When RXCIE set, UART Receive Complete interrupt will executed when (one). cleared reading UDR. When interrupt-driven data reception used, UART Receive Complete Interrupt routine must read order clear RXC, otherwise interrupt will occur once interrupt routine terminates. TXC: UART Transmit Complete This (one) when entire character (including stop bit) Transmit Shift Register been shifted data been written UDR. This flag especially useful half-duplex communications interfaces, where transmitting application must enter Receive mode free communications immediately after completing transmission. When TXCIE set, setting causes UART Transmit Complete interrupt executed. cleared hardware when executing corresponding interrupt handling vector. Alternatively, cleared (zero) writing logical bit. UDRE: UART Data Register Empty This (one) when character written transferred Transmit Shift Register. Setting this indicates that Transmitter ready receive character transmission. When UDRIE set, UART Transmit Complete interrupt executed long UDRE set. UDRE cleared writing UDR. When interrupt-driven data transmittal used, UART Data Register Empty Interrupt routine must write order clear UDRE, otherwise interrupt will occur once interrupt routine terminates. UDRE (one) during reset indicate that Transmitter ready.
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Framing Error This Framing Error condition detected, i.e., when stop incoming character zero. cleared when stop received data one. OverRun This OverRun condition detected, i.e., when character already present Register read before next character transferred from Receiver Shift Register. buffered, which means that will once valid data still UDRE read. cleared (zero) when data received transferred UDR. Bits Res: Reserved Bits These bits reserved bits ATmega103(L) will always read zero. UART Control Register
($2A) Read/Write Initial Value RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8
RXCIE: Complete Interrupt Enable When this (one), setting will cause Receive Complete Interrupt routine executed, provided that global interrupts enabled. TXCIE: Complete Interrupt Enable When this (one), setting will cause Transmit Complete Interrupt routine executed, provided that global interrupts enabled. UDRIE: UART Data Register Empty Interrupt Enable When this (one), setting UDRE will cause UART Data Register Empty Interrupt routine executed, provided that global interrupts enabled. RXEN: Receiver Enable This enables UART Receiver when (one). When Receiver disabled, RXC, Status Flags cannot become set. these flags set, turning RXEN does cause them cleared. TXEN: Transmitter Enable This enables UART Transmitter when (one). When disabling Transmitter while transmitting character, Transmitter disabled before character Shift Register plus following character been completely transmitted. CHR9: 9-bit Characters When this (one), transmitted received characters nine bits long, plus start stop bits. ninth read written using RXB8 TXB8 bits UCR, respectively. ninth data used extra stop parity bit.
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RXB8: Receive Data When CHR9 (one), RXB8 ninth data received character. TXB8: Transmit Data When CHR9 (one), TXB8 ninth data character transmitted.
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Baud Rate Generator baud rate generator frequency divider that generates baud rates according following equation: BAUD UBRR BAUD baud rate clock frequency UBRR contents UART Baud Rate Register, UBRR 255)
standard crystal frequencies, most commonly used baud rates generated using UBRR settings Table Observe that clock frequency lower than XTAL frequency XTAL divider enabled. UBRR values that yield actual baud rate differing less than from target baud rate boldface table. However, using baud rates that have more than error recommended. High error ratings give less noise resistance.
0945I-AVR-02/07
Table UBRR Settings Various Frequencies
Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 Baud Rate 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 %Error 1.8432 %Error %Error 2.4576 %Error UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= 22.9 UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= 12.5 UBRR= UBRR= 22.9 UBRR= 33.3 UBRR= 22.9 UBRR= UBRR= 84.3 UBRR= UBRR= 25.0 UBRR= 3.2768 %Error 3.6864 %Error %Error 4.608 %Error UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= 12.5 UBRR= UBRR= UBRR= UBRR= 12.5 UBRR= UBRR= UBRR= UBRR= 12.5 UBRR= UBRR= 20.0 UBRR= 7.3728 %Error %Error 9.216 %Error 11.059 %Error UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR= UBRR=
UART Baud Rate Register UBRR
($29) Read/Write Initial Value
UBRR
UBRR 8-bit read/write register that specifies UART baud rate according description previous page.
ATmega103(L)
0945I-AVR-02/07
ATmega103(L)
Analog Comparator
analog comparator compares input values positive input (AC+) negative input (AC-). When voltage positive input (AC+) higher than voltage negative input (AC-), Analog Comparator Output (ACO) (one). output comparator trigger Timer/Counter1 Input Capture function. addition, comparator trigger separate interrupt, exclusive analog comparator. user select interrupt triggering comparator output rise, fall toggle. block diagram comparator surrounding logic shown Figure Figure Analog Comparator Block Diagram
ACIE (AC+) ANALOG COMPARATOR ACIS1 ACIS0 ACIC
INTERRUPT SELECT
(AC-)
T/C1 CAPTURE TRIGGER
Analog Comparator Control Status Register ACSR
($28) Read/Write Initial Value
ACIE
ACIC
ACIS1
ACIS0 ACSR
ACD: Analog Comparator Disable When this (one), power analog comparator switched off. This time turn analog comparator. This will reduce power consumption active Idle mode. When changing bit, Analog Comparator interrupt must disabled clearing ACIE ACSR. Otherwise, interrupt occur when changed. Res: Reserved This reserved ATmega103(L) will always read zero. ACO: Analog Comparator Output directly connected comparator output. ACI: Analog Comparator Interrupt Flag This (one) when comparator output event triggers interrupt mode defined ACI1 ACI0. Analog Comparator Interrupt routine executed ACIE (one) I-bit SREG (one). cleared hardware when execut-
0945I-AVR-02/07
corresponding interrupt handling vector. Alternatively, cleared writing logical flag. Observe, however, that another this register modified using instruction, will cleared become before operation. ACIE: Analog Comparator Interrupt Enable When ACIE (one) I-bit Status Register (one), Analog Comparator interrupt activated. When cleared (zero), interrupt disabled. ACIC: Analog Comparator Input Capture Enable When (one), this enables Input Capture function Timer/Counter1 triggered analog comparator. comparator output this case, directly connected Input Capture front-end logic, making comparator utilize noise canceler edge select features Timer/Counter1 Input Capture interrupt. When cleared (zero), connection between analog comparator Input Capture function given. make comparator trigger Timer/Counter1 Input Capture interrupt, TICIE1 Timer Interrupt Mask Register (TIMSK) must (one). Bits ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine which comparator events that trigger Analog Comparator interrupt. different settings shown Table Table ACIS1/ACIS0 Settings
ACIS1 ACIS0 Interrupt Mode Comparator Interrupt Output Toggle Reserved Comparator Interrupt Falling Output Edge Comparator Interrupt Rising Output Edge
When changing ACIS1/ACIS0 bits, Analog Comparator interrupt must disabled clearing Interrupt Enable ACSR Register. Otherwise, interrupt occur when bits changed. Caution: Using instruction other bits than this register will write back into read set, thus clearing flag.
ATmega103(L)
0945I-AVR-02/07
ATmega103(L)
Analog-to-Digital Converter
Feature list:
10-bit Resolution Absolute Accuracy Integral Non-linearity Conversion Time kSPS Multiplexed Input Channels Interrupt Conversion Complete Sleep Mode Noise Canceler
ATmega103(L) features 10-bit successive approximation ADC. connected 8-channel Analog Multiplexer, which allows each Port used input ADC. contains Sample Hold Amplifier, which ensures that input voltage held constant level during conversion. block diagram shown Figure separate analog supply voltage pins, AVCC AGND. AGND must connected GND, voltage AVCC must differ more than 0.3V from VCC. section "ADC Noise Canceling Techniques" page connect these pins. external reference voltage must applied AREF pin. This voltage must range AGND AVCC. Figure Analog-to-Digital Converter Block Schematic
CONVERSION COMPLETE
8-BIT DATA
External Reference Voltage
ADIF
ADIE
DATA REGISTER (ADCH/ADCL)
MULTIPLEXER SELECT (ADMUX)
MUX2 MUX1 MUX0
CTRL STATUS REGISTER (ADCSR)
ADEN ADSC ADIE ADIF ADPS2 ADPS1 ADPS0
10-BIT 8CHANNEL
CONVERSION LOGIC
Analog Inputs
SAMPLE HOLD COMPARATOR
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Operation
operates Single Conversion mode, each conversion will have initiated user. enabled writing logical Enable bit, ADEN ADCSR. first conversion that started after enabling will preceded dummy conversion initialize ADC. user, only difference will that this conversion takes more clock pulses than normal conversion (see Figure 48). conversion started writing logical Start Conversion bit, ADSC. This will stay high long conversion progress zero hardware when conversion completed. different data channel selected while conversion progress, will finish current conversion before performing channel change. generates 10-bit result, Data Registers, ADCH ADCL, must read result when conversion complete. Special data protection logic used ensure that contents Data Registers belong same result when they read. This mechanism works follows: When reading data, ADCL must read first. Once ADCL read, access Data Registers blocked. This means that ADCL been read, conversion completes before ADCH read, none registers updated result from conversion lost. When ADCH read, access ADCH ADCL Registers re-enabled. interrupt, ADIF, which triggered when conversion completes. When access Data Registers prohibited between reading ADCL ADCH, interrupt will trigger even result lost.
Prescaling
Figure Prescaler
ADEN Reset 7-BIT PRESCALER
ADPS0 ADPS1 ADPS2
CLOCK SOURCE
contains prescaler, which divides system clock acceptable clock frequency. accepts input clock frequencies range kHz. Applying higher input frequency will result poorer accuracy (see "ADC Characteristics" page 83). ADPS0 ADPS2 bits ADCSR used generate proper clock input frequency from XTAL frequency above kHz. prescaler starts counting from moment switched setting ADEN ADCSR. prescaler
ATmega103(L)
0945I-AVR-02/07
CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
ATmega103(L)
keeps running long ADEN continuously reset when ADEN low. When initiating conversion setting ADSC ADCSR, conversion starts following falling edge clock cycle. actual sample-and-hold takes place clock cycle after start conversion. result ready written Result Register after cycles. needs more clock cycles before conversion started. ADSC high this period, will start conversion immediately. summary conversion times, Table Figure Timing Diagram, First Conversion
Cycle number
clock ADEN ADSC Hold strobe ADIF ADCH ADCL result result
Dummy Conversion
Actual Conversion
Second Conversion
Table Conversion Time
Sample Cycle Number Result Ready (Cycle Number) Total Conversion Time (Cycles) Total Conversion Time (µs)
Condition Conversion Single Conversion
Figure Timing Diagram
Cycle number clock ADSC Hold strobe ADIF ADCH ADCL result result
Conversion
Next Conversion
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Noise Canceler Function
features noise canceler that enables conversion during Idle mode reduce noise induced from core. make this feature, following procedure should used: Turn clearing ADEN. Turn simultaneously start conversion setting ADEN ADSC. This starts dummy conversion that will followed valid conversion. Within clock cycles, enter Idle mode. other interrupts occur before conversion completes, interrupt will wake execute conversion complete interrupt routine.
Multiplexer Select Register ADMUX
($27) Read/Write Initial Value
MUX2
MUX1
MUX0 ADMUX
Bits Res: Reserved Bits These bits reserved bits ATmega103(L) always read zero. Bits MUX2.MUX0: Analog Channel Select Bits value these three
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