8k-flash Microcontroller ATAM894 Description ATAM894 member
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8-bit EEPROM EEPROM Programmable Options Read Protection EEPROM Program Memory 4-bit 16-bit Data EEPROM Seven External/Internal Interrupt Sources Eight Hardware Software Interrupt Priorities Bi-directional I/Os Wide Supply-voltage Range (1.8V 6.5V) Very Sleep Current Synchronous Serial Interface (2-wire, 3-wire) Multifunction Timer/Counter with Prescaler/Interval Timer Voltage Monitoring Inclusive Lo_BAT Detect Watchdog, Brown-out Function
8k-flash Microcontroller ATAM894
Description
ATAM894 member Atmel's family 4-bit single chip microcontrollers with 8-bit EEPROM program memory. based version ATAM893 fully compatible with this versions ATAR090/890 ATAR092/892. Figure 1-1. Block Diagram
OSC1 OSC2
Brown-out protect. RESET Voltage monitor External input BP10 Port BP13
Data direction
Crystal oscillators oscillators
External clock input
UTCM Timer interval- watchdog timer Timer with prescaler
Clock management
EEPROM
Modulator
BP20/NTE
Port
MARC4
4-bit core
Serial interface Modulator Demodulator Timer timer/counter
BP21 BP22 BP23
Data direction alternate function Port
Data direction interrupt control Port
Data dir. alt. function Port
EEPROM
BP40 BP42 BP52 BP50 INT3 INT6 INT1 BP43 BP51 BP53 BP41 INT3 INT6 INT1
BP60
BP63
Rev. 4679D-4BMCU-05/05
Configuration
Figure 2-1. Pinning SSO24 Package
BP40/INT3/SC
BP43/INT3/SD BP42/T2O BP41/VMI/T2I BP23 BP22 BP21 BP20/NTE BP63/T3I BP13
BP53/INT1 BP52/INT1 BP51/INT6 BP50/INT6
OSC1 OSC2 BP60/T3O BP10
Table 2-1.
Description
Symbol BP40 BP53 BP52 BP51 BP50 OSC1 OSC2 BP60 BP10 BP13 BP63 BP20 BP21 BP22 BP23 Type Function connected connected Supply voltage Alternate Function Reset State Input Input Input Input Input
Bi-directional line Port SC-serial clock INT3 external interrupt input Bi-directional line Port INT1 external interrupt input Bi-directional line Port INT1 external interrupt input Bi-directional line Port INT6 external interrupt input Bi-directional line Port INT6 external interrupt input Oscillator input Oscillator output
4-MHz crystal input 32-kHz crystal input external Input clock input external trimming resistor input 4-MHz crystal output 32-kHz crystal output external clock input Input Input Input Input Input
Bi-directional line Port Timer output Bi-directional line Port Bi-directional line Port Bi-directional line Port Timer input
test mode enable, section "Master Reset" Bi-directional line Port Input page Bi-directional line Port Bi-directional line Port Bi-directional line Port Input Input Input
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Table 2-1.
Description (Continued)
Symbol BP41 BP42 BP43 Type Function Bi-directional line Port Alternate Function voltage monitor input external clock input Timer Reset State Input Input Input Input
Bi-directional line Port Timer output Bi-directional line Port serial data INT3 external interrupt input Circuit ground connected connected
Introduction
ATAM894 member Atmel's family 4-bit single-chip microcontrollers. Instead contains EEPROM, RAM, parallel ports, 8-bit programmable multifunction timer/counters, voltage supervisor, interval timer with watchdog function sophisticated on-chip clock generation with integrated RC-, 32-kHz 4-MHz crystal oscillators.
Differences Between ATAM894 ATARx90/x92
Program Memory
program memory device realized EEPROM. memory size user programs 8192 bytes. programmed 32-byte blocks data. implemented LOCK function user selectable protects device from unauthorized read program memory.
Configuration Memory
additional area bytes EEPROM used store information about hardware configuration. options that selectable versions available user. This includes only different port options also possibilities select different capacitors OSC1 OSC2, option enable disable hardlock watchdog, option select OSC2 instead OSC1 external clock input option enable external clock monitor reset source. Activating options performed reset circuitry. Reset starts download sequence transfer information from memory into shift register (configuration register).
Data Memory
ATAM894 contains internal data EEPROM that organized pages bit. necessary compatible with parts, only page must used with flash part. Also compatibility reasons access EEPROM handled (serial interface) corresponding parts. behavioral difference that only needs considered error handling seen, when communication terminated correctly. missing STOP condition leads significantly higher current consumption parts compared flash parts. slightly different concept read amplifiers memory makes flash part more tolerant terms communication errors.
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Reset Function
During each reset (power-on brown-out) configuration register reset reloaded with data from configuration memory. This leads slightly different behavior compared versions. Both devices switch their I/Os input during reset part mask selected pull-up pull-down resistors active while them removed until download finished.
MARC4 Architecture
General Description
MARC4 microcontroller consists advanced stack-based, 4-bit core on-chip peripherals. based Harvard architecture with physically separate program memory (ROM) data memory (RAM). Three independent buses, instruction bus, memory bus, used parallel communication between ROM, peripherals. This enhances program execution speed allowing both instruction prefetching, simultaneous communication on-chip peripheral circuitry. extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast efficient processing hardware events. MARC4 designed high-level programming language qFORTH. core includes both, expression return stack. This architecture enables high-level language programming without loss efficiency code density. Figure 5-1. MARC4 Core
MARC4 CORE
Reset Program memory 4-bit
Reset Clock
Instruction Memory Instruction decoder Interrupt controller
System clock Sleep
On-chip peripheral modules
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Components MARC4 Core
core contains ROM, RAM, ALU, program counter, address registers, instruction decoder interrupt controller. following sections describe each functional block more detail.
5.2.1
Program Memory program memory (EEPROM) electrically programmable erasable with customer application program. program memory addressed 12-bit wide program counter additional bank register, thus predefining maximum linear adressable program bank size Kbytes. upper Kbytes exchanged banking, thus allowing address maximum Kbytes user program. Kbytes program memory available within ATAM894. lowest user (EEP)ROM address segment taken 512-byte zero page which contains predefined start addresses interrupt service routines special subroutines accessible with single byte instructions (SCALL).
corresponding memory shown Figure 5-2. Look-up tables constants also held accessed MARC4's built-in table instruction.
Figure 5-2.
Bank
Port 11xxb
Bank
1FFh
1E8h 1E0h
1E0h
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
Port 10xxb
SCALL addresses
Bank
FFFh Port 01xxb
Bank
Port 00xxb
page
100h 080h
800h 7FFh
Base bank
Zero page 000h
000h
020h 008h 000h
000h
$RESET $AUTOSLEEP
5.2.1.1
Banking customers programming with qFORTH bank switching fully supported compiler. MARC4 switches from bank another writing bank number Bank Register (RBR). Conventional program space (power-up bank) resides bank Each bank consists Kbyte address space whereby lowest Kbyte, base bank, common banks, that addresses between 000h 7FFh always access same data (see Figure 5-2). When banking used, compiler will, necessary, insert program code save restore condition bank switching.
ATAM894 contains 4-bit wide static random access memory (RAM). used expression stack, return stack data memory variables arrays. addressed four 8-bit wide address registers
5.2.2
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5.2.2.1
Expression Stack 4-bit wide expression stack addressed with expression Stack Pointer (SP). arithmetic, memory reference operations take their operands from, return their results expression stack. MARC4 performs operations with stack items (TOS TOS-1). register contains element expression stack works same accumulator. This stack also used passing parameters between subroutines scratch area temporary storage data. Return Stack 12-bit wide return stack addressed Return stack Pointer (RP). used storing return addresses subroutines, interrupt routines keeping loop index counts. return stack also used temporary storage area.
MARC4 instruction supports exchange data between elements expression stack return stack. stacks within have user definable location maximum depth.
5.2.2.2
Figure 5-3.
(256 4-bit) Autosleep Global variables
Expression stack
TOS-1 TOS-2
address register:
4-bit
TOS-1
Expression stack Return stack
Return stack
Global variables 12-bit
5.2.3
Registers
MARC4 controller seven programmable registers condition code register. They shown following programming model.
5.2.3.1
Program Counter (PC) program counter 12-bit register which contains address next instruction fetched from ROM. Instructions currently being executed decoded instruction decoder determine internal micro-operations. linear code calls branches) program counter incremented with every instruction cycle. branch-, call-, return-instruction interrupt executed, program counter loaded with address. program counter also used with table instruction fetch 8-bit wide constants.
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Figure 5-4.
Programming Model
Program counter
banking register
Return stack pointer
Expression stack pointer
address register
address register
stack register
Condition code register
Interrupt enable Branch Reserved Carry/borrow
5.2.3.2
Banking Register (RBR) banking register 4-bit register whereby ATAM894 only uses bit. This register indicates which bank presently being addressed. accessed with standard qFORTH peripheral read write instruction OUT, port address hex). Address Registers addressed with four 8-bit wide address registers: These registers allow access nibbles. Expression Stack Pointer (SP) stack pointer contains address next-to-top 4-bit item (TOS-1) expression stack. pointer automatically pre-incremented nibble moved onto stack postdecremented nibble removed from stack. Every post-decrement operation moves item (TOS-1) register before decremented. After reset stack pointer initialized with ">SP allocate start address expression stack area. Return Stack Pointer (RP) return stack pointer points element 12-bit wide return stack. pointer automatically pre-increments element moved onto stack, post-decrements element removed from stack. return stack pointer increments decrements steps This means that every time 12-bit element stacked, 4-bit location left unwritten. This location used qFORTH compiler allocate 4-bit variables. After reset return stack pointer initialized ">RP FCh".
5.2.3.3
5.2.3.4
5.2.3.5
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5.2.3.6
Address Registers registers used address 4-bit item RAM. fetch operation moves addressed nibble onto TOS. store operation moves addressed location. using either pre-increment post-decrement addressing mode arrays compared, filled moved. Stack (TOS) stack register accumulator MARC4. arithmetic/logic, memory reference operations this register. register receives data from ALU, ROM, bus. Condition Code Register (CCR) 4-bit wide condition code register contains branch, carry interrupt enable flag. These bits indicate current state CPU. flags reset operations. instructions SET_BCF, TOG_BF, CCR! allow direct manipulation condition code register. Carry/Borrow carry/borrow flag indicates that borrowing carrying Arithmetic Logic Unit (ALU) occurred during last arithmetic operation. During shift rotate operations, this used fifth bit. Boolean operations have affect C-flag. Branch
branch flag controls conditional program branching. Should branch flag have been previous instruction, conditional branch will cause jump. This flag affected arithmetic, logic, shift, rotate operations.
5.2.3.7
5.2.3.8
5.2.3.9
5.2.3.10
5.2.3.11
Interrupt Enable interrupt enable flag globally enables disables triggering interrupt routines with exception non-maskable reset. After reset executing instruction, interrupt enable flag reset, thus disabling interrupts. core will accept further interrupt requests until interrupt enable flag been again either executing SLEEP instruction.
5.2.4
4-bit performs arithmetic, logical, shift rotate operations with elements expression stack (TOS TOS-1) returns result TOS. operations affect carry/borrow branch flag condition code register (CCR).
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Figure 5-5.
Zero-address Operations
TOS-1 TOS-2 TOS-3 TOS-4
5.2.5
ports registers peripheral modules mapped. communication between core on-chip peripherals takes place associated control. With MARC4 instructions allows direct read write access primary addresses. More about access on-chip peripherals described section "Peripheral Modules" page internal accessible customer final microcontroller device, used interface MARC4 emulation (see section "Emulation" page 92).
5.2.6 Instruction
MARC4 instruction optimized high level programming language qFORTH. Many MARC4 instructions qFORTH words. This enables compiler generate fast compact program code. instruction pipeline allowing controller prefetch instruction from program memory same time present instruction being executed. MARC4 zero address machine, instructions containing only operation performed source destination address fields. operations implicitly performed data placed stack. There byte instructions which executed within machine cycles. MARC4 machine cycle made system clock cycles (SYSCL). Most instructions only byte long executed single machine cycle. more information refer "MARC4 Programmer's Guide".
5.2.7 Interrupt Structure MARC4 handle interrupts with eight different priority levels. They generated from internal external interrupt sources software interrupt from itself. Each interrupt level hard-wired priority associated vector service routine program memory (see Table page 11). programmer postpone processing interrupts resetting interrupt enable flag CCR. interrupt occurrence will still registered, interrupt routine only started after flag set. interrupts masked, priority individually software configured programming appropriate control register interrupting module (see section "Peripheral Modules" page 22).
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5.2.8
Interrupt Processing processing eight interrupt levels, MARC4 includes interrupt controller with 8-bit wide "interrupt pending" "interrupt active" registers. interrupt controller samples interrupt requests during every non-I/O instruction cycle latches these interrupt pending register. higher priority interrupt present interrupt active register, signals interrupt current program execution. interrupt enable set, processor enters interrupt acknowledge cycle. During this cycle short call (SCALL) instruction service routine executed current saved return stack. interrupt service routine completed with instruction. This instruction resets corresponding bits interrupt pending/active register fetches return address from return stack program counter. When interrupt enable flag reset (triggering interrupt routines disabled), execution interrupt service routines inhibited logging interrupt requests interrupt pending register. execution interrupt delayed until interrupt enable flag again. Note that interrupts only lost interrupt request occurs while corresponding pending register still (i.e., interrupt service routine finished). Interrupt Latency interrupt latency time from occurrence interrupt interrupt service routine being activated. MARC4 this extremely short (taking between machine cycles depending state core).
5.2.9
Figure 5-6.
Interrupt Handling
INT7
Priority Level
Main/ Autosleep INT3 INT5
INT7 active
INT5 active
INT2 INT3 active INT2 pending INT2 active SWI0
INT0 pending
INT0 active Main Autosleep
Time
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Table 5-1.
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Interrupt Priority Table
Priority Lowest Highest Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Interrupt Opcode (SCALL 040h) (SCALL 080h) (SCALL 0C0h) (SCALL 100h) (SCALL 140h) (SCALL 180h) (SCALL 1C0h) (SCALL 1E0h) Function Software interrupt (SWI0) External hardware interrupt, edge BP52 BP53 Timer interrupt interrupt external hardware interrupt BP40 BP43 Timer interrupt Timer interrupt External hardware interrupt, edge BP50 BP51 Voltage Monitor (VM) interrupt
Table 5-2.
Hardware Interrupts
Interrupt Mask
Interrupt INT1 INT2 INT3 INT4 INT5
Register P5CR SISC T2CM T3CM1 T3CM2 P5CR
P52M1, P52M2 P53M1, P53M2 T1IM T2IM T3IM1 T3IM2 T3EIM P50M1, P50M2 P51M1, P51M2
Interrupt Source edge BP52 edge BP53 Timer buffer full/empty BP40/BP43 interrupt Timer compare match/overflow Timer compare register match Timer compare register match Timer edge event occurs (T3I) edge BP50 edge BP51 External/internal voltage monitoring
INT6 INT7
5.2.9.1
Software Interrupts programmer generate interrupts using software interrupt instruction (SWI) which supported qFORTH predefined macros named SWI0 SWI7. software triggered interrupt operates exactly like hardware triggered interrupt. instruction takes elements from expression stack writes corresponding bits interrupt pending register. Therefore, using instruction, interrupts re-prioritized lower priority processes scheduled later execution. Hardware Interrupts ATAM894, there eleven hardware interrupt sources with seven different levels. Each source masked individually mask bits corresponding control registers. overview possible hardware configurations shown Table page
5.2.9.2
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Master Reset
master reset forces into well-defined condition. unmaskable activated independent current program state. triggered either initial supply power-up, short collapse power supply, brown-out detection circuitry, watchdog time-out, external input clock supervisor stage (see Figure page 12). master reset activation will reset interrupt enable flag, interrupt pending register interrupt active register. During power-on reset phase control signals reset mode thereby initializing on-chip peripherals. bi-directional ports input mode.
Attention: During reset phase, BP20/NTE input driven towards strong pullup transistor. This must pulled down during reset external circuitry representing resistor less than
Releasing reset results short call instruction (opcode C1h) EEPROM address 008h. This activates initialization routine $RESET which turn initialize necessary variables, stack pointers peripheral configuration registers (see Table page 23).
Figure 5-7.
Reset Configuration
Pull-up NRST Reset timer Internal reset
SYSCL/4 Power-on reset Brown-out detection Watchres
Ext. clock supervisor
ExIn
5.3.1
Power-on Reset Brown-out Detection ATAM894 fully integrated power-on reset brown-out detection circuitry. reset generation external components needed.
These circuits ensure that core held reset state until minimum operating supply voltage been reached. reset condition will also generated should supply voltage drop momentarily below minimum operating level except when power down mode activated (the core SLEEP mode peripheral clock stopped). this power-down mode brown-out detection disabled. values brown-out voltage threshold programmable register.
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power-on reset pulse generated rise across default voltage level (1.7V). brown-out reset pulse generated when falls below brown-out voltage threshold. values brown-out voltage threshold programmable register. When controller runs upper supply voltage range with high system clock frequency, high threshold must used. When runs with lower system clock frequency, threshold wider supply voltage range chosen. further details, electrical specification register description programming.
Figure 5-8.
Brown-out Detection
Reset Reset (typically)
Note:
brown-out voltage threshold 1.7V reset value). high brown-out voltage threshold 2.0V.
5.3.2
Watchdog Reset watchdog's function enabled register triggers reset with every watchdog counter overflow. suppress watchdog reset, watchdog counter must regularly reset reading watchdog register address (CWD). reacts exactly same manner reset stimulus from above sources. External Clock Supervisor external input clock supervisor function enabled external input clock selected within registers clock module. reacts exactly same manner reset stimulus from above sources.
5.3.3
Voltage Monitor
voltage monitor consists comparator with internal voltage reference. used supervise supply voltage external voltage pin. comparator supply voltage three internal programmable thresholds: lower threshold (2.2V), middle threshold (2.6 higher threshold (3.0V). external voltages pin, comparator threshold 1.3V. indicates supervised voltage below (VMS above (VMS this threshold. interrupt generated when reset detect rising falling slope. voltage monitor interrupt (INT7) enabled when interrupt mask (VIM) reset register.
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Figure 5-9.
Voltage Monitor
Voltage monitor BP41/ INT7
VMC:
VMST:
5.4.1
Voltage Monitor Control/ Status Register
Primary register address: 'F'hex VMC: Write VMST: Read reserved Reset value: 1111b Reset value: xx11b
VM2: Voltage monitor Mode VM1: Voltage monitor Mode VM0: Voltage monitor Mode
Table 5-3.
Voltage Monitor Modes
Function Disable voltage monitor External (VIM input), internal reference threshold (1.3V), interrupt with negative slope allowed External (VMI input), internal reference threshold (1.3V), interrupt with positive slope Internal (supply voltage), high threshold (3.0V), interrupt with negative slope Internal (supply voltage), middle threshold (2.6V), interrupt with negative slope Internal (supply voltage), threshold (2.2V), interrupt with negative slope allowed
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Voltage Interrupt Mask
voltage monitor interrupt enabled voltage monitor interrupt disabled
Voltage Monitor Status
voltage comparator input below VRef voltage comparator input above VRef
Figure 5-10. Internal Supply Voltage Supervisor
threshold Middle threshold High threshold
threshold Middle threshold High threshold
Figure 5-11. External Input Voltage Supervisor
Internal reference level Negative slope Positive slope Interrupt negative slope Interrupt positive slope
5.5.1
Clock Generation
Clock Module
ATAM894 contains clock module with different internal oscillator types: RC-oscillators, 4-MHz crystal oscillator 32-kHz crystal oscillator. pins OSC1 OSC2 interface connect crystal either 4-MHz, 32-kHz crystal oscillator. OSC1 used input external clocks connect external trimming resistor RC-oscillator necessary circuitry except crystal trimming resistor integrated on-chip. these oscillator types external input clock selected generate system clock (SYSCL). applications that require exact timing, possible fully integrated RC-oscillator without external components. RC-oscillator center frequency tolerance better than ±50%. RC-oscillator trimmable oscillator whereby oscillator frequency trimmed with external resistor attached between OSC1 VDD. this configuration, RC-oscillator frequency maintained stable within tolerance ±15% over full operating temperature voltage range.
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clock module programmable software with clock management register (CM) system configuration register (SC). required oscillator configuration selected with register. programmable 4-bit divider stage allows adjustment system clock speed. special feature clock management that external oscillator used switched port power-down mode. Before external clock switched off, internal RC-oscillator must selected with then SLEEP mode activated. this state interrupt wake controller with RC-oscillator, external oscillator activated selected software. synchronization stage avoids clock periods that short clock source clock speed changed. external input clock selected, supervisor circuit monitors external input generates hardware reset external clock source fails drops below more than
Figure 5-12. Clock Module
OSC1 Oscin
Ext. clock
ExIn
RCoscillator
ExOut Stop Stop RCOut1 Control Divider 4Out Stop
SYSCL
RC-oscillator
Trim
RCOut2 Stop
4-MHz oscillator
Oscin Oscout OSC2 Oscout
32-kHz oscillator
Oscin Oscout 32Out Osc-Stop Sleep Cin/16 NSTOP CSS1 CSS0 SUBCL
configurable -OS1
Table 5-4.
Clock Modes
Clock Source SYSCL Clock Source SUBCL Cin/16 Cin/16 Cin/16
Mode
RC-oscillator (intern) RC-oscillator (intern) RC-oscillator (intern) RC-oscillator (intern)
External input clock RC-oscillator with external trimming resistor 4-MHz oscillator 32-kHz oscillator
clock module generates output clocks. system clock (SYSCL) other periphery (SUBCL). SYSCL supply core peripherals SUBCL supply only peripherals with clocks. modes clock sources programmable with register register.
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5.5.2 Oscillator Circuits External Clock Input Stage ATAM894 series consists four different internal oscillators: RC-oscillators, 4-MHz crystal oscillator, 32-kHz crystal oscillator external clock input stage.
5.5.2.1
RC-oscillator Fully Integrated timing insensitive applications, possible fully integrated RC-oscillator operates without external components saves additional costs. RC-oscillator center frequency tolerance better than ±50% over full temperature voltage range. basic center frequency RC-oscillator MHz. RC-oscillator selected default after power-on reset.
Figure 5-13. RC-oscillator
RC-oscillator RcOut1 Stop RcOut1 Osc-Stop
Control
5.5.2.2
External Input Clock OSC1 OSC2 driven external clock source provided meets specified duty cycle, rise fall times input levels. Additionally, external clock stage contains supervisory circuit input clock. supervisor function controlled OS1, register register. external input clock missing more than register, supervisory circuit generates hardware reset.
Figure 5-14. External Input Clock
Ext. input clock Ext. Clock Ext. Clock OSC2 Clock monitor OSC1 ExIn Stop ExOut
RcOut1 Osc-Stop
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Table 5-5.
Supervisor Function Control Bits
Supervisor Reset Output (Res) Enable Disable Disable
5.5.2.3
RC-oscillator with External Trimming Resistor RC-oscillator high resolution trimmable oscillator whereby oscillator frequency trimmed with external resistor between OSC1 VDD. this configuration, RC-oscillator frequency maintained stable with tolerance ±15% over full operating temperature voltage range from 2.5V 6.0V.
example: output frequency RC-oscillator obtained connecting resistor Rext (see Figure 5-15).
Figure 5-15. RC-oscillator
Rext OSC1 RTrim Stop OSC2 RC-oscillator RcOut2 RcOut2 Osc-Stop
5.5.2.4
4-MHz Oscillator ATAM894 4-MHz oscillator options need crystal ceramic resonator connected OSC1 OSC2 pins establish oscillation. necessary oscillator circuitry, with exception actual crystal, resonator, integrated on-chip.
Figure 5-16. 4-MHz Crystal Oscillator
OSC1 XTAL configurable Oscin 4Out 4-MHz oscillator Oscout OSC2 Stop
4Out
Osc-Stop
Note:
Both, 4-MHz 32-kHz crystal oscillator, integrated stage divider circuit stabilize oscillation before oscillator output used system clock. This results additional delay about 4-MHz crystal about 32-kHz crystal.
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Figure 5-17. Ceramic Resonator
OSC1 Oscin Cer. configurable 4Out 4-MHz oscillator Oscout OSC2 Stop 4Out
Osc-Stop
Note:
Both, 4-MHz 32-kHz crystal oscillator, integrated stage divider circuit stabilize oscillation before oscillator output used system clock. This results additional delay about 4-MHz crystal about 32-kHz crystal.
5.5.2.5
32-kHz Oscillator Some applications require long-term time keeping resolution timing. this case, on-chip, power 32-kHz crystal oscillator used generate both SUBCL SYSCL. this mode, power consumption greatly reduced. 32-kHz crystal oscillator stopped while power-down mode operation.
Figure 5-18. 32-kHz Crystal Oscillator
OSC1 Oscin XTAL configurable 32Out 32-kHz oscillator Oscout OSC2 32Out
Note:
Both, 4-MHz 32-kHz crystal oscillator, integrated stage divider circuit stabilize oscillation before oscillator output used system clock. This results additional delay about 4-MHz crystal about 32-kHz crystal.
5.5.3
Clock Management clock management register controls system clock divider synchronization stage. Writing this register triggers synchronization cycle.
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5.5.3.1
Clock Management Register (CM)
Auxiliary register address: '3'hex NSTOP CSS1 CSS0 Reset value: 1111b
NSTOP
STOP peripheral clock NSTOP stops peripheral clock while core SLEEP mode NSTOP enables peripheral clock while core SLEEP mode Core Clock Select internal RC-oscillator generates SYSCL 4-MHz crystal oscillator, 32-kHz crystal oscillator, external clock source RC-oscillator with external resistor OSC1 generates SYSCL dependent setting system configuration register Core Speed Select Core Speed Select
CSS1 CSS0
Table 5-6.
CSS1
Core Speed Select
CSS0 Divider Reset value Note
5.5.3.2
System Configuration Register (SC)
Primary register address: '3'hex write Reset value: 1x11b
Brown-Out Threshold brown-out voltage threshold (1.65V) high brown-out voltage threshold (1.95V) Oscillator Select Oscillator Select
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Table 5-7.
Mode Note:
Oscillator Select
Input SUBCL Cin/16 Cin/16 Cin/16
Selected Oscillators RC-oscillator external input clock RC-oscillator RC-oscillator RC-oscillator 4-MHz crystal oscillator RC-oscillator 32-kHz crystal oscillator
CM-register RC-oscillator always stops.
Power-down Modes
sleep mode shut-down condition which used reduce average system power consumption applications where microcontroller fully utilized. this mode, system clock stopped. sleep mode entered SLEEP instruction. This instruction sets interrupt enable condition code register enable interrupts stops core. During sleep mode peripheral modules remain active able generate interrupts. microcontroller exits sleep mode carrying interrupt reset. sleep mode only kept when none interrupt pending active register bits set. application $AUTOSLEEP routine ensures correct function sleep mode. standard applications $AUTOSLEEP routine enter power-down mode. Using SLEEP instruction instead $AUTOSLEEP following instruction requires insertion non-I/O instruction cycles (for example NOP, NOP, NOP) between command SLEEP command. total power consumption directly proportional active time microcontroller. rough estimation expected average system current consumption, following formula should used:
active total syscl Sleep depends fsyscl total
ATAM894 various power-down modes. During sleep mode clock MARC4 core stopped. With NSTOP clock management register (CM) programmable clock on-chip peripherals active stopped during sleep mode. clock core peripherals stopped selected oscillator switched off. exception 32-kHz oscillator, selected runs continuously independent NSTOP bit. oscillator stopped 32-kHz oscillator selected, power consumption extremely low.
Table 5-8.
Power-down Modes
OscStop(1) Brown-out Function Active Active STOP RC-Oscillator RC-Oscillator 4-MHz Oscillator STOP 32-kHz Oscillator External Input Clock STOP
Mode Active Power-down SLEEP Note:
Core SLEEP SLEEP
Osc-Stop SLEEP NSTOP
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Peripheral Modules
Addressing Peripherals
Accessing peripheral modules takes place (see Figure 6-1). instructions allow direct addressing modules. dual register addressing scheme been adopted enable direct addressing primary register. address auxiliary register, access must switched with auxiliary switching module. Thus, single OUT) module address will read write into) module primary register. Accessing auxiliary register performed with same instruction preceded writing module address into auxiliary switching module. Byte wide registers accessed multiple OUT-) instructions. more complex peripheral modules, with larger number registers, extended addressing used. this case bank subport registers indirectly addressed with subport address. first OUT-instruction writes subport address subaddress register, second OUT-instruction reads data from writes data addressed subport.
Figure 6-1.
Example Addressing
Module
(Address Pointer) Subaddress Reg. Bank Primary Regs. Subport Subport
Module
Module
Aux. Reg.
Module
Auxiliary Switch Module
Primary Reg.
Subport Subport Primary Reg.
Primary Reg.
other modules
Indirect Subport Access
Dual Register Access (Primary Register Write)
Single Register Access (Primary Register Write)
(Subport Register Write)
Addr. (SPort) Addr. (M1) SPort_Data Addr. (M1)
Prim._Data Addr. (M2) (Auxiliary Register Write)
Prim._Data Addr. (M3) (Primary Register Read)
(Subport Register Read) Addr. (SPort) Addr. (M1) Addr. (M1) (Subport Register Write Byte)
Addr. (M2) Addr. (ASW) Aux._Data Addr. (M2) (Primary Register Read)
Addr. (M3)
Example qFORTH Program Code
Addr. (M2) (Auxiliary Register Read
Addr. (SPort) Addr. (M1) SPort_Data (lo) Addr. (M1) SPort_Data (hi) Addr. (M1) (Subport Register Read Byte)
Addr. (M2) Addr. (ASW) Addr. (M2) (Auxiliary Register Write Byte)
Addr. (SPort) Addr. (M1) Addr. (M1) (hi) Addr. (M1) (lo)
Addr. (M2) Addr. (ASW) Aux._Data (lo) Addr. (M2) Aux._Data (hi) Addr. (M2)
Addr. (ASW) Auxililiary Switch Module Address Addr. (Mx) Module Address Addr. (SPort) Subport Address Prim._Data Data written into Primary Register Aux._Data Data written into Auxiliary Register Aux._Data (lo) Data written into Auxiliary Register (low nibble)
Aux._Data (hi) Data written into Auxiliary Register (high nibble) SPort_Data (lo) Data written into Subport (low nibble) SPort_Data (hi) Data written into Subport (high nibble) (lo) SPort_Data (low nibble) (hi) SPort_Data (high nibble)
ATAM894
4679D-4BMCU-05/05
ATAM894
Table 6-1.
Port Address Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary T3ST -VMC VMST SIC1 SISC SIC2 T3SUB Subport address T3CS T3CM1 T3CM2 T3CO1 T3CP T3CO2 1111b 1111b 0000b 0000b 1111 1111b xxxx xxxxb 1111 1111b 1111b 0000b x000b 1111b xx11b Timer mode register Timer clock select register Timer compare mode register Timer compare mode register Timer compare register (byte) Timer capture register (byte) Timer compare register (byte) Reserved Reserved Timer control register Timer status register Reserved Voltage monitor control register Voltage monitor status register page page page page page page page page page page page 1111b xxxx xxxxb xxxx xxxxb 1111b 1x11b 1111b
Peripheral Addresses
Name P1DAT P2DAT P2CR P4DAT P4CR P5DAT P5CR P6DAT P6CR T12SUB Subport address T2M1 T2M2 T2CM T2CO1 T2CO2 T1C1 T1C2 0000b 1111b 1111b 0000b 1111b 1111 1111b 1111b x111b 1111b Timer control register Timer mode register Timer mode register Timer compare mode register Timer compare register Timer compare register (byte) Reserved Reserved Timer control register Timer control register Watchdog control register Reserved Auxiliary/switch register Serial transmit buffer (byte) Serial receive buffer (byte) Serial interface control register Serial interface status/control register Serial interface control register Data to/from Timer subport page page page page page page page page page page page page page page page page Write/Read Reset Value 1xx1b 1111b 1111b 1x11b xxxxb 1111b 1111b 1111 1111b 1111b 1111 1111b 1xx1b 1111b Register Function Port data register/input data Port data register/pin data Port control register System configuration register Watchdog reset Clock management register Port data register/pin data Port control register (byte) Port data register/pin data Port control register (byte) Port data register/pin data Port control register (byte) Data Timer subport Module Type Page page page page page page page page page page page page page page
4679D-4BMCU-05/05
Bi-directional Ports
With exception Port Port other ports bits wide. Port Port have data width bits (bit ports used data input output. ports equipped with Schmitt trigger inputs variety mask options open drain, open source, full complementary outputs, pull-up pull-down transistors. Port Data Registers (PxDAT) mapped primary address register respective port address Port Control Register (PxCR), corresponding auxiliary register. There five different directional ports available: Port Port Port Port Port 2-bit wide bi-directional ports with automatic full width direction switching 4-bit wide bit-wise-programmable port 4-bit wide bit-wise-programmable bi-directional port with optional strong pull-ups programmable interrupt logic 4-bit wide bit-wise-programmable bi-directional port also provides interface Timer SSI, voltage monitor input external interrupt input 2-bit wide bit-wise-programmable bi-directional port also provides interface Timer external interrupt input
6.2.1
Bi-directional Port Port data direction register independently software programmable, direction complete port being switched automatically when instruction occurs (see Figure page 25). port switched output mode instruction input instruction. data written port will stored into output data latches appears immediately port following instruction. After RESET output latches port switched input mode. instruction reads condition associated pins.
Note: Care must taken when switching bi-directional port from output input. capacitive loading this port conjunction with high resistance pull-ups cause read contents output data register rather than external input state. avoid this, following programming techniques should used: IN-instructions DROP first data nibble. first switches port from output input DROP removes first invalid nibble. second reads valid state. OUT-instruction followed IN-instruction. OUT-instruction, capacitive load charged discharged depending optional pull-up/pull-down configuration. Write pins with pull-up resistors pins with pull-down resistors.
ATAM894
4679D-4BMCU-05/05
ATAM894
Figure 6-2.
Bi-directional Port
(Data out)
Switched pull-up
Static pull-up
P1DATy Reset (Direction) Master reset
BP1y
Flash options
Switched pull-down
Static pull-down
6.2.2
Bi-directional Port other bi-directional ports, this port includes bit-wise-programmable Control Register (P2CR), which enables individual programming each port input output. also opens possibility reading condition when output mode. This useful feature self testing serial applications.
However, Port increased drive capability additional resistance pull-up/down transistor mask option. Care should taken connecting external components BP20/NTE. During reset phase, BP20/NTE input driven towards additional internal strong pull-up transistor. This must pulled down (active passive) during reset external circuitry representing resistor less than This prevents circuit from unintended switching test mode enable through application circuitry BP20/NTE. Resistors less than might lead undefined state internal test logic, thus disabling application firmware. avoid conflict with optional internal pull-down transistors, BP20 handles pull-down options different than other ports. BP20 only port that switches pulldown transistors during reset.
4679D-4BMCU-05/05
Figure 6-3.
Bi-directional Port
Switched pull-up
Static Pull-up
(Data out) Master reset P2DATy
BP2y
P2CRy
Static Pull-down
(Direction)
Flash options
Switched pull-down
6.2.2.1
Port Data Register (P2DAT)
Primary register address: '2'hex P2DAT Note: P2DAT3 P2DAT2 P2DAT1 P2DAT0 Reset value: 1111b
MSB,
6.2.2.2
Port Control Register (P2CR)
Auxiliary register address: '2'hex P2CR Note: P2CR3 P2CR2 P2CR1 P2CR0 Reset value: 1111b
Value 1111b means pins input mode
Table 6-2.
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Port Control Register
Function BP20 input mode BP20 output mode BP21 input mode BP21 output mode BP22 input mode BP22 output mode BP23 input mode BP23 output mode
ATAM894
4679D-4BMCU-05/05
ATAM894
6.2.3 Bi-directional Port other bi-directional ports, this port includes bit-wise-programmable Control Register (P5CR), which allows individual programming each port input output. also opens possibility reading condition when output mode. This useful feature self-testing serial applications.
port pins also used external interrupt inputs (see Figure page Figure page 27). interrupts (INT1 INT6) masked independently configured trigger either edge. interrupt configuration port direction controlled Port Control Register (P5CR). additional resistance pull-up/-down transistor mask option provides internal pull-up serial applications. Port Data Register (P5DAT) mapped primary address register address '5'h Port Control Register (P5CR) corresponding auxiliary register. P5CR byte-wide register configured writing first nibble then high nibble (see section "Addressing Peripherals" page 22).
Figure 6-4.
Bi-directional Port
Switched pull-up
Static pull-up
(Data out) P5DATy Master reset enable
BP5y
Static pull-down
Flash options
Switched pull-down
Figure 6-5.
Port External Interrupts
INT1
Data BP52
INT6
Data
Bidir. Port
IN_Enable
Bidir. Port
IN_Enable
I/O-bus
I/O-bus
Data BP53
Data
Bidir. Port
IN_Enable Decoder Decoder Decoder Decoder
Bidir. Port
IN_Enable
P5CR: P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
1376
4679D-4BMCU-05/05
6.2.3.1
Port Data Register (P5DAT)
Primary register address: '5'hex P5DAT P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b
6.2.3.2
Port Control Register (P5CR) Byte Write
Auxiliary register address: '5'hex P5CR First write cycle Second write cycle P51M2 P53M2 P51M1 P53M1 P50M2 P52M2 P50M1 P52M1 Reset value: 1111b Reset value: 1111b
P5xM2, P5xM1 Port Interrupt Mode/Direction Code
Table 6-3.
Port Control Register
Second Write Cycle Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function BP52 input mode interrupt disabled BP52 input mode rising edge interrupt BP52 input mode falling edge interrupt BP52 output mode interrupt disabled BP53 input mode interrupt disabled BP53 input mode rising edge interrupt BP53 input mode falling edge interrupt BP53 output mode interrupt disabled
Auxiliary Address: '5'hex First Write Cycle Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function BP50 input mode interrupt disabled BP50 input mode rising edge interrupt BP50 input mode falling edge interrupt BP50 output mode interrupt disabled BP51 input mode interrupt disabled BP51 input mode rising edge interrupt BP51 input mode falling edge interrupt BP51 output mode interrupt disabled
6.2.4
Bi-directional Port bi-directional Port bit-wise configurable port provides external pins Timer voltage monitor input (VMI). normal port, performs exactly same bi-directional Port (see Figure page 26). additional multiplexes allow data port direction control passed over other internal modules (Timer SSI). pins lines have additional mode generate SSI-interrupt.
four Port pins individually switched P4CR register. Figure page shows internal interfaces bi-directional Port
ATAM894
4679D-4BMCU-05/05
ATAM894
Figure 6-6.
Bi-directional Port Port
Intx
POut PxDATy Master reset
PxMRy
Static pull-up
Switched pull-up
BPxy
(Direction)
Static pull-down
PxCRy Flash options PDir Switched pull-down
6.2.4.1
Port Data Register (P4DAT)
Primary register address: '4'hex P4DAT P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b
6.2.4.2
Port Control Register (P4CR) Byte Write
Auxiliary register address: '4'hex P4CR First write cycle Second write cycle P41M2 P43M2 P41M1 P43M1 P40M2 P42M2 P40M1 P42M1 Reset value: 1111b Reset value: 1111b
P4xM2, P4xM1 Port Interrupt Mode/Direction Code
4679D-4BMCU-05/05
Table 6-4.
Port Control Register
Second Write Cycle Code 3210 xx11 xx10 xx0x 11xx 10xx 01xx 00xx Function BP42 input mode BP42 output mode BP42 enable alternate function (T2O Timer BP43 input mode BP43 output mode BP43 enable alternate function SSI) BP43 enable alternate function (falling edge interrupt input INT3)
Auxiliary Address: '4'hex First Write Cycle Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Function BP40 input mode BP40 output mode BP40 enable alternate function SSI) BP40 enable alternate function (falling edge interrupt input INT3) BP41 input mode BP41 output mode BP41 enable alternate function (VMI voltage monitor input) BP41 enable alternate function (T2I external clock input Timer
6.2.5
Bi-directional Port bi-directional Port bit-wise configurable port provides external pins Timer normal port, performs exactly same bi-directional Port (see Figure page 29). additional multiplexes allow data port direction control passed over other internal modules (Timer line additional mode generate Timer 3-interrupt. Port pins individually switched P6CR register. Figure page shows internal interfaces bi-directional Port
6.2.5.1
Port Data Register (P6DAT)
Primary register address: '6'hex P6DAT P6DAT3 P6DAT0 Reset value: 1xx1b
6.2.5.2
Port Control Register (P6CR)
Auxiliary register address: '6'hex P6CR P63M2 P63M1 P60M2 P60M0 Reset value: 1111b
P6xM2, P6xM1 Port Interrupt Mode/Direction Code
Table 6-5.
Code 3210 xx11 xx10 xx0x
Port Control Register
Auxiliary Address: '6'hex Function BP60 input mode BP60 output mode BP60 enable alternate port function (T3O Timer Write Cycle Function BP63 input mode BP63 output mode BP63 enable alternate port function (T3I Timer Code 3210 11xx 10xx 0xxx
ATAM894
4679D-4BMCU-05/05
ATAM894
Universal Timer/Counter/ Communication Module (UTCM)
Universal Timer/counter/Communication Module (UTCM) consists three timers (Timer 1,Timer Timer Synchronous Serial Interface (SSI). Timer interval timer that used generate periodic interrupts prescaler Timer Timer serial interface watchdog function. Timer 8/12-bit timer with external clock input (T2I) output (T2O). Timer 8-bit timer/counter with input (T3I) output (T3O). operates two-wire serial interface shift register modulation demodulation. modulator demodulator units work together with timers shift data bits into shift register. There multitude modes which timers serial interface work together.
Figure 6-7.
UTCM Block Diagram
SYSCL SUBCL from clock module
Timer
Watchdog Interval/Prescaler NRST INT2
T1OUT
Timer
Capture Control Demodulator Modulator INT5
8-bit Counter Compare Compare
TOG3
Timer
4-bit Counter Compare Modulator
POUT
Control 8-bit Counter INT4 Compare
TOG2
Receive buffer
8-bit shift register Transmit buffer
Control INT3
4679D-4BMCU-05/05
6.3.1
Timer
Timer interval timer which used generate periodic interrupts prescaler Timer Timer serial interface watchdog function. Timer consists programmable 14-stage divider that driven either SUBCL SYSCL. timer output signal used prescaler clock SUBCL source Timer interrupt. Because other system requirements Timer output T1OUT synchronized with SYSCL. Therefore, power-down mode SLEEP (CPU core sleep OSC-Stop yes) output T1OUT stopped (T1OUT Nevertheless, Timer active SLEEP generate Timer interrupts. interrupt maskable T1IM SUBCL bypassed T1BP T1C2 register. time interval timer output programmed Timer control register T1C1. This timer starts running automatically after power-on reset! watchdog function activated, timer restarted writing into T1C1 register with T1RM Timer also used watchdog timer prevent system from stalling. watchdog timer 3-bit counter that supplied separate output Timer generates system reset when 3-bit counter overflows. avoid this, 3-bit counter must reset before overflows. application software accomplish this reading register. After power-on reset watchdog must activated software $RESET initialization routine. There watchdog modes, mode watchdog switched software, other mode watchdog active locked. This mode only stopped carrying system reset. watchdog timer operation mode time interval watchdog reset programmed watchdog control register (WDC).
Figure 6-8.
Timer Module
SYSCL SUBCL WDCL
14-bit Prescaler
4-bit Watchdog
NRST
INT2 T1CS T1MUX T1BP T1IM T1OUT
ATAM894
4679D-4BMCU-05/05
ATAM894
Figure 6-9.
Timer Watchdog
T1C2 T1BP T1IM
T1C1 T1RM T1C2 T1C1 T1C0 Write T1C1 register
T1IM=0 T1MUX
Decoder
interval timer
T1IM=1
INT2
T1OUT SUBCL Watchdog Divider/8
Decoder
WDT1 WDT0
watchdog timer WDCL
Read register Divider RESET RESET (NRST)
Watchdog mode control
6.3.1.1
Timer Control Register (T1C1)
Address: '7'hex Subaddress: '8'hex T1C1 Note: T1RM T1C2 T1C1 T1C0 Reset value: 1111b
MSB,
T1RM T1C2 T1C1 T1C0
T1RM write access without Timer restart T1RM write access with Timer restart Note: Timer restart impossible Timer Control Timer Control Timer Control
Timer Restart Mode
three bits T1C[2:0] select divider timer resulting time interval depends this divider timer input clock source. timer input supplied system clock, 32-kHz oscillator clock management. clock management generates SUBCL, selected input clock from RC-oscillator, 4-MHz oscillator external clock divided
4679D-4BMCU-05/05
Table 6-6.
T1C2 T1C1
Timer Control Bits
T1C0 Divider 2048 16384 Time Interval with SUBCL SUBCL/2 SUBCL/4 SUBCL/8 SUBCL/16 SUBCL/32 SUBCL/256 SUBCL/2048 SUBCL/16384 Time Interval with SUBCL 0.977 7.812 62.5 Time Interval with SYSCL µs/2 µs/4 µs/8 µs/16 µs/32 µs/256 1024 µs/2048 8192 µs/16384
6.3.1.2
Timer Control Register (T1C2)
Address: '7'hex Subaddress: '9'hex T1C2 Note:
T1BP
T1CS
T1IM Reset value: x111b
MSB,
T1BP
Timer SUBCL ByPassed T1BP TIOUT T1MUX T1BP T1OUT SUBCL Timer input Clock Select T1CS SUBCL (see Figure page T1CS SYSCL (see Figure page Timer Interrupt Mask T1IM disables Timer interrupt T1IM enables Timer interrupt
T1CS
T1IM
6.3.1.3
Watchdog Control Register (WDC)
Address: '7'hex Subaddress: 'A'hex Note:
WDT1
WDT0 Reset value: 1111b
MSB,
WatchDog Lock mode watchdog enabled disabled using watchdog enabled locked. this mode effect. After cleared, watchdog active until system reset power-on reset occurs WatchDog stop mode watchdog stopped/disabled watchdog active/enabled WatchDog Time WatchDog Time
WDT1 WDT0
ATAM894
4679D-4BMCU-05/05
ATAM894
Both these bits control time interval watchdog reset.
Table 6-7.
WDT1
Watchdog Time Control Bits
WDT0 Divider 2048 16384 131072 Delay Time Reset with 1/32 15.625 62.5 Delay Time Reset with 1/(2/1 MHz) 0.256 ms/0.512 1.024 ms/2.048 ms/16.4 65.5 ms/131
6.3.2
Timer
6.3.2.1
8/12-bit timer Interrupt, square-wave, pulse duty cycle generation Baud-rate generation internal shift register Manchester Bi-phase modulation together with Carrier frequency generation modulation together with Timer used interval timer interrupt generation, signal generator baud-rate generator modulator serial interface. consists 4-bit 8-bit counter stage which both have compare registers. 4-bit counter stages Timer cascadable 12-bit timer 8-bit timer with 4-bit prescaler. timer also configured 8-bit timer separate 4-bit prescaler. Timer input supplied system clock, external input clock (T2I), Timer output clock shift clock serial interface. external input clock synchronized with SYSCL. Therefore, possible Timer with higher clock speed than SYSCL. Furthermore, with that input clock Timer operates power-down mode SLEEP (CPU core sleep OSC-Stop yes) well POWER-DOWN (CPU core sleep OSC-Stop no). other clock sources supply clock signal SLEEP NSTOP 4-bit counter stages Timer have additional clock output (POUT). output modulator stage that allows generation pulses well generation modulation carrier frequencies. Timer output modulate with shift register data output generate Bi-phase- Manchester code. serial interface used modulate bit-stream, 4-bit stage Timer special task. shift register only handle bit-stream lengths divisible other lengths, 4-bit counter stage used stop modulator after right bit-count shifted out. timer used carrier frequency modulation, 4-bit stage works together with additional 2-bit duty cycle generator like 6-bit prescaler generate carrier frequency duty cycle. 8-bit counter used enable disable modulator output programmable count pulses.
4679D-4BMCU-05/05
programming time interval, timer 4-bit 8-bit compare register. programming timer function, four mode control registers. comparator output stage controlled special compare mode register (T2CM). This register contains mask bits actions (counter reset, output toggle, timer interrupt) which triggered compare match event counter overflow. This architecture enables timer function various modes. Timer 4-bit compare register (T2CO1) 8-bit compare register (T2CO2). Both these compare registers cascadable 12-bit compare register, 8-bit compare register 4-bit compare register. 12-bit compare data value: 8-bit compare data value: 4-bit compare data value:
Figure 6-10. Timer
I/O-bus
n=y+1
4095
P4CR
T2M1
T2M2
SYSCL T1OUT TOG3
DCGO
CL2/1
4-bit Counter
OVF1 POUT
CL2/2
8-bit Counter
OVF2 TOG2
OUTPUT
MOUT
Compare
Control
Compare
INT4
Modulator
T2CO1
POUT
T2CM
T2CO2
Bi-phase Manchester modulator
Timer modulator output-stage
I/O-bus
Control
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.2.2 Timer Modes Mode 12-bit Compare Counter
4-bit stage 8-bit stage work together 12-bit compare counter. compare match signal 4-bit 8-bit stage generates signal counter reset, toggle flip-flop interrupt. compare action programmable compare mode register (T2CM). 4-bit counter overflow (OVF1) supplies clock output (POUT) with clocks. duty cycle generator (DCG) bypassed this mode.
Figure 6-11. 12-bit Compare Counter
POUT (CL2/1 /16) CL2/1
4-bit counter
8-bit counter
OVF2 TOG2
INT4
4-bit compare
8-bit compare
Timer output mode T2OTM-bit
4-bit register
T2D1,
8-bit register
T2RM
T2O
T2IM
T2C
Mode 8-bit Compare Counter with 4-bit Programmable Prescaler
4-bit stage used programmable prescaler 8-bit counter stage. this mode, duty cycle stage also available. This stage used additional 2-bit prescaler generating duty cycles 25%, 50%. 4-bit compare output (CM1) supplies clock output (POUT) with clocks.
Figure 6-12. 8-bit Compare Counter
DCGO POUT CL2/1 OVF2 TOG2 INT4
4-bit counter
8-bit counter
4-bit compare
8-bit compare
Timer output mode T2OTM-bit
4-bit register
T2D1,
8-bit register
T2RM
T2O
T2IM
T2C
4679D-4BMCU-05/05
Mode 3/4: 8-bit Compare Counter 4-bit Programmable Prescaler
these modes 4-bit 8-bit counter stages work independently 4-bit prescaler 8-bit timer with 2-bit prescaler duty cycle generator. Only mode mode 8-bit counter supplied external clock input (T2I) which selected P4CR register. 4-bit prescaler started activating mode stopped reset mode Changing mode effect 8-bit timer stage. 4-bit stage used prescaler Timer generate stop signal modulator modulator
Figure 6-13. 4-/8-bit Compare Counter
DCGO SYSCL CL2/2
8-bit counter
OVF2 TOG2
INT4 Timer output mode T2OTM-bit P4CR P41M2, T2D1,
8-bit compare
8-bit register
T2RM
T2O
T2IM
T2C
TOG3 T1OUT SYSCL
CL2/1
4-bit counter
POUT
4-bit compare
T2CS1,
4-bit register
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.2.3 Timer Output Modes signal timer output generated modulator toggle mode, compare match event toggles output T2O. high resolution duty cycle modulation bits bits used toggle output. duty-cycle burst modulator modes output connected switched either toggle flip-flop output serial data line SSI. Modulator also modes output content serial interface Biphase Manchester code.
modulator output stage configured output control bits T2M2 register. modulator started with start shift register (SIR stopped either carrying shift register stop (SIR compare match event stage (CM1) Timer this task, Timer mode must used prescaler supplied with internal shift clock (SCL).
Figure 6-14. Timer Modulator Output Stage
DCGO TOG2 Bi-phase/ Manchester modulator Toggle RES/SET Modulator OMSK T2M2 T2OS2, T2TOP
CONTROL
6.3.2.4
Timer Output Signals Timer Output Mode
Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 6-15. Interrupt Timer/Square Wave Generator Output Toggles with Each Edge Compare Match Event
Input Counter
Counter INT4
4679D-4BMCU-05/05
Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 6-16. Pulse Generator Timer Output Toggles with Timer Start T2TS
Input Counter
4095/
Counter INT4
Toggle start
Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 6-17. Pulse Generator Timer Toggles with Timer Overflow Compare Match
Input Counter
4095/
Counter OVF2 INT4
ATAM894
4679D-4BMCU-05/05
ATAM894
Timer Output Mode Duty Cycle Burst Generator output signal (DCGO) given output,
gated output flip-flop (M2)
Figure 6-18. Carrier Frequency Burst Modulation with Timer Toggle Flip-flop Output
DCGO
Counter TOG2
Counter compare register
Timer Output Mode Duty Cycle Burst Generator output signal (DCGO) given output,
gated internal data output (SO)
Figure 6-19. Carrier Frequency Burst Modulation with Data Output
DCGO
Counter TOG2
Counter compare register
Timer Output Mode Bi-phase Modulator: Timer Modulates Internal Data Output (SO) Bi-phase Code. Figure 6-20. Bi-phase Modulation
TOG2
8-bit data
Data: 00110101
4679D-4BMCU-05/05
Timer Output Mode Manchester Modulator: Timer Modulates internal data output (SO) Manchester code Figure 6-21. Manchester Modulation
TOG2
8-bit data
Data: 00110101
Timer Output Mode Mode: Pulse-width modulation output Timer output (T2O)
this mode timer overflow defines period compare register defines duty-cycle. During period only first compare match occurrence used toggle timer output flip-flop. Until overflow further compare match ignored. This avoids situation that changing compare register causes occurrence several compare match during period. resolution pulse-width modulation Timer mode 12-bit other Timer modes 8-bit.
Figure 6-22. Modulation
Input clock Counter
Counter OVF2 INT4
load next compare value T2CO2 load load
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.2.5 Timer Registers Timer control registers configure timer mode, time interval, input clock output function. registers indirectly addressed using extended addressing described section "Addressing Peripherals" page alternate functions Ports BP41 BP42 must selected with Port control register P4CR, Timer modes require input T2I/BP41 output T2O/BP42. Timer Control Register (T2C)
Address: '7'hex Subaddress: '0'hex T2CS1 T2CS0 T2TS Reset value: 0000b
6.3.2.6
T2CS1 T2CS0 T2TS
Timer Clock Select Timer Clock Select Timer Toggle with Start T2TS output flip-flop Timer toggled with timer start T2TS output flip-flop Timer toggled when timer started with Timer Timer stop reset Timer
Table 6-8.
T2CS1
Timer Clock Select Bits
T2CS0
Input Clock 2/1) Counter Stage
System clock (SYSCL) Output signal Timer (T1OUT) Internal shift clock (SCL) Reserved
6.3.2.7
Timer Mode Register (T2M1)
Address: '7'hex Subaddress: '1'hex T2M1 T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b
T2D1 T2D0 T2MS1 T2MS0
Timer Duty cycle Timer Duty cycle Timer Mode Select Timer Mode Select
4679D-4BMCU-05/05
Table 6-9.
T2D1
Timer Duty Cycle Bits
T2D0 Function Duty Cycle Generator (DCG) Bypassed (DCGO0) Duty cycle (DCGO1) Duty cycle (DCGO2) Duty cycle (DCG03) Additional Divider Effect
Table 6-10.
Mode
Timer Mode Select Bits
T2MS1 T2MS0 Clock Output (POUT) 4-bit counter overflow (OVF1) Timer Modes 12-bit compare counter, have bypassed this mode 8-bit compare counter with 4-bit programmable prescaler duty cycle generator 8-bit compare counter clocked SYSCL external clock input T2I, 4-bit prescaler run, counter starts after writing mode 8-bit compare counter clocked SYSCL external clock input T2I, 4-bit prescaler stop resets
4-bit compare output (CM1)
4-bit compare output (CM1)
4-bit compare output (CM1)
6.3.2.8
Duty Cycle Generator duty cycle generator generates duty cycles 25%, 50%. frequency duty cycle generator output depends duty cycle Timer prescaler setting. DCG-stage also used additional programmable prescaler Timer
Figure 6-23. Output Signals
DCGIN DCGO0 DCGO1 DCGO2 DCGO3
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.2.9 Timer Mode Register (T2M2)
Address: '7'hex Subaddress: '2'hex T2M2 T2TOP T2OS2 T2OS1 T2OS0 Reset value: 1111b
T2TOP
Timer Toggle Output Preset This allows programmer preset Timer output T2O. T2TOP resets toggle outputs with write cycle T2TOP sets toggle outputs with write cycle Note: output preset possible Timer Output Select Timer Output Select Timer Output Select
T2OS2 T2OS1 T2OS0
Table 6-11.
Output Mode
Timer Output Select Bits
T2OS2 T2OS1 T2OS0 Clock Output Toggle mode: Timer compare match toggles output flip-flop (M2) Duty cycle burst generator output signal (DCG0) given output gated output flip-flop (M2) Duty cycle burst generator output signal (DCGO) given output gated internal data output (SO) Bi-phase modulator: Timer modulates internal data output (SO) Bi-phase code Manchester modulator: Timer modulates internal data output (SO) Manchester code output: used directly internal data output (SO) mode: 8/12-bit mode allowed
these output modes used alternate function Port must also activated.
6.3.2.10
Timer Compare Compare Mode Registers Timer separate compare registers, T2CO1 4-bit stage T2CO2 8-bit stage Timer timer compares contents compare register current counter value matches generates output signal. Depending timer mode, this signal used generate timer interrupt, toggle output flip-flop clock clock next counter stage.
12-bit timer mode, T2CO1 contains bits T2CO2 bits 12-bit compare value. other modes, compare registers work independently 8-bit compare register. When assigned compare register compare event will suppressed.
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6.3.2.11
Timer Compare Mode Register (T2CM)
Address: '7'hex Subaddress: '3'hex T2CM T2OBit T2CBit T2RM T2IM Reset value: 0000b
T2O
Timer Overflow Toggle Mask T2O= disable overflow toggle T2O= enable overflow toggle, counter overflow (OVF2) toggles output flip-flop (TOG2). T2Obit set, only counter overflow generate interrupt except Timer output mode Timer Compare Toggle Mask T2C= disable compare toggle T2C= enable compare toggle, match counter with compare register toggles output flip-flop (TOG2). Timer output mode when T2Cbit set, only match counter with compare register generate interrupt Timer Reset Mask T2RM disable counter reset T2RM enable counter reset, match counter with compare register resets counter Timer Interrupt Mask T2IM disable Timer interrupt T2IM enable Timer interrupt
T2C
T2RM
T2IM
Table 6-12.
Timer Toggle Mask Bits
T2O0 T2Cx Timer Interrupt Source Compare match (CM2) Overflow (OVF2) Compare match (CM2)
Timer Output Mode
6.3.2.12
Timer COmpare Register (T2CO1)
Address: '7'hex Subaddress: '4'hex T2CO1 Write cycle Reset value: 1111b
prescaler mode clock bypassed compare register T2CO1 contains
6.3.2.13
Timer COmpare Register (T2CO2) Byte Write
Address: '7'hex Subaddress: '5'hex T2CO2 First write cycle Second write cycle Reset value: 1111b Reset value: 1111b
ATAM894
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ATAM894
6.3.3 Timer
6.3.3.1
Compare Registers Capture Register Edge Sensitive Input with Zero Cross Detection Capability Trigger Single Action Modes Output Control Modes Automatic Modulation Demodulation Modes Modulation Pulse width Modulation (PWM) Manchester Demodulation Together with Bi-phase Demodulation Together with Pulse-width Demodulation Together with
Figure 6-24. Timer
I/O-bus T3CS
T3EX T3CP T3EX SYSCL T1OUT POUT CM31 INT5 T3ST TOG3 Compare Compare Control TOG2 T3CO1 T3CO2 T3CM1 T3CM2 Control Demodulator
8-bit Counter
Modulator
I/O-bus Timer
Timer consists 8-bit up-counter with compare registers capture register. timer used event counter, timer signal generator. output programmed modulator demodulator serial interface. compare registers enable various modes signal generation, modulation demodulation. counter driven internal external clock sources. external clock sources, programmable edgesensitive input which used counter input, capture signal input trigger input. This timer input synchronized with SYSCL. Therefore, power-down mode SLEEP (CPU core sleep OSC-Stop yes), this timer input stopped too. counter readable capture register while running. capture mode, counter value captured programmable capture event from Timer input Timer output.
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special feature this timer trigger- single-action mode. trigger mode, counter starts counting triggered external signal input. single-action mode, counter counts only time programmed compare match event. These modes very useful modulation, demodulation, signal generation, signal measurement phase control. phase control, timer input protected against negative voltages zero-cross detection capability. Timer modulator output stage input functions demodulation. modulator works together with Timer serial interface. When shift register used modulation data shifted register encoded bit-wise. demodulation modes, decoded data bits shifted automatically into shift register.
Figure 6-25. Counter Stage
TOG2
T3EIM
Control
INT5
Capture register
T3SM1 T3RM1 T3IM1 T3TM1 T3M1
8-bit counter
CM31
8-bit comparator
Control
CM32
TOG3
Compare register
T3SM2 T3RM2 T3IM2 T3TM2 T3M2
Compare register
6.3.3.2
Timer/Counter Modes Timer timer modes modulator/demodulator modes. mode Timer Mode Register T3M.
these modes, compare register compare-mode register belonging define counter value compare match action compare match. match current counter value with content compare register triggers counter reset, Timer interrupt toggling output flip-flop. compare mode registers T3M1 T3M2 contain mask bits enabling disabling these actions. counter also enabled execute single actions with both compare registers. this mode corresponding compare match event generated only once after counter starts.
ATAM894
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ATAM894
Most timer modes their compare registers alternately. After start been activated, first comparison carried compare register second carried compare register third carried again compare register This makes easy generate signals with constant periods variable duty cycle generate signals with variable pulse space widths. single-action mode compare register, comparison always carried after first cycle other compare register. counter started stopped control register T3C. This register also controls initial level output before start. contains interrupt mask input interrupt. Timer clock-select register, internal external clock source selected. This register selects also active edge external input. edge external input generate also interrupt T3EIM Timer stopped (T3R register. status timer well occurrence compare match edge detect input signal indicated status register T2ST. This allows identification interrupt source because these events share only timer interrupt. Timer compares data values. Timer 8-bit compare registers (T3CO1, T3CO2). compare data value each Timer compare registers. compare data value compare registers
Timer Mode Timer/Counter
selected clock from internal external source increments 8-bit counter. this mode, timer used event counter external clocks timer generating interrupts pulses T3O. counter value read software capture register.
Figure 6-26. Counter Reset with Each Compare Match
Counter CM31 CM32 INT5
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Figure 6-27. Counter Reset with Compare Register Toggle with Start
Counter CM31 CM32 INT5
Toggle start
Figure 6-28. Single Action Compare Register
Counter CM31 CM32
Toggle start
Timer Mode
Timer/Counter, External Trigger Restart External Capture (with Input)
counter driven internal clock source. After starting with T3R, first edge from external input starts counter. following edges load current counter value into capture register, resets counter restarts edge selected programmable edge decoder timer input stage. single-action mode activated both compare registers trigger signal restarts single action.
Figure 6-29. Externally Triggered Counter Reset Start Combined with Single-action Mode
Counter T3EX CM31 CM32
ATAM894
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ATAM894
Timer Mode Timer/Counter, Internal Trigger Restart Internal Capture (with TOG2)
counter driven internal external (T3I) clock source. output toggle signal Timer resets counter. counter value before reset saved capture register. single-action mode activated both compare registers, trigger signal restarts single actions. This mode used frequency measurements event counter with time gate (see section "Combination Mode 10").
Figure 6-30. Event Counter with Time Gate
Counter TOG2 T3CPRegister
Capture value
Capture value
Capture value
Timer Mode Timer/Counter
timer runs timer/counter mode output used output Timer output signal.
Timer Mode Timer/Counter, External Trigger Restart External Capture (with Input)
Timer runs timer/counter mode output used output Timer output signal.
6.3.3.3
Timer Modulator/Demodulator Modes Timer Mode Carrier Frequency Burst Modulation Controlled Timer Output Toggle Flip-Flop (M2)
Timer counter driven internal external clock source. compare- compare mode registers must programmed generate carrier frequency output toggle flip-flop. output toggle flip-flop Timer used enable disable Timer output. Timer driven toggle output signal Timer other clock source (see section "Combination Mode 11").
Timer Mode Carrier Frequency Burst Modulation Controlled Internal Output (SO)
Timer counter driven internal external clock source. compare- compare mode registers must programmed generate carrier frequency output toggle flip-flop. output (SO) used enable disable Timer output. should supplied with toggle signal Timer (see section "Combination Mode 12").
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Timer Mode Modulation with Shift Register Data (SO)
compare registers used generating different time intervals. internal data output (SO) selects which compare register used output frequency generation. level data output enables compare register level enables compare register compare- compare mode registers must programmed generate frequencies output toggle flip-flop. supplied with toggle signal Timer Timer counter driven internal external clock source. Timer counter driven Counter (TOG3) (see section "Combination Mode 13").
Figure 6-31. Modulation
Counter CM31 CM32
Timer Mode Pulse-width Modulation with Shift Register
compare registers used generating different time intervals. internal data output (SO) selects which compare register used output pulse generation. this mode both compare- compare mode registers must programmed generating pulse widths. also useful enable single-action mode extreme duty-cycles. Timer used baud-rate generator trigger restart Timer must supplied with toggle signal Timer counter driven internal external clock source (see section "Combination Mode 7").
Figure 6-32. Pulse-width Modulation
TOG2
Counter CM31 CM32
9101112131415 101112131415
ATAM894
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ATAM894
Timer Mode Manchester Demodulation/ Pulse-width Demodulation
Manchester demodulation, edge detection stage must programmed detect each edge input. These edges evaluated demodulator stage. timer stage used generate shift clock SSI. compare register match event defines correct moment shifting state from input decoded into shift register after that demodulator waits next edge synchronize timer reset next bit. compare register also used detect time-out error handle with interrupt routine (see section "Combination Mode 8").
Figure 6-33. Manchester Demodulation
Timer mode T3EX CM31 SR-DATA Synchronize Manchester demodulation mode
Timer Mode Bi-phase Demodulation
Bi-phase demodulation mode, timer operates like Manchester demodulation mode. difference that bits decoded toggle flip-flop. This flip-flop samples edge middle bit-frame compare register match event shifts toggle flip-flop output into shift register (see section "Combination Mode 9").
Figure 6-34. Bi-phase Demodulation
Timer mode T3EX CM31 Reset Counter SR-DATA Synchronize Bi-phase demodulation mode
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Timer Mode Timer/Counter with External Capture Mode (T3I)
counter driven internal clock source edge external input loads counter value into capture register. edge selected with programmable edge detector timer input stage. This mode used signal pulse measurements.
Figure 6-35. External Capture Mode
1011 1718 2526 3132 3839
Counter T3CPRegister Capture value Capture value Capture value
6.3.3.4
Timer Modulator Carrier Frequency Burst Modulation output stage operates pulse-width modulator shift register output stopped with stage Timer this task, timer mode must used prescaler must supplied internal shift clock shift register.
modulator started with start shift register (SIR stopped either shift register stop (SIR compare match event stage Timer this task, Timer must used mode prescaler stage must supplied internal shift clock shift register.
Figure 6-36. Modulator
TOG3
T3TOP
Timer Mode other
SSI/ Control OMSK
ATAM894
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6.3.3.5 Timer Demodulator Bi-phase, Manchester Pulse-width-modulated Signals demodulator stage Timer used decode Bi-phase, Manchester puls-width-coded signals
Figure 6-37. Timer Demodulator
Demodulator T3EX
CM31
Counter Reset
Counter Control
6.3.3.6 6.3.3.7
Timer Registers Timer Mode Register (T3M)
Address: 'B'hex Subaddress: '0'hex T3M3 T3M2 T3M1 T3M0 Reset value: 1111b
T3M3 T3M2 T3M1 T3M0
Timer Mode select Timer Mode select Timer Mode select Timer Mode select
Table 6-13.
Mode
Timer Mode Select Bits
T3M2 T3M1 T3M0 Timer Modes Timer/counter with read access Timer/counter, external capture external trigger restart mode (T3I) Timer/counter, internal capture internal trigger restart mode (TOG2) Timer/counter mode without output (T2O T3O) Timer/counter mode without output (T2O T3O) Burst modulation with Timer (M2) Burst modulation with shift register (SO) modulation with shift register (SO) Pulse-width modulation with shift register (SO) Timer (TOG2), internal trigger restart (SCO) counter reset
T3M3
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Table 6-13.
Mode Note:
Timer Mode Select Bits (Continued)
T3M2 T3M1 T3M0 Timer Modes Manchester demodulation/pulse-width demodulation(1) (T2O T3O) Biphase demodulation (T2O T3O) Timer/counter with external capture mode (T3I) allowed allowed allowed allowed
T3M3
this mode, used only demodulator (8-bit rising edge). other modes allowed.
6.3.3.8
Timer Control Register (T3C) Write
Primary register address: 'C'hex Write Write T3EIM T3TOP T3TS Reset value: 0000b
T3EIM
Timer Edge Interrupt Mask T3EIM disables interrupt when edge event Timer occurs (T3I) T3EIM enables interrupt when edge event Timer occurs (T3I) Timer Toggle Output Preset T3TOP sets toggle output (M3) T3TOP sets toggle output (M3) Note: output preset possible Timer Toggle with Start T3TS Timer output toggled during start T3TS Timer output toggled started with Timer Timer stop reset Timer
T3TOP
T3TS
6.3.3.9
Timer Status Register (T3ST) Read
Primary register address: 'C'hex Read Read -Bit T3ED T3C2 T3C1 Reset value: x000b
T3ED T3C2 T3C1 Note:
Timer Edge Detect This will edge-detect logic Timer input (T3I) Timer Compare This will when match occurs between Counter T3CO2 Timer Compare This will when match occurs between Counter T3CO1 status bits T3C1, T3C2 T3ED will reset after READ access T3ST.
ATAM894
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ATAM894
6.3.3.10 Timer Clock Select Register (T3CS)
Address: 'B'hex Subaddress: '1'hex T3CS T3E1 T3E0 T3CS1 T3CS0 Reset value: 1111b
T3E1 T3E0
Timer Edge select Timer Edge select
Table 6-14.
T3E1
Timer Edge Select Bits
T3E0 Timer Input Edge Select (T3I) Positive edge Negative edge Each edge
T3CS1 T3CS0
Timer Clock Source select Timer Clock Source select
Table 6-15.
T3CS1
Timer Clock Select Bits
TCS0 Counter Input Signal (CL3) System clock (SYSCL) Output signal Timer (POUT) Output signal Timer (T1OUT) External input signal from edge detect
6.3.3.11
Timer Compare- Compare Mode Register Timer separate compare registers T3CO1 T3CO2 8-bit stage Timer timer compares content compare register with current counter value. both match, generates signal. This signal used counter reset, generate timer interrupt, toggling output flip-flop, clock clock next counter stage. each compare register, compare-mode register exists. These registers contain mask bits enable disable generation interrupt, counter reset, output toggling with occurrence compare match corresponding compare register. mask bits activating single-action mode also located compare mode registers. When assigned compare register compare event will suppressed.
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6.3.3.12
Timer Compare Mode Register (T3CM1)
Address: 'B'hex Subaddress: '2'hex T3CM1 T3SM1 T3TM1 T3RM1 T3IM1 Reset value: 0000b
T3SM1
Timer Single action Mask T3SM1 disables single-action compare mode T3SM1 enables single-compare mode. After this set, compare register (T3CO1) used until next compare match Timer compare Toggle action Mask T3TM1 disables compare toggle T3TM1 enables compare toggle. match Counter with compare register (T3CO1) toggles output flip-flop (TOG3) Timer Reset Mask T3RM1 disables counter reset T3RM1 enables counter reset. match Counter with compare register (T3CO1) resets Counter Timer Interrupt Mask T3RM1 disables Timer interrupt T3CO1 register. T3RM1 enables Timer interrupt T3CO1 register
T3TM1
T3RM1
T3IM1
T3CM1 contains mask bits match event Counter compare register
6.3.3.13
Timer Compare Mode Register (T3CM2)
Address: 'B'hex Subaddress: '3'hex T3CM2 T3SM2 T3TM2 T3RM2 T3IM2 Reset value: 0000b
T3SM2
Timer Single action Mask T3SM2 disables single-action compare mode T3SM2 enables single-compare mode. After this set, compare register (T3CO2) used until next compare match Timer compare Toggle action Mask T3TM2 disables compare toggle T3TM2 enables compare toggle. match Counter with compare register (T3CO2) toggles output flip-flop (TOG3) Timer Reset Mask T3RM2 disables counter reset T3RM2 enables counter reset. match Counter with compare register (T3CO2) resets Counter Timer Interrupt Mask T3RM2 disables Timer interrupt T3CO2 register T3RM2 enables Timer interrupt T3CO2 register
T3TM2
T3RM2
T3IM2
T3CM2 contains mask bits match event Counter compare register
ATAM894
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ATAM894
compare registers corresponding counter reset masks used program counter time intervals toggle masks used program output signal. single-action mask also used this mode. starts operating after timer started with T3R.
6.3.3.14
Timer COmpare Register (T3CO1) Byte Write
Address: 'B'hex Subaddress: '4'hex High Nibble Second write cycle Reset value: 1111b
Nibble First write cycle Reset value: 1111b
6.3.3.15
Timer COmpare Register (T3CO2) Byte Write
Address: 'B'hex Subaddress: '5'hex High Nibble Second write cycle Reset value: 1111b
Nibble First write cycle Reset value: 1111b
6.3.3.16
Timer Capture Register counter content read capture register. There ways capture register. modes possible read current counter value directly capture register. capture modes capture event like edge Timer input signal from Timer stores current counter value into capture register. This counter value read from capture register. Timer CaPture Register (T3CP) Byte Read
Address: 'B'hex Subaddress: '4'hex High Nibble First read cycle Reset value: xxxxb
6.3.3.17
Nibble Second read cycle Reset value: xxxxb
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6.3.4
Synchronous Serial Interface (SSI)
6.3.4.1
3-wire 2-wire mode (MCL compatible), additional internal 2-wire link multi-chip packaging solutions With Timer Bi-phase modulation Manchester modulation Pulse-width demodulation Burst modulation With Timer Pulse-width modulation (PWM) modulation Bi-phase demodulation Manchester demodulation Pulse-width demodulation Pulse position Demodulation
6.3.4.2
Peripheral Configuration synchronous serial interface (SSI) used either serial communication with external devices such EEPROMs, shift registers, display drivers, other microcontrollers, means generating capturing on-chip serial streams data. External data communication takes place Port (BP4), multi-functional port which software configured writing appropriate control word into P4CR register. configured following ways:
2-wire external interface bi-directional data communication with data terminal shift clock. uses Port BP43 bi-directional serial data line (SD) BP40 shift clock line (SC). 3-wire external interface simultaneous input output serial data, with serial input data terminal (SI), serial output data terminal (SO) shift clock (SC). uses BP40 shift clock (SC), while serial data input (SI) applied BP43 (configured P4CR input!). Serial output data (SO) this case passed through BP42 (configured P4CR T2O) Timer output stage (T2M2 configured mode Timer/SSI combined modes used together with Timer Timer capable performing variety data modulation demodulation functions (see section "Timer"). modulating data converted into continuous serial stream data which turn modulated timer functional blocks. Serial demodulated data serially captured read controller. Timer modes (demodulation modes) only used demodulator. Multi-chip link (MCL) also used interchip data interface single package multi-chip modules hybrids. such applications, provided with dedicated pads (MCL_SD MCL_SC) which two-wire chipto-chip link. activated control bit. Should these pads used SSI, standard pins required corresponding Port ports available conventional data ports.
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Figure 6-38. Block Diagram Synchronous Serial Interface
I/O-bus Timer 2/Timer SIC1 SIC2 SISC Control SSI-Control Output
Shift_CL
INT3
MCL_SC
TOG2 POUT T1OUT SYSCL
8-bit Shift Register
MCL_SD
Transmit Buffer I/O-bus
Receive Buffer
6.3.4.3
General Operation comprised essentially 8-bit shift register with associated 8-bit buffers receive buffer (SRB) capturing incoming serial data transmit buffer (STB) intermediate storage data serially output. Both buffers directly accessible software. Transferring parallel buffer data into shift register controlled automatically control, that both single byte transfers continuous streams supported.
generate shift clock (SC) either from several on-chip clock sources accept external clock. external shift clock output applied Port BP40. Selection external clock source performed Serial Clock Direction control (SCD). combinational modes, required clock selected corresponding timer mode. operate three data transfer modes synchronous 8-bit shift mode, compatible 9-bit shift modes 8-bit pseudo protocol (without acknowledge-bit). External clocking supported these modes. should thus generate full control over shift clock that always regarded Master device. directional control external data port used handled automatically dependent transmission direction Serial Data Direction (SDD) control bit. This control defines whether currently operating Transmit (TX) mode Receive (RX) mode. Serial data organized 8-bit telegrams which shifted with most significant first. 9-bit mode, additional acknowledge appended telegram handshaking purposes (see section "MCL Protocol" page 65). beginning every telegram, control loads transmit buffer into shift register proceeds immediately shift data serially out. same time, incoming data shifted into shift register input. This incoming data automatically loaded into receive buffer when complete telegram been received. Thus, data simultaneously received transmitted required.
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Before data transferred, must first activated. This performed means reset control (SIR) bit. further operation then depends data directional mode (TX/RX) present status buffer registers shown Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates (empty/full) status either transmit buffer mode), receive buffer mode). control logic ensures that data shifting temporarily halted time, appropriate receive/transmit buffer ready (SRDY SRDY status will then automatically back data shifting resumed soon application software loads data into transmit register mode) frees shift register reading into receive buffer mode). Another activity status (ACT) indicates present status serial communication. remains high duration serial telegram stop start conditions currently being generated. Both current SRDY status read status register. deactivate SSI, must high.
6.3.4.4
8-bit Synchronous Mode
Figure 6-39. 8-bit Synchronous Mode
(rising edge) (falling edge) DATA SD/TO2 Data: 00110101
8-bit synchronous mode, operate either 3-wire interface (see section "SSI Peripheral Configuration" page 60). serial data (SD) received transmitted format, synchronized either rising falling edge shift clock (SC). choice clock edge defined Serial Mode Control bits (SM0,SM1). should noted that transmission edge refers clock edge with which changes. avoid clock skew problems, incoming serial input data shifted with opposite edge. When used together with timer modulator demodulator stages, must 8-bit synchronous mode mode, soon activated (SIR shift clocks generated incoming serial data shifted into shift register. This first telegram automatically transferred into receive buffer SRDY indicating that receive buffer contains valid data. same time interrupt enabled) generated. then continues shifting following 8-bit telegram. during this time first telegram been read controller, second telegram will also transferred same into receive buffer will continue clocking next telegram. Should, however, first telegram have been read (SRDY then will stop, temporarily holding second telegram shift register until certain point time when controller able service receive buffer. this data lost overwritten.
ATAM894
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ATAM894
Deactivating (SIR mid-telegram will immediately stop shift clock latch present contents shift register into receive buffer. This used clocking data telegram less than bits length. Care should taken read final complete 8-bit data telegram multiple word message before deactivating (SIR terminating reception. After termination, shift register contents will overwrite receive buffer.
Figure 6-40. Example 8-bit Synchronous Transmit Operation
data
data
data
SRDY
Interrupt (IFN Interrupt (IFN Write data Write data Write data
Figure 6-41. Example 8-bit Synchronous Receive Operation
data data
data
SRDY
Interrupt (IFN Interrupt (IFN Read data Read data Read data
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6.3.4.5
9-bit Shift Mode 9-bit shift mode, able handle protocol (described below). always operates master device, i.e., always generated output SSI. Both start stop conditions automatically generated whenever activated deactivated bit. accordance with protocol, output data always changed clock phase shifted high phase.
Before activating (SIR commencing dialog, appropriate data direction first word must using control bit. state this controls direction data port (BP43 MCL_SD). Once started, data bits are, depending selected direction, either clocked into shift register. During clock period, port direction automatically switched over that corresponding acknowledge shifted read transmit mode, acknowledge received from slave device captured Status Register (TACK) where read controller. receive mode, state acknowledge returned slave device predetermined Status Register (RACK). Changing directional mode (TX/RX) should performed during transfer telegram. should wait until telegram which detected using interrupt (IFN interrogating status. Once started, 9-bit telegram will always completion will prematurely terminated bit. telegram, will complete current transfer terminate dialog with stop condition.
Figure 6-42. Example Transmit Dialog
Start Stop
data
data
SRDY
Interrupt (IFN Interrupt (IFN
Write data
Write data
ATAM894
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ATAM894
Figure 6-43. Example Receive Dialog
Start Stop
data
data
SRDY
Interrupt (IFN Interrupt (IFN
Write data
Read data
6.3.4.6
8-bit Pseudo Mode this mode, exhibits typical operational features except acknowledge-bit which never expected transmitted. Protocol protocol constitutes simple 2-wire bi-directional communication highway which devices communicate control data information. Although protocol support multi-master configurations, mode intended purely master controller single master system. reference multiple control contention will omitted this point.
data packaged into 8-bit telegrams plus trailing handshaking acknowledge-bit. Normally communication channel opened with so-called start condition, which initializes devices connected bus. This then followed data telegram, transmitted master controller device. This telegram usually contains 8-bit address code activate single slave device connected onto bus. Each slave receives this address compares with unique address. addressed slave device, ready receive data, will respond pulling line during clock pulse. This represents so-called acknowledge. controller detecting this affirmative acknowledge then opens connection required slave. Data then passed back forth master controller, each 8-bit telegram being acknowledged respective recipient. communication finally closed master device slave device back into standby applying stop condition onto bus.
6.3.4.7
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Figure 6-44. Protocol
Start condition
Data valid
Data change
Data valid
Stop condition
busy Start data transfer Stop data transfer Data valid
Both data clock lines remain HIGH. HIGH transition line while clock (SC) HIGH defines START condition. HIGH transition line while clock (SC) HIGH defines STOP condition. state data line represents valid data when, after START condition, data line stable duration HIGH period clock signal. address data words serially transmitted from device eight-bit words. receiving device returns zero data line during ninth clock cycle acknowledge word receipt.
Acknowledge
Figure 6-45. Protocol
Start
Stop
6.3.4.8
Interrupt
interrupt INT3 generated either buffer register status (i.e., transmit buffer empty receive buffer full), data telegram falling edge SC/SD pins Port (see P4CR). interrupt selection performed Interrupt Function control (IFN). interrupt usually used synchronize software control inform controller present status. Port interrupts used together with itself required, additional external interrupt sources. either case this interrupt capable waking controller sleep mode. enable select relevant interrupts interrupt mask (SIM) Interrupt Function (IFN) while Port interrupts enabled setting appropriate control bits P4CR register.
ATAM894
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ATAM894
6.3.4.9 Modulation Demodulation shift register used together with Timer Timer modulation demodulation purposes, 8-bit synchronous mode must used. this case, unused Port pins used conventional bi-directional ports.
modulation demodulation stages, enabled, operate soon activated (SIR cease when deactivated (SIR byte-orientated data control, (when running normally) generates serial streams which submultiples bits. output masking (OMSK) function permits, however, generation streams length. OMSK signal derived indirectly from 4-bit prescaler Timer masks programmable number unrequired trailing data bits during shifting final data word stream. number non-masked data bits defined value pre-programmed prescaler compare register. output masking, modulator stop mode (MSM) must before programming final data word into transmit buffer. This turn, enables shift clocks prescaler when this final word shifted out. reaching compare value, prescaler triggers OMSK signal following data bits blanked.
6.3.4.10
Internal 2-wire Multi-chip Link additional on-chip pads (MCL_SC MCL_SD) line used chip-to-chip link multi-chip applications. These pads activated setting SISC register. They also used interface internal data EEPROM
Figure 6-46. Multi-chip Link
U505M
Multi-chip link MCL_SC BP40/SC MCL_SD BP43/SD
Microcontroller
BP10 BP13
Figure 6-47. Output Masking Function
Timer CL2/1 Compare OMSK Control SSI-control Output TOG2 POUT T1OUT SYSCL Shift_CL 8-bit shift register
4-bit counter
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6.3.4.11 6.3.4.12
Serial Interface Registers Serial Interface Control Register (SIC1)
Auxiliary register address: '9'hex SIC1 SCS1 SCS0 Reset value: 1111b
Serial Interface Reset inactive active Serial Clock Direction line used output line used input Note: This during mode Timer mode
SCS1 SCS0 Note:
Serial Clock source Select Serial Clock source Select With bits SCS1 SCS0 insignificant
Table 6-16.
SCS1
Serial Clock Source Select Bits
SCS0 Internal Clock SYSCL/2 T1OUT/2 POUT/2 TOG2/2
transmit mode (SDD shifting starts only transmit buffer been loaded (SRDY Setting loads contents shift register into receive buffer (synchronous 8-bit mode only). modes, writing generates start condition writing generates stop condition.
ATAM894
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ATAM894
6.3.4.13 Serial Interface Control Register (SIC2)
Auxiliary register address: 'A'hex SIC2 Reset value: 1111b
Modular Stop Mode modulator stop mode disabled (output masking off) modulator stop mode enabled (output masking used modulation modes generating streams which multiples bit. Serial Mode control Serial Mode control
Table 6-17.
Mode
Serial Mode Control Bits
Mode 8-bit NRZ-data changes with rising edge 8-bit NRZ-data changes with falling edge 9-bit two-wire mode 8-bit two-wire pseudo mode acknowledge)
Serial Data Direction transmit mode line used output (transmit data). SRDY transmit buffer write access receive mode line used input (receive data). SRDY receive buffer read access controls port directional control defines reset function SRDY-flag
Note:
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6.3.4.14
Serial Interface Status Control Register (SISC)
Primary register address: 'A'hex SISC write SISC read -Bit RACK TACK SRDY Reset value: 1111b Reset value: xxxxb
Multi-Chip Link activation multi-chip link disabled. This during transactions to/from internal EEPROM connects additionally internal multi-chip link pads Receive ACKnowledge status/control mode RACK transmit acknowledge next receive telegram RACK transmit acknowledge last receive telegram Transmit ACKnowledge status/control mode TACK acknowledge received last transmit telegram TACK acknowledge received last transmit telegram Serial Interrupt Mask disable interrupts enable serial interrupt. interrupt generated Interrupt FuNction serial interrupt generated telegram serial interrupt generated when SRDY goes (i.e., buffer becomes empty/full transmit/receive mode) Serial interface buffer ReaDY status flag SRDY receive mode: receive buffer empty transmit mode: transmit buffer full SRDY receive mode: receive buffer full transmit mode: transmit buffer empty Transmission ACTive status flag transmission active, i.e., serial data transfer. Stop start conditions currently progress. transmission inactive
RACK
TACK
SRDY
6.3.4.15
Serial Transmit Buffer (STB) Byte Write
Primary register address: '9'hex First write cycle Second write cycle
Reset value: xxxxb Reset value: xxxxb
transmit buffer SSI. transfers transmit buffer into shift register starts shifting with most significant bit.
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.4.16 Serial Receive Buffer (SRB) Byte Read
Primary register address: '9'hex First read cycle Second read cycle
Reset value: xxxxb Reset value: xxxxb
receive buffer SSI. shift register clocks serial data (most significant first) loads content into receive buffer when complete telegram been received.
6.3.5 Combination Modes UTCM consists timers (Timer Timer serial interface. There multitude modes which timers serial interface work together.
8-bit wide serial interface operates shift register modulation demodulation. modulator demodulator units work together with timers shift data bits into shift register.
6.3.5.1
Combination Mode Timer
Figure 6-48. Combination Timer
I/O-bus
P4CR
T2M1
T2M2
DCGO SYSCL T1OUT TOG3 CL2/1 4-bit Counter OVF1 POUT CL2/2
8-bit Counter OVF2 TOG2
OUTPUT
Compare
POUT
Timer control
Compare
INT4
MOUT Bi-phase Manchester modulator
T2CO1
TOG2
T2CM
T2CO2
Timer modulator output-stage
Control
I/O-bus
SIC1
TOG2 POUT T1OUT SYSCL SCLI
SIC2
SISC
Control INT3
SSI-control
MCL_SC Output
Shift_CL
MCL_SD
8-bit shift register
Transmit buffer I/O-bus
Receive buffer
4679D-4BMCU-05/05
Combination Mode Burst Modulation
mode Timer mode Timer output mode
8-bit internal data output Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler Duty cycle burst generator
Figure 6-49. Carrier Frequency Burst Modulation with Internal Data Output
DCGO
Counter TOG2
Counter compare register
Combination Mode Bi-phase Modulation
mode Timer mode Timer output mode
8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler modulator Timer modulates internal data output Bi-phase code
Figure 6-50. Bi-phase Modulation
TOG2
8-bit data
Data: 00110101
Combination Mode Manchester Modulation
mode Timer mode Timer output mode
8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler modulator Timer modulates internal data output Manchester code
ATAM894
4679D-4BMCU-05/05
ATAM894
Figure 6-51. Manchester Modulation
TOG2
8-bit data
Data: 00110101
Combination Mode Manchester Modulation
mode Timer mode Timer output mode
8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter 4-bit prescaler modulator Timer modulates data output Manchester code
4-bit stage used prescaler generate stop signal modulator special mode supply prescaler with shift clock. control output signal (OMSK) used stop signal modulator. This example 12-bit Manchester telegram:
Figure 6-52. Manchester Modulation
SCLI Buffer full Timer Mode Counter OMSK Counter Compare Register
4679D-4BMCU-05/05
Combination Mode Bi-phase Modulation
mode Timer mode Timer output mode
8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter 4-bit prescaler modulator Timer modulates data output Bi-phase code
4-bit stage used prescaler generate stop signal modulator special mode supply prescaler shift clock. control output signal (OMSK) used stop signal modulator. This example 13-bit Biphase telegram.
Figure 6-53. Bi-phase Modulation
SCLI Buffer full Timer Mode Counter OMSK Counter Compare Register
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.5.2 Combination Mode Timer
Figure 6-54. Combination Timer
I/O-bus T3CS T3EX T3CP T3EX SYSCL T1OUT POUT Compare Compare Timer control CM31 T3ST INT5 TOG3 Control Modulator Demodulator
8-bit Counter
T3CO1
T3CO2
T3CM1
T3CM2
SIC1 TOG2 POUT T1OUT SYSCL
SIC2
SISC
Control
INT3
MCL_SC Output
SCLI
SSI-control
Shift_CL
8-bit shift register
MCL_SD
Transmit buffer I/O-bus
Receive buffer
Combination Mode Modulation
mode Timer mode
8-bit shift register internal data output (SO) Timer modulation with shift register data (SO)
compare registers used generate varied time intervals. data output selects which compare register used output frequency generation. '0'-level data output enables compare register '1'-level enables compare register compare compare mode registers must programmed generate frequencies output toggle flip-lop. supplied with toggle signal Timer other clock source. Timer counter driven internal external clock source.
4679D-4BMCU-05/05
Figure 6-55. Modulation
Counter CM31 CM32
Combination Mode Pulse-width Modulation (PWM)
mode Timer mode
8-bit shift register internal data output (SO) Timer Pulse-width modulation with shift register data (SO)
compare registers used generate varied time intervals. data output selects which compare register used output pulse generation. this mode, both compare compare mode registers must programmed generate pulse width. also useful enable single-action mode extreme duty cycles. Timer used baudrate generator triggered restart Timer must supplied with toggle signal Timer counter driven internal external clock source.
Figure 6-56. Pulse-width Modulation
TOG2
Counter CM31 CM32
9101112131415 101112131415
ATAM894
4679D-4BMCU-05/05
ATAM894
Combination Mode Manchester Demodulation/Pulse-width Demodulation
mode Timer mode
8-bit shift register internal data input (SI) internal shift clock (SCI) from Timer Manchester demodulation/pulse-width demodulation with Timer
Manchester demodulation, edge detection stage must programmed detect each edge input. These edges evaluated demodulator stage. timer stage used generate shift clock SSI. compare register match event defines correct moment shifting state from input decoded into shift register. After that, demodulator waits next edge synchronize timer reset next bit. compare register used detect time error handle with interrupt routine. Before activating demodulator mode timer demodulator stage must synchronized with bit-stream. Manchester code timing consists parts with half bit-length complete bit-length. synchronization routine must start demodulator after interval with complete bit-length. counter driven internal clock source. output used Timer this mode. Manchester decoder also used pulse-width demodulation. input must programmed detect positive edge. demodulator timer must synchronized with leading edge pulse. After that counter match with compare register shifts state input into shift register. next positive edge input restarts timer.
Figure 6-57. Manchester Demodulation
Timer mode T3EX CM31 SR-DATA Synchronize Manchester demodulation mode
4679D-4BMCU-05/05
Combination Mode Bi-phase Demodulation
mode Timer mode
8-bit shift register internal data input (SI) internal shift clock (SCI) from Timer Bi-phase demodulation with Timer
Bi-phase demodulation mode timer works like Manchester demodulation mode. difference that bits decoded with toggle flip-flop. This flip-flop samples edge middle bit-frame compare register match event shifts toggle flipflop output into shift register. Before activating demodulation timer demodulation stage must synchronized with bit-stream. Bi-phase code timing consists parts with half bit-length complete bit-length. synchronization routine must start demodulator after interval with complete bit-length. counter driven internal clock source output used Timer this mode.
Figure 6-58. Bi-phase Demodulation
Timer mode T3EX CM31 Reset Counter SR-DATA Synchronize Bi-phase demodulation mode
ATAM894
4679D-4BMCU-05/05
ATAM894
6.3.5.3 Combination Mode Timer Timer
Figure 6-59. Combination Timer Timer
I/O-bus T3CS T3EX T3CP T3EX SYSCL T1OUT POUT Compare Compare Timer control TOG2 T3CO1 T3CO2 T3CM1 T3CM2 I/O-bus CM31 T3ST INT5 TOG3 Control
Modulator
Demodulator
8-bit Counter
P4CR
T2M1
DCGO
T2M2
TOG3 SYSCL T1OUT
CL2/1
4-bit Counter
OVF1
CL2/2 POUT
8-bit Counter
OVF2 TOG2
OUTPUT
MOUT INT4
Compare
Timer control
POUT
Compare
Bi-phase Manchester modulator
T2CO1 I/O-bus
T2CM
T2CO2
Timer modulator output-stage
Control (RE, SCO, OMSK)
Combination Mode Frequency Measurement Event Counter with Time Gate
Timer mode 1/2: Timer output mode 1/6: Timer mode
12-bit compare counter/8-bit compare counter 4-bit prescaler Timer compare match toggles (TOG2) Timer Timer/Counter; integrated trigger restart integrated capture (with Timer TOG2-signal)
counter driven external (T3I) clock source. output signal (TOG2) Timer resets counter. counter value before reset saved capture register. singleaction mode activated both compare registers, trigger signal restarts also single actions. This mode used frequency measurements event counter with time gate.
4679D-4BMCU-05/05
Figure 6-60. Frequency Measurement
11121314151617 101112131415161718 Counter
TOG2 T3CPRegister
Capture value
Capture value
Capt. value
Figure 6-61. Event Counter with Time Gate
Counter TOG2 T3CPRegister
Capture value Capture value
Cap. value
Combination Mode Burst Modulation
Timer mode 1/2: Timer output mode 1/6: Timer mode
12-bit compare counter/8-bit compare counter 4-bit prescaler Timer compare match toggles output flip-flop (M2) Timer Carrier frequency burst modulation controlled Timer output (M2)
Timer counter driven internal external clock source. compare- compare mode registers must programmed generate carrier frequency with output toggle flip-flop. output toggle flip-flop (M2) Timer used enable disable Timer output. Timer driven toggle outp
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