8-MHz Crystal Oscillator (System Clock) 32-kHz Crystal Oscillator RC-o
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Programmable System Clock with Prescaler Five Different Clock Sources
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MARC4 4-bit Universal Microcontroller ATAM510
Description
ATAM510 Multi-time Programmable (MTP) microcontroller which functionally compatible Atmel's ATAR510 mask programmable microcontroller. contains EEPROM, RAM, digital pins, maskable external interrupt sources, maskable internal interrupts, watchdog timer, interval timer, 8-bit multifunction timer/counter modules versatile software configurable on-chip system clock module.
Rev. 4711B-4BMCU-01/05
Figure 0-1.
Block Diagram
SCLIN OSCIN OSCOUT AVDD NRST TIM1
Test Sleep
System clock
Real time clock
Master reset
Timer/ counter Watchdog Prescaler Timer Timer Melody buzzer
MARC4
4-bit core
Interrupt reset
Interrupt
Interrupt
Port Port Port Port
Port
Port
Port
Port
Port
ATAM510
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ATAM510
Configuration
Figure 1-1. Pinning SSO44
AVDD OSCIN OSCOUT SCLIN BPC3 BPC2 NRST BPB2 BPA0 BPB1 BPA1 BPB3 BPB0 BPA2 BP11 BPA3 BP10
BP71
BP72
BP73
BP70
BP61
BP60
ATAM510
BPC1
BPC0
BP13
TIM1
BP53
BP52
BP51
BP00
BP50
BP43
BP42
BP41
BP40
BP03
BP02
BP01
Table 1-1.
Description
Symbol BP53 BP52 BP51 BP50 BP43 (NBUZ) BP42 (BUZ) BP41 (T0OUT1) BP40 (T0OUT0) BP03 BP02 BP01 BP00 TIM1 BPC1 BPC0 BP13 Function Circuit ground line high current Port wise configurable line high current Port wise configurable line high current Port wise configurable line high current Port wise configurable Power supply voltage +2.2 +6.2 High current line BP43 Port configurable buzzer output NBUZ High current line BP42 Port configurable buzzer output line BP41 Port configurable timer/counter T0OUT1 line BP40 Port configurable timer/counter T0OUT0 line Port automatic nibble wise configurable line Port automatic nibble wise configurable line Port automatic nibble wise configurable line Port automatic nibble wise configurable Dedicated Timer line Port wise configurable Test mode input, used control production test modes (internal pull-down) line Port wise configurable line Port automatic nibble wise configurable
BP12
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Table 1-1.
Description
Symbol BP12 BP11 BP10 BPA3 BPA2 BPA1 BPA0 NRST OSCOUT OSCIN AVDD BPC2 BPC3 BPB0 BPB1 BPB2 BPB3 BP60 BP61 SCLIN BP73 BP72 BP71 BP70 Function line Port automatic nibble wise configurable line Port automatic nibble wise configurable line Port automatic nibble wise configurable line Port wise configurable, inputs port monitor module optional coded reset inputs line Port wise configurable, inputs port monitor module optional coded reset inputs line Port wise configurable, inputs port monitor module optional coded reset inputs line Port wise configurable, inputs port monitor module optional coded reset inputs Reset input (/output), logic this resets device. internal watchdog coded reset generate pulse this 32-kHz 4-MHz quartz crystal output 32-kHz 4-MHz quartz crystal input Analog power supply voltage +2.2 +6.2 line Port wise configurable line Port wise configurable line Port wise configurable inputs port monitor module line Port wise configurable inputs port monitor module line Port wise configurable inputs port monitor module line Port wise configurable inputs port monitor module line Port wise configurable external programmable interrupts line Port wise configurable external programmable interrupts External trimming resistor external clock input program mode enable (internal pull-down) line high current Port wise configurable line high current Port wise configurable line high current Port wise configurable line high current Port wise configurable
ATAM510
4711B-4BMCU-01/05
ATAM510
MARC4 Architecture
General Description
functionality, programming pinning ATAM510 compatible with ATAR510 mask programmable microcontroller from Atmel. on-chip modules addressed controlled with exactly same programming code, that program targeted ATAR510 read directly into ATAM510 will operate same fashion. MARC4 microcontroller consists advanced stack-based 4-bit core on-chip peripherals. based Harvard architecture with physically separate program memory (ROM) data memory (RAM). Three independent buses, instruction bus, memory bus, used parallel communication between ROM, peripherals. This enhances program execution speed allowing both instruction prefetching, simultaneous communication on-chip peripheral circuitry. extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast efficient processing hardware events. MARC4 designed high-level programming language qFORTH. core includes both expression return stack. This architecture enables high-level language programming without loss efficiency code density. Figure 2-1. MARC4 Core
MARC4 CORE
Reset Program memory Reset Clock Instruction Memory Instruction decoder System clock Interrupt controller 4-bit
Sleep
On-chip peripheral modules
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Components MARC4 Core
core contains ROM, RAM, ALU, program counter, address registers, instruction decoder interrupt controller. following sections describe each functional block more detail.
2.2.1
EEPROM program memory (EEPROM) programmed with customer application program. EEPROM addressed 12-bit wide program counter, thus predefining maximum program bank size Kbytes. lowest user address segment taken 512-byte zero page which contains predefined start addresses interrupt service routines special subroutines accessible with single byte instructions (SCALL). corresponding memory shown Figure 2-2. Look-up tables constants also held EEPROM accessed MARC4's built-in table instruction. Figure 2-2. EEPROM ATAM510
FFFh FFFh 1F8h 1F0h 1E8h 1E0h
EEPROM
bit)
180h
SCALL addresses
140h 100h 080h
1FFh
Zero page
000h
018h 010h 008h
040h
008h 000h
2.2.2
MARC4 contains 4-bit wide static random access memory (RAM). used expression stack, return stack data memory variables arrays. addressed four 8-bit wide address registers Figure 2-3.
(256 4-bit) Autosleep Global variables
Expression stack
TOS-1 TOS-2 4-bit Expression stack Return stack
address register:
TOS-1
Return stack
Global variables 12-bit
ATAM510
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ATAM510
2.2.3 Expression Stack 4-bit wide expression stack addressed with expression stack pointer (SP). arithmetic, memory reference operations take their operands from, return their results expression stack. MARC4 performs operations with stack items (TOS TOS-1). register contains element expression stack works same accumulator. This stack also used passing parameters between subroutines scratch area temporary storage data. Return Stack 12-bit wide return stack addressed return stack pointer (RP). used storing return addresses subroutines, interrupt routines keeping loop index counts. return stack also used temporary storage area. MARC4 instruction supports exchange data between elements expression stack return stack. stacks, within RAM, have user definable location maximum depth.
2.2.4
Registers
MARC4 controller seven programmable registers condition code register. They shown following programming model.
2.3.1
Program Counter (PC) program counter 12-bit register which contains address next instruction fetched from ROM. Instructions currently being executed decoded instruction decoder determine internal micro-operations. linear code calls branches) program counter incremented with every instruction cycle. branch, call, return instruction interrupt executed, program counter loaded with address. program counter also used with table instruction fetch 8-bit wide constants. Figure 2-4.
Programming Model
Program counter
Return stack pointer
Expression stack pointer
address register
address register
stack register
Condition code register
Interrupt enable Branch Reserved Carry/borrow
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2.3.2
Address Registers addressed with four 8-bit wide address registers: These registers allow access nibbles. Expression Stack Pointer (SP) stack pointer contains address next-to-top 4-bit item (TOS-1) expression stack. pointer automatically pre-incremented nibble moved onto stack postdecremented nibble removed from stack. Every post-decrement operation moves item (TOS-1) register before decremented. After reset stack pointer initialized with allocate start address expression stack area. Return Stack Pointer (RP) return stack pointer points element 12-bit wide return stack. pointer automatically pre-increments element moved onto stack, post-decrements element removed from stack. return stack pointer increments decrements steps This means that every time 12-bit element stacked, 4-bit location left unwritten. This location used qFORTH compiler allocate 4-bit variables. After reset return stack pointer initialized FCh. Address Registers registers used address 4-bit item RAM. fetch operation moves addressed nibble onto TOS. store operation moves addressed location. using either pre-increment post-decrement addressing mode arrays compared, filled moved. Stack (TOS) stack register accumulator MARC4. arithmetic/logic, memory reference operations this register. register receives data from ALU, ROM, bus. Condition Code Register (CCR) 4-bit wide condition code register contains branch, carry interrupt enable flag. These bits indicate current state CPU. flags reset operations. instructions SET_BCF, TOG_BF, CCR! allow direct manipulation condition code register. Carry/Borrow carry/borrow flag indicates that borrow carry Arithmetic Logic Unit (ALU) occurred during last arithmetic operation. During shift rotate operations, this used fifth bit. Boolean operations have affect C-flag. Branch branch flag controls conditional program branching. Should branch flag have been previous instruction, conditional branch will cause jump. This flag affected arithmetic, logic, shift, rotate operations.
2.3.3
2.3.4
2.3.5
2.3.6
2.3.7
2.3.8
2.3.9
ATAM510
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ATAM510
2.3.10 Interrupt Enable interrupt enable flag globally enables disables triggering interrupt routines with exception non-maskable reset. After reset while executing instruction, interrupt enable flag reset, thus disabling interrupts. core will accept further interrupt requests until interrupt enable flag been again either executing SLEEP instruction.
4-bit performs arithmetic, logical, shift rotate operations with elements expression stack (TOS TOS-1) returns result TOS. operations affect carry/borrow branch flag condition code register (CCR). Figure 2-5. Zero-address Operations
TOS-1 TOS-2 TOS-3 TOS-4
2.4.1
Instruction MARC4 instruction optimized high level programming language qFORTH. Many MARC4 instructions qFORTH words. This enables compiler generate fast compact program code. instruction pipeline which allows controller prefetch instruction from EEPROM same time present instruction being executed. MARC4 zero-address machine, instructions contain only operation performed source destination address fields. operations implicitly performed data placed stack. There byte instructions which executed within machine cycles. MARC4 machine cycle made system clock cycles (SYSCL). Most instructions only byte long executed single machine cycle.
2.4.2
ports registers peripheral modules mapped. communication between core on-chip peripherals takes place associated control. With MARC4 instructions allows direct read write access primary addresses. More about access on-chip peripherals described section "Peripheral Modules". internal accessible customer final microcontroller device, used interface MARC4 emulation.
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Interrupt Structure
MARC4 handle interrupts with eight different priority levels. They generated from internal external interrupt sources software interrupt from itself. Each interrupt level hard-wired priority associated vector service routine (see Table page 11). programmer postpone processing interrupts resetting interrupt enable flag CCR. interrupt occurrence will still registered, interrupt routine only started after flag set. interrupts masked, priority individually software configured programming appropriate control register interrupting module (see section "Peripheral Modules").
2.5.1
Interrupt Processing processing eight interrupt levels, MARC4 includes interrupt controller with 8bit wide interrupt pending interrupt active registers. interrupt controller samples interrupt requests during every non-I/O instruction cycle latches these interrupt pending register. Whenever interrupt request detected, interrupts program currently being executed, condition that higher priority interrupt present interrupt active register. interrupt enable set, processor enters interrupt acknowledge cycle. During this cycle short call (SCALL) instruction service routine executed current saved return stack. interrupt service routine completed with instruction. This instruction resets corresponding bits interrupt pending/active register fetches return address from return stack program counter. When interrupt-enable flag reset (triggering interrupt routines disabled), execution interrupt service routines inhibited logging interrupt requests interrupt pending register. execution interrupt delayed until interrupt-enable flag again. Note that interrupts only lost interrupt request occurs while corresponding pending register still (i.e., interrupt service routine finished). After master reset (power-on, brown-out watchdog reset), interrupt-enable flag interrupt pending interrupt active registers reset.
2.5.2
Interrupt Latency interrupt latency time from occurrence interrupt interrupt service routine being activated. MARC4 this extremely short (taking between machine cycles depending state core).
ATAM510
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ATAM510
Figure 2-6. Interrupt Handling
INT7
Priority Level
Main Autosleep INT3 INT5
INT7 active
INT5 active
INT2 INT3 active INT2 pending INT2 active SWI0
INT0 pending
INT0 active Main/ Autosleep
Time
Table 2-1.
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Interrupt Priority Table
Priority Lowest Highest Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Maskable Interrupt Opcode (SCALL 040h) (SCALL 080h) (SCALL 0C0h) (SCALL 100h) (SCALL 140h) (SCALL 180h) (SCALL 1C0h) (SCALL 1E0h)
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Table 2-2.
Hardware Interrupts
Possible Interrupt Priorities Interrupt Mask Register PAIPR PBIPR P6CR P6CR ITIPR ITIPR T0CR T1CR Function level active time Level inputs edge, input edge, input edge edge frequencies frequencies 8192 Overflow/compare/ measurement Compare
Interrupt Source NRST external Watchdog Port coded reset Port monitor Port monitor Port external Port external Interval timer INTA Interval timer INTB Timer Timer
Hardwired (neither optional software configurable) Customer mask option (see "Hardware Options") Software configurable (see "Peripheral Modules" section further details)
ATAM510, there eleven hardware interrupt sources which programmed occupy variety priority levels. With exception reset sources (RST), each source individually masked mask bits corresponding control registers. overview possible hardware configurations shown Table 2-2. 2.5.3 Software Interrupts programmer generate interrupts using software interrupt instruction (SWI) which supported qFORTH predefined macros named SWI0 SWI7. software triggered interrupt operates exactly like hardware triggered interrupt. instruction takes elements from expression stack writes corresponding bits interrupt pending register. Therefore, using instruction, interrupts re-prioritized lower priority processes scheduled later execution.
ATAM510
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ATAM510
Hardware Reset
master reset forces into well-defined condition. unmaskable activated independent current program state. triggered either initial supply power-up, short collapse power supply, watchdog time-out, activation NRST input, occurrence coded reset Port (see Figure 2-7). master reset activation will reset interrupt enable flag, interrupt pending registers interrupt active registers initializes on-chip peripherals. this state ports take high resistance input status with deactivated pull-up pull-down transistors (see Figure page When reset condition disappears, hardware configuration previously programmed configuration EEPROM (see section "MTP Programming") loaded into peripherals that port characteristics pull-up/downs reflect programmed configuration. This configuration period immediately followed further reset delay time (approximately ms), after which short call instruction (opcode C1h) EEPROM address 008h performed. This activates initialization routine $RESET which turn initializes necessary variables, stack pointers peripheral configuration registers. Figure 2-7. Reset Configuration/Start-up Sequence
Pull-up NRST
Configuration
Reset delay timer
reset
Power-on reset
reset code
CODE(1)
Watchdog(1)
Time Port
reset
Port
2.6.1
Power-on Reset fully integrated power-on reset circuit ensures that core held reset state until minimum operating supply voltage been reached. reset condition also generated should supply voltage drop momentarily below minimum operating supply. External Reset (NRST) external reset triggered with NRST pin. activate external reset, should minimum Coded Reset (Port coded reset circuit connected directly Port terminals. using mask option, user define hardwired code combination (e.g., pins low) which, occurring Port will generate reset same NRST pin.
2.6.2
2.6.3
4711B-4BMCU-01/05
Table 2-3.
Multiple Reset Options
NO_RST RST2 RST3 RST4 RST5 RST6 RST7 Note:
used (default) BPA0 BPA1 BPA0 BPA1 BPA2 BPA0 BPA1 BPA2 BPA3 BPA0 BPA1 high BPA0 BPA1 BPA2 high BPA0 BPA1 BPA2 BPA3 high
this option used, reset maskable will also trigger predefined code written Port itself. Care should also taken generate unwanted reset inadvertently passing through reset code input transitions. This applies especially pins have high capacitive load.
2.6.4
Watchdog Reset watchdog's function enabled mask option triggers reset with every watchdog counter overflow. suppress watchdog reset, counter must regularly reset reading watchdog register address (CWD). reacts exactly same manner reset stimulus from above sources. Normal Mode Start-up
Figure 2-8.
NRST
Device status
Reset
Configuration period
Power-on reset delay
Application program execution
Port status
Program defined
Input mode
Input mode
Input mode
Program defined
Pull-up/ pull-down configuration
config.
pull-up/-down
pull-up/-down
configuration
configuration
ATAM510
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ATAM510
2.7.1
Clock Generation
Clock Module clock module generates clocks. system clock (SYSCL) supplies peripherals while lower frequency periphery sub-clock (SUBCL) supplies only peripherals. modes clock sources programmable with OS1-bit OS0-bit SCregister CCS-bit CM-register. clock module includes different internal oscillator types: RC-oscillators, 4-MHz crystal oscillator 32-kHz crystal oscillator. pins OSC1 OSC2 provide interface connect crystal either 4-MHz, 32-kHz crystal oscillator. SCLIN used input external clock connect external trimming resistor RCoscillator necessary components with exception crystal trimming resistor integrated on-chip. these clock sources selected generate system clock (SYSCL). applications that require exact timing, possible fully integrated RC-oscillator without external components. RC-oscillator more stable oscillator frequency must trimmed with external resistor attached between SCLIN VDD. this configuration, system clock frequencies below MHz, RC-oscillator frequency maintained stable with tolerance ±10% over full operating temperature voltage range. clock module software programmable using clock management register (CM) system configuration register (SC). required oscillator configuration selected with OS(1:0)-bits SC-register. programmable 4-bit divider stage allows adjustment system clock speed. synchronization stage avoids clock glitches which could caused clock source switching. always requires SYSCL clocks execute instructions, process interrupts enter leave SLEEP state. Internal oscillators are, depending condition NSTOP-bit automatically stopped started where necessary. Special care must however taken when using external clock source which gated microcontroller port signals. This configuration hang external oscillator switched while external clock source still selected. therefore advisable such case switch first internal RC-oscillator source using CSS-bit. external source then reselected later when external oscillator again been restarted.
4711B-4BMCU-01/05
Figure 2-9.
Clock Module
Ext. clock
ExIn ExOut Stop Stop RCOut1 Control Divider chain 4Out Stop
SCLIN
RCoscillator
RC[1:0]
SYSCLmax SYSCL
RC-oscillator2
OSCIN RTrim RCOut2 Stop
Timer/ counter
4-MHz oscillator
Oscin Oscout
32-kHz oscillator
OSCOUT Oscin Oscout 32Out Stop SUBCL NSTOP CSS1 CSS0 Sleep
SYSCLmax/64
Table 2-4.
Clock Modes
Clock Source SYSCL Clock Source SUBCL SCLIN/128
Mode
RC-oscillator (internal) RC-oscillator (internal) RC-oscillator (internal) RC-oscillator (internal)
External input clock SYCLmax/64 RC-oscillator with external trimming resistor 4-MHz oscillator 32-kHz oscillator SYCLmax/64 SYCLmax/64
SYCLmax/64 fXTAL/128
2.7.2 2.7.2.1
Oscillator Circuits External Clock Input Stage RC-oscillator Fully Integrated timing insensitive applications, possible fully integrated RC-oscillator operates without external components saves additional costs. RC-oscillator center frequency tolerance better than ±50% over full temperature voltage range. reduction application operating supply voltage temperature ranges will result improved frequency tolerance. more detailed information Figure Figure page basic center frequency RC-oscillator programmable with RC0-bits SC-register.
ATAM510
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ATAM510
Figure 2-10. RC-oscillator
RCoscillator RcOut1 Stop Control RcOut1 Osc-Stop
2.7.2.2
External Input Clock SCLIN driven external clock source provided meets specified duty cycle, rise fall times input levels. maximum system clock frequency fSYSCLmax that core operate fSCLIN/2 (see Figure 2-11). Figure 2-11. External Input Clock
Ext. input clock Ext. Clock SCLIN ExIn Stop ExOut
ExOut Osc-Stop
2.7.2.3
RC-oscillator with External Trimming Resistor RC-oscillator high stability oscillator whereby oscillator frequency trimmed with external resistor between SCLIN VDD. this configuration, long system clock frequency does exceed MHz, RC-oscillator frequency maintained stable with tolerance ±10% over full operating temperature voltage range. example: SYSCLmax frequency MHz, obtained connecting resistor Rext (see Figure 2-12, Figure page Figure page 65). Figure 2-12. RC-oscillator
Rext SCLIN RTrim Stop RCoscillator RcOut2 RcOut2 Osc-Stop
2.7.2.4
4-MHz Oscillator integrated system clock oscillator requires external crystal ceramic resonator connected between OSCIN OSCOUT pins establish oscillation. necessary oscillator circuitry, with exception actual crystal, resonator optional integrated on-chip.
4711B-4BMCU-01/05
Figure 2-13. System Clock Oscillator
OSCIN Oscin 4Out XTAL Cer. 4-MHz oscillator Oscout OSCOUT Stop 4Out
Osc-Stop
2.7.2.5
32-kHz Oscillator Some applications require accurate long-term time keeping without putting excessive demands alternatively resolution computing power. this case, on-chip ultra power 32-kHz crystal oscillator used generate both SUBCL and/or SYSCL. this mode, power consumption significantly reduced. 32-kHz crystal oscillator will operating (not stopped) during power-down/SLEEP mode. Figure 2-14. 32-kHz Crystal Oscillator
OSCIN Oscin 32Out XTAL 32-kHz oscillator Oscout OSCOUT 32Out
Note:
Both, 4-MHz 32-kHz crystal oscillator, integrated stage divider circuit stabilize oscillation before oscillator output used system clock. This results additional delay about 4-MHz crystal about 32-kHz crystal.
2.7.2.6
Quartz Oscillator Configuration customer's application necessitates quartz crystal clock source this requires capacitive trimming, trimming capacitors integrated into unlike ATAR510 should therefore connected externally discrete components between respective Quartz Crystal terminals (OSCIN, OSCOUT) VSS.
ATAM510
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ATAM510
2.7.3 Clock Management Register (CM) clock management register controls system clock divider chain, well peripheral clock power-down modes.
Auxiliary register address: 'E'hex NSTOP CSS1 CSS0 Reset value: 1111b
NSTOP
STOP peripheral clock NSTOP stops peripheral clock while core SLEEP mode 32-kHz crystal oscillator SUBCL clock cannot stopped NSTOP enables peripheral clock while core SLEEP mode Core Clock Select internal RC-oscillator generates SYSCL 4-MHz crystal oscillator, 32-kHz crystal oscillator, external clock source RC-oscillator (with external resistor) will generate SYSCL dependent setting system configuration register Core Speed Select These bits control system clock divider chain
CSS1 (1:0)
Table 2-5.
CSS1
Core Speed Select
CSS0 Divider Note SYSCLmax/8 SYSCLmax/4 SYSCLmax/2 Reset value SYSCLmax
2.7.4
System Configuration Register (SC)
Primary register address: 'E'hex write Reset value: 1111b
Table 2-6.
Internal Oscillator Frequency Selection (SYSCLmax)
SYSCLmax 25°C, (fiRC0) (fiRC1) (fiRC2) (fiRC3) Note Reset value
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OS1,
Oscillator selection bits conjunction with CCS-bit)
Table 2-7.
Note:
Oscillator Select
SYSCLmax/64 SYSCLmax/64 SUBCL System Oscillator Selection External input clock SCLIN RC-oscillator with Rext 4-MHz crystal oscillator 32-kHz crystal oscillator RC-oscillator
CM-register, RC-oscillator stopped.
2.7.5
Power-down Modes ATAM510 incorporates several modes which enable power consumption tailored minimum without sacrificing computational power. When controller exits lowest priority interrupt task, reverts SLEEP state. This shutdown condition which used reduce average system power consumption where itself only partially utilized. SLEEP, clocking system deactivated whereby peripherals associated clock sources remain active (Standby Mode) they also halted (Halt Mode). Standby Mode, peripherals able continue operation required also generate interrupts which can, along with reset, reactivate bring sleep state. SLEEP only maintained when none interrupt pending active register bits set. application $AUTOSLEEP routine ensures correct function sleep mode. both Standby Active modes current consumption largely dependent frequency system clock (SYSCL) supply voltage (VDD) (see Figure Figure page while Halt Mode current merely controller static leakage current. Selection Standby Halt mode performed NSTOP clock management register (CM). should noted that power 32-kHz crystal oscillator, enabled will always remain active both Standby Halt modes.
Table 2-8.
Power-down Modes
Core State SLEEP SLEEP RC-Oscillator RC-Oscillator 4-MHz Oscillator STOP 32-kHz Oscillator External Input Clock SCLIN Enabled Enabled Disabled
Mode Active Standby Halt
NSTOP
ATAM510
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ATAM510
2.7.6 Clock Monitor Mode Figure 2-15. Clock Monitoring
NRST
SYSCL clocks
BP11 SUBCL clocks
BP10
Oscillator supervisory mode Normal operation
trimming purposes, ATAM510 into clock monitor mode. forcing test input (TE) high, SYSCL clock will appear BP11 (Port SUBCL clock Port BP10 (Port releasing pin, BP10 BP11 will resume their normal function (see Figure 2-15).
Peripheral Modules
Addressing Peripherals
Accessing peripheral modules takes place (see Figure page 22). instructions allow direct addressing modules. dual register addressing scheme been adopted which addresses "primary register" directly. address "auxiliary register", access must switched with "auxiliary switching module". Thus, single OUT) module address will read write) into module primary register. Accessing auxiliary register performed with same instruction preceded writing module address into auxiliary switching module. Byte-wide registers accessed multiple OUT) instructions. Extended addressing used more complex peripheral modules, with larger number registers. this case, bank subport registers indirectly addressed with subport address being initially written into auxiliary register. Please refer "HARDC510.SCR" hardware interface file programming guideline.
4711B-4BMCU-01/05
Figure 3-1.
Example Addressing
Module Module
(Address Pointer) Aux. Reg. Bank Primary Reg. Subport Subport Aux. Reg.
Module
Module
Auxiliary Switch Module
Subport Primary Reg. Subport Primary Reg. Primary Reg.
other modules
Indirect Subport Access (Subport Register Write)
Dual Register Access (Primary Register Write)
Single Register Access (Primary Register Write)
Addr. (M1) Addr. (ASW) Addr. (SPort) Addr. (M1) SPort_Data Addr. (M1) (Subport Register Read)
Pirm._Data Addr. (M2)
Prim._Data Address (M3)
(Auxiliary Register Write) Addr. (M2) Addr. (ASW) Aux._Data Addr. (ASW) (Primary Register Read) Addr. (M2) (Primary Register Read) Address (M3)
Addr. (M1) Addr. (ASW) Addr. (SPort) Addr. (M1) Addr. (M1) (Subport Register Write Byte)
Example qFORTH Program Code
(Auxiliary Register Read) Addr. (M2) Addr. (ASW) Addr. (M2) (Auxiliary Register Write Byte) Addr. (M2) Addr. (ASW) Aux._Data (lo) Addr. (M2) Aux._Data (hi) Addr. (M2)
Addr. (M1) Addr. (ASW) Addr. (SPort) Addr. (M1) SPort_Data (lo) Addr. (M1) SPort_Data (hi) Addr. (M1)
(Subport Register Read Byte) Addr. (M1) Addr. (ASW) Addr. (SPort) Addr. (M1) Addr. (M1) Addr. (M1)
(Auxiliary Register Read) Addr. (M1) Addr. (ASW) Addr. (M1)
Addr. (ASW) Auxiliary Switch Module Address Addr. (Mx) Module Address Addr. (SPort) Subport Address Prim._Data data written into Primary Register Aux._Data data written into Auxiliary Register Aux._Data (lo) data written into Auxiliary Register (low nibble) Aux._Data (hi) data written into Auxiliary Register (high nibble) SPort_Data (lo) data written into Subport (low nibble) SPort_Data (hi) data written into Subport (high nibble)
ATAM510
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ATAM510
Table 3-1. Peripheral Addresses
Name P0DAT P1DAT PAIPR Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary PAICR PBIBR PBICR P4DAT P4DDR P5DAT P5DDR P6DAT P6CR P7DAT P7DDR T0SR TCSUB Subport address Auxiliary Auxiliary Auxiliary Auxiliary Auxiliary PADAT PADDR PBDAT PBDDR PCDAT PCDDR ITFSR ITFSR T0MO T0CR T1M0 T1CR TCMO TCIOR TCCR TCIP T1CP T1CA T0CP T0CA BZCR 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b xxxx xxxxb xxxx xxxxb xxxx xxxxb xxxx xxxxb 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b Timer mode register Timer control register Timer mode register Timer control register Timer/counter mode register Timer/counter control register Timer/counter control register Timer/counter interrupt priority Timer compare register (byte) Timer capture register (byte) Timer compare register (byte) Timer capture register (byte) Buzzer control register Reserved Port data register/pin data Port data direction register Port data register/pin data Port data direction register Port data register/pin data Port data direction register Reserved System configuration register Clock management register Interval timer frequency select register Interval timer interrupt priority register Write/Read Reset Value 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 1111b 0011b 1111 1111b 1111b 1111b 1111b 1111b 0000b 1111b Register Function Port data register/input data Port data register/input data Port interrupt priority register Port interrupt control register Watchdog timer reset Port interrupt priority register Port interrupt control register Port data register/pin data Port data direction register Port data register/pin data Port data direction register Port data register/pin data Port control register (byte) Port data register/pin data Port data direction register Auxiliary switch register Data to/from subport addressed TCSUB Timer interrupt status register Timer/counter subport address pointer Module Type Page
Port Address
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Bi-directional Ports
Overview Port 500k none 500k none 500k 500k 500k External interrupt 500k 500k Port monitor/ coded reset 500k Port monitor 500k
Table 3-2.
Port Address Number bits
wise programmable direction Output drivers mask configurable(1) Dynamic pull-up/-down typ. (Ohm)(3) Static pull-up/-down typ. (Ohm)(4) Schmitt trigger inputs
Additional functions Notes:
Timer
Either "open drain down", "open drain CMOS output configuration This output must always CMOS Dynamic pull-up/-down transistors mask programmable programmed, only activated when associated complementary driver transistor off. i.e. dynamic pull transistor only active when port either input mode (both drivers off) when logical written port (low driver off) output mode (Figure page static pull-up/-down transistors mask programmed programmed always active independent port direction driven state (Figure page
further data section Operating Characteristics". Ports with exception Port bits wide. Port data width only bits (bit ports used data input output. ports that either directly indirectly generate interrupt equipped with Schmitt trigger inputs. variety mask options available such open drain, open source full complementary outputs well different types pull-up pull-down transistors. Port Data Registers (PxDAT) mapped primary address register respective port address, Port Data Direction Register (PxDDR) corresponding auxiliary register. bi-directional ports except Port Port include wise programmable Data Direction Register (PxDDR) which allows individual programming each port input output. also possible read condition when output mode. This useful feature selftesting collision detection wired-OR systems. There five different types bi-directional ports: Ports 4-bit wide, bi-directional ports with automatic full width direction switching Port 4-bit wide, wise programmable bi-directional port also provides interface Timer Buzzer Ports 4-bit wide, wise programmable high drive ports Port 2-bit wide, wise programmable bi-directional port with optional static pullup/-down programmable interrupt logic Ports 4-bit wide, wise programmable bi-directional ports with optional port monitor function
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3.2.1 Port Data Register (PxDAT)
Primary register address: 'Port address' PxDAT PxDAT3 PxDAT2 PxDAT1 PxDAT0 Reset value: 1111b
MSB, LSB, Port address 3.2.2 Port Data Direction Register (PxDDR)
Auxiliary register address: 'Port address' PxDDR PxDDR3 PxDDR2 PxDDR1 PxDDR0 Reset value: 1111b
Table 3-3.
Port Data Direction Register (PxDDR)
Function BPx0 input mode BPx0 output mode BPx1 input mode BPx1 output mode BPx2 input mode BPx2 output mode BPx3 input mode BPx3 output mode
Code: xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
3.2.3
Bi-directional Port Port this port type, data direction register independently software programmable because direction complete port switched automatically when instruction occurs (see Figure page 26). port switched output mode with instruction input with instruction. data written port will stored output data latches appears immediately port following instruction. After RESET, output latches ports switched input mode. instruction reads condition associated pins.
Note: Care must taken when switching these bi-directional ports from output input. capacitive loading this port, conjunction with high resistance pull-ups, cause read contents output data register rather than external input state. This avoided using either following programming techniques: instructions DROP first data nibble. first switches port from output input DROP removes first invalid nibble. second reads valid state. instruction followed instruction. With instruction, capacitive load charged discharged depending optional pull-up /pull-down configuration. Write pins with pull-up resistors, pins with pull-down resistors.
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Figure 3-2.
Bi-directional Port
(Data out)
Pull-up
PxDATy Reset (Direction) Master reset
BPxy
Flash options Port only
Pull-down
3.2.4
Bi-directional Port Port Port bi-directional ports except Port Port include wise programmable Data Direction Register (PxDDR) which allows individual programming each port input output. also enables reading condition output mode. bi-directional Ports well Port Port equipped with same standard logic. However, Port Port Port include standard CMOS input stages, whereas Port Port other digital signal pins have Schmitt trigger inputs. Port Port have high current output drive capability Whereby instantaneous output currents should exceed Figure 3-3. Bi-directional Ports
Port Port with Schmitt trigger Pull-up
Static Pull-up
(Data out) Master reset PxDATy
BPxy
PxDDRy
Static Pull-down
Flash options
Pull-down
(Direction)
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3.2.5 Bi-directional Port Port with Port Monitor Function Port Monitor Module Port Port
Connected Ports PxICR ENx3
BPx3 BPx2 BPx1 BPx0
PRx1 PRx2
Figure 3-4.
ENx2
ENx1
ENx0
IMAx
ITRx
PRx1
PRx2
PxIPR Decoder
INT7 INT5 INT3 INT1
INT7 INT5 INT3 INT1
addition standard functions described section "Bi-directional Port Port Port both Port (BPA3 BPA0) Port (BPB3 BPB0) equipped with Schmitt trigger inputs port monitor module. This module connected across four port pins (see Figure 3-4) intended monitoring those pins selected control bits Enx3 Enx0 generating interrupt when first leaves preselected logical default idle state. This state defined control ITRx. Transitions other pins will only cause interrupt other pins have first returned idle state. This, example useful interrupt initiated port scanning without power consuming task continuously polling port activity. Using Port Interrupt Control Register (PxICR), pins individually selected. nonselected cannot generate interrupt. Port Interrupt Priority Register (PxIPR) allows masking each interrupt, definition interrupt edge programming interrupt priority levels. When programming reprogramming either port monitor control registers, previously generated interrupt that port which been acknowledged interrupt generated reprogramming itself automatically cleared. Port also used mask programmable coded reset. more information section "Hardware Reset". Port Interrupt Priority Registers PAIPR PBIPR mapped primary address registers Port Monitor Module addresses '2'h '3'h respectively. Port Interrupt Control Registers PAICR PBICR mapped corresponding auxiliary registers. 3.2.5.1 Port Monitor Interrupt Priority Register (PxIPR)
(Port (Port (Port Primary register address: '2'hex (Port Primary register address: '3'hex PxIPR ITRx PRx2.1 ITRx PRx2 PRx1 Reset value: 1111b
Interrupt Mask Interrupt Transition Interrupt Priority code
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Table 3-4.
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 0xxx 1xxx
Port Monitor Interrupt Priority Register (PxIPR)
Function Port monitor interrupt priority Port monitor interrupt priority Port monitor interrupt priority Port monitor interrupt priority Port monitor interrupt falling edge Port monitor interrupt rising edge Port monitor interrupt enabled Port monitor interrupt disabled
3.2.5.2
Port Monitor Interrupt Control Register (PxICR)
(Port (Port (Port Primary register address: '2'hex (Port Primary register address: '3'hex PxICR ENx3 ENx2 ENx1 ENx0 Reset value: 1111b
ENx3. port monitor input ENable code
Table 3-5.
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Port Monitor Interrupt Control Register (PxICR)
Function generate interrupt cannot generate interrupt generate interrupt cannot generate interrupt generate interrupt cannot generate interrupt generate interrupt cannot generate interrupt
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3.2.6 Bi-directional Port Figure 3-5. Bi-directional Port
Pull-up
Strong Static Pull-up
(Data out) P6DATy Master reset enable
BP6y
Strong Static Pull-down
Flash options
Pull-down
This 2-bit bi-directional port used wise programmable I/O. data aligned that MSB's will appear port pins when written. port pins also used external interrupt inputs (see Figure Figure page 31). Both interrupts masked independently configured trigger either edge. interrupt priority levels also configurable. interrupt configuration port direction controlled Port Control Register (P6CR). additional resistance pull-up transistor (flash option) provides internal pull-up serial applications. output mode (PxDDR respective Port Data Register (PxDAT) appears port pin, driven output port driver stage which mask programmed open drain, full complementary CMOS. With instruction actual state read back into controller time without changing port directional mode. output port flash configured open drain driver, controller able receive external data this without switching into input mode long output transistor switched off. input mode (PxDDR output driver stage deactivated, that instruction will directly read state which driven from external source. this case, state Port Data Register (PxDAT), although appearing itself, remains unchanged. High resistance mask selectable pull-up pull-down transistors automatically switched onto port input mode. Port Data Register written respective port address with instruction. Port Data Register (P6DAT) mapped primary address register address '6'hex Port Control Register (P6CR) corresponding auxiliary register. P6CR byte wide register written writing nibble first then high nibble (see section "Addressing peripherals").
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3.2.6.1
Port Data Register (P6DAT)
Primary register address: '6'hex P6DAT used used P6DAT1 P6DAT0 Reset value: xx11b
unused bits read. 3.2.6.2 Port Control Register (P6CR)
Auxiliary register address: '6'hex P6CR First write cycle P61IM2 Second write P61PR2 cycle P61IM1 P61PR1 P60IM2 P60PR2 P60IM1 P60PR1 Reset value: 1111b Reset value: 1111b
P6xIM2, P6xIM1 Port interrupt mode/direction code P6xPR2, P6xPR1 BP6x interrupt priority code
Table 3-6.
Port Control Register (P6CR)
Auxiliary Address: '6'hex First Write Cycle Second Write Cycle Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx Function BP60 priority BP60 priority BP60 priority BP60 priority BP61 priority BP61 priority BP61 priority BP61 priority
Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx
Function BP60 input mode interrupt disabled BP60 input mode rising edge interrupt BP60 input mode falling edge interrupt BP60 output mode interrupt disabled BP61 input mode interrupt disabled BP61 input mode rising edge interrupt BP61 input mode falling edge interrupt BP61 output mode interrupt disabled
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Figure 3-6. Port External Interrupts
INT6
Mask
INT4 INT2 INT0
Edge Data Dir. Edge Data Dir. BP60 BP61
Bidir. Port
IN_Enable
INT7 INT5 INT3 INT1
Mask
Bidir. Port
IN_Enable
decode P6CR:
decode
decode
decode
INT6 INT4 INT2 INT0 INT7 INT5 INT3 INT1
Dir.
edge
disabled
3.2.7
Bi-directional Port bi-directional Port both wise configurable port provides external pins both Timer internal buzzer generator. port, performs exactly same bi-directional Port (see Figure page 26). additional multiplexers allow data port direction control passed over other internal modules (Timer Buzzer). Each four Port pins individually switched Timer/Counter Register (TCIO). Figure shows internal interfaces Port Bi-directional Port
T0In T0Out P4DATy Master reset (Direction) Pull-down Flash options
Figure 3-7.
Pull-up
TCIOy
Static Pull-up
BP4y
(Data out)
Static Pull-down
P4DDRy TDir
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3.2.8
TIM1 Dedicated Timer Figure 3-8. Bi-directional TIM1
T1IN (Timer input) Pull-up
T1OUT (Timer output)
TIM1
T1Dir (direction control)
Flash
options
Pull-down
TIM1 dedicated bi-directional stage signal communication from Timer timer/counter module (see Figure 3-8). interface directly accessible from CPU. Direction control performed from timer/counter configuration registers.
Interval Timers/Prescaler
interval timers based frequency divider generating independent time base interrupts. driven SUBCL generated clock module (see Figure page consists 15-stage binary divider programmable multiplexers selecting appropriate interrupt frequencies each interrupt source (see Figure page 33). Each multiplexer completely independent controlled common Interval Timer Frequency Select Register (ITFSR). Buffer registers store respective frequency select codes ensure complete programming independence each interrupt channel. Interrupt masking programming interrupt priority levels performed with Interval Timer Interrupt Priority Register (ITIPR).
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Figure 3-9. Interval Timers/Prescaler
ITIPR INT5 INT1
Buffer Buffer
ITFSR
INT6 INT2
INTB
8092 2048 4096
8192 4096 2048 1024
INTA
1024
SUBCL
(e.g. SUBCL kHz)
15-stage binary counter
3.3.1
Interval Timer Registers Interval Timer Frequency Select Register (ITFSR) mapped primary address register prescaler/interval timer address ('F'hex) Interval Timer Interrupt Priority Register (ITIPR) corresponding auxiliary register. interrupt masks enable interrupt masking INTA INTB respectively. Each interrupt source programmed with interrupt priority levels. Disabling both interrupts resets interval timer. Interval Timer Interrupt Priority Register (ITIPR)
Auxiliary register address (write only): 'F'hex ITIPR Reset value: 1111b
3.3.1.1
Priority select Interval Timer Interrupt INTB
Priority select Interval Timer Interrupt INTA Mask Interval Timer Interrupt INTB Mask Interval Timer Interrupt INTA
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Table 3-7.
Code 3210 xx11 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Interval Timer Interrupt Priority Register (ITIPR)
Function Reset prescaler halt Interrupt disabled Interrupt enabled Interrupt disabled Interrupt enabled Interrupt priority Interrupt priority Interrupt priority Interrupt priority
3.3.1.2
Interval Timer Frequency Select Register
Primary register address (write only): 'F'hex ITFSR Reset value: 1111b
Frequency select code
Table 3-8.
Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Interval Timer Frequency Select Register (ITFSR)
Function SUBCL divide
SUBCL Select Select Select Select Select Select Select Select Select Select Select Select Select 1024 Select 2048 Select 4096 Select 8192
INTA
INTB
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control determines whether INTA INTB buffer register loaded with select code (FS2-FS0). This allows independent programming interval times INTA INTB.
Watchdog Timer
Figure 3-10. Watchdog Timer
NRST
17-stage binary counter SUBCL Read WDRES Master Reset
Watchdog enable
Configurable option
watchdog timer 17-stage binary divider clocked SUBCL generated within clock module (see Figure page Figure 3-10 page 35). only enabled configurable option whereby must periodically reset from application program. program cannot disable watchdog. finds itself extended length time SLEEP mode section program that includes watchdog reset, then watchdog will overflow, thus forcing NRST low. This initiates master reset. timeout period 0.5, seconds SUBCL kHz) using configurable option. reset watchdog, program must perform IN-instruction address ('3'hex). relevant data usually received. operation therefore normally followed DROP flush data from stack.
Timer/Counter Module (TCM)
consists timer/counter blocks (Timer Timer which used separately, together single 16-bit counter/timer (see Figure 3-11 page Figure 3-13 page 40). Each timer supplied various internal external clock sources. These selected divided under program control using Timer/Counter Control Register (TCCR), Timer Control Register (T0CR) Timer Control Register (T1CR). Capture compare registers (T0CA,T1CA,T0CP T1CP) only allow event counting, also generation various timed output waveforms including programmable frequencies, modulated melody tones, Pulse Width Modulated (PWM) Pulse Density Modulated (PDM) output signals. When these signal generation modes, capture register acts timer shadow register, current timer state frozen whenever read CPU. Timer further equipped perform variety time measurement operations. this mode capture register used together with gating logic performing asynchronous, externally triggered snapshot measurements. These measurements include single input pulse width period measurements also dual input phase positional measurements. mode configuration Timer Timer Mode Registers (T0MO T1MO).
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Each timer represents single maskable interrupt source (T0INT T1INT), priority which configured under program control. Timer interrupt caused three conditions (overflow, compare end-of-measurement). associated status register (T0SR) differentiates between these. status register necessary Timer interrupt caused only compare condition. Figure 3-11. Timer/Counter Module
T0IN1 T0IN0 SYSCL SUBCL Prescaler Capture register Gating control up/down T0CA T0SR
Timer
Status register
Clock control reset
up/down counter
overflow
end-ofmeasurement
Reload control
Compare
T0OUT1 T0CP Compare register Int. enable Output control T0OUT0 T0CR T0MO T0INT
T1OUT TCCR TCMO T0OUT0
16-bit mode T1CR T1MO
Int. enable Compare register T1CP carr T1INT Output control T1OUT
Reload control reset
Compare
Clock control
up/down counter
overflow
SUBCL SYSCL T1IN
Prescaler
T1CA Capture register
Timer
Read/write registers
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3.5.1 General Timer/Counter Control Registers With exception Timer Interrupt Status Register (T0SR), timer/counter registers indirectly addressed using extended addressing described section "Addressing Peripherals". overview register subport addresses shown Table page Timer/Counter auxiliary register (TCSUB) holds subport address particular register about accessed. Care taken ensure that this subport access sequence interrupted. Please refer "HARDC510.SCR" hardware interface file programming guideline. 3.5.1.1 Timer/Counter Clock Control Register (TCCR)
Subport address (indirect write access): '6'hex Port address '9'hex TCCR T1CL2 T1CL1 T0CL2 T0CL1 Reset value: 1111b
T0CL2, T0CL1 Timer Clock source select T1CL2, T1CL1 Timer Clock source select
Table 3-9.
Code 3210 xx00 xx01 xx10 xx11 00xx 01xx 10xx 11xx Note:
Timer/Counter Clock Control Register (TCCR)
Function Timer clock SUBCL Timer clock SYSCL Timer clock Timer1 output (T1OUT connected internally) Timer clock T0IN0 (BP40 Timer clock SUBCL Timer clock SYSCL Timer clock Timer output (T0OUT0 connected internally) Timer clock TIM1
Direction (TDir) BP40(1) TIM1
TCIO0 (connects Timer Port
Timer/Counter Clock Control Register (TCCR) controls clock source both Timer Timer prescalers. external clock source BP40 TIM1) selected, then corresponding port direction automatically switched input mode (see Figure 3-11 page 36).
Note: TCIO0 must BP40 external timer/counter access.
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3.5.1.2
Timer/Counter Interrupt Priority Register (TCIP) Timer/Counter Interrupt Priority register (TCIP) used configure Timer Timer interrupt priority levels.
Subport address (indirect write access): '7'hex Port address '9'hex TCIP T1IP2 T1IP1 T0IP2 T0IP1 Reset value: 1111b
T0IP2, T0IP1 Timer Interrupt Priority code T1IP2, T1IP1 Timer Interrupt Priority code
Table 3-10.
Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx
Timer/Counter Interrupt Priority Register (TCIP)
Function Timer interrupt priority Timer interrupt priority Timer interrupt priority Timer interrupt priority Timer interrupt priority Timer interrupt priority Timer interrupt priority Timer interrupt priority
3.5.1.3
Timer/Counter Control Register (TCIOR)
Subport address (indirect write access): '5'hex Port address '9'hex TCIOR TCIO3 TCIO2 TCIO1 TCIO0 Reset value: 1111b
TCIO3.0 Timer/Counter mode select
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Table 3-11.
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Timer/Counter Control Register (TCIOR)
Function BP40 standard port mode BP40 Timer clock input (T0IN0) Timer output (T0OUT0) BP41 standard port mode BP41 Timer gate input (T0IN1) Timer output (T0OUT1) BP42 standard port mode BP42 Buzzer output (BUZ) BP43 standard port mode BP43 Buzzer output (NBUZ)
using Timer/Counter Control Register (TCIOR) program configure respective Port pins either standard data ports external signal ports Timer Buzzer. Timer uses dedicated TIM1, whose direction controlled solely TCCR (see Figure 3-12). should noted that TCIOR low, then corresponding port data direction register (P4DDR) longer influences port direction. case BP40 BP41, port direction then controlled entirely timer/counter configuration registers (TCCR,T0MO), while pins BP42 BP43 become uni-directional buzzer outputs. Figure 3-12. Timer/Counter Buzzer External Interface
TIMER
T0IN0
P4DAT0
T0OUT0
BP40
TCIO0 TCCR
Select Ext. Clock
T0IN1
P4DDR0
P4DAT1
T0OUT1
BP41
T0MO PWM,PDM
Melody,Counter
TCIO1 P4DDR1 P4DAT2
BUZZER
BP42
TCIO2 P4DDR2
P4DAT3
NBUZ
BP43
TCIO3 P4DDR3
TIMER
T1IN T1OUT
TIM1
TCCR
Select Ext. Clock
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3.5.1.4
Timer/Counter Mode Register (TCMO)
Subport address (indirect write access): '4'hex Port address '9'hex TCMO T0NINV T1STP T0STP T0NINV T1RST T0RST Reset value: 1111b
Timer output (BP41) appears non-inverted BP40 Timer/Counter 8-/16-bit mode Timer Stop/Run Timer Stop/Run
Table 3-12.
Code 3210 xxx0 xxx1 xx0x xx1x x0xx x1xx 0xxx 1xxx
Timer/Counter Mode Register (TCMO)
Function Timer running Timer halted Timer running Timer halted Timer/counter 16-bit mode Timer/counter 8-bit mode Inverted output BP41 appears BP40 (BP40 BP41) Non-inverted output BP41 appears BP40 (BP40 BP41)
3.5.2
Timer/Counter 16-bit Mode Figure 3-13. 16-bit Mode
Compare Register
Timer
Compare Register
Timer
Comparator
Carry 8bit/16bit
Comparator
Compare Interrupt
Prescaler
Counter
Prescaler
Counter
TIM1
Overflow/compare
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16-bit mode, Timer Timer cascaded thus forming 16-bit counter (see Figure 313) whereby, irrespective state Timer interrupt mask (T0IM), Timer counts both Timer overflow compares interrupt events. These generated according state Timer Mode Register described T0MO table. comparators also cascaded that when both Timer Timer match their respective compare registers, Timer generates both output signal compare interrupt unmasked). measurement modes, only Timer capture register loaded with Timer contents end-of-measurement event. Timer capture register operates solely shadow register. There 16-bit capture operation, user program must check Timer incremented between reading lower higher byte. Likewise, there automatic suppression spurious interrupts which could conceivably generated between writing Timer Timer compare registers. 3.5.3 Timer Modes Timer mode configuration defined Timer Mode Register (T0MO). available modes effect Timer interrupt interrupt flags shown below. modes except position measurement mode, Timer acts up-counter, related clock frequency being defined selected clock source prescaler division factor. counter reset halted time T0RST TCMO register which also resets interrupt status flags capture registers. Whenever Port BP40 BP41 pins required Timer I/O, then appropriate TCIOR enable must low. this case, port direction switching handled automatically hardware. modes where BP40 used timer clock input melody envelope output, BP40 outputs same signal that appearing BP41. With help T0NINV Timer/Counter Mode Register (TCMO), BP41 output inverted that BP40 BP41 form differential output stage which used directly driving piezo buzzers small stepper motors. 3.5.3.1 Timer Mode Register (T0MO)
Subport address (indirect write access): '0'hex Port address '9'hex T0MO T0MO3 T0MO2 T0MO1 T0MO0 Reset value: 1111b
T0MO3 Timer Mode Code
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Table 3-13.
Code 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Notes:
Timer Mode Register (T0MO)
Assuming TCIOR1 TCIOR0 BP40 BP41 Envelope (out) Tone (out) Toggle (out)/Clock (in) Toggle (out)/Clock (in) (out)/Clock (in) (out)/Clock (in) Signal (in) Signal (in) Clock (in) Clock (in) Strobe (out)/Clock (in) Strobe (out)/Clock (in) Clock (in) Tone (out) Tone (out) Toggle (out) Toggle (out) (out) (out) Signal (in) Signal (in) Signal (in) Signal (in) Strobe (out) Strobe (out) Signal (in) Interrupt Set/ T0SR Affected
Function Reserved Reserved Modulated melody mode Melody mode Counter-auto reload (50% duty cycle) Counter-free running (50% duty cycle) Pulse density modulation Pulse width modulation Phase measurement Position measurement pulse width measurement High pulse width measurement Counter-auto reload (strobe) Counter-free running (strobe) Period measurement (rising edge)
Period measurement (falling edge) Clock (in) Signal (in) compare interrupt/status flag only when counting overflow interrupt/status flag both overflow underflow BP40 signals inverted T0NINV=0 (TCMO register)
3.5.3.2
Timer Interrupt Status Register (T0SR)
Auxiliary register address (read access): '9'hex T0SR used T0EOM T0OFL T0CMP Reset value: x000b
Note: status register reset automatically when read also when Timer reset. T0EOM Timer Measurement status flag T0OFL T0CMP Timer OverFLow status flag Timer CoMPare status flag
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Table 3-14.
Code 3210 xxx1 xx1x x1xx
Timer Interrupt Status Register (T0SR)
Function Timer compare occurred (Timer T0CP) Timer overflow underflow occurred Timer measurement completed
interrupt flags will whenever associated condition occurs irrespective whether corresponding interrupt triggered. Therefore, status flags still interrupt condition occurs when interrupt masked. exactly when flags set, T0MO control code, Table 3-13 page Reading from timer/counter auxiliary register will access Timer Interrupt Status Register (T0SR). 3.5.3.3 Timer Control Register (T0CR) T0CR responsible predivision selected Timer input clock (see TCCR). divided used directly clock up/down counter. mask Timer interrupt.
Subport address (indirect write access): '1'hex Port address '9'hex T0CR T0FS3 T0IM T0FS3 T0FS2 T0FS1 T0IM Reset value: 1111b
Timer prescaler division factor code Timer Interrupt Mask
Table 3-15.
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x
Timer Control Register (T0CR)
Function Timer interrupt disabled Timer interrupt enabled Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler bypassed
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3.5.3.4
Timer Compare Register (T0CP) Byte Write
Subport address (indirect read access): '9'hex Port address '9'hex T0CP First write cycle T0CP3 Second write T0CP7 cycle T0CP2 T0CP6 T0CP1 T0CP5 T0CP0 T0CP4 Reset value: xxxxb Reset value: xxxxb
T0CP3 T0CP0 Timer Compare Register Data (low nibble) first write cycle T0CP7 T0CP4 Timer Compare Register Data (high nibble) second write cycle compare register T0CP 8-bit wide must accessed byte wide subport (see section "Addressing Peripherals"). First, nibble data written then followed high nibble. timer interrupts automatically suppressed until complete compare value been transferred. 3.5.3.5 Timer Capture Register (T0CA) Byte Read
Subport address (indirect read access): '9'hex Port address '9'hex T0CA First write cycle T0CA7 Second write T0CA3 cycle T0CA6 T0CA2 T0CA5 T0CA1 T0CA4 T0CA0 Reset value: xxxxb Reset value: xxxxb
T0CA7. T0CA4 Timer Capture Register Data (high nibble) first read cycle T0CA3 T0CA0 Timer Capture Register Data (low nibble) second read cycle
Note: timer read mode only) order will appear reversed, that T0CA0 MSB, T0CA1 T0CA6 T0CA7 LSB.
8-bit capture register T0CA read byte wide subport. Note, however, unlike writing compare register, high nibble read first followed nibble. 8-bit timer state captured reading first nibble held until complete byte been read. During this transfer, timer free continue counting. 3.5.3.6 Timer Free Running Counter Modes (Strobe Duty Cycle) free running counter mode, Timer used event counter summing external event pulses BP40, timer with internal time-based clock. When enabled, counter will count generating output signal BP41 whenever counter contents match compare register (see Figure 3-14 page 45). This signal appear either strobe pulse simple toggling output state (50% duty cycle) depending timer mode. Interrupts masked) generated every clocks overflow condition. current counter state read time reading capture register,. compare register effect counter cycle time will influence interrupts.
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Figure 3-14. Timer Free Running Counter Mode
Timer State Overflow Interrupt
strobe
T0OUT1 (BP41)
duty cycle
Timer Clock Timer resets overflow Timer compare register
3.5.3.7
Timer Counter Reload Modes (Strobe Duty Cycle) free running mode, counter also clocked from either external signal BP40 from internal clock source. this mode, counter repetition period completely defined contents compare register (T0CP) (see Figure 3-15). counter counts with selected clock frequency. When reaches value held compare register, counter then returns zero state. same time, depending selected timer mode, BP41 either toggles generates strobe pulse. Timer interrupt unmasked, compare interrupt also generated. resultant output frequency fOUT fIN/2 (n+1) where compare value 255).
Figure 3-15. Timer Counter Reload Mode
Timer State Compare Interrupt
strobe
T0OUT1 (BP41)
duty cycle
Timer Clock
Timer compare register Resets timer
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3.5.3.8
Melody Mode (with/without Modulation) non-modulated melody mode identical auto-reload counter (50% duty cycle) mode. melody tone frequency appearing BP41 and/or BP40 determined exactly same value written into comparator register. modulated melody mode, ATAM510 generates output signals, melody tone envelope pulse (see Figure 316). tone frequency output BP41 generated exactly same simple melody mode. While envelope pulse BP40 single pulse clock period duration which appears shortly after loading compare value into compare register. this mode, analog switch activated between BP40 BP41 outputs (see Figure 3-17). With external capacitor connected, resultant signal BP41 exhibits melody chime effect with exponential decay.
Figure 3-16. Modulated Melody Mode
Timer State Compare Interrupt T0OUT1 (BP41) T0OUT0 (BP40) Timer Clock
value loaded into compare register
Timer compare register resets timer
Figure 3-17. Modulated Melody Output Circuit
T0OUT0 (melody output) Modulated melody mode T0OUT1 (envelope) T0OUT1 Analog switch BP40
(optional)
10.47
Piezo buzzer
BP41
T0OUT0 BP41 BP40
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3.5.3.9 Timer Pulse Width Modulation Mode pulse width modulated (PWM) signal exhibits fixed repetition frequency variable mark space ratio. often used simple method conversion, where high period proportional digital value converted. Therefore connecting simple low-pass network signal, analog value retrieved. Timer generates signal comparing state free running counter with contents compare register (see Figure 3-18). result less than compare register value, then BP41 output high. result greater equal compare register value, then BP41 output low. Thus, high phase signal directly proportional compare register contents. total possible discrete mark space ratios generated ranging from continuous signal over variable pulse width signal continuous high signal. signal repetition period clocks, interrupt unmasked) being generated every overflow event. Care should taken SYSCL clock used clock source because stop goes into SLEEP mode (see section "Power-Down Modes"). Figure 3-18. Timer Pulse Width Modulation
Timer State Overflow Interrupt t_hi T0OUT1 (BP41) Timer Clock Timer compare register t_hi (comparator value) clock period t_low (255-comparator value) clock period t_low
3.5.3.10
Pulse Density Modulation Mode Pulse density modulation (PDM) also used simple conversion. Unlike signal where high signal phases always continuous during single repetition cycle, distributes these evenly series pulses (see Figure 3-19 page 48). This advantage that, used together with smoothing filter conversion, either ripple less than PWM, corresponding ripple error, filter components smaller clock frequency lower. generate output BP41, pulse density controlled contents compare register same generation. Each pulses width equal counter clock period.
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Figure 3-19. Example 4-bit PWM/PDM Comparison
Repetition period 0.25
0.75
0.25
0.75
3.5.3.11
Period Measurement Modes (Rising Falling Edge) During period measurement mode, counter counts number either internal external clocks period BP41 input signal (see Figure 3-20). Depending mode chosen, this will from rising edge next rising edge conversely, falling edge following falling edge. trigger edge, counter state loaded into capture register subsequently reset. measured value remains capture register until overwritten following measured value. Interrupts generated either overflow condition end-of-measurement (EOM) event. event signals that measured value present capture register read, required.
Figure 3-20. Period Measurement
Captures resets timer
Interrupt
t_period t_period
T0IN1 (BP41)
Falling edge triggered
Rising edge triggered
3.5.3.12
Pulse Width Measurement Modes (High Low) this mode, selected clock source gated counter duration each input pulse received BP41 (see Figure 3-21 page 49). Whether measurement takes place during high phase depends selected mode. each pulse, counter state loaded into capture register subsequently reset. Interrupts generated either overflow condition end-of-measurement (EOM) event. event signals that measured value present capture register read required.
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Figure 3-21. Pulse Width Measurement
Captures resets timer "eom" Interrupt t_low T0IN1 (BP41) t_high
3.5.3.13
Phase Measurement Mode This mode allows Timer measure phase misalignment between mark space ratio input signals connected BP40 BP41 pins (see Figure 3-22). counter clock gated with phase misalignment period (tp), during which time counter increments with selected clock frequency. This misalignment period defined period during which BP40 high BP41 low. Capturing resetting counter always takes place rising edge BP41. measured value remains capture register until overwritten next measurement. Interrupts generated either overflow condition end-ofmeasurement (EOM) event. event signals that measured value present capture register read, required.
Figure 3-22. Phase Measurement
Captures resets timer
Interrupt
T0IN0 (BP40) T0IN1 (BP41)
3.5.3.14
Position Measurement Mode This mode intended evaluation positional sensors with bi-phase output signals. Figure 3-23 page illustrates typical positional sensor system which delivers both incremental positional stepping signals also directional information. direction deduced from relative phase signals. Therefore BP40 high rising edge BP41, moving mask travels left then travels right. direction (left/right) information used direction up/down counter which enables BP40 pulses counted. Assuming that system been reset reference position, counter will always hold absolute current position moving mask. This read necessary. This mode only which counter allowed decrement. Therefore, this case possible both underflow overflow occur. overflow interrupt unmasked) will trigger either these conditions while compare interrupt other hand will only trigger counter counting upwards. differentiate between overflow underflow, compare value hex, example.
4711B-4BMCU-01/05
overflow would then both overflow compare status flags while underflow sets overflow status flag only. Figure 3-23. Position Measurement Mode
T0IN0 T0IN1
Typical sensor
light left movement light right movement
Moving mask Static mask
Timer T0IN0 (BP40) T0IN1 (BP41)
3.5.4
Timer Modes Timer meant perform event counting timing functions (see Figure 3-11 page 36). has, unlike Timer gated clock externally triggered capture modes. counter counts with internal external clock, depending state Timer Control Register (T1CR) Timer/Counter Clock Control Register (TCCR) generates compare interrupt whenever counter matches Timer compare register. This only Timer interrupt source. Masking performed using mask Timer Control Register (T1CR) priority defined Timer/Counter Interrupt Priority Register (TCIP). TIM1 used Timer either clock/event input timer output. control Timer TIM1 controlled entirely hardware, therefore TIM1 selected external clock event source TCCR), there Timer signal output. this case, timer would used solely generate interrupts. autostop operation, Timer will halt both itself Timer whenever Timer compare value reached. This feature used example generate exact burst pulses. Both timers will remain stopped until restarted. Restarting performed normal setting appropriate control bits Timer/Counter Mode Register (TCM0).
3.5.4.1
Timer Mode Register (T1MO)
Subport address (indirect write access): '2'hex Port address '9'hex T1MO T1MO3 T1MO2 T1MO1 T1MO0 Reset value: 1111b
T1MO3 Timer Mode Code
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Table 3-16.
Code 3210 xx00 xx01 xx10 xx11 x0xx x1xx 1xxx 0xxx
Timer Mode Register (T1MO)
Function Counter free running (50% duty cycle) Counter auto reload (50% duty cycle) Pulse width modulation Counter auto-reload (strobe output) Increment falling edge clock Increment rising edge clock Normal operation autostop) Autostop operation (Timer stops Timer Compare Interrupt
3.5.4.2
Timer Control Register (T1CR) T1CR responsible predivision selected Timer input clock (see TCCR). divided used directly clock counter. mask Timer interrupt.
Subport address (indirect write access): '3'hex Port address '9'hex T1CR T1FS3 T1IM T1FS3 T1FS2 T1FS1 T1IM Reset value: 1111b
Timer Prescaler Division Factor Code Timer Interrupt Mask
Table 3-17.
Code 3210 xxx1 xxx0 000x 001x 010x 011x 100x 101x 110x 111x
Timer Control Register (T1CR)
Function Timer interrupt disabled Timer interrupt enabled Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler divide Timer prescaler bypassed
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3.5.4.3
Timer Compare Register (T1CP) Byte Write
Subport address (indirect read access): '8'hex Port address '9'hex T1CP First write cycle T1CP3 Second write T1CP7 cycle T1CP2 T1CP6 T1CP1 T1CP5 T1CP0 T1CP4 Reset value: xxxxb Reset value: xxxxb
T1CP3 T1CP0 Timer Compare Register Data (low nibble) first write cycle T1CP7 T1CP4 Timer Compare Register Data (high nibble) second write cycle compare register T1CP bits wide must accessed byte wide subport (see section "Addressing Peripherals"). data written nibble first, followed high nibble. timer interrupts automatically suppressed until complete compare value been transferred. 3.5.4.4 Timer Capture Register (T1CA) Byte Read
Subport address (indirect read access): '8'hex Port address '9'hex T1CA First write cycle T1CA7 Second write T1CA3 cycle T1CA6 T1CA2 T1CA5 T1CA1 T1CA4 T1CA0 Reset value: xxxxb Reset value: xxxxb
T1CA7. T1CA4 Timer Capture Register Data (high nibble) first read cycle T1CA3 T1CA0 Timer Capture Register Data (low nibble) second read cycle 8-bit capture register T1CA read byte wide subport. Note, however, unlike writing compare register, high nibble read first followed nibble. 8-bit timer state captured reading first nibble held until complete byte been read. During this transfer, timer free continue counting. previous capture value will held until timer restarted again.
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3.5.4.5 Timer Counter Free Running (50% Duty Cycle) free running counter mode, counter counts with either internal external clock cycles through timer states. clock following match between compare register (T1CR) counter, compare interrupt unmasked) generated TIM1 toggled (see Figure 3-23 page 50).
Figure 3-24. Timer Counter Free Running (50% Duty Cycle)
Timer State Compare Interrupt T1OUT (TIM1)
duty cycle
Timer Clock
(clock rising edge)
Timer compare register
3.5.4.6
Timer Counter Auto Reload (Strobe Duty Cycle) auto-reload mode, counter counts with either internal external clock. clock cycle following match between compare register (T1CR) counter, compare interrupt unmasked) generated. TIM1 output either strobed toggled counter reset (see Figure 3-25). Therefore, counter cycle period defined contents compare register. duty cycle mode frequency TIM1 fTIM1 fin/2(n+1) where compare value
Figure 3-25. Timer Counter Auto Reload
Timer State Compare Interrupt strobe T1OUT (TIM1) duty cycle Timer Clock
(clock neg. edge) Timer compare register Resets timer
4711B-4BMCU-01/05
3.5.4.7
Timer Pulse Width Modulation Timer generates signal comparing state free running counter with contents compare register (see Figure 3-26). result less equal compare register value, then TIM1 output high. result greater than compare register value, then TIM1 output low. Thus, high phase signal directly proportional compare register contents. total possible discrete mark space ratios generated ranging from continuous signal over variable pulse width signal. signal repetition period clock periods, interrupt unmasked) being generated every compare event. Care should taken SYSCL used clock source. output stop goes into SLEEP mode depending programming NSTOP CMregister. using this mode operation recommended NSTOP
Figure 3-26. Timer Pulse Width Modulation
Timer State
Compare Interrupt t_hi T1OUT (TIM1) Timer Clock t_hi (comparator value) clock period t_low (256-comparator value) clock period Timer compare register t_low
ATAM510
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Buzzer Module
buzzer stage frequency divider which divides SUBCL depending state Buzzer Control Register (BZCR) output four frequencies. external piezo buzzer driven complementary buzzer outputs (BUZ NBUZ) which directed Port (BP42 BP43) under control Timer/Counter Register (TCIOR) shown Figure 3-11 page When buzzer switched off, both buzzer outputs take same logical state. This controlled BZOP BZCR. Figure 3-27. Buzzer Module
BZCR
BZFS2 BZFS1 BZOP BZOF
NBUZ
SUBCL kHz) SUBCL/4 kHz) SUBCL/8 kHz) SUBCL/16 kHz)
SUBCL
stage divider
3.6.0.8
Buzzer Control Register (BZCR)
Subport address (indirect write access): 'A'hex Port address '9'hex BZCR BZFS2,BZFS2 BZOP BZOF BZFS2 BZFS1 BZOP BZOF Reset value: 1111b
Buzzer Frequency Select code Buzzer Output Stop State Buzzer off/on
4711B-4BMCU-01/05
Table 3-18.
Code 3210 xxx0 xxx1 xx0x xx1x 00xx 01xx 10xx 11xx
Buzzer Control Register (BZCR)
Function Buzzer Buzzer Buzzer output stop state: BP42 BP43 Buzzer output stop state: BP42 BP43 high Buzzer frequency: SUBCL) Buzzer frequency: SUBCL/4) Buzzer frequency: SUBCL/8) Buzzer frequency: SUBCL/16)
Figure 3-28. Buzzer Waveform
BZOP
NBUZ BUZZER
BZOP NBUZ
Programming
Figure 3-29. Programmer System
In-Circuit Programmer (ICP) Target Programmer Interface (TPI)
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accommodate application program associated hardware option configuration, ATAM510 equipped with on-chip EEPROM memory blocks. These written 6-signal Target Programmer Interface (TPI), comprising power lines (VDD VSS), Program Mode signal (PM) data lines which multiplexed onto ATAM510 functional pins BP00, BP01 BP02 (see Figure page 63). required hardware options download these along with application program into ATAM510, customer supplied with dedicated based programmer software operating under Windows 95/98 Windows In-Circuit Programmer unit (ICP). connected standard serial interface port target device application board (for in-system programming) flat band cable.
Table 3-19.
Target Programmer Interface Signals
Name BP02 BP01 BP00 ATAM510 Function Programming mode Input Supply Port02 (Clock) input Port01 (Data) input Port00 (Data) output Ground Supply connected connected connected connected
Connector
state ATAM510 defines operational mode i.e. high (Program Mode), (Normal operation Mode) while data lines used serially load read customer's data into ATAM510. 3.7.1 Application Program Programmer software requires only customer's binary *.hex file which generated MARC4 program compiler also provides primary data base emulation. This displayed screen editable hexadecimal memory map. Contents already programmed device read back displayed same hex. form provided that device's "Read Lock" been set. "Read Lock" Protected device, read will appear full hex. Hardware Configuration hardware configurations within software's intuitive user interface selecting required options from masks provided. available configurable hardware options similar those ATAR510 (see "Hardware Options" section). These affect primarily port configurations, watchdog coded reset settings. port driver strengths, although mask programmable ATAR510 configurable MTP, output drivers being internally "hardwired" default "standard drive" strength.
3.7.2
4711B-4BMCU-01/05
3.7.3
Read Lock Protection programmer software incorporates called "Read Lock" which user. This provided customer security purposes inhibits reading customer's Application Program unauthorized persons. set, "Read Lock" sets hardware EEPROM which disables reading Program/Configuration data. should noted that this "Read Lock" "Write Lock", even lock set, still possible overwrite customer data with program code. In-System Programming "in-system programming", application circuit board must fitted with 10-pin male connector accommodate connector. ensure conflict-free access target ATAM510 related pins (BP00, BP01, BP02 recommended that these equipped with jumpers (J5, avoid signal contention with other board driver sources. (see Figure page 63). However, these overdriven, Port used application, then jumpers omitted replaced isolating resistors. Prior connecting TPI, other application power supply sources should disconnected from application circuit board. Should other board components either present excessive power supply load unable withstand 5-Volt supply voltage, then power line should also jumpered (J2). During programming operation ports into input mode, with previously programmed pull-up/pull-down transistors deactivated. normal operational mode, strapped ground Port reverts port function described section "Bi-directional Port Port
3.7.4
Figure 3-30. In-System Programming
BP53 BP52 BP51 BP50 BP43 BP42 BP41 BP40 BP03 BP02 BP01 BP00 TIM1 BPC1 BPC0 BP13 BP12 BP11 BP10
BP70 BP71 BP72 BP73 SCLIN BP61 BP60 BPB3
Programmer interface
ATAM510
Application:
BP00
BP01
BP02
BPB2 BPB1 BPB0 BPC3 BPC2 AVDD OSCIN OSCOUT NRST BPA0 BPA1 BPA2 BPA3
*Optional jumpers
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Noise Considerations
When designing microcontroller based application, several factors should taken into consideration increase noise immunity reduce electromagnetic emissions (EME). Many such potential problems avoided careful layout printed circuit board (PCB). contains many parasitic components which first sight apparent. tracks antennas coupling capacitors. Long stretches parallel tracks long high frequency signal lines should thus avoided wherever possible minimize chance picking transmitting unwanted signals. 3.8.1 Noise Immunity following guidelines will increase system noise immunity: Unconnected inputs should left open. port pins required then recommended pull-up pull-down options these pins. Special care should taken when laying that interrupt, reset clock signal lines kept short carefully shielded have sufficient spacing from other board noise generating sources. quartz crystal should always located right next microcontroller crystal oscillator terminals (OSCIN OSCOUT), connections being always very short. This avoids, only signal coupling onto clock source, also reduces EME. PCB's should, where economically possible, equipped with adequate ground planes. microcontroller power supply should decoupled with electrolytic capacitance (approximate parallel with ceramic capacitance (approximate situated close microcontroller device possible. 3.8.2 Electromagnetic Emissions Electromagnetic emissions caused rapidly changing electrical currents (dI/dt) long antenna like connection lines cables. This result electrical interference other telecommunication devices. These current spikes more often than present system power supply lines driver signal lines. following guide will help reduce EME: Keep length current switching signal tracks minimum. Adopt star power routing system connected point. Many microcontroller port outputs configured with several drive strengths. This means that high drive output will switch signal faster than example standard drive output. resulting change current signal power lines will also increase, causing increase EME. wherever speed drive current necessary ports should configured with lowest drive possible. possible, write application program avoid multiple outputs switching instant. Cables equipped with ferrite rings slow current spikes system encased grounded conducting casing.
4711B-4BMCU-01/05
Absolute Maximum Ratings
Voltages given relative VSS. Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. inputs outputs protected against high electrostatic voltages HBM) electric fields. However, precautions minimize build-up electrostatic charges during handling recommended. Reliability operation enhanced unused inputs connected appropriate logic voltage level (e.g., VDD). Parameters Supply voltage Input voltage pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (SSO44) Soldering temperature Symbol tshort Tamb Tstg RthJA Tsld Value -0.3 -0.3 +0.3 indefinite +150 Unit
Operating Characteristics
Supply voltage Tamb -40°C 85°C unless otherwise specified. Typical values relate Tamb 25°C reference only. Parameters Power Supply Supply Voltage Active current Quotient IDD/SYSCL_iR3 Halt current Power-on Reset Threshold Voltage threshold voltage Schmitt Trigger Input Voltage: (All Inputs Except Port Negative-going threshold voltage Positive-going threshold voltage Hysteresis (VT+ VT-) Input Pins: NRST Input voltage Input voltage HIGH Note: VTVT+ 0.55 VPOR running TestROM SYSCL_iRC3 running TestROM SYSCL_iRC3 sleep mode, NSTOP IDDQ IHalt 0.25 µA/kHz Test Conditions Symbol Min. Typ. Max. Unit
total port static output currents must exceed port currents switched instant (dI/dt) must exceed
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Operating Characteristics (Continued)
Supply voltage Tamb -40°C 85°C unless otherwise specified. Typical values relate Tamb 25°C reference only. Parameters Input NRST with Pull-up Resistor Input current Input with Pull-down Resistor Input HIGH current Bi-directional Ports TIM1 Input voltage Input voltage HIGH Dynamic input current (pull-up) Dynamic input HIGH current (pull-down) Output current VIL= -100 -0.2 0.15 -150 -0.3 -1.35 0.25 -220 -0.5 -1.0 -1.5 -3.0 VIL= -1.0 -1.5 -3.0 Test Conditions Symbol Min. Typ. Max. Unit
Output HIGH current
Bi-directional Port BP4, BP5, BP7, BPA, Input current Static pull-up Input HIGH current Static pull-down Bi-directional Port BP60 BR61 Input current Static pull-up
Input HIGH current Static pull-down Note: total port static output currents must exceed port currents switched instant (dI/dt) must exceed
4711B-4BMCU-01/05
Characteristics
Supply voltage Tamb -40°C 85°C unless otherwise specified. Typical values relate Tamb 25°C reference only. Parameters Reset Timing Power-on reset delay NRST input time Interrupt Request Input Timing Interrupt request time Interrupt request HIGH time SLEEP mode, 0011b, 1100b active, 0011b, 1100b SLEEP mode, 0111b, 1101b active, 0111b, 1101b SLEEP mode, 1011b, 1110b active, 1011b, 1110b SLEEP mode, 1111b, 1111b active, 1111b, 1111b ±20% SLEEP mode, 4-MHz crystal active SLEEP mode, Rext (±1%) active, Rext active/running SLEEP mode AVDD tIRL tIRH VPOR tPOR tNRST Test Conditions Symbol Min. Typ. Max. Unit
Internal Oscillator (For Additional Characteristics Figure page Figure 7-11 page Standby current iRC0 SYSCL_iRC0 Standby current iRC1 SYSCL_iRC1 Standby current iRC2 SYSCL_iRC2 Standby current iRC3 SYSCL_iRC3 Stability IiRC0 fSYSCL IiRC1 fSYSCL IiRC2 fSYSCL IiRC3 fSYSCL df/f0 0.60 0.80 10.5
System Clock Crystal/Ceramic Oscillator (For Additional Characteristics Figure page Standby current Start-up time Stability Ixtal tstartup df/f0
Oscillator External Resistor (For Additional Characteristics Figure page Figure page Standby current Frequency Stability 32-kHz Crystal Oscillator Active current HALT current Start-up time Stability IDD32k IHALTx tstartup df/f0 IxRC fSYSCL df/f0
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Characteristics (Continued)
Supply voltage Tamb -40°C 85°C unless otherwise specified. Typical values relate Tamb 25°C reference only. Parameters Test Conditions active, rise/fall time Figure page rise/fall time Symbol Min. Typ. Max. Unit External Clock Input SCLIN, TIM1 T0IN SCLIN input clock fSCLIN fSYSCL TIM1, T0IN input frequency Number programming cycles fSYSCL 1000 Cycles
EEPROM Program/Configuration Memory
Crystal Characteristics
Parameters 32-kHz Crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance Load capacitance System Clock Crystal Crystal frequency Series resistance Static capacitance Dynamic capacitance 32.768 12.5 Test Conditions Symbol Min. Typ. Max. Unit
Figure 7-1.
Crystal Equivalent Circuit
OSCIN
OSCOUT
Equivalent circuit
4711B-4BMCU-01/05
Figure 7-2.
Worst Case Minimum/Maximum System Frequency (Using External Crystal Oscillator)
100.000
10.000 fSYSCLmax
fSYSCL (MHz)
1.000
0.100
fSYSCLmin
0.010
0.001
Figure 7-3.
(fSYSCL),
10000.00 Tamb 25°C 1000.00 100% active
(µA)
100.00 Standby
10.00
1.00 Halt 0.10
0.01 1000 10000
fSYSCL (kHz)
Figure 7-4.
(fSYSCL),
10000.00 Tamb 25°C 100% active
1000.00
100.00
Standby
(µA)
10.00
1.00 Halt 0.10
0.01 1000 10000
fSYSCL (kHz)
ATAM510
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ATAM510
Figure 7-5. fSYSCL (Tamb); External
2200 Rext 2150 2100
SYSCL (kHz)
2050
2000
1950
1900
Tamb (°C)
Figure 7-6.
fSYSCL (Rext)
10000 Tamb 25°C
SYSCL (kHz)
1000
1000
Rext
Figure 7-7.
fSYSCL (VDD, Rext)
6000 Rext Tamb 25°C 4000
5000
SYSCL (kHz)
3000 Rext 2000
1000 Rext
4711B-4BMCU-01/05
Figure 7-8.
fSYSCL (VDD); Internal
7000 6000 5000 fiRC0 Tamb 25°C
SYSCL (kHz)
4000 fiRC1 3000 fiRC2 2000 1000 fiRC3
Figure 7-9.
fSYSCL (Tamb),
9000 8000 7000 6000 fiRC3
SYSCL (kHz)
5000 4000 3000 2000 fiRC0 1000 fiRC1 fiRC2
Tamb (°C)
Figure 7-10. fSYSCL (Tamb),
10000 9000 8000 7000
fiRC3
SYSCL (kHz)
6000 5000 4000 3000 2000 1000
fiRC2 fiRC1 fiRC0
Tamb (°C)
ATAM510
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ATAM510
Figure 7-11. Typical High Output Driver,
(mA)
Figure 7-12. Typical Output Driver,
(mA)
Figure 7-13. Typical Output Driver,
(mA)
4711B-4BMCU-01/05
Figure 7-14. Typical High Output Driver Layout,
(mA)
Emulation
basic function emulation test evaluate customer's program hardware real time. This therefore enables analysis timing, hardware software problem. emulation purposes, MARC4 controllers include special emulation mode. this mode, internal core inactive buses available Port Port allow external access on-chip peripherals. MARC4 emulator uses this mode control peripherals MARC4 controller (target chip) emulates lost ports application. MARC4 emulator stop restart program specified points during execution, making possible applications engineer view memory contents those various registers during program execution. designer also gains ability analyze executed instruction sequences activities. Figure 8-1. MARC4 Emulation
MARC4 emulator Program memory MARC4 emulation-CPU
Emulator target board
MARC4 target chip
Port
control
Port
Trace memory
CORE
CORE (inactive) Peripherals
Port Control logic
Port
Emulation control
SYSCL/ TCL, NRST Application-specific hardware
Personal computer
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ATAM510
Ordering Information
Extended Type Number ATAM510x-ILQY ATAM510x-ILSY Note: Hardware revision Lead-free Program Memory Data-EEPROM Package SSO44 SSO44 Delivery Taped reeled Tubes
Package Information
Package SSO44
Dimensions
18.05 17.80 9.15 8.65 7.50 7.30
2.35 16.8 0.25 0.10
0.25 10.50 10.20
technical drawings according specifications
4711B-4BMCU-01/05
Revision History
Please note that following page numbers referred this section refer specific revision mentioned, this document. Revision History datasheet template Features page changed Lead-free Logo page added Table "Pin Description" pages changed Figure "Programming Model" page changed Section 2.7.2.5 "32-kHz Oscillator" page changed Title Table page added Table "Peripheral Addresses" page changed Figure "Bi-directional Port page changed Figure "Bi-directional Ports page changed Figure "Bi-directional Port page changed Section 3.26 "Bi-directional Port page changed Figure "Bi-directional Port page changed Figure "Bi-directional TIM1" page changed heading rows Table "Absolute Maximum Ratings" page added Section "Emulation" page added "Ordering Information" page changed
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Table Contents
Features Description Configuration MARC4 Architecture
General Description Components MARC4 Core Registers Interrupt Structure Hardware Reset Clock Generation
Peripheral Modules
Addressing Peripherals Bi-directional Ports Interval Timers/Prescaler Watchdog Timer Timer/Counter Module (TCM) Buzzer Module Programming Noise Considerations
Absolute Maximum Ratings Operating Characteristics Characteristics Crystal Characteristics Emulation Ordering Information
Package Information Revision History
4711B-4BMCU-01/05
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LTC3620 - LTC3620 LTC3620 Datasheet
LTC3620-1 - LTC3620-1 LTC3620-1 Datasheet
LTC3620 - LTC3620 LTC3620 Datasheet
LTC3620EDC - LTC3620EDC LTC3620EDC Datasheet
LTC3620EDC-1 - LTC3620EDC-1 LTC3620EDC-1 Datasheet
CAT24FC64 - CAT24FC64 CAT24FC64 Datasheet
AT7310 - AT7310 AT7310 Datasheet
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