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PIC24HJ32GP202/204 PIC24HJ16GP304 Data Sheet
High-Performance, 16-bit Microcontrollers
2007 Microchip Technology Inc.
DS70289A
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, rfPIC SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2007, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS70289A-page
2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
High-Performance, 16-bit Microcontrollers
Operating Range:
MIPS operation 3.0-3.6V): Industrial temperature range (-40°C +85°C) Extended temperature range (-40°C +125°C)
Digital I/O:
Peripheral Select Functionality programmable digital pins Wake-up/Interrupt-on-Change pins Output pins drive from 3.0V 3.6V output with open drain configuration digital input pins tolerant sink pins
High-Performance CPU:
Modified Harvard architecture compiler optimized instruction 16-bit wide data path 24-bit wide instructions Linear program memory addressing instruction words Linear data memory addressing Kbytes base instructions, mostly word/1 cycle Sixteen 16-bit General Purpose Registers Flexible powerful addressing modes Software stack multiply operations 32/16 16/16 divide operations ±16-bit shifts 40-bit data
System Management:
Flexible clock options: External, crystal, resonator, internal Fully integrated Phase-Locked Loop (PLL) Extremely jitter Power-up Timer Oscillator Start-up Timer/Stabilizer Watchdog Timer with oscillator Fail-Safe Clock Monitor Reset multiple sources
Power Management:
On-chip 2.5V voltage regulator Switch between clock sources real time Idle, Sleep Doze modes with fast wake-up
Interrupt Controller:
5-cycle latency interrupt vectors available interrupt sources external interrupts programmable priority levels processor exceptions
Timers/Capture/Compare:
Timer/Counters, three 16-bit timers: pair make 32-bit timer timer runs Real-Time Clock with external 32.768 oscillator Programmable prescaler Input Capture channels): Capture down both edges 16-bit capture input functions 4-deep FIFO each capture Output Compare channels): Single Dual 16-Bit Compare mode 16-bit Glitchless Mode
On-Chip Flash SRAM:
Flash program memory Kbytes) Data SRAM Kbytes) Boot General Security Program Flash
2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
Communication Modules:
4-wire Framing supports interface simple codecs Supports 8-bit 16-bit data Supports serial clock formats sampling modes I2C- Full Multi-Master Slave mode support 7-bit 10-bit addressing collision detection arbitration Integrated signal conditioning Slave address masking UART Interrupt address detect Interrupt UART error Wake-up Start from Sleep mode 4-character FIFO buffers support IrDA® encoding decoding hardware High-Speed Baud mode Hardware Flow Control with
Analog-to-Digital Converters (ADCs):
10-bit, Msps 12-bit, Ksps conversion: simultaneous samples (10-bit ADC) input channels with auto-scanning Conversion start manual synchronized with trigger sources Conversion possible Sleep mode integral nonlinearity differential nonlinearity
CMOS Flash Technology:
Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial extended temperature Low-power consumption
Packaging:
28-pin SDIP/SOIC/QFN-S 44-pin QFN/TQFP Note: device variant tables exact peripheral features device.
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2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
PIC24HJ32GP202/204 PIC24HJ16GP304 Product Families
device names, counts, memory sizes peripheral availability each family listed below, followed their pinout diagrams.
TABLE
PIC24HJ32GP202/204 PIC24HJ16GP304 CONTROLLER FAMILIES
Program Flash Memory (Kbyte) 10-Bit/12-Bit Remappable Peripherals Output Compare Std. Input Capture Remappable Pins 16-bit Timer Pins (Max)
UART
PIC24HJ32GP202
3(1)
Device
ADC,
SDIP SOIC QFN-S TQFP TQFP
PIC24HJ32GP204 PIC24HJ16GP304
3(1) 3(1)
ADC, ADC,
Note
Only timers Remappable
2007 Microchip Technology Inc.
DS70289A-page
Packages
I2C
Pins
PIC24HJ32GP202/204 PIC24HJ16GP304
Diagrams
28-Pin SDIP, SOIC
MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/RP4/CN1/RB4 SOSCO/T1CK/CN0/RA4 PGED3/ASDA1/RP5/CN27/RB5
AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16 RB10 VCAP/VDDCORE TDO/SDA1/RP9/CN21/RB9 TCK/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6/CN24/RB6
PIC24HFJ32GP202
28-Pin QFN-S
PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/RP4/CN1/RB4 PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 TCK/SCL1/RP8/CN22/RB8 SOSCO/T1CK/CN0/RA4 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16/RB10 VCAP/VDDCORE TDO/SDA1/RP9/CN21/RB9
PIC24HJ32GP202
DS70289A-page
AN10/RP14/CN12/RB14
AVSS AN9/RP15/CN11/RB15
AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR
AVDD
2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
Diagrams (Continued)
44-Pin TQFP
PGEC1/AN3/C2IN+/RP1/CN5/RB1 PGED1/AN2/C2IN-/RP0/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 TCK/RA7 TMS/RA10
2007 Microchip Technology Inc.
SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19/CN28/RC3 RP20/CN25/RC4 RP21/CN26/RC5 PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 SCL1/RP8/CN22/RB8
AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4
PIC24HJ32GP204 PIC24HJ16GP304
AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/RP11/CN15/RB11 PGED2/RP10/CN16/RB10 VCAP/VDDCORE RP25/CN19/RC9 RP24/CN20/RC8 RP23/CN17/RC7 RP22/CN18/RC6 SDA1/RP9/CN21/RB9
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PIC24HJ32GP202/204 PIC24HJ16GP304
Diagrams (Continued)
44-Pin TQFP
PGEC1/AN3/C2IN+/RP1/CN5/RB1 PGED1/AN2/C2IN-/RP0/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 TCK/RA7 TMS/RA10
SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19/CN28/RC3 RP20/CN25/RC4 RP21/CN26/RC5 PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 SCL1/RP8/CN22/RB8
AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4
PIC24HJ32GP204 PIC24HJ16GP304
AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/RP11/CN15/RB11 PGED2/RP10/CN16/RB10 VCAP/VDDCORE RP25/CN19/RC9 RP24/CN20/RC8 RP23/CN17/RC7 RP22/CN18/RC6 SDA1/RP9/CN21/RB9
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Table Contents
Device Overview CPU. Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. Ports 10.0 Timer1 11.0 Timer2/3 Feature. 12.0 Input Capture. 13.0 Output Compare. 14.0 Serial Peripheral Interface (SPI). 15.0 Inter-Integrated Circuit (I2C) 16.0 Universal Asynchronous Receiver Transmitter (UART) 17.0 10-bit/12-bit Analog-to-Digital Converter (ADC) 18.0 Special Features 19.0 Instruction Summary 20.0 Development Support. 21.0 Electrical Characteristics 22.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
errata sheet, describing minor operational differences from data sheet recommended workarounds, exist current devices. device/documentation issues become known will publish errata sheet. errata will specify revision silicon revision document which applies. determine errata sheet exists particular device, please check with following: Microchip's Worldwide site; http://www.microchip.com Your local Microchip sales office (see last page) When contacting sales office, please specify which device, revision silicon data sheet (include literature number) using.
Customer Notification System
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2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
NOTES:
DS70289A-page
2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
Note:
DEVICE OVERVIEW
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
This document contains device-specific information following devices: PIC24HJ32GP202 PIC24HJ32GP204 PIC24HJ16GP304 Figure shows general block diagram core peripheral modules PIC24HJ32GP202/204 PIC24HJ16GP304 family devices. Table lists functions various pins shown pinout diagrams.
2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
FIGURE 1-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Address Latch
PORTB
PIC24HJ32GP202/204 PIC24HJ16GP304 BLOCK DIAGRAM
Data Data Latch
PORTA
Address Generator Units
Remappable Pins
Address Latch
Program Memory Address Data Latch Latch
Literal Data
Instruction Decode Control Control Signals Various Blocks
OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Instruction
Multiplier Register Array
Divide Support
16-bit
VDDCORE/VCAP
VDD,
MCLR
Timers
ADC1
UART1
IC1,2,7,8
PWM1,2
SPI1
I2C1
Note:
pins features implemented device pinout configurations. pinout diagrams specific pins features present each device.
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2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
TABLE 1-1:
Name AN0-AN12 CLKI CLKO
PINOUT DESCRIPTIONS
Type Buffer Type Analog ST/CMOS Analog input channels. External clock source input. Always associated with OSC1 function. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. Always associated with OSC2 function. Oscillator crystal input. buffer when configured mode; CMOS otherwise. Oscillator crystal output. Connects crystal resonator Crystal Oscillator mode. Optionally functions CLKO modes. 32.768 low-power oscillator crystal input; CMOS otherwise. 32.768 low-power oscillator crystal output. Change notification inputs. software programmed internal weak pull-ups inputs. Capture inputs Capture inputs Compare Fault input (for Compare Channels Compare outputs through External interrupt External interrupt External interrupt PORTA bidirectional port. PORTB bidirectional port. PORTC bidirectional port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. UART1 clear send. UART1 ready send. UART1 receive. UART1 transmit. Synchronous serial clock input/output SPI1. SPI1 data SPI1 data out. SPI1 slave synchronization frame pulse I/O. Synchronous serial clock input/output I2C1. Synchronous serial data input/output I2C1. Alternate synchronous serial clock input/output I2C1. Alternate synchronous serial data input/output I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel Data programming/debugging communication channel Clock input programming/debugging communication channel logic filter capacitor connection. Ground reference logic pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Description
OSC1 OSC2 SOSCI SOSCO CN0-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RA7-RA15 RB0-RB15 RC0-RC9 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SCL1 SDA1 ASCL1 ASDA1 PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3 VDDCORE VREF+ VREF-
ST/CMOS ST/CMOS Analog Analog
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels
Analog Analog input Input
Output Power
2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
TABLE 1-1:
Name AVDD MCLR AVSS
PINOUT DESCRIPTIONS (CONTINUED)
Type Buffer Type Description Positive supply analog modules. Master Clear (Reset) input. This active-low Reset device. Ground reference analog modules. Positive supply peripheral logic pins.
Legend: CMOS CMOS compatible input output Schmitt Trigger input with CMOS levels
Analog Analog input Input
Output Power
DS70289A-page
2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
Note:
This data sheet summarizes features this group PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
Data Addressing Overview
PIC24HJ32GP202/204 PIC24HJ16GP304 modules have 16-bit (data) modified Harvard architecture with enhanced instruction addressing modes. 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses bits user program memory space. actual amount program memory implemented varies device. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double word move (MOV.D) instruction table instructions. Overhead-free, singlecycle program loop constructs supported using REPEAT instruction, which interruptible point. PIC24HJ32GP202/204 PIC24HJ16GP304 devices have sixteen, 16-bit working registers programmer's model. Each working registers serve data, address address offset register. 16th working register (W15) operates software Stack Pointer (SP) interrupts calls. PIC24HJ32GP202/204 PIC24HJ16GP304 instruction includes many addressing modes designed optimum compiler efficiency. most instructions, PIC24HJ32GP202/204 PIC24HJ16GP304 capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three parameter instructions supported, allowing operations executed single cycle. block diagram shown Figure 2-1, programmer's model PIC24HJ32GP202/ PIC24HJ16GP304 shown Figure 2-2.
data space linearly addressed words Kbytes using Address Generation Unit (AGU). upper Kbytes data space memory optionally mapped into program space program word boundary defined 8-bit Program Space Visibility Page (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. data space also includes Kbytes RAM, which primarily used data transfers, this used general purpose RAM.
Special Features
PIC24HJ32GP202/204 PIC24HJ16GP304 feature 17-bit 17-bit, single-cycle multiplier. multiplier perform signed, unsigned mixedsign multiplication. Using 17-bit 17-bit multiplier 16-bit 16-bit multiplication makes mixed-sign multiplication possible. PIC24HJ32GP202/204 PIC24HJ16GP304 supports 16/16 32/16 integer divide operations. divide instructions iterative operations. They must executed within REPEAT loop, resulting total execution time instruction cycles. divide operation interrupted during those cycles without loss data. multi-bit data shifter used perform 16-bit, left right shift single cycle.
2007 Microchip Technology Inc.
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FIGURE 2-1:
Table Data Access Control Block Interrupt Controller Program Counter Loop Stack Control Control Logic Logic Data
PIC24HJ32GP202/204 PIC24HJ16GP304 CORE BLOCK DIAGRAM
Data Latch Address Latch
Address Latch Address Generator Units
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction Multiplier
Control Signals Various Blocks
Divide Support
Register Array
16-bit
Peripheral Modules
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FIGURE 2-2: PIC24HJ32GP202/204 PIC24HJ16GP304 PROGRAMMER'S MODEL
W0/WREG W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers
Shadow
PUSH.S Shadow
Legend
PC22 TBLPAG PSVPAG Data Table Page Address
Program Counter
Program Space Visibility Page Address RCOUNT REPEAT Loop Counter
CORCON
Core Configuration Register
IPL2 IPL1 IPL0
STATUS Register
2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
Control Registers
STATUS REGISTER
R/W-0 R/W-0(2) IPL<2:0>(2) Legend: Clear only only 15-9 Readable Writable cleared Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte sized data) low-order (for word sized data) result occurred carry-out from low-order (for byte sized data) low-order (for word sized data) result occurred IPL<2:0>: Interrupt Priority Level Status bits(2) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow This used signed arithmetic (2's complement). indicates overflow magnitude which causes sign change state. Overflow occurred signed arithmetic this arithmetic operation) overflow occurred Zero operation which affects some time past most recent operation which affects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant (MSb) result occurred carry-out from Most Significant result occurred Unimplemented bit, read Value unknown R/W-0(2) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0(1)
REGISTER 2-1:
Note IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read only when NSTDIS (INTCON1<15>).
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REGISTER 2-2:
Legend: Readable cleared 15-4 Clear only Writable unknown
CORCON: CORE CONTROL REGISTER
R/C-0 IPL3(1) R/W-0
Value Unimplemented bit, read
Unimplemented: Read IPL3: Interrupt Priority Level Status 3(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read Note IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form interrupt priority level.
2007 Microchip Technology Inc.
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Arithmetic Logic Unit (ALU)
2.4.2 DIVIDER
PIC24HJ32GP202/204 PIC24HJ16GP304 Arithmetic Logic Unit (ALU) bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register depending operation. Status bits operate Borrow Digit Borrow bits respectively, subtraction operations. perform 8-bit 16-bit operations depending mode instruction that used. Data operation come from register array, data memory depending addressing mode instruction. Likewise, output data from written register array data memory location. Refer "dsPIC30F/33F Programmer's Reference Manual" (DS70157) more information bits affected each instruction. PIC24HJ32GP202/204 PIC24HJ16GP304 incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division. divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operations with following data sizes. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
quotient divide instructions ends remainder 16-bit signed unsigned instructions specify register both 16-bit divisor (Wn) register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/ 16-bit 16-bit/16-bit instructions take same number cycles execute.
2.4.3
MULTI-BIT DATA SHIFTER
multi-bit data shifter capable performing 16-bit arithmetic logic right shifts, 16-bit left shifts single cycle. source either working register memory location. shifter requires signed binary value determine both magnitude (number bits) direction shift operation. positive value shifts operand right. negative value shifts operand left. value does modify operand.
2.4.1
MULTIPLIER
Using high-speed 17-bit 17-bit multiplier, supports unsigned, signed mixed-sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
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Note:
MEMORY ORGANIZATION
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
Program Address Space
program address memory space PIC24HJ32GP202/204 PIC24HJ16GP304 devices instructions. space addressable 24-bit value derived either from 23-bit Program Counter (PC) during program execution, from table operation data space remapping described Section "Interfacing Program Data Memory Spaces". User application access program memory space restricted lower half address range (0x000000 0x7FFFFF). exception TBLRD/TBLWT operations, which TBLPAG<7> permit access Configuration bits Device sections configuration memory space. memory maps PIC24HJ32GP202/204 PIC24HJ16GP304 devices shown Figure 3-1.
PIC24HJ32GP202/204 PIC24HJ16GP304 architecture features separate program data memory spaces buses. This architecture also allows direct access program memory from data space during code execution.
FIGURE 3-1:
PROGRAM MEMORY PIC24HJ32GP202/204 PIC24HJ16GP304 DEVICES
PIC24HJ32GP202/204 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
PIC24HJ16GP304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
User Memory Space
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
User Memory Space
User Program Flash Memory (11264 instructions)
0x0057FE 0x005800
User Program Flash Memory (5632 instructions)
0x002BFE 0x002C00
Unimplemented (Read `0's)
Unimplemented (Read `0's)
0x7FFFFE 0x800000
0x7FFFFE 0x800000
Reserved
Configuration Memory Space Configuration Memory Space
Reserved
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Reserved
Reserved
DEVID
0xFEFFFE 0xFF0000 0xFFFFFE
DEVID
0xFEFFFE 0xFF0000 0xFFFFFE
2007 Microchip Technology Inc.
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PIC24HJ32GP202/204 PIC24HJ16GP304
3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.2 INTERRUPT TRAP VECTORS
PIC24HJ32GP202/204 PIC24HJ16GP304 devices reserve addresses between 0x00000 0x000200 hard-coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user application 0x000000, with actual address start code 0x000002. PIC24HJ32GP202/204 PIC24HJ16GP304 devices also have interrupt vector tables, located from 0x000004 0x0000FF 0x000100 0x0001FF. These vector tables allow each many device interrupt sources handled separate Interrupt Service Routines (ISRs). Section "Interrupt Vector Table" provides more detailed discussion interrupt vector tables.
program memory space organized wordaddressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (See Figure 3-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement provides compatibility with data memory space addressing makes data program memory space accessible.
FIGURE 3-2:
Address 0x000001 0x000003 0x000005 0x000007
PROGRAM MEMORY ORGANIZATION
most significant word 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0') Instruction Width least significant word 0x000000 0x000002 0x000004 0x000006 Address (lsw Address)
DS70289A-page
2007 Microchip Technology Inc.
PIC24HJ32GP202/204 PIC24HJ16GP304
Data Address Space
PIC24HJ32GP202/204 PIC24HJ16GP304 separate 16-bit-wide data memory space. data space accessed using separate Address Generation Units (AGUs) read write operations. data memory maps shown Figure 3-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This arrangement gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved Program Space Visibility area (see Section 3.4.3 "Reading Data From Program Memory Using Program Space Visibility"). PIC24HJ32GP202/204 PIC24HJ16GP304 devices implement Kbytes data memory. Should point location outside this area, all-zero word byte will returned. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, when translating from 8-bit code. misaligned read write attempted, address error trap generated. error occurred read, instruction underway completed. instruction occurred write, instruction executed write does occur. either case, trap then executed, allowing system and/or user application examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, user applications clear register executing zero-extend (ZE) instruction appropriate address.
3.2.1
DATA SPACE WIDTH
data memory space organized byte addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes (LSBs) each word have even addresses, while Most Significant Bytes (MSBs) have addresses.
3.2.3
SPACE
first Kbytes Near Data Space, from 0x0000 0x07FF, primarily occupied Special Function Registers (SFRs). These used PIC24HJ32GP202/204 PIC24HJ16GP304 core peripheral modules control operation device. SFRs distributed among modules that they control, generally grouped together module. Much space contains unused addresses; these read `0'. complete listing implemented SFRs, including their addresses, shown Table through Table 3-21. Note: actual peripheral features interrupts varies device. Refer corresponding device tables pinout diagrams device-specific information.
3.2.2
DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24HJ32GP202/204 PIC24HJ16GP304 instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through wordaligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [WS++] will result value byte operations word operations. Data byte reads will read complete word that contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel byte-wide entities with shared (word) address decode, separate write lines. Data byte writes only write corresponding side array register that matches byte address.
3.2.4
NEAR DATA SPACE
8-Kbyte area between 0x0000 0x1FFF referred Near Data Space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing mode with 16-bit address field, using Indirect Addressing mode using working register address pointer.
2007 Microchip Technology Inc.
DS70289A-page
PIC24HJ32GP202/204 PIC24HJ16GP304
FIGURE 3-3: DATA MEMORY PIC24HJ32GP202/204 PIC24HJ16GP304 DEVICES WITH
Address Kbyte Space 0x0001 Space 0x07FF 0x0801 Data 0x0FFF 0x1001 0x1FFF 0x2001 0x0FFE 0x1000 0x1FFE 0x2000 0x07FE 0x0800 Kbyte Near data space Address 0x0000
bits
Kbyte SRAM Space
0x8001
0x8000
Optionally Mapped into Program Memory
Data Unimplemented
0xFFFF
0xFFFE
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2007 Microchip Technology Inc.
TABLE 3-1:
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Register Program Counter Word Register IPL2 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL1 IPL0 Disable Interrupts Counter Register IPL3
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
Name
Addr
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
2007 Microchip Technology Inc.
Repeat Loop Counter Register
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
002E
0030
PIC24HJ32GP202/204 PIC24HJ16GP304
TBLPAG
0032
PSVPAG
0034
RCOUNT
0036
0042
CORCON
0044
DISICNT
0052
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70289A-page
TABLE 3-2:
CN13IE CN24PUE CN23PUE CN22PUE CN21PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN24IE CN23IE CN22IE CN21IE CN16IE CN0PUE CN16PUE CN29IE CN27PUE CN27IE CN12IE CN11IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE Resets 0000 0000 0000 0000
CHANGE NOTIFICATION REGISTER PIC24HJ32GP202
Name
Addr
CNEN1
0060
CN15IE
CN14IE
DS70289A-page
CN13IE CN29IE CN6PUE CN5PUE CN4PUE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN19IE CN3PUE CN2IE CN18IE CN2PUE CN1IE CN17IE CN1PUE CN0IE CN16IE CN0PUE Resets 0000 0000 0000 0000
CNEN2
0062
CN30IE
CNPU1
0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CNPU2
006A
CN30PUE CN29PUE
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-3:
CHANGE NOTIFICATION REGISTER PIC24HJ32GP204 PIC24HJ16GP304
Name
Addr
CNEN1
0060
CN15IE
CN14IE
CNEN2
0062
CN30IE
CNPU1
0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE
CNPU2
006A
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
PIC24HJ32GP202/204 PIC24HJ16GP304
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2007 Microchip Technology Inc.
TABLE 3-4:
DIV0ERR OC2IF IC7IF OC2IE IC7IE IC1IP<2:0> IC2IP<2:0> SPI1EIP<2:0> AD1IP<2:0> MI2C1IP<2:0> INT2IP<2:0> U1EIP<2:0> VECNUM<6:0> INT1IE CNIE IC2IE T1IE OC1IE INT1IF CNIF IC2IF T1IF OC1IF IC1IF MI2C1IF U1EIF IC1IE U1EIE INT0IP<2:0> T3IP<2:0> U1TXIP<2:0> SI2C1IP<2:0> INT1IP<2:0> INT2EP INT1EP MATHERR ADDRERR STKERR OSCFAIL AD1IF INT2IF AD1IE INT2IE T1IP<2:0> T2IP<2:0> U1RXIP<2:0> CNIP<2:0> IC8IP<2:0> ILR<3:0>> IC7IP<2:0> SPI1IP<2:0> OC2IP<2:0> OC1IP<2:0> IC8IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE IC8IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF INT0EP INT0IF SI2C1IF INT0IE MI2C1IE SI2C1IE
INTERRUPT CONTROLLER REGISTER
Resets 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444
Name
Addr
INTCON1
0080
NSTDIS
INTCON2
0082
ALTIVT
DISI
IFS0
0084
IFS1
0086
IFS4
008C
IEC0
0094
2007 Microchip Technology Inc.
IEC1
0096
IEC4
009C
IPC0
00A4
IPC1
00A6
IPC2
00A8
IPC3
00AA
IPC4
00AC
IPC5
00AE
IPC7
00B2
IPC16
00C4
INTTREG
00E0
PIC24HJ32GP202/204 PIC24HJ16GP304
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70289A-page
TABLE 3-5:
Timer1 Register Period Register Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register Period Register TSIDL TGATE TCKPS<1:0> TSIDL TGATE TCKPS<1:0> TSIDL TGATE TCKPS<1:0> TSYNC Resets xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000
TIMER REGISTER
Name
Addr
TMR1
0100
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Input Capture Register Input Capture Register Input Capture Register Input 8Capture Register ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> ICSIDL ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> Resets xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 Resets xxxx Output Compare Register OCSIDL Output Compare Register OCSIDL OCFLT OCTSEL OCM<2:0> Output Compare Secondary Register OCFLT OCTSEL OCM<2:0> xxxx 0000 xxxx xxxx 0000 Output Compare Secondary Register
0102
T1CON
0104
TMR2
0106
TMR3HLD
0108
TMR3
010A
010C
010E
T2CON
0110
T3CON
0112
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-6:
INPUT CAPTURE REGISTER
Name
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
PIC24HJ32GP202/204 PIC24HJ16GP304
IC2CON
0146
IC7BUF
0158
IC7CON
015A
IC8BUF
015C
IC8CON
015E
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-7:
OUTPUT COMPARE REGISTER
Name
Addr
OC1RS
0180
OC1R
0182
OC1CON
0184
OC2RS
0186
OC2R
0188
OC2CON
018A
2007 Microchip Technology Inc.
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
I2CSIDL Address Mask Register Address Register GCSTAT ADD10 IWCOL I2COV SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN RSEN Baud Rate Generator Register Transmit Register Receive Register
I2C1 REGISTER
Resets 0000 00FF 0000 1000 0000 0000 0000
Name
Addr
I2C1RCV
0200
I2C1TRN
0202
I2C1BRG
0204
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT
TRSTAT
I2C1ADD
020A
2007 Microchip Technology Inc.
USIDL Baud Rate Generator Prescaler UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD URXINV RIDLE BRGH PERR PDSEL<1:0> FERR OERR STSEL URXDA UART Transmit Register UART Receive Register SPISIDL FRMPOL DISSCK DISSDO MODE16 SSEN SPIROV MSTEN SPRE<2:0> SPITBF FRMDLY SPIRBF PPRE<1:0> SPI1 Transmit Receive Buffer Register
I2C1MSK
020C
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-9:
UART1 REGISTER
Resets 0000 0110 xxxx 0000 0000
Name
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
UTXINV UTXISEL0
U1TXREG
0224
U1RXREG
0226
U1BRG
0228
PIC24HJ32GP202/204 PIC24HJ16GP304
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-10:
SPI1 REGISTER
Resets 0000 0000 0000 0000
Name
Addr
SPI1STAT
0240
SPIEN
SPI1CON1
0242
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70289A-page
TABLE 3-11:
SCK1R<4:0> U1CTSR<4:0> U1RX<R4:0> SDI1R<4:0> SS1R<4:0> OCFAR<4:0> IC8R<4:0> IC7R<4:0> IC2R<4:0> IC1R<4:0> T3CKR<4:0> T2CKR<4:0> INT2R<4:0> INT1R<4:0> Resets 1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F
PERIPHERAL SELECT INPUT REGISTER
File Name
Addr
RPINR0
0680
DS70289A-page
RP15R<4:0> RP13R<4:0> RP11R<4:0> RP9R<4:0> RP7R<4:0> RP5R<4:0> RP3R<4:0> RP1R<4:0> RP0R<4:0> RP2R<4:0> RP4R<4:0> RP6R<4:0> RP8R<4:0> RP10R<4:0> RP12R<4:0> RP14R<4:0> Resets 0000 0000 0000 0000 0000 0000 0000 0000
RPINR1
0682
RPINR3
0686
RPINR7
068E
RPINR10
0694
RPINR11
0696
RPINR18
06A4
RPINR20
06A8
RPINR21
06AA
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-12:
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ32GP202
File Name
Addr
RPOR0
06C0
RPOR1
06C2
PIC24HJ32GP202/204 PIC24HJ16GP304
RPOR2
06C4
RPOR3
06C6
RPOR4
06C8
RPOR5
06CA
RPOR6
06CC
RPOR7
06CE
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2007 Microchip Technology Inc.
TABLE 3-13:
RP23R<4:0> RP21R<4:0> RP19R<4:0> RP17R<4:0> RP15R<4:0> RP13R<4:0> RP11R<4:0> RP10R<4:0> RP12R<4:0> RP14R<4:0> RP16R<4:0> RP18R<4:0> RP20R<4:0> RP22R<4:0> RP24R<4:0> RP9R<4:0> RP8R<4:0> RP7R<4:0> RP6R<4:0> RP5R<4:0> RP4R<4:0> RP3R<4:0> RP2R<4:0> RP1R<4:0> RP0R<4:0>
PERIPHERAL SELECT OUTPUT REGISTER PIC24HJ32GP204 PIC24HJ16GP304
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
RPOR0
06C0
RPOR1
06C2
RPOR2
06C4
RPOR3
06C6
RPOR4
06C8
RPOR5
06CA
2007 Microchip Technology Inc.
RPOR6
06CC
RPOR7
06CE
RPOR8
06D0
RPOR9
06D2
RPOR10
06D4
RPOR11
06D6
RPOR12
Legend:
RP25R<4:0> 06D8 unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24HJ32GP202/204 PIC24HJ16GP304
DS70289A-page
TABLE 3-14:
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer CSS12 CSS11 CSS10 CSS9 CSS8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 CH0SB<4:0> CH123NB<1:0> CH123SB CH0NA PCFG7 CSS7 SAMC<4:0> PCFG6 CSS6 PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 CSCNA CHPS<1:0> BUFS ADSIDL AD12B FORM<1:0> SSRC<2:0> SIMSAM SMPI<3:0> ADCS<7:0> CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA ASAM SAMP BUFM DONE ALTS Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000
ADC1 REGISTER PIC24HJ32GP204 PIC24HJ16GP304
File Name
Addr
ADC1BUF0
0300
DS70289A-page
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFE
031E
PIC24HJ32GP202/204 PIC24HJ16GP304
AD1CON1
0320
ADON
AD1CON2
0322
VCFG<2:0>
AD1CON3
0324
ADRC
AD1CHS123
0326
AD1CHS0
0328
CH0NB
AD1PCFGL
032C
AD1CSSL
0330
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
2007 Microchip Technology Inc.
TABLE 3-15:
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer CSS12 CSS11 CSS10 CSS9 PCFG12 PCFG11 PCFG10 PCFG9 CH0SB<4:0> CH123NB<1:0> CH123SB CH0NA SAMC<4:0> PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 CSCNA CHPS<1:0> BUFS ADSIDL AD12B FORM<1:0> SSRC<2:0> SIMSAM SMPI<3:0> ADCS<7:0> CH123NA<1:0> CH0SA<4:0> PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA ASAM SAMP BUFM DONE ALTS
ADC1 REGISTER PIC24HJ32GP202
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
2007 Microchip Technology Inc.
ADC1BUF5
030A
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
PIC24HJ32GP202/204 PIC24HJ16GP304
AD1CON1
0320
ADON
AD1CON2
0322
VCFG<2:0>
AD1CON3
0324
ADRC
AD1CHS123
0326
AD1CHS0
0328
CH0NB
AD1PCFGL
032C
AD1CSSL
0330
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
DS70289A-page
TABLE 3-16:
TRISA4 LATA4 ODCA4 ODCA3 ODCA2 ODCA1 LATA3 LATA2 LATA1 LATA0 ODCA0 TRISA3 TRISA2 TRISA1 TRISA0 Resets 001F xxxx xxxx xxxx
PORTA REGISTER PIC24HJ32GP202
File Name
Addr
TRISA
02C0
DS70289A-page
TRISA10 RA10 LATA10 ODCA10 ODCA9 ODCA8 ODCA7 ODCA4 LATA9 LATA8 LATA7 LATA4 LATA3 ODCA3 TRISA9 TRISA8 TRISA7 TRISA4 TRISA3 TRISA2 LATA2 ODCA2 TRISA1 LATA1 ODCA1 TRISA0 LATA0 ODCA0 Resets 079F xxxx xxxx xxxx TRISB13 RB13 LATB13 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 RB12 RB11 RB10 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 LATB6 ODCB6 TRISB5 LATB5 ODCB5 TRISB4 LATB4 ODCB4 TRISB3 LATB3 ODCB3 TRISB2 LATB2 ODCB2 TRISB1 LATB1 ODCB1 TRISB0 LATB0 ODCB0 Resets FFFF xxxx xxxx xxxx TRISC9 LATC9 ODCC9 TRISC8 LATC8 ODCC8 TRISC7 LATC7 ODCC7 TRISC6 LATC6 ODCC6 TRISC5 LATC5 ODCC5 TRISC4 LATC4 ODCC4 TRISC3 LATC4 ODCC4 TRISC2 LATC2 ODCC2 TRISC1 LATC1 ODCC1 TRISC0 LATC0 ODCC0 Resets 03FF xxxx xxxx xxxx
PORTA
02C2
LATA
02C4
ODCA
02C6
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-17:
PORTA REGISTER PIC24HJ32GP204 PIC24HJ16GP304
File Name
Addr
TRISA
02C0
PORTA
02C2
LATA
02C4
ODCA
02C6
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-18:
PORTB REGISTER
PIC24HJ32GP202/204 PIC24HJ16GP304
File Name
Addr
TRISB
02C8
TRISB15
TRISB14
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODCB15
ODCB14
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal PinHigh devices.
TABLE 3-19:
PORTC REGISTER PIC24HJ32GP204 PIC24HJ16GP304
File Name
Addr
TRISC
02D0
PORTC
02D2
LATC
02D4
ODCC
02D6
2007 Microchip Technology Inc.
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-20:
WRERR NVMKEY<7:0> ERASE NVMOP<3:0>
REGISTER
Resets 0000(1) 0000
File Name
Addr
NVMCON
0760
WREN
NVMKEY
0766
2007 Microchip Technology Inc.
T3MD IC2MD IC1MD T2MD T1MD I2C1MD U1MD SPI1MD OC2MD AD1MD OC1MD
Legend: Note
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal. Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 3-21:
REGISTER
Resets 0000 0000
File Name
Addr
PMD1
0770
PMD2
0772
IC8MD
IC7MD
Legend:
unknown value Reset, unimplemented, read `0'. Reset values shown hexadecimal.
PIC24HJ32GP202/204 PIC24HJ16GP304
DS70289A-page
PIC24HJ32GP202/204 PIC24HJ16GP304
3.2.5 SOFTWARE STACK 3.2.6 DATA PROTECTION FEATURE
addition working register, register PIC24HJ32GP202/204 PIC24HJ16GP304 devices also used software Stack Pointer. Stack Pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops postincrements stack pushes, shown Figure 3-4. push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing concatenates register prior push. PIC24H product family supports Data protection features that enable segments protected when used conjunction with Boot Secure Code Segment Security. BSRAM (Secure segment accessible only from Boot Segment Flash code when enabled. SSRAM (Secure segment RAM) accessible only from Secure Segment Flash code when enabled. Table overview BSRAM SSRAM SFRs.
Instruction Addressing Modes
Stack Pointer Limit register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. Similarly, Stack Pointer, SPLIM<0> forced because stack operations must word aligned. When generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. example, cause stack error trap when stack grows beyond address 0x2000 RAM, initialize SPLIM with value 0x1FFE. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found lesser than 0x0800. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
addressing modes shown Table 3-22 form basis addressing modes optimized support specific features individual instructions. addressing modes provided class instructions differ from those other instruction types.
3.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions 13-bit address field directly address data present first 8192 bytes data memory (Near Data Space). Most file register instructions employ working register, which denoted WREG these instructions. destination typically either same file register WREG (with exception instruction), which writes result register register pair. instruction allows additional flexibility access entire data space.
3.3.2
INSTRUCTIONS
three-operand instructions form: Operand Operand <function> Operand where, Operand always working register (that addressing mode only register direct), which referred Operand register, fetched from data memory, 5-bit literal. result location either register data memory location. following addressing modes supported instructions: Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit 10-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
FIGURE 3-4:
0x0000
CALL STACK FRAME
Stack Grows Toward Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
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TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description address file register specified explicitly. contents register accessed directly. contents forms Effective Address (EA.) contents forms post-modified (incremented decremented) constant value. pre-modified (incremented decremented) signed constant value form Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified
Register Indirect with Register Offset forms (Register Indexed) Register Indirect with Literal Offset literal forms summary, move instructions support following addressing modes: Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: instructions support addressing modes given above. Individual instructions support different subsets these addressing modes.
3.3.3
MOVE (MOV) INSTRUCTION
Move instructions provide greater degree addressing flexibility than other instructions. addition Addressing modes supported most instructions, instructions also support Register Indirect with Register Offset Addressing mode. This also referred Register Indexed mode. Note: instructions, addressing mode specified instruction differ source destination However, 4-bit (Register Offset) field shared both source destination (but typically only used one).
3.3.4
OTHER INSTRUCTIONS
Besides addressing modes outlined previously, some instructions literal constants various sizes. example, (branch) instructions 16-bit signed literals specify branch destination directly, whereas DISI instruction uses 14-bit unsigned literal field. some instructions, such Acc, source operand result implied opcode itself. Certain operations, such NOP, have operands.
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Interfacing Program Data Memory Spaces
3.4.1 ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Page register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 3-23 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, D<15:0> refers data space word.
PIC24HJ32GP202/204 PIC24HJ16GP304 architecture uses 24-bit-wide program space 16-bit wide data space. architecture also modified Harvard scheme, which means that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24HJ32GP202/ PIC24HJ16GP304 architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (Program Space Visibility) Table instructions allow application read write small areas program memory. This capability makes method ideal accessing data tables that need updated periodically. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look from large table static data. application only access Least Significant word program word.
TABLE 3-23:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Address <23> xxxx TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1>
Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Program Space Visibility (Block Remap/Read) Note
User
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
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FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2)
TBLPAG bits bits bits
Select Program Space Visibility(1) (Remapping) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note Least Significant (LSb) program space addresses always fixed maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
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3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when Byte Select `1'; lower byte selected when `0'. TBLRDH (Table Read High): Word mode, this instruction maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, `phantom byte', will always `0'. Byte mode, this instruction maps upper lower byte program word D<7:0> data address, TBLRDL instruction. Note that data will always when upper `Phantom' byte selected (Byte Select similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Page register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space.
TBLRDL TBLWTL instructions offer direct method read write lower word address within program space without going through data space. TBLRDH TBLWTH instructions only methods read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit wide word address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space that contains least significant data word. TBLRDH TBLWTH access space that contains upper data byte. table instructions provided move byte word sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, this instruction maps lower word program space location (P<15:0>) data address (D<15:0>).
FIGURE 3-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
0x000000
00000000 00000000 00000000 00000000
0x020000 0x030000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
0x800000
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3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space location used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This option provides transparent access stored constant data from data space without need special instructions (such TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Core Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area cycle instruction being executed, since program memory fetches required. Although each data space address 8000h higher maps directly into corresponding program memory address (see Figure 3-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions require instruction cycle addition specified execution time. other instructions require instruction cycles addition specified execution time. operations that PSV, executed inside REPEAT loop, these instances require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction using access data execute single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 0x000000 0x010000 0x018000 data page designated PSVPAG mapped into upper half data memory space.
Data Space
0x0000 Data EA<14:0>
0x8000
Area .while lower bits specify exact address within 0xFFFF area. This corresponds exactly same lower bits actual program space address.
0x800000
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Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user application write program memory data either `blocks' `rows' instructions (192 bytes) time single program memory word, erase program memory blocks `pages' instructions (1536 bytes) time.
PIC24HJ32GP202/204 PIC24HJ16GP304 devices contain internal Flash program memory store execute application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed ways: In-Circuit Serial Programming(ICSPTM) programming capability Run-Time Self-Programming (RTSP) ICSP allows PIC24HJ32GP202/204 PIC24HJ16GP304 device serially programmed while application circuit. This done with lines programming clock programming data (one alternate programming pairs: PGC1/ PGD1, PGC2/PGD2 PGC3/PGD3), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
Table Instructions Flash Programming
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using bits <7:0> TBLPAG register Effective Address (EA) from register specified table instruction, shown Figure 4-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
FIGURE 4-1:
ADDRESSING TABLE REGISTERS
bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG bits bits
User/Configuration Space Select
24-bit
Byte Select
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RTSP Operation Control Registers
PIC24HJ32GP202/204 PIC24HJ16GP304 Flash program memory array organized into rows instructions bytes. RTSP allows user application erase page memory, which consists eight rows (512 instructions) time, program word time. 8-row erase pages single write rows edge-aligned from beginning program memory, boundaries 1536 bytes bytes, respectively. program memory implements holding buffers that contain instructions programming data. Prior actual programming operation, write data must loaded into buffers sequentially. instruction words loaded must always from group boundary. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. total TBLWTL TBLWTH instructions required load instructions. table write operations single-word writes (two instruction cycles) because only buffers written. programming cycle required programming each row. SFRs used read write program Flash memory: NVMCON: Flash Memory Control Register NVMKEY: Non-Volatile Memory Register NVMCON register (Register 4-1) controls which blocks need erased, which memory type programmed start programming cycle. NVMKEY (Register 4-2) write-only register that used write protection. start programming erase sequence, user application must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
complete programming sequence necessary programming erasing internal Flash RTSP mode. programming operation nominally duration processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation, automatically cleared when operation finished.
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REGISTER 4-1:
R/SO-0(1) Legend: Readable Value Satiable only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) R/W-0(1) R/W-0(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR R/W-0(1) WREN
R/W-0(1)
NVMOP<3:0>
Write Control Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable Perform erase operation specified NVMOP<3:0> next command Perform program operation specified NVMOP<3:0> next command Unimplemented: Read NVMOP<3:0>: Operation Select bits(2) ERASE 1111 Memory bulk erase operation 1101 Erase General Segment 1100 Erase Secure Segment 0011 operation 0010 Memory page erase operation 0001 operation 0000 Erase single Configuration register byte ERASE 1111 operation 1101 operation 1100 operation 0011 Memory word program operation 0010 operation 0001 Memory program operation 0000 Program single Configuration register byte
12-7
Note
These bits only reset POR. other combinations NVMOP<3:0> unimplemented.
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REGISTER 4-2:
Legend: Readable Value 15-8 Satiable only Writable Unimplemented bit, read cleared unknown
NVMKEY: NON-VOLATILE MEMORY REGISTER
NVMKEY<7:0>
Unimplemented: Read NVMKEY<7:0>: Register (Write Only) bits
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4.4.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
Write first instructions from data into program memory buffers (see Example 4-2). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
Programmers program program Flash memory time. this, necessary erase 8-row erase page that contains desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 4-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address page erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically.
protect against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user application must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 4-3.
EXAMPLE 4-1:
ERASING PROGRAM MEMORY PAGE
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 4-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++] 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++]
EXAMPLE 4-3:
DISI BSET
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
#0x55, NVMKEY #0xAA, NVMKEY NVMCON,
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Note:
RESETS
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
active source Reset makes SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets. Note: Refer specific peripheral section this manual register Reset states.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset BOR: Brown-out Reset MCLR: Master Clear Reset SWR: RESET Instruction WDTO: Watchdog Timer Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode, Uninitialized Register Reset, Security Reset Configuration Mismatch Reset Figure shows simplified block diagram Reset module.
types device Reset will corresponding status RCON register indicate type Reset (see Register 5-1). will clear bits, except (RCON<0>), that set. user application clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software does cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter MCLR Module Sleep Idle SYSRST
Internal Regulator Rise Detect
Trap Conflict Illegal Opcode Uninitialized Register Configuration Mismatch
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REGISTER 5-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 R/W-0 VREGS R/W-1
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read Configuration Mismatch Flag configuration mismatch Reset occurred. configuration mismatch Reset occurred. VREGS: Voltage Regulator Standby During Sleep Voltage regulator active during Sleep Voltage regulator goes into Standby mode during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake-up from Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up from Idle Flag Device Idle mode Device Idle mode Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
13-10
Note
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REGISTER 5-1:
RCON: RESET CONTROL REGISTER(1)
BOR: Brown-out Reset Flag Brown-out Reset occurred Brown-out Reset occurred POR: Power-on Reset Flag Power-up Reset occurred Power-up Reset occurred Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
Note
TABLE 5-1:
RESET FLAG OPERATION
Flag Setting Event Trap conflict event Illegal opcode uninitialized register access Configuration mismatch MCLR Reset RESET instruction time-out PWRSAV #SLEEP instruction PWRSAV #IDLE instruction Clearing Event POR, POR, POR, POR, PWRSAV instruction, POR, BOR, CLRWDT instruction POR, POR,
TRAPR (RCON<15>) IOPUWR (RCON<14>) (RCON<9>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) Note:
Reset flag bits cleared user software.
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Clock Source Selection Reset Device Reset Times
clock switching enabled, system clock source device Reset chosen shown Table 5-2. clock switching disabled, system clock source always selected according oscillator Configuration bits. Refer Section "Oscillator Configuration" further details. Reset times various types device Reset summarized Table 5-3. system Reset signal, SYSRST, released after PWRT delay times expire. time which device actually begins execute code also depends system oscillator delays, which include Oscillator Start-up Timer (OST) lock time. lock times occur parallel with applicable SYSRST delay times. FSCM delay determines time which FSCM begins monitor system clock source after SYSRST signal released.
TABLE 5-2:
OSCILLATOR SELECTION TYPE RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant Oscillator Configuration bits (FNOSC<2:0>) COSC Control bits (OSCCON<14:12>)
Reset Type MCLR WDTR
TABLE 5-3:
Reset Type
RESET DELAY TIMES VARIOUS DEVICE RESETS
Clock Source FRC, LPRC ECPLL, FRCPLL SOSC XTPLL, HSPLL SYSRST Delay TPOR TSTARTUP TRST TPOR TSTARTUP TRST TPOR TSTARTUP TRST TPOR TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TRST TRST TRST TRST TRST TRST System Clock Delay TLOCK TOST TOST TLOCK TLOCK TOST TOST TLOCK FSCM Delay TFSCM TFSCM TFSCM TFSCM TFSCM TFSCM Notes
FRC, LPRC ECPLL, FRCPLL SOSC XTPLL, HSPLL
MCLR Software Illegal Opcode Uninitialized Trap Conflict Note
Clock Clock Clock Clock Clock Clock
TPOR Power-on Reset delay nominal). TSTARTUP Conditional delay nominal on-chip regulator enabled) nominal Power-up Timer delay regulator disabled). TSTARTUP also applied returns from powered-down states, including waking from Sleep mode, only regulator enabled. TRST Internal state Reset time nominal). TOST Oscillator Start-up Timer. 10-bit counter counts 1024 oscillator periods before releasing oscillator clock system. TLOCK lock time nominal). TFSCM Fail-Safe Clock Monitor delay (100 nominal).
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5.2.1 LONG OSCILLATOR START-UP TIMES 5.2.2.1 FSCM Delay Crystal Clock Sources
oscillator start-up circuitry associated delay timers linked device Reset delays that occur power-up. Some crystal circuits (especially low-frequency crystals) have relatively long start-up time. Therefore, more following conditions possible after SYSRST released. oscillator circuit begun oscillate. Oscillator Start-up Timer expired crystal oscillator used). achieved lock used). device will begin execute code until valid clock source been released system. Therefore, oscillator start-up delays must considered when Reset delay time must known.
When system clock source provided crystal oscillator and/or PLL, short delay, TFSCM, automatically inserted after PWRT delay times. FSCM does start monitor system clock source until this delay expires. FSCM delay time nominally provides additional time oscillator and/or stabilize. most cases, FSCM delay prevents oscillator failure trap device Reset when PWRT disabled.
Special Function Register Reset States
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) DEVICE RESETS
FSCM enabled, begins monitor system clock source when SYSRST released. valid clock source available, device automatically switches oscillator user application switch desired crystal oscillator Trap Service Routine.
Most Special Function Registers (SFRs) associated with peripherals reset particular value device Reset. SFRs grouped their peripheral function, their Reset values specified each section this manual. Reset value each does depend type Reset, with exception registers: Reset value Reset Control register, RCON, depends type device Reset. Reset value Oscillator Control register, OSCCON, depends type Reset programmed values Oscillator Configuration bits FOSC Configuration register.
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Note:
INTERRUPT CONTROLLER
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
6.1.1
ALTERNATE INTERRUPT VECTOR TABLE
Alternate Interrupt Vector Table (AIVT) located after IVT, shown Figure 6-1. Access AIVT provided ALTIVT control (INTCON2<15>). ALTIVT set, interrupt exception processes alternate vectors instead default vectors. alternate vectors organized same manner default vectors. AIVT supports debugging providing means switch between application support environment without requiring interrupt vectors reprogrammed. This feature also enables switching between applications evaluation different software algorithms time. AIVT needed, AIVT should programmed with same addresses used IVT.
PIC24HJ32GP202/204 PIC24HJ16GP304 interrupt controllers reduce numerous peripheral interrupt request signals single interrupt request signal PIC24HJ32GP202/204 PIC24HJ16GP304 CPU. following features: processor exceptions software traps user-selectable priority levels Interrupt Vector Table (IVT) with vectors unique vector each interrupt exception source Fixed priority within specified user priority level Alternate Interrupt Vector Table (AIVT) debug support Fixed interrupt entry return latencies
Reset Sequence
Interrupt Vector Table
Figure shows Interrrupt Vector Table. resides program memory, starting location 000004h. contains vectors consisting nonmaskable trap vectors sources interrupt. general, each interrupt source vector. Each interrupt vector contains 24-bit wide address. value programmed into each interrupt vector location starting address associated Interrupt Service Routine (ISR). Interrupt vectors prioritized terms their natural priority; this priority linked their position vector table. Lower addresses generally have higher natural priority. example, interrupt associated with vector will take priority over interrupts other vector address. PIC24HJ32GP202/204 PIC24HJ16GP304 devices implement unique interrupts nonmaskable traps. These summarized Table Table 6-2.
device Reset true exception because interrupt controller involved Reset process. PIC24HJ32GP202/204 PIC24HJ16GP304 device clear registers response Reset, which forces zero. microcontroller then begins program execution location 0x000000. user application GOTO instruction Reset address which redirects program execution appropriate start-up routine. Note: unimplemented unused vector locations AIVT should programmed with address default interrupt handler routine that contains RESET instruction.
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FIGURE 6-1: PIC24HJ32GP202/204 PIC24HJ16GP304 INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Start Code 0x000000 0x000002 0x000004
0x000014
Decreasing Natural Order Priority
0x00007C 0x00007E 0x000080
Interrupt Vector Table (IVT)(1)
0x0000FC 0x0000FE 0x000100 0x000102
0x000114
Alternate Interrupt Vector Table (AIVT)(1) 0x00017C 0x00017E 0x000180
0x0001FE 0x000200
Note Table list implemented interrupt vectors.
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TABLE 6-1:
Vector Number
INTERRUPT VECTORS
Interrupt Request (IRQ) Number Address 0x000014 0x000016 0x000018 0x00001A 0x00001C 0x00001E 0x000020 0x000022 0x000024 0x000026 0x000028 0x00002A 0x00002C 0x00002E 0x000030 0x000032 0x000034 0x000036 0x000038 0x00003A 0x00003C 0x00003E 0x000040 0x000042 0x000044 0x000046 0x000048 0x00004A 0x00004C 0x00004E 0x000050 0x000052 0x000054 0x000056 0x000058 0x00005A 0x00005C 0x00005E 0x000060 0x000062 0x000064 0x000066 0x000068 0x00006A 0x00006C 0x00006E AIVT Address 0x000114 0x000116 0x000118 0x00011A 0x00011C 0x00011E 0x000120 0x000122 0x000124 0x000126 0x000128 0x00012A 0x00012C 0x00012E 0x000130 0x000132 0x000134 0x000136 0x000138 0x00013A 0x00013C 0x00013E 0x000140 0x000142 0x000144 0x000146 0x000148 0x00014A 0x00014C 0x00014E 0x000150 0x000152 0x000154 0x000156 0x000158 0x00015A 0x00015C 0x00015E 0x000160 0x000162 0x000164 0x000166 0x000168 0x00016A 0x00016C 0x00016E Interrupt Source INT0 External Interrupt Input Compare Output Compare Timer1 Reserved Input Capture Output Compare Timer2 Timer3 SPI1E SPI1 Error SPI1 SPI1 Transfer Done U1RX UART1 Receiver U1TX UART1 Transmitter ADC1 Reserved Reserved SI2C1 I2C1 Slave Events MI2C1 I2C1 Master Events Reserved Change Notification Interrupt INT1 External Interrupt Reserved Input Capture Input Capture Reserved Reserved Reserved Reserved Reserved INT2 External Interrupt Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
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TABLE 6-1:
Vector Number 80-125
INTERRUPT VECTORS (CONTINUED)
Interrupt Request (IRQ) Number 72-117 Address 0x000070 0x000072 0x000074 0x000076 0x000078 0x00007A 0x00007C 0x00007E 0x000080 0x000082 0x000084 0x000086 0x000088 0x00008A 0x00008C 0x00008E 0x000090 0x000092 0x000094 0x000096 0x000098 0x00009A 0x00009C 0x00009E 0x0000A0 0x0000A2 0x0000A40x0000FE AIVT Address 0x000170 0x000172 0x000174 0x000176 0x000178 0x00017A 0x00017C 0x00017E 0x000180 0x000182 0x000184 0x000186 0x000188 0x00018A 0x00018C 0x00018E 0x000190 0x000192 0x000194 0x000196 0x000198 0x00019A 0x00019C 0x00019E 0x0001A0 0x0001A2 0x0001A40x0001FE Interrupt Source Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved UART1 Error Reserved Reserved Reserved Reserved Reserved Reserved Reserved
TABLE 6-2:
TRAP VECTORS
Address 0x000004 0x000006 0x000008 0x00000A 0x00000C 0x00000E 0x000010 0x000012 AIVT Address 0x000104 0x000106 0x000108 0x00010A 0x00010C 0x00010E 0x000110 0x000112 Trap Source Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
Vector Number
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Interrupt Control Status Registers
6.3.4 IPCx
registers used interrupt priority level each source interrupt. Each user interrupt source assigned eight priority levels.
PIC24HJ32GP202/204 PIC24HJ16GP304 devices implement total registers interrupt controller: Interrupt Control Register (INTCON1) Interrupt Control Register (INTCON2) Interrupt Flag Status Registers (IFSx) Interrupt Enable Control Registers (IECx) Interrupt Priority Control Registers (IPCx) Interrupt Control Status Register (INTTREG)
6.3.5
INTTREG
INTTREG register contains associated interrupt vector number interrupt priority level, which latched into vector number (VECNUM<6:0>) Interrupt level (ILR<3:0>) fields INTTREG register. interrupt priority level priority pending interrupt. interrupt sources assigned IFSx, IECx IPCx registers same sequence that they listed Table 6-1. example, INT0 (External Interrupt shown having vector number natural order priority Thus, INT0IF found IFS0<0>, INT0IE IEC0<0>, INT0IP bits first position IPC0 (IPC0<2:0>).
6.3.1
INTCON1 INTCON2
Global interrupt control functions controlled from INTCON1 INTCON2. INTCON1 contains Interrupt Nesting Disable (NSTDIS) well control status flags processor trap sources. INTCON2 register controls external interrupt request signal behavior Alternate Interrupt Vector Table.
6.3.6
STATUS REGISTERS
6.3.2
IFSx
registers maintain interrupt request flags. Each source interrupt status bit, which respective peripherals external signal this cleared software.
Although these specifically part interrupt control hardware, Control registers contain bits that control interrupt functionality: STATUS register, contains IPL<2:0> bits (SR<7:5>). These bits indicate current interrupt priority level. user change current priority level writing bits. CORCON register contains IPL3 which, together with IPL<2:0>, also indicates current priority level. IPL3 read-only bit, that trap events cannot masked user software. Interrupt registers described Register through Register 6-19 following pages.
6.3.3
IECx
registers maintain interrupt enable bits. These control bits used individually enable interrupts from peripherals external signals.
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REGISTER 6-1:
R/W-0(3) IPL2(2) Legend: Clear only only Readable Writable cleared Unimplemented bit, read Value unknown R/W-0(3) IPL1
STATUS REGISTER(1)
R/W-0 R/W-0(3) IPL0(2) R/W-0 R/W-0 R/W-0 R/W-0
IPL<2:0>: Interrupt Priority Level Status bits(1) Interrupt Priority Level (15), user interrupts disabled Interrupt Priority Level (14) Interrupt Priority Level (13) Interrupt Priority Level (12) Interrupt Priority Level (11) Interrupt Priority Level (10) Interrupt Priority Level Interrupt Priority Level complete register details, Register 2-1: "SR: STATUS Register". IPL<2:0> bits concatenated with IPL<3> (CORCON<3>) form Interrupt Priority Level. value parentheses indicates IPL<3> User interrupts disabled when IPL<3> IPL<2:0> Status bits read-only when NSTDIS (INTCON1<15>)
Note
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REGISTER 6-2:
Legend: Readable cleared Clear only Writable unknown
CORCON: CORE CONTROL REGISTER(1)
R/C-0 IPL3(2) R/W-0
Value Unimplemented bit, read
IPL3: Interrupt Priority Level Status 3(2) interrupt priority level greater than interrupt priority level less complete register details, Register 2-2: "CORCON: CORE Control Register". IPL3 concatenated with IPL<2:0> bits (SR<7:5>) form Interrupt Priority Level.
Note
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REGISTER 6-3:
R/W-0 NSTDIS Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 DIV0ERR R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL
INTCON1: INTERRUPT CONTROL REGISTER
NSTDIS: Interrupt Nesting Disable Interrupt nesting disabled Interrupt nesting enabled Unimplemented: Read `0'. DIV0ERR: Arithmetic Error Status Math error trap caused divide zero Math error trap caused divide zero Unimplemented: Read MATHERR: Arithmetic Error Status Math error trap occurred Math error trap occurred ADDRERR: Address Error Trap Status Address error trap occurred Address error trap occurred STKERR: Stack Error Trap Status Stack error trap occurred Stack error trap occurred OSCFAIL: Oscillator Failure Trap Status Oscillator failure trap occurred Oscillator failure trap occurred Unimplemented: Read
14-7
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REGISTER 6-4:
R/W-0 ALTIVT Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER
DISI R/W-0 INT0EP
ALTIVT: Enable Alternate Interrupt Vector Table alternate vector table standard (default) vector table DISI: DISI Instruction Status DISI instruction active DISI instruction active Unimplemented: Read INT2EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT1EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT0EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge
13-3
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REGISTER 6-5:
R/W-0 T2IF Legend: Readable Value 15-4 Writable Unimplemented bit, read cleared unknown R/W-0 OC2IF R/W-0 IC2IF R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF
IFS0: INTERRUPT FLAG STATUS REGISTER
R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPI1EIF R/W-0 T3IF R/W-0 INT0IF
Unimplemented: Read AD1IF: ADC1 Conversion Complete Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1TXIF: UART1 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1RXIF: UART1 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1IF: SPI1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1EIF: SPI1 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred T3IF: Timer3 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T2IF: Timer2 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC2IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC2IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read T1IF: Timer1 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC1IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-5:
IFS0: INTERRUPT FLAG STATUS REGISTER (CONTINUED)
IC1IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT0IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-6:
R/W-0 IC8IF Legend: Readable Value 15-4 Writable Unimplemented bit, read cleared unknown R/W-0 IC7IF R/W-0 INT1IF R/W-0 CNIF R/W-0 MI2C1IF
IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 INT2IF R/W-0 SI2C1IF
Unimplemented: Read INT2IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read IC8IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC7IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT1IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred CNIF: Input Change Notification Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read MI2C1IF: I2C1 Master Events Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C1IF: I2C1 Slave Events Interrupt Flag Status Interrupt request occurred Interrupt request occurred
12-8
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REGISTER 6-7:
Legend: Readable Value 15-2 Writable Unimplemented bit, read cleared unknown U1EIF
IFS4: INTERRUPT FLAG STATUS REGISTER
Unimplemented: Read U1EIF: UART1 Error Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read
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REGISTER 6-8:
R/W-0 T2IE Legend: Readable Value 15-4 Writable Unimplemented bit, read cleared unknown R/W-0 OC2IE R/W-0 IC2IE R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE
IEC0: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPI1EIE R/W-0 T3IE R/W-0 INT0IE
Unimplemented: Read AD1IE: ADC1 Conversion Complete Interrupt Enable Interrupt request enabled Interrupt request enabled U1TXIE: UART1 Transmitter Interrupt Enable Interrupt request enabled Interrupt request enabled U1RXIE: UART1 Receiver Interrupt Enable Interrupt request enabled Interrupt request enabled SPI1IE: SPI1 Event Interrupt Enable Interrupt request enabled Interrupt request enabled SPI1EIE: SPI1 Error Interrupt Enable Interrupt request enabled Interrupt request enabled T3IE: Timer3 Interrupt Enable Interrupt request enabled Interrupt request enabled T2IE: Timer2 Interrupt Enable Interrupt request enabled Interrupt request enabled OC2IE: Output Compare Channel Interrupt Enable Interrupt request enabled Interrupt request enabled IC2IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read T1IE: Timer1 Interrupt Enable Interrupt request enabled Interrupt request enabled OC1IE: Output Compare Channel Interrupt Enable Interrupt request enabled Interrupt request enabled
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REGISTER 6-8:
IEC0: INTERRUPT ENABLE CONTROL REGISTER (CONTINUED)
IC1IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled INT0IE: External Interrupt Enable Interrupt request enabled Interrupt request enabled
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REGISTER 6-9:
R/W-0 IC8IE Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 IC7IE R/W-0 INT1IE R/W-0 CNIE R/W-0 MI2C1IE
IEC1: INTERRUPT ENABLE CONTROL REGISTER
R/W-0 INT2IE R/W-0 SI2C1IE
Unimplemented: Read INT2IE: External Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read IC8IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled IC7IE: Input Capture Channel Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read INT1IE: External Interrupt Enable Interrupt request enabled Interrupt request enabled CNIE: Input Change Notification Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read MI2C1IE: I2C1 Master Events Interrupt Enable Interrupt request enabled Interrupt request enabled SI2C1IE: I2C1 Slave Events Interrupt Enable Interrupt request enabled Interrupt request enabled
12-8
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REGISTER 6-10:
Legend: Readable Value 15-2 Writable Unimplemented bit, read cleared unknown R/W-0 U1EIE
IEC4: INTERRUPT ENABLE CONTROL REGISTER
Unimplemented: Read U1EIE: UART1 Error Interrupt Enable Interrupt request enabled Interrupt request enabled Unimplemented: Read
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REGISTER 6-11:
Legend: Readable Value 14-12 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 IC1IP<2:0> R/W-0 R/W-1 R/W-0 INT0IP<2:0>
IPC0: INTERRUPT PRIORITY CONTROL REGISTER
R/W-1 R/W-0 T1IP<2:0> R/W-0 R/W-1 R/W-0 OC1IP<2:0> R/W-0 R/W-0
Unimplemented: Read T1IP<2:0>: Timer1 Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read OC1IP<2:0>: Output Compare Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read IC1IP<2:0>: Input Capture Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read INT0IP<2:0>: External Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled
10-8
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REGISTER 6-12:
Legend: Readable Value 14-12 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 IC2IP<2:0> R/W-0
IPC1: INTERRUPT PRIORITY CONTROL REGISTER
R/W-1 R/W-0 T2IP<2:0> R/W-0 R/W-1 R/W-0 OC2IP<2:0> R/W-0
Unimplemented: Read T2IP<2:0>: Timer2 Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read OC2IP<2:0>: Output Compare Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read IC2IP<2:0>: Input Capture Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read
10-8
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REGISTER 6-13:
Legend: Readable Value 14-12 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 SPI1EIP<2:0> R/W-0 R/W-1 R/W-0 T3IP<2:0>
IPC2: INTERRUPT PRIORITY CONTROL REGISTER
R/W-1 R/W-0 U1RXIP<2:0> R/W-0 R/W-1 R/W-0 SPI1IP<2:0> R/W-0 R/W-0
Unimplemented: Read U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read SPI1IP<2:0>: SPI1 Event Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read T3IP<2:0>: Timer3 Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled
10-8
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REGISTER 6-14:
Legend: Readable Value 15-7 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 AD1IP<2:0> R/W-0 R/W-1 R/W-0 U1TXIP<2:0>
IPC3: INTERRUPT PRIORITY CONTROL REGISTER
R/W-0
Unimplemented: Read AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled
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REGISTER 6-15:
Legend: Readable Value 14-12 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 MI2C1IP<2:0> R/W-0 R/W-1 R/W-0 SI2C1IP<2:0>
IPC4: INTERRUPT PRIORITY CONTROL REGISTER
R/W-1 R/W-0 CNIP<2:0> R/W-0 R/W-0
Unimplemented: Read CNIP<2:0>: Change Notification Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled
11-7
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REGISTER 6-16:
Legend: Readable Value 14-12 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 INT1IP<2:0>
IPC5: INTERRUPT PRIORITY CONTROL REGISTER
R/W-1 R/W-0 IC8IP<2:0> R/W-0 R/W-1 R/W-0 IC7IP<2:0> R/W-0 R/W-0
Unimplemented: Read IC8IP<2:0>: Input Capture Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read IC7IP<2:0>: Input Capture Channel Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read INT1IP<2:0>: External Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled
10-8
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REGISTER 6-17:
Legend: Readable Value 15-7 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 INT2IP<2:0> R/W-0
IPC7: INTERRUPT PRIORITY CONTROL REGISTER
Unimplemented: Read INT2IP<2:0>: External Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read
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REGISTER 6-18:
Legend: Readable Value 15-7 Writable Unimplemented bit, read cleared unknown R/W-1 R/W-0 U1EIP<2:0> R/W-0
IPC16: INTERRUPT PRIORITY CONTROL REGISTER
Unimplemented: Read U1EIP<2:0>: UART1 Error Interrupt Priority bits Interrupt priority (highest priority interrupt) Interrupt priority Interrupt source disabled Unimplemented: Read
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REGISTER 6-19:
Legend: Readable Value 15-12 11-8 Writable Unimplemented bit, read cleared unknown VECNUM<6:0>
INTTREG: INTERRUPT CONTROL STATUS REGISTER
ILR<3:0>
Unimplemented: Read ILR: Interrupt Priority Level bits 1111 Interrupt Priority Level 0001 Interrupt Priority Level 0000 Interrupt Priority Level Unimplemented: Read VECNUM: Vector Number Pending Interrupt bits 0111111 Interrupt Vector pending number 0000001 Interrupt Vector pending number 0000000 Interrupt Vector pending number
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6.4.1
Interrupt Setup Procedures
INITIALIZATION
6.4.3
TRAP SERVICE ROUTINE
configure interrupt source initialization: NSTDIS (INTCON1<15>) nested interrupts desired. Select user-assigned priority level interrupt source writing control bits appropriate IPCx register. priority level will depend specific application type interrupt source. multiple priority levels desired, IPCx register control bits enabled interrupt sources programmed same non-zero value. Note: device Reset, IPCx registers initialized such that user interrupt sources assigned priority level
Trap Service Routine (TSR) coded like ISR, except that appropriate trap status flag INTCON1 register must cleared avoid re-entry into TSR.
6.4.4
INTERRUPT DISABLE
user interrupts disabled using this procedure: Push current value onto software stack using PUSH instruction. Force priority level inclusive ORing value with SRL.
enable user interrupts, instruction used restore previous value. Note: Only user interrupts with priority level lower disabled. Trap sources (level 8-level cannot disabled.
Clear interrupt flag status associated with peripheral associated IFSx register. interrupt enable control associated with source appropriate IECx register enable interrupt source.
DISI instruction provides convenient disable interrupts priority levels fixed period time. Level interrupt sources disabled DISI instruction.
6.4.2
INTERRUPT SERVICE ROUTINE
method used declare initialize with correct vector address depends programming language Assembler) language development toolsuite used develop application. general, user application must clear interrupt flag appropriate IFSx register source interrupt that handles. Otherwise, program will re-enter immediately after exiting routine. coded assembly language, must terminated using RETFIE instruction unstack saved value, value priority level.
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NOTES:
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Note:
OSCILLATOR CONFIGURATION
This data sheet summarizes features PIC24HJ32GP202/204 PIC24HJ16GP304 devices. intended comprehensive reference source. complement information this data sheet, refer "PIC24H Family Reference Manual".
PIC24HJ32GP202/204 PIC24HJ16GP304 oscillator system provides: External internal oscillator options clock sources
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