28/44-Pin General Purpose, 16-Bit Flash Microcontrollers 2007 Mic
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PIC24FJ64GA004 Family Data Sheet
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
2007 Microchip Technology Inc.
DS39881B
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Trademarks Microchip name logo, Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, MATE, PowerSmart, rfPIC, SmartShunt registered trademarks Microchip Technology Incorporated U.S.A. other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, logo, SEEVAL, SmartSensor Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2007, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper.
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona, Gresham, Oregon Mountain View, California. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
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2007 Microchip Technology Inc.
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28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
Modified Harvard Architecture MIPS Operation Internal Oscillator with Option Multiple Divide Options 17-Bit 17-Bit Single-Cycle Hardware Multiplier 32-Bit 16-Bit Hardware Divider 16-Bit 16-Bit Working Register Array Compiler Optimized Instruction Architecture: base instructions Flexible addressing modes Address Generation Units Separate Read Write Addressing Data Memory
Analog Features:
10-Bit, 13-Channel Analog-to-Digital Converter: ksps conversion rate Conversion available during Sleep Idle Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:
Peripheral Select: Allows independent mapping many peripherals available pins (44-pin devices) Continuous hardware integrity checking safety interlocks prevent unintentional configuration changes 8-Bit Parallel Master/Slave Port (PMP/PSP): 16-bit multiplexed addressing, with dedicated address pins 44-pin devices Programmable polarity control lines Hardware Real-Time Clock/Calendar (RTCC): Provides clock, calendar alarm functions Programmable Cyclic Redundancy Check (CRC) 3-Wire/4-Wire modules (support Frame modes) with 8-Level FIFO Buffer I2Cmodules support Multi-Master/Slave mode 7-Bit/10-Bit Addressing UART modules: Supports RS-485, RS-232, On-chip hardware encoder/decoder IrDA® Auto-wake-up Start Auto-Baud Detect 4-level deep FIFO buffer Five 16-Bit Timers/Counters with Programmable Prescaler Five 16-Bit Capture Inputs Five 16-Bit Compare/PWM Outputs Configurable Open-Drain Outputs Digital Pins External Interrupt Sources
Special Microcontroller Features:
Operating Voltage Range 2.0V 3.6V 5.5V Tolerant Input (digital pins only) High-Current Sink/Source mA/18 Pins Flash Program Memory: 10,000 erase/write 20-year data retention minimum Power Management modes: Sleep, Idle, Doze Alternate Clock modes Operating current A/MIPS typical 2.0V Sleep current typical 2.0V Fail-Safe Clock Monitor Operation: Detects clock failure switches on-chip, low-power oscillator On-Chip, 2.5V Regulator with Tracking mode Power-on Reset (POR), Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip, Low-Power Oscillator Reliable Operation In-Circuit Serial Programming(ICSPTM) In-Circuit Debug (ICD) Pins JTAG Boundary Scan Programming Support
Comparators
Remappable Peripherals 10-Bit (ch) Program Memory (bytes) Remappable Pins SRAM (bytes) Compare/ Output Capture Input Timers 16-Bit PIC24FJ Device UART IrDA® I2CPins
PMP/PSP
16GA002 32GA002 48GA002 64GA002 16GA004 32GA004 48GA004 64GA004
2007 Microchip Technology Inc.
DS39881B-page
JTAG
PIC24FJ64GA004 FAMILY
Diagrams
28-Pin SPDIP, SSOP, SOIC(1)
MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 AN9/RP15/CN11/PMCS1/RB15 AN11/RP13/CN13/PMRD/RB13 AN12/RP12/CN14/PMD0/RB12 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7
28-Pin QFN(1)
AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3
PIC24FJXXGA002 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 PGC3/EMUC3/RP6/SCL1 /CN24/PMD6/RB6 RP7/INT0/CN23/PMD5/RB7 TCK/RP8/SCL1/CN22/PMD4/RB8
AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AN9/RP15/CN11/PMCS1/RB15
PIC24FJXXGA002
AN11/RP13/CN13/PMRD/RB13 AN12/RP12/CN14/PMD0/RB12 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9
Legend: Note
represents remappable peripheral pins. pins configured function following peripherals: timers, UART, input capture, output compare, PWM, comparator digital outputs SPI. more information, Section "Peripheral Select" specific peripheral sections. Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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Diagrams (Continued)
RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/T1CK/CN0/RA4 TMS/PMA10/RA10 TCK/PMA7/RA7 AN9/RP15/CN11/PMCS1/RB15 AVSS AVDD MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1
44-Pin
RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13
PIC24FJXXGA004
SOSCI/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/CN30/RA2 AN8/RP18/CN10/PMA2/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1IN+/RP3/SCL2/CN7/RB3 AN4/C1IN-/RP2/SDA2/CN6/RB2
Legend: Note
represents remappable peripheral pins. pins configured function following peripherals: timers, UART, input capture, output compare, PWM, comparator digital outputs SPI. more information, Section "Peripheral Select" specific peripheral sections. Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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Diagrams (Continued)
RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/T1CK/CN0/RA4 RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13
44-Pin TQFP
Legend: Note
represents remappable peripheral pins. pins configured function following peripherals: timers, UART, input capture, output compare, PWM, comparator digital outputs SPI. more information, Section "Peripheral Select" specific peripheral sections. Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
TMS/PMA10/RA10 TCK/PMA7/RA7 AN9/RP15/CN11/PMCS1/RB15 AVSS AVDD MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1
PIC24FJXXGA004
SOSCI/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/CN30/RA2 AN8/RP18/CN10/PMA2/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1IN+/RP3/SCL2/CN7/RB3 AN4/C1IN-/RP2/SDA2/CN6/RB2
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Table Contents
Device Overview Memory Organization Flash Program Memory. Resets Interrupt Controller Oscillator Configuration Power-Saving Features. Ports 10.0 Timer1 11.0 Timer2/3 Timer4/5 12.0 Input Capture. 13.0 Output Compare. 14.0 Serial Peripheral Interface (SPI). 15.0 Inter-Integrated Circuit (I2CTM) 16.0 Universal Asynchronous Receiver Transmitter (UART) 17.0 Parallel Master Port (PMP). 18.0 Real-Time Clock Calendar (RTCC) 19.0 Programmable Cyclic Redundancy Check (CRC) Generator 20.0 10-bit High-Speed Converter. 21.0 Comparator Module. 22.0 Comparator Voltage Reference. 23.0 Special Features 24.0 Development Support. 25.0 Instruction Summary 26.0 Electrical Characteristics 27.0 Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
2007 Microchip Technology Inc.
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Most Current Data Sheet
obtain most up-to-date version this data sheet, please register Worldwide site http://www.microchip.com determine version data sheet examining literature number found bottom outside corner page. last character literature number version number, (e.g., DS30000A version document DS30000).
Errata
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DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information following devices: PIC24FJ16GA002 PIC24FJ32GA002 PIC24FJ48GA002 PIC24FJ64GA002 PIC24FJ16GA004 PIC24FJ32GA004 PIC24FJ48GA004 PIC24FJ64GA004 devices PIC24FJ64GA004 family incorporate range features that significantly reduce power consumption during operation. items include: On-the-Fly Clock Switching: device clock changed under software control Timer1 source internal, low-power oscillator during operation, allowing user incorporate power-saving ideas into their software designs. Doze Mode Operation: When timing-sensitive applications, such serial communications, require uninterrupted operation peripherals, clock speed selectively reduced, allowing incremental power savings without missing beat. Instruction-Based Power-Saving Modes: microcontroller suspend operations, selectively shut down core while leaving peripherals active, with single instruction software.
This family introduces line Microchip devices: 16-bit microcontroller family with broad peripheral feature enhanced computational performance. PIC24FJ64GA004 family offers migration option those high-performance applications which outgrowing their 8-bit platforms, don't require numerical processing power digital signal processor.
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.3
Central PIC24F devices 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC® digital signal controllers. PIC24F core offers wide range enhancements, such 16-bit data 24-bit address paths with ability move information between data memory spaces Linear addressing Mbytes (program space) Kbytes (data) 16-element working register array with built-in software stack support hardware multiplier with support integer math Hardware support 16-bit division instruction that supports multiple addressing modes optimized high-level languages such Operational performance MIPS
OSCILLATOR OPTIONS FEATURES
devices PIC24FJ64GA004 family offer five different oscillator options, allowing users range choices developing application hardware. These include: Crystal modes using crystals ceramic resonators. External Clock modes offering option divide-by-2 clock output. Fast Internal Oscillator (FRC) with nominal output, which also divided under software control provide clock speeds kHz. Phase Lock Loop (PLL) frequency multiplier, available external oscillator modes oscillator, which allows clock speeds MHz. separate internal oscillator (LPRC) with fixed output, which provides low-power option timing-insensitive applications. internal oscillator block also provides stable reference source Fail-Safe Clock Monitor. This option constantly monitors main clock source against reference signal provided internal oscillator enables controller switch internal oscillator, allowing continued low-speed operation safe application shutdown.
2007 Microchip Technology Inc.
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1.1.4 EASY MIGRATION
Regardless memory size, devices share same rich peripherals, allowing smooth migration path applications grow evolve. consistent pinout scheme used throughout entire family also aids migrating next larger device. This true when moving between devices with same count, even jumping from 28-pin 44-pin devices. PIC24F family pin-compatible with devices dsPIC33 family, shares some compatibility with pinout schema PIC18 dsPIC30. This extends ability applications grow from relatively simple, powerful complex, still selecting Microchip device.
Details Individual Family Members
Devices PIC24FJ64GA004 family available 28-pin 44-pin packages. general block diagram devices shown Figure 1-1. devices differentiated from each other ways: Flash program memory Kbytes PIC24FJ64GA devices, Kbytes PIC24FJ48GA devices, Kbytes PIC24FJ32GA devices Kbytes PIC24FJ16GA devices). Internal SRAM memory PIC24FJ16GA devices, other devices family). Available pins ports pins ports 28-pin devices pins ports 44-pin devices).
Other Special Features
Communications: PIC24FJ64GA004 family incorporates range serial communication peripherals handle range application requirements. There independent modules that support both Master Slave modes operation. Devices also have, through peripheral select feature, independent UARTs with built-in IrDA encoder/decoders modules. Peripheral Select: peripheral select feature allows most digital peripherals mapped over fixed digital pins. Users independently input and/or output many digital peripherals pins. Parallel Master/Enhanced Parallel Slave Port: general purpose ports reconfigured enhanced parallel data communications. this mode, port configured both master slave operations, supports 8-bit 16-bit data transfers with external address lines Master modes. Real-Time Clock/Calendar: This module implements full-featured clock calendar with alarm functions hardware, freeing timer resources program memory space core application. 10-Bit Converter: This module incorporates programmable acquisition time, allowing channel selected conversion initiated without waiting sampling period, well faster sampling speeds.
other features devices this family identical. These summarized Table 1-1. list features available PIC24FJ64GA004 family devices, sorted function, shown Table 1-2. Note that this table shows location individual peripheral features they multiplexed same pin. This information provided pinout diagrams beginning data sheet. Multiplexed features sorted priority given feature, with highest priority peripheral being listed first.
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TABLE 1-1: DEVICE FEATURES PIC24FJ64GA004 FAMILY
16GA002 32GA002 48GA002 64GA002 16GA004 32GA004 48GA004 Features 64GA004 22,016
Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) Ports Total Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART (3-wire/4-wire) I2CParallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Remappable Pins Resets (and delays) Ports 5,504 4096 11,008 16,512 8192
22,016 5,504 4096 (39/4) Ports 5(1) 5(1) 5(1) 2(1) 2(1) POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction Hardware Traps, Configuration Word Mismatch (PWRT, OST, Lock) Base Instructions, Multiple Addressing Mode Variations 28-Pin SPDIP/SSOP/SOIC/QFN 44-Pin QFN/TQFP 11,008 16,512 8192
Instruction Packages Note
Peripherals accessible through remappable pins.
2007 Microchip Technology Inc.
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PIC24FJ64GA004 FAMILY
FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Interrupt Controller
Data
Data Latch Program Counter Repeat Stack Control Control Logic Logic Data Address Latch PORTA(1) RA0:RA9
Table Data Access Control Block
Address Latch Program Memory
Read Write
PORTB RB0:RB15
Data Latch
Address
Literal Data Inst Latch
PORTC(1) RC0:RC9
Inst Register Instruction Decode Control Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD(2) 16-Bit RP(1) RP0:RP25 Divide Support 17x17 Multiplier Array
OSCO/CLKO OSCI/CLKI
Timing Generation FRC/LPRC Oscillators Precision Band Reference
DISVREG Voltage Regulator
VDDCORE/VCAP
VDD,
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit
Comparators(3)
PMP/PSP
IC1-5(3)
PWM/ OC1-5(3)
CN1-22(1)
SPI1/2(3)
I2C1/2
UART1/2(3)
Note
pins features implemented device pinout configurations. Table port descriptions. functionality provided when on-board voltage regulator enabled. Peripheral I/Os accessible through remappable pins.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Number Function 28-Pin SPDIP/ SSOP/SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
AN10 AN11 AN12 AVDD AVSS C1INC1IN+ C2INC2IN+ CLKI CLKO Legend: Note
Analog Inputs.
Positive Supply Analog Modules. Ground Reference Analog Modules. Comparator Negative Input. Comparator Positive Input. Comparator Negative Input. Comparator Positive Input. Main Clock Input Connection. System Clock Output.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SSOP/SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CVREF DISVREG EMUC1 EMUD1 EMUC2 EMUD2 EMUC3 EMUD3 INT0 MCLR Legend: Note
Interrupt-on-Change Inputs.
Comparator Voltage Reference Output. Voltage Regulator Disable. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. External Interrupt Input. Master Clear (device Reset) Input. This line brought cause Reset.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SSOP/SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
OSCI OSCO PGC1 PGD1 PGC2 PGD2 PGC3 PGD3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend: Note
Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger ICSPProgramming Clock In-Circuit Debugger ICSP Programming Data. In-Circuit Debugger ICSP Programming Clock. In-Circuit Debugger ICSP Programming Data. In-Circuit Debugger ICSP Programming Clock. In-Circuit Debugger ICSP Programming Data. Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address Input (Buffered Slave modes) Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select Strobe/Address Parallel Master Port Data (Demultiplexed Master mode) Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe. Parallel Master Port Write Strobe.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SSOP/SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
RA10 RB10 RB11 RB12 RB13 RB14 RB15 Legend: Note
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SSOP/SOIC 15(1) 14(1) 28-Pin 12(1) 11(1) 41(1) 44-Pin QFN/TQFP 42(1) Input Buffer Description
RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RTCC SCL1 SCL2 SDA1 SDA2 SOSCI SOSCO Legend: Note
Remappable Peripheral.
Real-Time Clock Alarm Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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TABLE 1-2: PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Number Function 28-Pin SPDIP/ SSOP/SOIC 28-Pin 44-Pin QFN/TQFP Input Buffer Description
T1CK VDDCAP VDDCORE VREFVREF+ Legend: Note
Timer1 Clock. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. Positive Supply Peripheral Digital Logic Pins. External Filter Capacitor Connection (regulator enabled). Positive Supply Microcontroller Core Logic (regulator disabled). Comparator Reference Voltage (low) Input. Comparator Reference Voltage (high) Input. Ground Reference Logic Pins.
input buffer Schmitt Trigger input buffer Analog level input/output I2C= I2C/SMBus input buffer Alternative multiplexing SDA1 SCL1 when I2C1SEL Configuration cleared.
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Note:
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer associated "PIC24F Family Reference Manual" chapter.
most instructions, core capable executing data program data) memory read, working register (data) read, data memory write program (instruction) memory read instruction cycle. result, three-parameter instructions supported, allowing trinary operations (that executed single cycle. high-speed, 17-bit 17-bit multiplier been included significantly enhance core arithmetic capability throughput. multiplier supports Signed, Unsigned Mixed mode, 16-bit 16-bit 8-bit 8-bit, integer multiplication. multiply instructions execute single cycle. 16-bit been enhanced with integer divide assist hardware that supports iterative non-restoring divide algorithm. operates conjunction with REPEAT instruction looping mechanism selection iterative divide instructions support 32-bit 16-bit), divided 16-bit, integer signed unsigned division. divide operations require cycles complete interruptible cycle boundary. PIC24F vectored exception scheme with sources non-maskable traps interrupt sources. Each interrupt source assigned seven priority levels. block diagram shown Figure 2-1.
PIC24F 16-bit (data) modified Harvard architecture with enhanced instruction 24-bit instruction word with variable length opcode field. Program Counter (PC) bits wide addresses instructions user program memory space. single-cycle instruction prefetch mechanism used help maintain throughput provides predictable execution. instructions execute single cycle, with exception instructions that change program flow, double-word move (MOV.D) instruction table instructions. Overhead-free program loop constructs supported using REPEAT instructions, which interruptible point. PIC24F devices have sixteen, 16-bit working registers programmer's model. Each working registers data, address address offset register. 16th working register (W15) operates Software Stack Pointer interrupts calls. upper Kbytes data space memory optionally mapped into program space word boundary defined 8-bit Program Space Visibility Page Address (PSVPAG) register. program data space mapping feature lets instruction access program space were data space. Instruction Architecture (ISA) been significantly enhanced beyond that PIC18, maintains acceptable level backward compatibility. PIC18 instructions addressing modes supported, either directly, through simple macros. Many enhancements have been driven compiler efficiency needs. core supports Inherent operand), Relative, Literal, Memory Direct three groups addressing modes. modes support Register Direct various Register Indirect modes. Each group offers seven addressing modes. Instructions associated with predefined addressing modes depending upon their functional requirements.
Programmer's Model
programmer's model PIC24F shown Figure 2-2. registers programmer's model memory mapped manipulated directly instructions. description each register provided Table 2-1. registers associated with programmer's model memory mapped.
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FIGURE 2-1:
Table Data Access Control Block Interrupt Controller Data Data Latch Program Counter Loop Stack Control Control Logic Logic Data Address Latch
PIC24F CORE BLOCK DIAGRAM
RAGU WAGU
Address Latch
Program Memory Address Data Latch Latch Literal Data
Instruction Decode Control
Instruction
Control Signals Various Blocks
Hardware Multiplier Divide Support
Register Array
16-Bit
Peripheral Modules
DS39881B-page
2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 2-1:
through SPLIM TBLPAG PSVPAG RCOUNT CORCON
CORE REGISTERS
Description Working Register Array 23-Bit Program Counter STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER'S MODEL
(WREG) Frame Pointer Stack Pointer Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register PSVPAG RCOUNT STATUS Register (SR) Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM TBLPAG
Control Register (CORCON)
IPL3
Registers bits shadowed PUSH.S POP.S instructions.
2007 Microchip Technology Inc.
DS39881B-page
PIC24FJ64GA004 FAMILY
Control Registers
STATUS REGISTER
R/W-0 R/W-0(1) IPL1
REGISTER 2-1:
R/W-0(1) IPL2 Legend: Readable Value 15-9
R/W-0(1) IPL0(2)
R/W-0
R/W-0
R/W-0
R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read Half Carry/Borrow carry-out from low-order (for byte-sized data) low-order (for word-sized data) result occurred carry-out from low-order result occurred IPL2:IPL0: Interrupt Priority Level Status bits(1,2) interrupt priority level (15); user interrupts disabled. interrupt priority level (14) Interrupt Priority Level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level REPEAT Loop Active REPEAT loop progress REPEAT loop progress Negative Result negative Result non-negative (zero positive) Overflow Overflow occurred signed (2's complement) arithmetic this arithmetic operation overflow occurred Zero operation which effects some time past most recent operation which effects cleared (i.e., non-zero result) Carry/Borrow carry-out from Most Significant result occurred carry-out from Most Significant result occurred Status bits read-only when NSTDIS (INTCON1<15>) Status bits concatenated with IPL3 (CORCON<3>) form Interrupt Priority Level (IPL). value parentheses indicates when IPL3
Note
DS39881B-page
2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
REGISTER 2-2:
Legend: Readable Value 15-4 Writable Unimplemented bit, read cleared unknown R/C-0 IPL3(1) R/W-0
CORCON: CONTROL REGISTER
Unimplemented: Read IPL3: Interrupt Priority Level Status bit(1) interrupt priority level greater than interrupt priority level less PSV: Program Space Visibility Data Space Enable Program space visible data space Program space visible data space Unimplemented: Read User interrupts disabled when IPL3
Note
Arithmetic Logic Unit (ALU)
PIC24F bits wide capable addition, subtraction, shifts logic operations. Unless otherwise mentioned, arithmetic operations complement nature. Depending operation, affect values Carry (C), Zero (Z), Negative (N), Overflow (OV) Digit Carry (DC) Status bits register. Status bits operate Borrow Digit Borrow bits, respectively, subtraction operations. perform 8-bit 16-bit operations, depending mode instruction that used. Data operation come from register array, data memory, depending addressing mode instruction. Likewise, output data from written register array data memory location.
PIC24F incorporates hardware support both multiplication division. This includes dedicated hardware multiplier support hardware 16-bit divisor division.
2.3.1
MULTIPLIER
contains high-speed, 17-bit 17-bit multiplier. supports unsigned, signed mixed sign operation several multiplication modes: 16-bit 16-bit signed 16-bit 16-bit unsigned 16-bit signed 5-bit (literal) unsigned 16-bit unsigned 16-bit unsigned 16-bit unsigned 5-bit (literal) unsigned 16-bit unsigned 16-bit signed 8-bit unsigned 8-bit unsigned
2007 Microchip Technology Inc.
DS39881B-page
PIC24FJ64GA004 FAMILY
2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT
divide block supports 32-bit/16-bit 16-bit/16-bit signed unsigned integer divide operations with following data sizes: 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide PIC24F supports both single single-cycle, multi-bit arithmetic logic shifts. Multi-bit shifts implemented using shifter block, capable performing 15-bit arithmetic right shift, 15-bit left shift, single cycle. multi-bit shift instructions only support Register Direct Addressing both operand source result destination. full summary instructions that shift operation provided below Table 2-2.
quotient divide instructions ends remainder Sixteen-bit signed unsigned instructions specify register both 16-bit divisor (Wn), register (aligned) pair (W(m 1):Wm) 32-bit dividend. divide algorithm takes cycle divisor, both 32-bit/16-bit 16-bit/16-bit instructions take same number cycles execute.
TABLE 2-2:
Instruction
INSTRUCTIONS THAT SINGLE MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register more bits. Shift left source register more bits. Logical shift right source register more bits.
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2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
MEMORY ORGANIZATION
Harvard architecture devices, PIC24F microcontrollers feature separate program data memory spaces busses. This architecture also allows direct access program memory from data space during code execution. from either 23-bit Program Counter (PC) during program execution, from table operation data space remapping, described Section "Interfacing Program Data Memory Spaces". User access program memory space restricted lower half address range (000000h 7FFFFFh). exception TBLRD/TBLWT operations which TBLPAG<7> permit access Configuration bits device sections configuration memory space. Memory maps PIC24FJ64GA004 family devices shown Figure 3-1.
Program Address Space
program address memory space PIC24FJ64GA004 family devices instructions. space addressable 24-bit value derived
FIGURE 3-1:
PROGRAM SPACE MEMORY PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ32GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ16GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (5.5K instructions) Flash Config Words User Memory Space
PIC24FJ48GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ64GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Flash Program Memory (11K instructions)
User Flash Program Memory (16K instructions) User Flash Program Memory (22K instructions)
002BFEh 002C00h
Flash Config Words Flash Config Words
0057FEh 005800h 0083FEh 008400h Flash Config Words 00ABFEh 00AC00h
Unimplemented Read
Unimplemented Read Unimplemented Read Unimplemented Read
7FFFFFh 800000h
Reserved Configuration Memory Space
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
Reserved
DEVID
DEVID
DEVID
DEVID
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas shown scale.
2007 Microchip Technology Inc.
DS39881B-page
PIC24FJ64GA004 FAMILY
3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
program memory space organized word-addressable blocks. Although treated bits wide, more appropriate think each address program memory lower upper word, with upper byte upper word being unimplemented. lower word always even address, while upper word address (Figure 3-2). Program memory addresses always word-aligned lower word, addresses incremented decremented during code execution. This arrangement also provides compatibility with data memory space addressing makes possible access data program memory space. PIC24FJ64GA004 family devices, words on-chip program memory reserved configuration information. device Reset, configuration information copied into appropriate Configuration registers. addresses Flash Configuration Word devices PIC24FJ64GA004 family shown Table 3-1. Their location memory shown with other memory vectors Figure 3-1. Configuration Words program memory compact format. actual Configuration bits mapped several different registers configuration memory space. Their order Flash Configuration Words reflect corresponding arrangement configuration space. Additional details device Configuration Words provided Section 23.1 "Configuration Bits".
3.1.2
HARD MEMORY VECTORS TABLE 3-1: FLASH CONFIGURATION WORDS PIC24FJ64GA004 FAMILY DEVICES
Program Memory words) Configuration Word Addresses 002BFCh: 002BFEh 0057FCh: 0057FEh 0083FCh: 0083FEh 00ABFCh: 00ABFEh
PIC24F devices reserve addresses between 00000h 000200h hard coded program execution vectors. hardware Reset vector provided redirect code execution from default value device Reset actual start code. GOTO instruction programmed user 000000h, with actual address start code 000002h. PIC24F devices also have interrupt vector tables, located from 000004h 0000FFh 000100h 0001FFh. These vector tables allow each many device interrupt sources handled separate ISRs. more detailed discussion interrupt vector tables provided Section "Interrupt Vector Table".
Device
PIC24FJ16GA PIC24FJ32GA PIC24FJ48GA PIC24FJ64GA
FIGURE 3-2:
Address
PROGRAM MEMORY ORGANIZATION
most significant word least significant word 000000h 000002h 000004h 000006h Instruction Width Address (lsw Address)
000001h 000003h 000005h 000007h
00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read `0')
DS39881B-page
2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Data Address Space
PIC24F core separate, 16-bit wide data memory space, addressable single linear range. data space accessed using Address Generation Units (AGUs), each read write operations. data space memory shown Figure 3-3. Effective Addresses (EAs) data memory space bits wide point bytes within data space. This gives data space address range Kbytes words. lower half data memory space (that when EA<15> used implemented memory addresses, while upper half (EA<15> reserved program space visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). PIC24FJ64GA family devices implement total Kbytes data memory. Should point location outside this area, zero word byte will returned.
3.2.1
DATA SPACE WIDTH
data memory space organized byte-addressable, 16-bit wide blocks. Data aligned data memory registers 16-bit words, data space resolve bytes. Least Significant Bytes each word have even addresses, while Most Significant Bytes have addresses.
FIGURE 3-3:
DATA SPACE MEMORY PIC24FJ64GA004 FAMILY DEVICES(1)
Address 0001h 07FFh 0801h Address 0000h 07FEh 0800h Space Near Data Space
Space
Implemented Data 1FFFh 2001h 27FFh(2) 2801h
Data 1FFEh 2000h 27FEh(2) 2800h Unimplemented Read 7FFFh 8001h 7FFFh 8000h
Program Space Visibility Area
FFFFh
FFFEh
Note
Data memory areas shown scale. Upper memory limit PIC24FJ16GAXXX devices 17FFh.
2007 Microchip Technology Inc.
DS39881B-page
PIC24FJ64GA004 FAMILY
3.2.2 DATA MEMORY ORGANIZATION ALIGNMENT
maintain backward compatibility with PIC® devices improve data space memory usage efficiency, PIC24F instruction supports both word byte operations. consequence byte accessibility, effective address calculations internally scaled step through word-aligned memory. example, core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result value byte operations word operations. Data byte reads will read complete word which contains byte, using determine which byte select. selected byte placed onto data path. That data memory registers organized parallel, byte-wide entities with shared (word) address decode separate write lines. Data byte writes only write corresponding side array register which matches byte address. word accesses must aligned even address. Misaligned word data fetches supported, care must taken when mixing byte word operations, translating from 8-bit code. misaligned read write attempted, address error trap will generated. error occurred read, instruction underway completed; occurred write, instruction will executed write will occur. either case, trap then executed, allowing system and/or user examine machine state prior execution address Fault. byte loads into register loaded into Least Significant Byte. Most Significant Byte modified. sign-extend instruction (SE) provided allow users translate 8-bit signed data 16-bit signed values. Alternatively, 16-bit unsigned data, users clear register executing zero-extend (ZE) instruction appropriate address. Although most instructions capable operating word byte data sizes, should noted that some instructions operate only words.
3.2.3
NEAR DATA SPACE
8-Kbyte area between 0000h 1FFFh referred near data space. Locations this space directly addressable 13-bit absolute address field within memory direct instructions. remainder data space addressable indirectly. Additionally, whole data space addressable using instructions, which support Memory Direct Addressing with 16-bit address field.
3.2.4
SPACE
first Kbytes near data space, from 0000h 07FFh, primarily occupied with Special Function Registers (SFRs). These used PIC24F core peripheral modules controlling operation device. SFRs distributed among modules that they control generally grouped together module. Much space contains unused addresses; these read `0'. diagram space, showing where SFRs actually implemented, shown Table 3-2. Each implemented area indicates 32-byte region where least address implemented SFR. complete listing implemented SFRs, including their addresses, shown Tables through 3-24.
TABLE 3-2:
IMPLEMENTED REGIONS DATA SPACE
Space Address xx00 xx20 Core Timers I2CA/D RTC/Comp UART System Capture NVM/PMD xx40 xx60 Compare xx80 xxA0 Interrupts xxC0 xxE0
000h 100h 200h 300h 400h 500h 600h 700h
Legend: implemented SFRs this block
DS39881B-page
2007 Microchip Technology Inc.
TABLE 3-3:
Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Working Register Stack Pointer Limit Value Register Program Counter Byte Register Repeat Loop Counter Register IPL2 IPL1 IPL0 Disable Interrupts Counter Register IPL3 Program Counter High Byte Register Table Memory Page Address Register Program Space Visibility Page Address Register
CORE REGISTERS
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
File Name
Addr
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
2007 Microchip Technology Inc.
CN13IE CN29IE CN27IE CN12PUE CN28IE(1) CN12IE CN11IE CN10IE(1) CN26IE(1)
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
002E
PIC24FJ64GA004 FAMILY
CN9IE(1) CN25IE(1) CN9PUE
0030
TBLPAG
0032
PSVPAG
0034
RCOUNT
0036
0042
CORCON
0044
DISICNT
0052
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-4:
REGISTER
CN8IE(1) CN24IE CN8PUE
File Addr Name
CN7IE CN23IE CN7PUE
CN6IE CN22IE CN6PUE
CN5IE CN21IE CN5PUE
CN4IE CN20IE(1) CN4PUE
CN3IE CN19IE(1) CN3PUE
CN2IE CN18IE(1) CN2PUE
CN1IE CN17IE(1) CN1PUE
CN0IE CN16IE CN0PUE
Resets 0000 0000 0000 0000
CNEN1 0060
CN15IE
CN14IE
CNEN2 0062
CN30IE
CNPU1 0068 CN15PUE CN14PUE CN13PUE
CN11PUE CN10PUE
CNPU2 006A
CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE
DS39881B-page
Legend: Note
unimplemented, read `0'. Reset values shown hexadecimal. Bits available 28-pin devices; read `0'.
TABLE 3-5:
AD1IF INT2IF LVDIF T3IE LVDIE OC1IP0 OC2IP0 SPI1IP0 CMIP0 OC4IP0 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 OC3IP2 MI2C1P2 MI2C1P1 OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 U1ERIP2 U1ERIP1 AD1IP2 AD1IP1 SPF1IP2 SPF1IP1 IC2IP2 IC2IP1 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 U1ERIP0 IC1IP2 IC1IP1 IC1IP0 CRCIE IC5IE IC4IE IC3IE INT1IE CNIE T2IE OC2IE IC2IE T1IE OC1IE CMIE MI2C2IE U2ERIE INT0IP2 T3IP2 U1TXIP2 SI2C1P2 INT1IP2 T5IP2 SPF2IP2 LVDIP2 CRCIF U2ERIF MI2C2IF IC5IF IC4IF IC3IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 T3IP1 U1TXIP1 SI2C1P1 INT1IP1 T5IP1 SPF2IP1 LVDIP1 INT1IF CNIF CMIF PMPIF AD1IE INT2IE PMPIE T1IP1 T2IP1 RTCIP2 RTCIP1 RTCIP0 MI2C2P2 MI2C2P1 MI2C2P0 IC4IP2 IC4IP1 IC4IP0 U2RXIP2 U2RXIP1 U2RXIP0 OC4IP2 OC4IP1 CMIP2 CMIP1 SPI1IP2 SPI1IP1 T2IP0 OC2IP2 OC2IP1 T1IP0 OC1IP2 OC1IP1 OC5IE T5IE T4IE OC4IE OC3IE U1TXIE U1RXIE SPI1IE SPF1IE OC5IF T5IF T4IF OC4IF OC3IF MI2C1IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF T1IF OC1IF IC1IF INT2EP INT1EP INT0EP INT0IF SI2C1IF SPF2IF INT0IE SI2C1IE SPF2IE INT0IP0 T3IP0 U1TXIP0 SI2C1P0 INT1IP0 T5IP0 SPF2IP0 LVDIP0 MATHERR ADDRERR STKERR OSCFAIL Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444
INTERRUPT CONTROLLER REGISTER
File Name
Addr
INTCON1
0080
NSTDIS
DS39881B-page
CNIP1 T4IP1 U2TXIP1 IC5IP1 CRCIP1 CRCIP0 IC5IP0 U2TXIP0 T4IP0 CNIP0 U2ERIP2 U2ERIP1 U2ERIP0
INTCON2
0082
ALTIVT
DISI
IFS0
0084
IFS1
0086
U2TXIF
U2RXIF
IFS2
0088
IFS3
008A
RTCIF
IFS4
008C
IEC0
0094
IEC1
0096
U2TXIE
U2RXIE
IEC2
0098
IEC3
009A
RTCIE
IEC4
009C
IPC0
00A4
T1IP2
IPC1
00A6
T2IP2
IPC2
00A8
U1RXIP2 U1RXIP1 U1RXIP0
IPC3
00AA
IPC4
00AC
CNIP2
IPC5
00AE
PIC24FJ64GA004 FAMILY
IPC6
00B0
T4IP2
IPC7
00B2
U2TXIP2
IPC8
00B4
IPC9
00B6
IC5IP2
IPC10
00B8
IPC11
00BA
IPC12
00BC
IPC15
00C2
IPC16
00C4
CRCIP2
IPC18
00C8
2007 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-6:
Timer1 Register Timer1 Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TSIDL TSIDL Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TSIDL TSIDL TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 TGATE TCKPS1 TCKPS0 TGATE TCKPS1 TCKPS0 TGATE TCKPS1 TCKPS0 TSYNC
TIMER REGISTER
Resets 0000 FFFF 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000
File Name
Addr
TMR1
0100
0102
T1CON
0104
TMR2
0106
TMR3H
0108
TMR3
010A
2007 Microchip Technology Inc.
Input Capture Register ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Input Capture Register ICSIDL ICTMR Input Capture Register ICSIDL ICTMR Input Capture Register ICSIDL ICTMR Input Capture Register ICSIDL ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0
010C
010E
T2CON
0110
T3CON
0112
TMR4
0114
TMR5H
0116
TMR5
0118
011A
011C
T4CON
011E
T5CON
0120
PIC24FJ64GA004 FAMILY
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-7:
INPUT CAPTURE REGISTER
Resets FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000
File Name
Addr
IC1BUF
0140
IC1CON
0142
IC2BUF
0144
IC2CON
0146
IC3BUF
0148
IC3CON
014A
IC4BUF
014C
IC4CON
014E
IC5BUF
0150
IC5CON
0152
DS39881B-page
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-8:
Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL Output Compare Secondary Register Output Compare Register OCSIDL OCFLT OCTSEL OCM2 OCM1 OCM0 OCFLT OCTSEL OCM2 OCM1 OCM0 OCFLT OCTSEL OCM2 OCM1 OCM0 OCFLT OCTSEL OCM2 OCM1 OCM0 OCFLT OCTSEL OCM2 OCM1 OCM0 Resets FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000
OUTPUT COMPARE REGISTER
File Name
Addr
OC1RS
0180
DS39881B-page
I2CSIDL I2CSIDL SCLREL IPMIEN A10M AMSK9 AMSK8 AMSK7 AMSK6 DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV AMSK9 AMSK8 AMSK7 AMSK6 GCSTAT ADD10 SCLREL IPMIEN A10M DISSLW SMEN GCEN IWCOL STREN I2COV Receive Register Transmit Register Baud Rate Generator Register AKDT ACKEN Address Register AMSK5 AMSK4 AMSK3 Receive Register Transmit Register Baud Rate Generator Register ACKDT ACKEN Address Register AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK` RCEN RSEN AMSK2 AMSK1 AMSK` RCEN RSEN Resets 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000
OC1R
0182
OC1CON
0184
OC2RS
0186
OC2R
0188
OC2CON
018A
OC3RS
018C
OC3R
018E
OC3CON
0190
OC4RS
0192
OC4R
0194
OC4CON
0196
OC5RS
0198
OC5R
019A
OC5CON
019C
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
PIC24FJ64GA004 FAMILY
TABLE 3-9:
I2CREGISTER
File Name
Addr
I2C1RCV
0200
I2C1TRN
0202
I2C1BRG
0204
I2C1CON
0206
I2CEN
I2C1STAT
0208
AKSTAT
TRSTAT
I2C1ADD
020A
I2C1MSK
020C
I2C2RCV
0210
I2C2TRN
0212
I2C2BRG
0214
I2C2CON
0216
I2CEN
I2C2STAT
0218
ACKSTAT
TRSTAT
I2C2ADD
021A
I2C2MSK
021C
2007 Microchip Technology Inc.
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-10:
USIDL Baud Rate Generator Prescaler Register USIDL URX8 URX7 URX6 URX5 URX4 URX3 UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTXBRK UTXEN UTXBF TRMT URCISEL1 URCISEL0 ADDEN RIDLE PERR IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 FERR UTX2 URX2 PDSEL0 OERR UTX1 URX1 STSEL URXDA UTX0 URX0 URX8 URX7 URX6 URX5 URX4 URX3 URX2 UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 URX1 UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR IREN RTSMD UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL URXDA UTX0 URX0
UART REGISTER
Resets 0000 0110 0000 0000 0000 0000 0110 0000 0000 0000
File Name
Addr
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1 UTXINV UTXISEL0
U1TXREG
0224
U1RXREG
0226
U1BRG
0228
2007 Microchip Technology Inc.
SPISIDL SPIFPOL DISSCK DISSDO MODE16 SSEN SPIBEC2 SPIBEC1 SPIBEC0 SPIROV MSTEN SPRE2 SPRE1 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPI1 Transmit/Receive Buffer SPISIDL SPIFPOL DISSCK DISSDO MODE16 SPIBEC2 SPIBEC1 SPIBEC0 SSEN SPIROV MSTEN SPRE2 SPRE1 SPRE0 SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN SPI2 Transmit/Receive Buffer
U2MODE
0230
UARTEN
U2STA
0232
UTXISEL1 UTXINV UTXISEL0
U2TXREG
0234
U2RXREG
0236
U2BRG
0238
Baud Rate Generator Prescaler
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
TABLE 3-11:
REGISTER
Resets 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
SPI1STAT
0240
SPIEN
SPI1CON1
0242
PIC24FJ64GA004 FAMILY
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
SPI2STAT
0260
SPIEN
SPI2CON1
0262
SPI2CON2
0264
FRMEN
SPIFSD
SPI2BUF
0268
Legend:
unimplemented, read `0'. Reset values shown hexadecimal.
DS39881B-page
TABLE 3-12:
ODA10(1) ODA4 ODA1 ODA9(1) ODA8(1) ODA7(1) ODA3(2) ODA2(3) LATA10(1) LATA4 LATA1 LATA9(1) LATA8(1) LATA7(1) LATA3(2) LATA2(3) RA10(1) RA9(1) RA8(1) RA7(1) RA3(2) RA2(3) LATA0 ODA0 TRISA10(1) TRISA9(1) TRISA8(1) TRISA7(1) TRISA4 TRISA1 TRISA0 TRISA3(2) TRISA2(3) Resets 079F 0000 0000 0000
PORTA REGISTER
File Name
Addr
TRISA
02C0
DS39881B-page
TRISB10 RB10 LATB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 ODB4 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 LATB3 ODB3 TRISB2 LATB2 ODB2 TRISB1 LATB1 ODB1 TRISB0 LATB0 ODB0 Resets FFFF 0000 0000 0000 RB13 LATB13 ODB13 ODB12 ODB11 LATB12 LATB11 RB12 RB11 ODC9 OSC8 LATC9 LATC8 LATC7 ODC7 TRISC9 TRISC8 TRISC7 TRISC6 LATC6 ODC6 TRISC5 LATC5 ODC5 TRISC4 LATC4 ODC4 TRISC3 LATC3 ODC3 TRISC2 LATC2 ODC2 TRISC1 LATC1 ODC1 TRISC0 LATC0 ODC0 Resets 03FF 0000 0000 0000 RTSECSEL PMPTTL Resets 0000
PORTA
02C2
LATA
02C4
ODCA
02C6
Legend: Note
unimplemented, read `0'. Bits available 28-pin devices; read `0'. Bits available only when primary oscillator disabled (POSCMD<1:0> 00); otherwise read `0'. Bits available only when primary oscillator disabled mode selected (POSCMD<1:0> CLKO disabled (OSCIOFNC otherwise, read `0'.
TABLE 3-13:
PORTB REGISTER
File Name
Addr
TRISB
02C8
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODB15
ODB14
Legend:
unimplemented, read
PIC24FJ64GA004 FAMILY
TABLE 3-14:
PORTC REGISTER
File Name
Addr
TRISC(1)
02D0
PORTC(1)
02D2
LATC(1)
02D4
ODCC(1)
02D6
Legend: Note
unimplemented, read Bits available 28-pin devices; read `0'.
TABLE 3-15:
CONFIGURATION REGISTER
File Name
Addr
PADCFG1
02FC
2007 Microchip Technology Inc.
Legend:
unimplemented, read
TABLE 3-16:
Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer Data Buffer ADSIDL VCFG0 SAMC4 PCFG12 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA PCFG6 CSSL6 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 CSCNA BUFS FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 PCFG5 CSSL5 SMPI2 ADCS4 PCFG4 CSSL4 SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0
REGISTER
Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
File Name
Addr
AD1BUF0
0300
AD1BUF1
0302
AD1BUF2
0304
AD1BUF3
0306
AD1BUF4
0308
AD1BUF5
030A
AD1BUF6
030C
2007 Microchip Technology Inc.
PSIDL IRQM0 ADDR10 INCM1 INCM0 MODE16 CSF1 MODE0 ADDR8 WAITB1 ADDR7 CSF0 WAITB0 ADDR6 WAITM3 ADDR5 WAITM2 ADDR4 CS1P WAITM1 ADDR3 WAITM0 ADDR2 WRSP WAITE1 ADDR1 RDSP WAITE0 ADDR0 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN MODE1 ADDR9 Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers Parallel Port Data Register (Buffers IB3F PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 PTEN6 OBUF PTEN5 PTEN4 PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E
AD1BUF7
030E
AD1BUF8
0310
AD1BUF9
0312
AD1BUFA
0314
AD1BUFB
0316
AD1BUFC
0318
AD1BUFD
031A
AD1BUFE
031C
AD1BUFF
031E
AD1CON1
0320
ADON
AD1CON2
0322
VCFG2
VCFG1
AD1CON3
0324
ADRC
AD1CHS0
0328
CH0NB
PIC24FJ64GA004 FAMILY
AD1PCFG
032C
AD1CSSL
0330
Legend:
unimplemented, read
TABLE 3-17:
PARALLEL MASTER/SLAVE PORT REGISTER
Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name Addr
PMCON
0600
PMPEN
PMMODE
0602
BUSY
IRQM1
PMADDR
0604
PMDOUT1
PMDOUT2 0606
PMDIN1
0608
PMDIN2
060A
PMAEN
060C
PTEN14
PMSTAT
060E
IBOV
DS39881B-page
Legend:
unimplemented, read `0'.
TABLE 3-18:
Alarm Value Register Window Based APTR<1:0> AMASK3 RTCC Value Register Window Based RTCPTR<1:0> RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Resets xxxx 0000 xxxx 0000
REAL-TIME CLOCK CALENDAR REGISTER
File Name
Addr
ALRMVAL
0620
DS39881B-page
C2EVT CVREN CVROE CVRR CVRSS C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG CVR3 C2POS CVR2 C1NEG CVR1 C1POS CVR0 Resets 0000 0000 CSIDL Data Input Register Result Register VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCGO PLEN3 PLEN2 PLEN1 PLEN0 Resets 0040 0000 0000 0000
ALCFGRPT
0622
ALRMEN CHIME
RTCVAL
0624
RCFGCAL
0626
RTCEN
Legend:
unimplemented, read
TABLE 3-19:
DUAL COMPARATOR REGISTER
File Name
Addr
CMCON
0630
CMIDL
CVRCON
0632
Legend:
unimplemented, read
TABLE 3-20:
REGISTER
File Name
Addr
PIC24FJ64GA004 FAMILY
CRCCON
0640
CRCXOR
0642
CRCDAT
0644
CRCWDAT
0646
Legend:
unimplemented, read
2007 Microchip Technology Inc.
TABLE 3-21:
RP19R4(1) RP19R3(1) RP19R2(1) RP19R1(1) RP19R0(1) RP21R4(1) RP21R3(1) RP21R2(1) RP21R1(1) RP21R0(1) RP23R4(1) RP23R3(1) RP23R2(1) RP23R1(1) RP23R0(1) RP25R4(1) RP25R3(1) RP25R2(1) RP25R1(1) RP25R0(1) RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1) RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 SDI2R4 SS2R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 SS1R4 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 SDI1R4 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 U2RXR4 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U1RXR4 U1RXR3 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 OCFAR4 OCFAR3 IC5R4 IC5R3 IC5R2 OCFAR2 U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 IC3R4 IC3R3 IC3R2 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 IC1R4 IC1R3 IC1R2 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 T4CKR4 T4CKR3 T4CKR2 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 OCFAR1 U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 INTR4 INTR3 INTR2 INTR1 INTR4 INTR3 INTR2 INTR1 INTR0 INTR0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 OCFAR0 U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1) RP18R4(1) RP18R3(1) RP18R2(1) RP18R1(1) RP18R0(1) RP20R4(1) RP20R3(1) RP20R2(1) RP20R1(1) RP20R0(1) RP22R4(1) RP22R3(1) RP22R2(1) RP22R1(1) RP22R0(1) RP24R4(1) RP24R3(1) RP24R2(1) RP24R1(1) RP24R0(1)
PERIPHERAL SELECT REGISTER
Resets 1F00 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 001F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
RPINR0
0680
RPINR1
0682
RPINR3
0686
RPINR4
0688
RPINR7
068E
RPINR8
0690
2007 Microchip Technology Inc.
RPINR9
0692
RPINR11
0696
RPINR18
06A4
RPINR19
06A6
RPINR20
06A8
RPINR21
06AA
RPINR22
06AC
RPINR23
06AE
RPOR0
06C0
RPOR1
06C2
RPOR2
06C4
RPOR3
06C6
PIC24FJ64GA004 FAMILY
RPOR4
06C8
RPOR5
06CA
RPOR6
06CC
RPOR7
06CE
RPOR8
06D0
RPOR9
06D2
RPOR10
06D4
RPOR11
06D6
RPOR12
06D8
Legend: Note
unimplemented, read Bits only available 44-pin devices; otherwise, they read `0'.
DS39881B-page
TABLE 3-22:
COSC1 DOZE1 TUN5 TUN4 TUN3 TUN2 TUN1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 TUN0 COSC0 NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK SOSCEN VREGS EXTR SWDTEN WDTO SLEEP IDLE Resets (Note
CLOCK CONTROL REGISTER
File Name
Addr
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
COSC2
OSWEN (Note 0100 0000
DS39881B-page
WRERR ERASE Resets NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000 NVMKEY<7:0> T3MD IC3MD CMPMD RTCCMD PMPMD CRCPMD IC2MD IC1MD I2C1MD IC5MD IC4MD T2MD T1MD U2MD U1MD SPI2MD OC5MD SPI1MD OC4MD OC3MD OC2MD I2C2MD ADC1MD OC1MD Resets 0000 0000 0000
CLKDIV
0744
DOZE2
OSCTUN
0748
Legend: Note
unimplemented, read RCON register Reset values dependent type Reset. OSCCON register Reset values dependent configuration fuses type Reset.
TABLE 3-23:
REGISTER
File Name
Addr
NVMCON
0760
WREN
NVMKEY
0766
Legend: Note
unimplemented, read Reset value shown only. Value other Reset states dependent state memory write erase operations time Reset.
TABLE 3-24:
REGISTER
PIC24FJ64GA004 FAMILY
File Name
Addr
PMD1
0770
T5MD
T4MD
PMD2
0772
PMD3
0774
Legend:
unimplemented, read
2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2.5 SOFTWARE STACK
addition working register, register PIC24F devices also used Software Stack Pointer. pointer always points first available free word grows from lower higher addresses. pre-decrements stack pops post-increments stack pushes, shown Figure 3-4. Note that push during CALL instruction, zero-extended before push, ensuring that always clear. Note: push during exception processing will concatenate register prior push.
Interfacing Program Data Memory Spaces
PIC24F architecture uses 24-bit wide program space 16-bit wide data space. architecture also modified Harvard scheme, meaning that data also present program space. this data successfully, must accessed that preserves alignment information both spaces. Aside from normal execution, PIC24F architecture provides methods which program space accessed during operation: Using table instructions access individual bytes words anywhere program space Remapping portion program space into data space (program space visibility) Table instructions allow application read write small areas program memory. This makes method ideal accessing data tables that need updated from time time. also allows access bytes program word. remapping method allows application access large block data read-only basis, which ideal look-ups from large table static data. only access least significant word program word.
Stack Pointer Limit Value register (SPLIM) associated with Stack Pointer sets upper address boundary stack. SPLIM uninitialized Reset. case Stack Pointer, SPLIM<0> forced because stack operations must word-aligned. Whenever generated using source destination pointer, resulting address compared with value SPLIM. contents Stack Pointer (W15) SPLIM register equal, push operation performed, stack error trap will occur. stack error trap will occur subsequent push operation. Thus, example, desirable cause stack error trap when stack grows beyond address 2000h RAM, initialize SPLIM with value, 1FFEh. Similarly, Stack Pointer underflow (stack error) trap generated when Stack Pointer address found less than 0800h. This prevents stack from interfering with Special Function Register (SFR) space. write SPLIM register should immediately followed indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since address ranges data program spaces bits, respectively, method needed create 23-bit 24-bit program address from 16-bit data registers. solution depends interface method used. table operations, 8-bit Table Memory Page Address register (TBLPAG) used define word region within program space. This concatenated with 16-bit arrive full 24-bit program space address. this format, Most Significant TBLPAG used determine operation occurs user memory (TBLPAG<7> configuration memory (TBLPAG<7> remapping operations, 8-bit Program Space Visibility Page Address register (PSVPAG) used define word page program space. When Most Significant `1', PSVPAG concatenated with lower bits form 23-bit program space address. Unlike table operations, this limits remapping operations strictly user memory area. Table 3-25 Figure show program created table operations remapping accesses from data Here, P<23:0> refers program space word, whereas D<15:0> refers data space word.
FIGURE 3-4:
0000h
CALL STACK FRAME
Stack Grows Towards Higher Address
PC<15:0> 000000000 PC<22:16> <Free Word>
(before CALL) (after CALL) [-W15] PUSH [W15++]
2007 Microchip Technology Inc.
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TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note User Program Space Address <23> TBLPAG<7:0> 0xxx xxxx TBLPAG<7:0> 1xxx xxxx PSVPAG<7:0> xxxx xxxx <22:16> <15> PC<22:1> xxxx xxxx xxxx xxxx xxx0 Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<15:0> xxxx xxxx xxxx xxxx Data EA<14:0>(1) xxxx xxxx xxxx <14:1> Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA<15> always this case, used calculating program space address. address PSVPAG<0>.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter bits
Table Operations(2) TBLPAG bits bits bits
Select Program Space (Remapping) Visibility(1) PSVPAG bits
bits bits
User/Configuration Space Select
Byte Select
Note program space addresses always fixed order maintain word alignment data program data spaces. Table operations required word-aligned. Table read operations permitted configuration memory space.
DS39881B-page
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PIC24FJ64GA004 FAMILY
3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
TBLRDH (Table Read High): Word mode, maps entire upper word program address (P<23:16>) data address. Note that D<15:8>, "phantom byte", will always `0'. Byte mode, maps upper lower byte program word D<7:0> data address, above. Note that data will always when upper "phantom" byte selected (byte select
TBLRDL TBLWTL instructions offer direct method reading writing lower word address within program space without going through data space. TBLRDH TBLWTH instructions only method read write upper bits program space word data. incremented each successive 24-bit program word. This allows program memory addresses directly data space addresses. Program memory thus regarded 16-bit word-wide address spaces, residing side side, each with same address range. TBLRDL TBLWTL access space which contains least significant data word, TBLRDH TBLWTH access space which contains upper data byte. table instructions provided move byte word-sized (16-bit) data from program space. Both function either byte word operations. TBLRDL (Table Read Low): Word mode, maps lower word program space location (P<15:0>) data address (D<15:0>). Byte mode, either upper lower byte lower program word mapped lower byte data address. upper byte selected when byte select `1'; lower byte selected when `0'.
similar fashion, table instructions, TBLWTH TBLWTL, used write individual bytes words program space address. details their operation explained Section "Flash Program Memory". table operations, area program memory space accessed determined Table Memory Page Address register (TBLPAG). TBLPAG covers entire program memory space device, including user configuration spaces. When TBLPAG<7> table page located user memory space. When TBLPAG<7> page located configuration space. Note: Only table read operations will execute configuration memory space, only then, implemented areas such device Table write operations allowed.
FIGURE 3-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA<15:0> 000000h
00000000 00000000
020000h 030000h
00000000 00000000
`Phantom' Byte
TBLRDH.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.B (Wn<0> TBLRDL.W
800000h
address table operation determined data within page defined TBLPAG register. Only read operations shown; write operations also valid user memory area.
2007 Microchip Technology Inc.
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3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word used contain data. upper bits program space locations used data should programmed with `1111 1111' `0000 0000' force NOP. This prevents possible issues should area code ever accidentally executed. Note: access temporarily disabled during table reads/writes.
upper Kbytes data space optionally mapped into word page program space. This provides transparent access stored constant data from data space without need special instructions (i.e., TBLRDL/H). Program space access through data space occurs Most Significant data space program space visibility enabled setting Control register (CORCON<2>). location program memory space mapped into data space determined Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines possible pages words program space. effect, PSVPAG functions upper bits program memory address, with bits functioning lower bits. Note that incrementing each program memory word, lower bits data space addresses directly lower bits corresponding program space addresses. Data reads this area additional cycle instruction being executed, since program memory fetches required. Although each data space address, 8000h higher, maps directly into corresponding program memory address (see Figure 3-7), only lower bits
operations that executed outside REPEAT loop, MOV.D instructions will require instruction cycle addition specified execution time. other instructions will require instruction cycles addition specified execution time. operations that which executed inside REPEAT loop, there will some instances that require instruction cycles addition specified execution time instruction: Execution first iteration Execution last iteration Execution prior exiting loop interrupt Execution upon re-entering loop after interrupt serviced other iteration REPEAT loop will allow instruction accessing data, using PSV, execute single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> EA<15>
Program Space
PSVPAG 000000h 010000h 018000h data page designated PSVPAG mapped into upper half data memory space.
Data Space
0000h Data EA<14:0>
8000h
Area .while lower bits specify exact address within area. This corresponds exactly same lower bits actual program space address.
FFFFh
800000h
DS39881B-page
2007 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer associated "PIC24F Family Reference Manual" chapter.
RTSP accomplished using TBLRD (table read) TBLWT (table write) instructions. With RTSP, user write program memory data blocks instructions (192 bytes) time, erase program memory blocks instructions (1536 bytes) time.
Table Instructions Flash Programming
PIC24FJ64GA004 family devices contains internal Flash program memory storing executing application code. memory readable, writable erasable during normal operation over entire range. Flash memory programmed four ways: In-Circuit Serial Programming (ICSP) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP)
Regardless method used, programming Flash memory done with table read table write instructions. These allow direct read write access program memory space from data memory while device normal operating mode. 24-bit target address program memory formed using TBLPAG<7:0> bits Effective Address (EA) from register specified table instruction, shown Figure 4-1. TBLRDL TBLWTL instructions used read write bits<15:0> program memory. TBLRDL TBLWTL access program memory both Word Byte modes. TBLRDH TBLWTH instructions used read write bits<23:16> program memory. TBLRDH TBLWTH also access program memory Word Byte mode.
ICSP allows PIC24FJ64GA004 family device serially programmed while application circuit. This simply done with lines programming clock programming data (which named PGCx PGDx, respectively), three other lines power (VDD), ground (VSS) Master Clear (MCLR). This allows customers manufacture boards with unprogrammed devices then program microcontroller just before shipping product. This also allows most recent firmware custom firmware programmed.
FIGURE 4-1:
ADDRESSING TABLE REGISTERS
Bits Using Program Counter Program Counter
Working Using Table Instruction TBLPAG Bits Bits
User/Configuration Space Select
24-Bit
Byte Select
2007 Microchip Technology Inc.
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RTSP Operation
PIC24F Flash program memory array organized into rows instructions bytes. RTSP allows user erase blocks eight rows (512 instructions) time program time. also possible program single words. 8-row erase blocks single write blocks edge-aligned, from beginning program memory, boundaries 1536 bytes bytes, respectively. When data written program memory using TBLWT instructions, data written directly memory. Instead, data written using table writes stored holding latches until programming sequence executed. number TBLWT instructions executed write will successfully performed. However, TBLWT instructions required write full memory. ensure that data corrupted during write, unused addresses should programmed with FFFFFFh. This because holding latches reset unknown state, addresses left Reset state, they overwrite locations rows which were rewritten. basic sequence RTSP programming Table Pointer, then series TBLWT instructions load buffers. Programming performed setting control bits NVMCON register. Data loaded order holding registers written multiple times before performing write operation. Subsequent writes, however, will wipe previous writes. Note: Writing page multiple times without erasing recommended.
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses on-board boot loader, known program executive, manage programming process. Using data frame format, program executive erase, program verify program memory. more information Enhanced ICSP, device programming specification.
Control Registers
There SFRs used read write program Flash memory: NVMCON NVMKEY. NVMCON register (Register 4-1) controls which blocks erased, which memory type programmed when programming cycle starts. NVMKEY write-only register that used write protection. start programming erase sequence, user must consecutively write NVMKEY register. Refer Section "Programming Operations" further details.
Programming Operations
complete programming sequence necessary programming erasing internal Flash RTSP mode. During programming erase operation, processor stalls (waits) until operation finished. Setting (NVMCON<15>) starts operation automatically cleared when operation finished. Configuration Word values stored last locations program memory. Performing page erase operation last page program memory clears these values enables code protection. result, avoid performing page erase operations last page program memory.
table write operations single-word writes instruction cycles), because only buffers written. programming cycle required programming each row.
JTAG Operation
PIC24F family supports JTAG programming boundary scan. Boundary scan improve manufacturing process verifying pin-to-PCB connectivity. Programming performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
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REGISTER 4-1:
R/SO-0(1) Legend: Readable Value Set-Only Writable Unimplemented bit, read cleared unknown R/W-0(1) ERASE R/W-0(1) NVMOP3
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WREN R/W-0(1) WRERR R/W-0(1) NVMOP2
R/W-0(1) NVMOP1
R/W-0(1) NVMOP0(2)
Write Control bit(1) Initiates Flash memory program erase operation. operation self-timed cleared hardware once operation complete. Program erase operation complete inactive WREN: Write Enable bit(1) Enable Flash program/erase operations Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) improper program erase sequence attempt termination occurred (bit automatically attempt bit) program erase operation completed normally Unimplemented: Read ERASE: Erase/Program Enable bit(1) Perform erase operation specified NVMOP3:NVMOP0 next command Perform program operation specified NVMOP3:NVMOP0 next command Unimplemented: Read NVMOP3:NVMOP0: Operation Select bits(1,2) 1111 Memory bulk erase operation (ERASE operation (ERASE 0)(3) 0011 Memory word program operation (ERASE operation (ERASE 0010 Memory page erase operation (ERASE operation (ERASE 0001 Memory program operation (ERASE operation (ERASE These bits only reset POR. other combinations NVMOP3:NVMOP0 unimplemented. Available ICSPmode only. Refer device programming specification.
12-7
Note
2007 Microchip Technology Inc.
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4.6.1 PROGRAMMING ALGORITHM FLASH PROGRAM MEMORY
user program program Flash memory time. this, necessary erase 8-row erase block containing desired row. general process Read eight rows program memory (512 instructions) store data RAM. Update program data with desired data. Erase block (see Example 4-1): NVMOP bits (NVMCON<3:0>) `0010' configure block erase. ERASE (NVMCON<6>) WREN (NVMCON<14>) bits. Write starting address block erased into TBLPAG registers. Write NVMKEY. Write NVMKEY. (NVMCON<15>). erase cycle begins stalls duration erase cycle. When erase done, cleared automatically. Write first instructions from data into program memory buffers (see Example 4-1). Write program block Flash memory: NVMOP bits `0001' configure programming. Clear ERASE WREN bit. Write NVMKEY. Write NVMKEY. bit. programming cycle begins stalls duration write cycle. When write Flash memory done, cleared automatically. Repeat steps using next available instructions from block data incrementing value TBLPAG, until instructions written back Flash memory.
protection against accidental operations, write initiate sequence NVMKEY must used allow erase program operation proceed. After programming command been executed, user must wait programming time until programming complete. instructions following start programming sequence should NOPs, shown Example 4-3.
EXAMPLE 4-1:
ERASING PROGRAM MEMORY BLOCK
Initialize NVMCON
NVMCON block erase operation #0x4042, NVMCON Init pointer ERASED #tblpage(PROG_ADDR), TBLPAG #tbloffset(PROG_ADDR), TBLWTL [W0] DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON,
Initialize Page Boundary Initialize in-page EA[15:0] pointer base address erase block Block interrupts with priority next instructions Write Write Start erase sequence Insert NOPs after erase command asserted
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EXAMPLE 4-2: LOADING WRITE BUFFERS
NVMCON programming operations #0x4001, NVMCON Initialize NVMCON pointer first program memory location written program memory selected, writes enabled #0x0000, TBLPAG Initialize Page Boundary #0x6000, example program memory address Perform TBLWT instructions write latches 0th_program_word #LOW_WORD_0, #HIGH_BYTE_0, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 1st_program_word #LOW_WORD_1, #HIGH_BYTE_1, TBLWTL [W0] Write word into program latch TBLWTH [W0++] Write high byte into program latch 2nd_program_word #LOW_WORD_2, #HIGH_BYTE_2, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0++] 63rd_program_word #LOW_WORD_31, #HIGH_BYTE_31, Write word into program latch TBLWTL [W0] Write high byte into program latch TBLWTH [W0]
EXAMPLE 4-3:
DISI BSET BTSC
INITIATING PROGRAMMING SEQUENCE
Block interrupts with priority next instructions Write Write Start erase sequence wait completed
#0x55, NVMKEY #0xAA, NVMKEY NVMCON, NVMCON,
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4.6.2 PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY
Flash location been erased, programmed using table write instructions write instruction word (24-bit) into write latch. TBLPAG register loaded with Most Significant Bytes Flash address. TBLWTL TBLWTH instructions write desired data into write latches specify lower bits program memory address write configure NVMCON register word write, NVMOP bits (NVMCON<3:0>) `0011'. write performed executing unlock sequence setting (see Example 4-4).
EXAMPLE 4-4:
PROGRAMMING SINGLE WORD FLASH PROGRAM MEMORY
Setup pointer data Program Memory #tblpage(PROG_ADDR), TBLPAG ;Initialize Page Boundary #tbloffset(PROG_ADDR), ;Initialize register with program memory address TBLWTL TBLWTH #LOW_WORD_N, #HIGH_BYTE_N, [W0] [W0++] Write word into program latch Write high byte into program latch
Setup NVMCON programming word data Program Memory #0x4003, NVMCON NVMOP bits 0011 DISI BSET #0x55, NVMKEY #0xAA, NVMKEY NVMCON, Disable interrupts while sequence written Write sequence
Start write cycle
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Note:
RESETS
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer associated "PIC24F Family Reference Manual" chapter.
Note:
Refer specific peripheral section this manual register Reset states.
Reset module combines Reset sources controls device Master Reset Signal, SYSRST. following list device Reset sources: POR: Power-on Reset MCLR: Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized Register Reset
types device Reset will corresponding status RCON register indicate type Reset (see Register 5-1). Power-on Reset will clear bits except bits (RCON<1:0>) which set. user clear time during code execution. RCON bits only serve status bits. Setting particular Reset status software will cause device Reset occur. RCON register also other bits associated with Watchdog Timer device power-saving states. function these bits discussed other sections this manual. Note: status bits RCON register should cleared after they read that next RCON register value after device Reset will meaningful.
simplified block diagram Reset module shown Figure 5-1. active source Reset will make SYSRST signal active. Many registers associated with peripherals forced known Reset state. Most registers unaffected Reset; their status unknown unchanged other Resets.
FIGURE 5-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction Glitch Filter MCLR Module Sleep Idle SYSRST
Rise Detect Brown-out Reset
Enable Voltage Regulator Trap Conflict Illegal Opcode Uninitialized Register
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REGISTER 5-1:
R/W-0 TRAPR R/W-0 EXTR Legend: Readable Value
RCON: RESET CONTROL REGISTER(1)
R/W-0 IOPUWR R/W-0 R/W-0 VREGS R/W-1
R/W-0
R/W-0 SWDTEN(2)
R/W-0 WDTO
R/W-0 SLEEP
R/W-0 IDLE
R/W-1
Writable
Unimplemented bit, read cleared unknown
13-10
TRAPR: Trap Reset Flag Trap Conflict Reset occurred Trap Conflict Reset occurred IOPUWR: Illegal Opcode Uninitialized Access Reset Flag illegal opcode detection, illegal address mode uninitialized register used Address Pointer caused Reset illegal opcode uninitialized Reset occurred Unimplemented: Read Configuration Word Mismatch Reset Flag Configuration Word Mismatch Reset occurred Configuration Word Mismatch Reset occurred VREGS: Voltage Regulator Standby Enable Regulator remains active during Sleep Regulator goes standby during Sleep EXTR: External Reset (MCLR) Master Clear (pin) Reset occurred Master Clear (pin) Reset occurred SWR: Software Reset (Instruction) Flag RESET instruction been executed RESET instruction been executed SWDTEN: Software Enable/Disable bit(2) enabled disabled WDTO: Watchdog Timer Time-out Flag time-out occurred time-out occurred SLEEP: Wake From Sleep Flag Device been Sleep mode Device been Sleep mode IDLE: Wake-up From Idle Flag Device been Idle mode Device been Idle mode BOR: Brown-out Reset Flag Brown-out Reset occurred. Note that also after Power-on Reset. Brown-out Reset occurred POR: Power-on Reset Flag Power-up Reset occurred Power-up Reset occurred Reset status bits cleared software. Setting these bits software does cause device Reset. FWDTEN Configuration (unprogrammed), always enabled, regardless SWDTEN setting.
Note
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TABLE 5-1: RESET FLAG OPERATION
Setting Event Trap Conflict Event Illegal Opcode Uninitialized Register Access MCLR Reset RESET Instruction Time-out PWRSAV #SLEEP Instruction PWRSAV #IDLE Instruction POR, Clearing Event PWRSAV Instruction, Flag TRAPR (RCON<15>) IOPUWR (RCON<14>) EXTR (RCON<7>) (RCON<6>) WDTO (RCON<4>) SLEEP (RCON<3>) IDLE (RCON<2>) (RCON<1>) (RCON<0>) Note:
Reset flag bits cleared user software.
Clock Source Selection Reset
Device Reset Times
clock switching enabled, system clock source device Reset chosen shown Table 5-2. clock switching disabled, system clock source always selected according oscillator configuration bits. Refer Section "Oscillator Configuration" further details.
Reset times various types device Reset summarized Table 5-3. Note that system Reset signal, SYSRST, released after PWRT delay times expire. time that device actually begins execute code will also depend system oscillator delays, which include Oscillator Start-up Timer (OST) lock time. lock times occur parallel with applicable SYSRST delay times. FSCM delay determines time which FSCM begins monitor system clock source after SYSRST signal released.
TABLE 5-2:
OSCILLATOR SELECTION TYPE RESET (CLOCK SWITCHING ENABLED)
Clock Source Determinant Oscillator Configuration Bits (CW2<10:8>) COSC Control bits (OSCCON<14:12>)
Reset Type MCLR WDTO
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TABLE 5-3:
Reset Type
RESET DELAY TIMES VARIOUS DEVICE RESETS
Clock Source SYSRST Delay System Clock Delay TLOCK TOST TLOCK TOST TOST TLOCK FSCM Delay TFSCM TFSCM TFSCM TFSCM TFSCM TFSCM Notes
FRC, FRCDIV, LPRC TPOR TSTARTUP TRST ECPLL, FRCPLL SOSC XTPLL, HSPLL TPOR TSTARTUP TRST TPOR TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TSTARTUP TRST TRST TRST TRST TRST TRST TRST
TPOR TSTARTUP TRST TOST TLOCK
FRC, FRCDIV, LPRC ECPLL, FRCPLL SOSC XTPLL, HSPLL
MCLR Software Illegal Opcode Uninitialized Trap Conflict Note
Clock Clock clock Clock Clock Clock
TPOR Power-on Reset delay nominal). TSTARTUP TVREG nominal) on-chip regulator enabled TPWRT nominal) on-chip regulator disabled. TRST Internal state Reset time nominal). TOST Oscillator Start-up Timer. 10-bit counter counts 1024 oscillator periods before releasing oscillator clock system. TLOCK lock time nominal). TFSCM Fail-Safe Clock Monitor delay (100 nominal).
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5.2.1 LONG OSCILLATOR START-UP TIMES 5.2.2.1 FSCM Delay Crystal Clock Sources
oscillator start-up circuitry associated delay timers linked device Reset delays that occur power-up. Some crystal circuits (especially low-frequency crystals) will have relatively long start-up time. Therefore, more following conditions possible after SYSRST released: oscillator circuit begun oscillate. Oscillator Start-up Timer expired crystal oscillator used). achieved lock used). device will begin execute code until valid clock source been released system. Therefore, oscillator start-up delays must considered when Reset delay time must known. When system clock source provided crystal oscillator and/or PLL, small delay, TFSCM, will automatically inserted after PWRT delay times. FSCM will begin monitor system clock source until this delay expires. FSCM delay time nominally provides additional time oscillator and/or stabilize. most cases, FSCM delay will prevent oscillator failure trap device Reset when PWRT disabled.
Special Function Register Reset States
5.2.2
FAIL-SAFE CLOCK MONITOR (FSCM) DEVICE RESETS
Most Special Function Registers (SFRs) associated with PIC24F peripherals reset particular value device Reset. SFRs grouped their peripheral function their Reset values specified each section this manual. Reset value each does depend type Reset, with exception four registers. Reset value Reset Control register, RCON, will depend type device Reset. Reset value Oscillator Control register, OSCCON, will depend type Reset programmed values FNOSC bits register (see Table 5-2). RCFGCAL NVMCON registers only affected POR.
FSCM enabled, will begin monitor system clock source when SYSRST released. valid clock source available this time, device will automatically switch oscillator user switch desired crystal oscillator Trap Service Routine.
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NOTES:
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Note:
INTERRUPT CONTROLLER
This data sheet summarizes features this group PIC24F devices. intended comprehensive reference source. more information, refer associated "PIC24F Family Reference Manual" chapter.
6.1.1
ALTERNATE INTERRUPT VECTOR TABLE
PIC24F interrupt controller reduces numerous peripheral interrupt request signals single interrupt request signal PIC24F CPU. following features: processor exceptions software traps user-selectable priority levels Interrupt Vector Table (IVT) with vectors unique vector each interrupt exception source Fixed priority within specified user priority level Alternate Interrupt Vector Table (AIVT) debug support Fixed interrupt entry return latencies
Alternate Interrupt Vector Table (AIVT) located after IVT, shown Figure 6-1. Access AIVT provided ALTIVT control (INTCON2<15>). ALTIVT set, interrupt exception processes will alternate vectors instead default vectors. alternate vectors organized same manner default vectors. AIVT supports emulation debugging efforts providing means switch between application support environment without requiring interrupt vectors reprogrammed. This feature also enables switching between applications evaluation different software algorithms time. AIVT needed, AIVT should programmed with same addresses used IVT.
Reset Sequence
Interrupt Vector Table
Interrupt Vector Table (IVT) shown Figure 6-1. resides program memory, starting location 000004h. contains vectors, consisting non-maskable trap vectors, plus sources interrupt. general, each interrupt source vector. Each interrupt vector contains 24-bit wide address. value programmed into each interrupt vector location starting address associated Interrupt Service Routine (ISR). Interrupt vectors prioritized terms their natural priority; this linked their position vector table. other things being equal, lower addresses have higher natural priority. example, interrupt associated with vector will take priority over interrupts other vector address. PIC24FJ64GA004 family devices implement non-maskable traps unique interrupts. These summarized Table Table 6-2.
device Reset true exception because interrupt controller involved Reset process. PIC24F devices clear their registers response Reset which forces zero. microcontroller then begins program execution location 000000h. user programs GOTO instruction Reset address, which redirects program execution appropriate start-up routine. Note: unimplemented unused vector locations AIVT should programmed with address default interrupt handler routine that contains RESET instruction.
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FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE
Reset GOTO Instruction Reset GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Interrupt Vector Start Code 000000h 000002h 000004h
000014h
Decreasing Natural Order Priority
00007Ch 00007Eh 000080h
Interrupt Vector Table (IVT)(1)
0000FCh 0000FEh 000100h 000102h
000114h
Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h
0001FEh 000200h
Note
Table interrupt vector list.
TABLE 6-1:
TRAP VECTOR DETAILS
Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 0001172h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved
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Vector Number
Trap Source
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TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS
Vector Number Address 00002Eh 000038h 00009Ah 000014h 00003Ch 00004Eh 000036h 000034h 000078h 000076h 000016h 00001Eh 00005Eh 000060h 000062h 00003Ah 000018h 000020h 000046h 000048h 000066h 00006Eh 000090h 000026h 000028h 000054h 000056h 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h 0000A4h AIVT Address 00012Eh 000138h 00019Ah 000114h 00013Ch 00014Eh 000136h 000034h 000178h 000176h 000116h 00011Eh 00015Eh 000160h 000162h 00013Ah 000118h 000120h 000146h 000148h 000166h 00016Eh 000190h 000126h 000128h 000154h 000156h 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h 000124h Interrupt Locations Flag IFS0<13> IFS1<2> IFS4<3> IFS0<0> IFS1<4> IFS1<13> IFS1<1> IFS1<0> IFS3<2> IFS3<1> IFS0<1> IFS0<5> IFS2<5> IFS2<6> IFS2<7> IFS1<3> IFS0<2> IFS0<6> IFS1<9> IFS1<10> IFS2<9> IFS2<13> IFS3<14> IFS0<9> IFS0<10> IFS2<0> IFS2<1> IFS0<3> IFS0<7> IFS0<8> IFS1<11> IFS1<12> IFS4<1> IFS0<11> IFS0<12> IFS4<2> IFS1<14> IFS1<15> IFS4<8> Enable IEC0<13> IEC1<2> IEC4<3> IEC0<0> IEC1<4> IEC1<13> IEC1<1> IEC1<0> IEC3<2> IEC3<1> IEC0<1> IEC0<5> IEC2<5> IEC2<6> IEC2<7> IEC1<3> IEC0<2> IEC0<6> IEC1<9> IEC1<10> IEC2<9> IEC2<13> IEC3<13> IEC0<9> IEC0<10> IEC0<0> IEC2<1> IEC0<3> IEC0<7> IEC0<8> IEC1<11> IEC1<12> IEC4<1> IEC0<11> IEC0<12> IEC4<2> IEC1<14> IEC1<15> IEC4<8> Priority IPC3<6:4> IPC4<10:8> IPC16<14:12> IPC0<2:0> IPC5<2:0> IPC7<6:4> IPC4<6:4> IPC4<2:0> IPC12<10:8> IPC12<6:4> IPC0<6:4> IPC1<6:4> IPC9<6:4> IPC9<10:8> IPC9<14:12> IPC4<14:12> IPC0<10:8> IPC1<10:8> IPC6<6:4> IPC6<10:8> IPC10<6:4> IPC11<6:4> IPC15<10:8> IPC2<6:4> IPC2<10:8> IPC8<2:0> IPC8<6:4> IPC0<14:12> IPC1<14:12> IPC2<2:0> IPC6<14:12> IPC7<2:0> IPC16<6:4> IPC2<14:12> IPC3<2:0> IPC16<10:8> IPC7<10:8> IPC7<14:12> IPC17<2:0> Interrupt Source ADC1 Conversion Done Comparator Event Generator External Interrupt External Interrupt External Interrupt I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture Input Capture Input Capture Input Capture Input Capture Input Change Notification Output Compare Output Compare Output Compare Output Compare Output Compare Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter Low-Voltage Detect
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Interrupt Control Status Registers
interrupt sources assigned IFSx, IECx IPCx registers same sequence that they listed Table 6-2. example, INT0 (External Interrupt shown having vector number natural order priority Thus, INT0IF status found IFS0<0>, INT0IE enable IEC0<0> INT0IP<2:0> priority bits first position IPC0 (IPC0<2:0>). Although they specifically part interrupt control hardware, control registers contain bits that control interrupt functionality. STATUS register (SR) contains IPL2:IPL0 bits (SR<7:5>). These indicate current interrupt priority level. user change current priority level writing bits. CORCON register contains IPL3 bit, which together with IPL2:IPL0, also indicates current priority level. IPL3 read-only that trap events cannot masked user software. interrupt registers described Register through Register 6-29, following pages.
PIC24FJ64GA004 family devices implement total registers interrupt controller: INTCON1 INTCON2 IFS0 through IFS4 IEC0 through IEC4 IPC0 through IPC12, IPC15, IPC16 IPC18
Global interrupt control functions controlled from INTCON1 INTCON2. INTCON1 contains Interrupt Nesting Disable (NSTDIS) bit, well control status flags processor trap sources. INTCON2 register controls external interrupt request signal behavior Alternate Interrupt Vector Table. IFSx registers maintain interrupt request flags. Each source interrupt status which respective peripherals, external signal, cleared software. IECx registers maintain interrupt enable bits. These control bits used individually enable interrupts from peripherals external signals. IPCx registers used interrupt priority level each source interrupt. Each user interrupt source assigned eight priority levels.
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REGISTER 6-1:
R/W-0 IPL2(2,3) Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 IPL1(2,3) R/W-0 IPL0(2,3) RA(1) R/W-0 N(1) R/W-0 OV(1) R/W-0 Z(1)
STATUS REGISTER CPU)
DC(1) R/W-0 C(1)
IPL2:IPL0: Interrupt Priority Level Status bits(2,3) interrupt priority level (15). User interrupts disabled. interrupt priority level (14) interrupt priority level (13) interrupt priority level (12) interrupt priority level (11) interrupt priority level (10) interrupt priority level interrupt priority level Register description remaining that dedicated interrupt control functions. bits concatenated with IPL3 (CORCON<3>) form interrupt priority level. value parentheses indicates Interrupt Priority Level IPL3 Status bits read-only when NSTDIS (INTCON1<15>)
Note
REGISTER 6-2:
Legend: Readable Value
CORCON: CONTROL REGISTER
R/C-0 IPL3(2) R/W-0 PSV(1) Clearable Writable Unimplemented bit, read cleared unknown
IPL3: Interrupt Priority Level Status bit(2) interrupt priority level greater than interrupt priority level less Register description remaining that dedicated interrupt control functions. IPL3 concatenated with IPL2:IPL0 bits (SR<7:5>) form interrupt priority level.
Note
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REGISTER 6-3:
R/W-0 NSTDIS Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL
INTCON1: INTERRUPT CONTROL REGISTER
NSTDIS: Interrupt Nesting Disable Interrupt nesting disabled Interrupt nesting enabled Unimplemented: Read MATHERR: Arithmetic Error Trap Status Overflow trap occurred Overflow trap occurred ADDRERR: Address Error Trap Status Address error trap occurred Address error trap occurred STKERR: Stack Error Trap Status Stack error trap occurred Stack error trap occurred OSCFAIL: Oscillator Failure Trap Status Oscillator failure trap occurred Oscillator failure trap occurred Unimplemented: Read
14-5
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REGISTER 6-4:
R/W-0 ALTIVT Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 INT2EP R/W-0 INT1EP
INTCON2: INTERRUPT CONTROL REGISTER
DISI R/W-0 INT0EP
ALTIVT: Enable Alternate Interrupt Vector Table Alternate Interrupt Vector Table standard (default) vector table DISI: DISI Instruction Status DISI instruction active DISI instruction active Unimplemented: Read INT2EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT1EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge INT0EP: External Interrupt Edge Detect Polarity Select Interrupt negative edge Interrupt positive edge
13-3
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REGISTER 6-5:
R/W-0 T2IF Legend: Readable Value 15-14
IFS0: INTERRUPT FLAG STATUS REGISTER
R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF R/W-0 INT0IF
R/W-0 OC2IF
R/W-0 IC2IF
R/W-0 T1IF
R/W-0 OC1IF
R/W-0 IC1IF
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read AD1IF: Conversion Complete Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1TXIF: UART1 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U1RXIF: UART1 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI1IF: SPI1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPF1IF: SPI1 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred T3IF: Timer3 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T2IF: Timer2 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC2IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC2IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read T1IF: Timer1 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC1IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC1IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT0IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-6:
R/W-0 U2TXIF Legend: Readable Value
IFS1: INTERRUPT FLAG STATUS REGISTER
R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF
Writable
Unimplemented bit, read cleared unknown
U2TXIF: UART2 Transmitter Interrupt Flag Status Interrupt request occurred Interrupt request occurred U2RXIF: UART2 Receiver Interrupt Flag Status Interrupt request occurred Interrupt request occurred INT2IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred T5IF: Timer5 Interrupt Flag Status Interrupt request occurred Interrupt request occurred T4IF: Timer4 Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC4IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred OC3IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read INT1IF: External Interrupt Flag Status Interrupt request occurred Interrupt request occurred CNIF: Input Change Notification Interrupt Flag Status Interrupt request occurred Interrupt request occurred CMIF: Comparator Interrupt Flag Status Interrupt request occurred Interrupt request occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred
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REGISTER 6-7:
R/W-0 IC5IF Legend: Readable Value 15-14 Writable Unimplemented bit, read cleared unknown R/W-0 IC4IF R/W-0 IC3IF R/W-0 SPI2IF
IFS2: INTERRUPT FLAG STATUS REGISTER
R/W-0 PMPIF R/W-0 OC5IF R/W-0 SPF2IF
Unimplemented: Read PMPIF: Parallel Master Port Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read OC5IF: Output Compare Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read IC5IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC4IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred IC3IF: Input Capture Channel Interrupt Flag Status Interrupt request occurred Interrupt request occurred Unimplemented: Read SPI2IF: SPI2 Event Interrupt Flag Status Interrupt request occurred Interrupt request occurred SPI2IF: SPI2 Fault Interrupt Flag Status Interrupt request occurred Interrupt request occurred
12-10
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REGISTER 6-8:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 MI2C2IF R/W-0 SI2C2IF
IFS3: INTERRUPT FLAG STATUS REGISTER
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