28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver n
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PIC16F913/914/916/917/946 Data Sheet
28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver nanoWatt Technology
2007 Microchip Technology Inc.
DS41250F
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Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
28/40/44/64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver nanoWatt Technology
High-Performance RISC CPU:
Only instructions learn: single-cycle instructions except branches Operating speed: oscillator/clock input instruction cycle Program Memory Read (PMR) capability Interrupt capability 8-level deep hardware stack Direct, Indirect Relative Addressing modes
Low-Power Features:
Standby Current: <100 2.0V, typical Operating Current: kHz, 2.0V, typical MHz, 2.0V, typical Watchdog Timer Current: 2.0V, typical
Peripheral Features:
Liquid Crystal Display module: 60/96/168 pixel drive capability 28/40/64-pin devices, respectively Four commons 24/35/53 pins input-only pin: High-current source/sink direct drive Interrupt-on-change Individually programmable weak pull-ups In-Circuit Serial Programming(ICSPTM) pins Analog comparator module with: analog comparators Programmable on-chip voltage reference (CVREF) module VDD) Comparator inputs outputs externally accessible Converter: 10-bit resolution channels Timer0: 8-bit timer/counter with 8-bit programmable prescaler Enhanced Timer1: 16-bit timer/counter with prescaler External Timer1 Gate (count enable) Option OSC1 OSC2 Timer1 oscillator INTOSCIO mode selected Timer2: 8-bit timer/counter with 8-bit period register, prescaler postscaler Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) Capture, Compare, modules: 16-bit Capture, max. resolution 12.5 16-bit Compare, max. resolution 10-bit PWM, max. frequency Synchronous Serial Port (SSP) with I2C
Special Microcontroller Features:
Precision Internal Oscillator: Factory calibrated ±1%, typical Software selectable frequency range Software tunable Two-Speed Start-up mode External Oscillator fail detect critical applications Clock mode switching during operation power savings Software selectable internal oscillator Power-Saving Sleep mode Wide operating voltage range (2.0V-5.5V) Industrial Extended temperature range Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) with software control option Enhanced Low-Current Watchdog Timer (WDT) with on-chip oscillator (software selectable nominal seconds with full prescaler) with software enable Multiplexed Master Clear with pull-up/input Programmable code protection High-Endurance Flash/EEPROM cell: 100,000 write Flash endurance 1,000,000 write EEPROM endurance Flash/Data EEPROM retention: years
2007 Microchip Technology Inc.
DS41250F-page
PIC16F913/914/916/917/946
Program Memory Flash (words/bytes) 4K/7K 4K/7K 8K/14K 8K/14K 8K/14K Data Memory SRAM (bytes) EEPROM (bytes) (segment drivers) 16(1) 16(1)
Device
10-bit (ch)
Timers 8/16-bit
PIC16F913 PIC16F914 PIC16F916 PIC16F917 PIC16F946 Note
COM3 SEG15 share same physical PIC16F913/916, therefore SEG15 available when using multiplex displays.
Diagrams PIC16F914/917, 40-Pin
40-pin PDIP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RE0/AN5/SEG21 RE1/AN6/SEG22 RE2/AN7/SEG23 RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RD0/COM3 RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 RD7/SEG20 RD6/SEG19 RD5/SEG18 RD4/SEG17 RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2
PIC16F914/917
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TABLE
Note
PIC16F914/917 40-PIN SUMMARY
AN2/VREFAN3/VREF+ SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 CCP2 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
2007 Microchip Technology Inc.
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PIC16F913/914/916/917/946
Diagrams PIC16F913/916, 28-Pin
28-pin PDIP, SOIC, SSOP
RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6
RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCK/SEG14 RB5/COM1 RB4/COM0 RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 RC7/RX/DT/SDI/SDA/SEG8 RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11
RB7/ICSPDAT/ICDDAT/SEG13
RB6/ICSPCLK/ICDCK/SEG14
28-pin
RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RE3/MCLR/VPP
PIC16F913/916 RB5/COM1
RB4/COM0
RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/COM3/SEG15 RA4/C1OUT/T0CKI/SEG4 RA5/AN4/C2OUT/SS/SEG5 RA7/OSC1/CLKIN/T1OSI RA6/OSC2/CLKOUT/T1OSO
RB3/SEG3 RB2/SEG2 RB1/SEG1 RB0/INT/SEG0 RC7/RX/DT/SDI/SDA/SEG8
PIC16F913/916
RC4/T1G/SDO/SEG11
RC5/T1CKI/CCP1/SEG10
RC6/TX/CK/SCK/SCL/SEG9
RC0/VLCD1
RC1/VLCD2
RC2/VLCD3
RC3/SEG6
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PIC16F913/914/916/917/946
TABLE
Note
PIC16F913/916 28-PIN (PDIP, SOIC, SSOP) SUMMARY
AN2/VREFAN3/VREF+ SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
2007 Microchip Technology Inc.
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PIC16F913/914/916/917/946
TABLE
Note
PIC16F913/916 28-PIN (QFN) SUMMARY
AN2/VREFAN3/VREF+ SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
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PIC16F913/914/916/917/946
Diagrams PIC16F914/917, 44-Pin
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2
44-pin TQFP
RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/C1-/AN0/SEG12 RA1/C2-/AN1/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/VREF+/C1+/SEG15
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 RB0/SEG0/INT RB1/SEG1 RB2/SEG2 RB3/SEG3
PIC16F914/917
RC0/VLCD1 RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
44-pin
RC6/TX/CK/SCK/SCL/SEG9 RC5/T1CKI/CCP1/SEG10 RC4/T1G/SDO/SEG11 RD3/SEG16 RD2/CCP2 RD0/COM3 RC3/SEG6 RC2/VLCD3 RC1/VLCD2 RC0/VLDC1
2007 Microchip Technology Inc.
RB3/SEG3 RB4/COM0 RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14 RB7/ICSPDAT/ICDDAT/SEG13 RE3/MCLR/VPP RA0/AN0/C1-/SEG12 RA1/AN1/C2-/SEG7 RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15
RC7/RX/DT/SDI/SDA/SEG8 RD4/SEG17 RD5/SEG18 RD6/SEG19 RD7/SEG20 RB0/INT/SEG0 RB1/SEG1 RB2/SEG2
PIC16F914/917
RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21 RA5/AN4/C2OUT/SS/SEG5 RA4/C1OUT/T0CKI/SEG4
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PIC16F913/914/916/917/946
TABLE
Note
PIC16F914/917 44-PIN (TQFP) SUMMARY
AN2/VREFAN3/VREF+ SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 CCP2 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
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PIC16F913/914/916/917/946
TABLE
Note
PIC16F914/917 44-PIN (QFN) SUMMARY
AN2/VREFAN3/VREF+ SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 CCP2 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
2007 Microchip Technology Inc.
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PIC16F913/914/916/917/946
Diagram PIC16F946
RC6/TX/CK/SCK/SCL/SEG9 RC7/RX/DT/SDI/SDA/SEG8
RC5/T1CKI/CCP1/SEG10
64-pin TQFP
RD5/SEG18 RD4/SEG17
RC4/T1G/SDO/SEG11
RD3/SEG16
RC2/VLCD3
RC1/VLCD2
RD0/COM3
RC3/SEG6
RD2/CCP2
RC0/VLCD1
RD6/SEG19 RD7/SEG20 RG0/SEG36 RG1/SEG37 RG2/SEG38 RG3/SEG39 RG4/SEG40 RG5/SEG41 RF0/SEG32 RF1/SEG33 RF2/SEG34 RF3/SEG35 RB0/INT/SEG0 RB1/SEG1
RF7/SEG31 RF6/SEG30 RF5/SEG29 RF4/SEG28 RE7/SEG27 RE6/SEG26 RE5/SEG25 RA6/OSC2/CLKOUT/T1OSO RA7/OSC1/CLKIN/T1OSI RE4/SEG24 RE3/MCLR/VPP RE2/AN7/SEG23 RE1/AN6/SEG22 RE0/AN5/SEG21
PIC16F946
RB7/ICSPDAT/ICDDAT/SEG13 AVSS
RB3/SEG3
RB5/COM1 RB6/ICSPCLK/ICDCK/SEG14
RA2/AN2/C2+/VREF-/COM2 RA3/AN3/C1+/VREF+/SEG15
RA5/AN4/C2OUT/SS/SEG5
RB2/SEG2
RB4/COM0
RA1/AN1/C2-/SEG7
RA4/C1OUT/T0CKI/SEG4
AVDD
RA0/AN0/C1-/SEG12
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PIC16F913/914/916/917/946
TABLE
Note
PIC16F946 64-PIN (TQFP) SUMMARY
AN2/VREFAN3/VREF+ SEG5 SEG12 SEG7 COM2 SEG15 SEG4 SEG0 SEG1 SEG2 SEG3 COM0 COM1 SEG14 SEG13 VLCD1 VLCD2 VLCD3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG32 SEG33 SEG34 Comparators C1C2C2+ C1OUT C2OUT Timers T0CKI T1OSO T1OSI T1CKI CCP1 CCP2 AUSART TX/CK RX/DT SCK/SCL SDI/SDA Interrupt Pull-Up Y(1) Basic OSC2/CLKOUT OSC1/CLKIN ICSPCLK/ICDCK ICSPDAT/ICDDAT MCLR/VPP
Pull-up enabled only with external MCLR configuration.
2007 Microchip Technology Inc.
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TABLE
Note
PIC16F946 64-PIN (TQFP) SUMMARY (CONTINUED)
SEG35 SEG28 SEG29 SEG30 SEG31 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 Comparators Timers AUSART Interrupt Pull-Up Basic AVDD AVSS
Pull-up enabled only with external MCLR configuration.
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Table Contents
Device Overview Memory Organization Ports Oscillator Module (With Fail-Safe Clock Monitor). Timer0 Module Timer1 Module with Gate Control. Timer2 Module Comparator Module. Addressable Universal Synchronous Asynchronous Receiver Transmitter (AUSART) 10.0 Liquid Crystal Display (LCD) Driver Module. 11.0 Programmable Low-Voltage Detect (PLVD) Module. 12.0 Analog-to-Digital Converter (ADC) Module 13.0 Data EEPROM Flash Program Memory Control 14.0 Module Overview 15.0 Capture/Compare/PWM (CCP) Module 16.0 Special Features CPU. 17.0 Instruction Summary 18.0 Development Support. 19.0 Electrical Specifications. 20.0 Characteristics Graphs Tables. 21.0 Packaging Information. Appendix Data Sheet Revision History. Appendix Migrating From Other PIC® Devices. Appendix Conversion Considerations Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System
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Errata
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2007 Microchip Technology Inc.
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PIC16F913/914/916/917/946
NOTES:
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PIC16F913/914/916/917/946
DEVICE OVERVIEW
PIC16F91X/946 devices covered this data sheet. They available 28/40/44/64-pin packages. Figure shows block diagram PIC16F913/916 device, Figure shows block diagram PIC16F914/917 device, Figure shows block diagram PIC16F946 device. Table shows pinout descriptions.
FIGURE 1-1:
PIC16F913/916 BLOCK DIAGRAM
Configuration Program Counter Flash 4K/8K Program Memory 8-Level Stack (13-bit) 256/352 bytes File Registers Addr PORTB PORTC Instruction Decode Control
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Data
PORTA
Program Instruction
Program Memory Read (PMR)
Addr Direct Addr Indirect Addr
STATUS
PORTE
OSC1/CLKIN OSC2/CLKOUT Timing Generation
Internal Oscillator Block
RE3/MCLR
Data EEPROM bytes Timer0 Timer1 Timer2 10-bit
Comparators
CCP1
Addressable USART
PLVD
2007 Microchip Technology Inc.
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FIGURE 1-2: PIC16F914/917 BLOCK DIAGRAM
Configuration Program Counter Flash 4K/8K Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) 256/352 bytes File Registers Addr PORTB PORTC Instruction Decode Control OSC1/CLKIN OSC2/CLKOUT Timing Generation
Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Data
PORTA
Program Memory Read (PMR)
Addr Indirect Addr
STATUS
PORTD
Internal Oscillator Block PORTE
RE3/MCLR
Timer0
Timer1
Timer2
10-bit
Data EEPROM bytes
Comparators
CCP1
CCP2
Addressable USART
PLVD
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FIGURE 1-3: PIC16F946 BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory Program Instruction Direct Addr 8-Level Stack (13-bit) bytes File Registers Addr Data PORTA PORTB PORTC PORTD PORTE RE3/MCLR PORTF PORTG Data EEPROM bytes
Program Memory Read (PMR)
Addr Indirect Addr
STATUS
Power-up Timer
Instruction Decode Control OSC1/CLKIN OSC2/CLKOUT Timing Generation
Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Internal Oscillator Block
AVDD AVSS
Timer0
Timer1
Timer2
10-bit
Comparators
CCP1
CCP2
Addressable USART
PLVD
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TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS
Function
C1SEG12 RA1/AN1/C2-/SEG7 C2SEG7 RA2/AN2/C2+/VREF-/COM2 VREFCOM2 RA3/AN3/C1+/VREF+/COM3(1)/ SEG15 VREF+ COM3(1) SEG15 RA4/C1OUT/T0CKI/SEG4 C1OUT T0CKI SEG4 RA5/AN4/C2OUT/SS/SEG5 C2OUT SEG5 RA6/OSC2/CLKOUT/T1OSO OSC2 CLKOUT T1OSO RA7/OSC1/CLKIN/T1OSI OSC1 CLKIN T1OSI RB0/INT/SEG0 SEG0 Legend: Analog input output compatible input High Voltage
Name
RA0/AN0/C1-/SEG12
Input Output Type Type
XTAL XTAL CMOS General purpose I/O.
Description
Analog input Channel Comparator negative input. analog output. Analog input Channel Comparator negative input. analog output. Analog input Channel Comparator positive input. External Voltage Reference negative. analog output. Analog input Channel Comparator positive input. External Voltage Reference positive. analog output. analog output.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Comparator output. XTAL XTAL Timer0 clock input. analog output. Analog input Channel Slave select input. analog output. Crystal/Resonator. Timer1 oscillator output. Crystal/Resonator. Clock input. Timer1 oscillator input. External interrupt pin. analog output.
CMOS General purpose I/O. CMOS Comparator output.
CMOS General purpose I/O. CMOS TOSC/4 reference clock. CMOS General purpose I/O.
CMOS General purpose I/O. Individually enabled pull-up.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels Power XTAL Crystal
Note
COM3 available PIC16F913/916 PIC16F914/917 PIC16F946. Pins available PIC16F914/917 PIC16F946 only. Pins available PIC16F946 only. Schmitt trigger inputs have special input levels.
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TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
SEG1 RB2/SEG2 RB3/SEG3 RB4/COM0 SEG2 SEG3 COM0 RB5/COM1 COM1 RB6/ICSPCLK/ICDCK/SEG14 ICSPCLK ICDCK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 ICSPDAT ICDDAT SEG13 RC0/VLCD1 RC1/VLCD2 RC2/VLCD3 RC3/SEG6 RC4/T1G/SDO/SEG11 VLCD1 VLCD2 VLCD3 SEG6 SEG11 RC5/T1CKI/CCP1/SEG10 T1CKI CCP1 SEG10 Legend: Analog input output compatible input High Voltage
Name
RB1/SEG1
Input Output Type Type
analog output. analog output. analog output.
Description
CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually enabled pull-up. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. analog output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. ICSPclock. clock. analog output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSP Data I/O. CMOS Data I/O. analog output. analog input. analog input. analog input. analog output. Timer1 gate input. analog output. Timer1 clock input. analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Serial data output. CMOS General purpose I/O. CMOS Capture input/Compare output/PWM output.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels Power XTAL Crystal
Note
COM3 available PIC16F913/916 PIC16F914/917 PIC16F946. Pins available PIC16F914/917 PIC16F946 only. Pins available PIC16F946 only. Schmitt trigger inputs have special input levels.
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TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
SEG9 RC7/RX/DT/SDI/SDA/SEG8 SEG8 RD0/COM3(1, RD1(2) RD2/CCP2(2) RD3/SEG16(2) RD4/SEG17(2) RD5/SEG18 RD6/SEG19
Name
RC6/TX/CK/SCK/SCL/SEG9
Input Output Type Type
ST(4)
Description
CMOS General purpose I/O. CMOS USART asynchronous serial transmit. CMOS USART synchronous serial clock. CMOS clock. I2Cclock. analog output. USART asynchronous serial receive.
CMOS General purpose I/O. CMOS USART synchronous serial data. CMOS data input. I2Cdata. analog output. analog output.
COM3 CCP2 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21
CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS Capture input/Compare output/PWM output. CMOS General purpose I/O. analog output. analog output. analog output. analog output. analog output. Analog input Channel analog output. Analog input Channel analog output. Analog input Channel analog output. Digital input only. Master Clear with internal pull-up. Programming voltage. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O.
RD7/SEG20(2) RE0/AN5/SEG21(2)
RE1/AN6/SEG22(2)
SEG22
CMOS General purpose I/O.
RE2/AN7/SEG23(2)
SEG23
CMOS General purpose I/O.
RE3/MCLR/VPP
MCLR
Legend:
Analog input output compatible input High Voltage
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels Power XTAL Crystal
Note
COM3 available PIC16F913/916 PIC16F914/917 PIC16F946. Pins available PIC16F914/917 PIC16F946 only. Pins available PIC16F946 only. Schmitt trigger inputs have special input levels.
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TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
SEG24 RE5/SEG25
Name
RE4/SEG24(3)
Input Output Type Type
CMOS General purpose I/O. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. analog output. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O. CMOS General purpose I/O.
Description
SEG25 SEG26 SEG27 SEG32 SEG33 SEG34 SEG35 SEG28 SEG29 SEG30 SEG31 SEG36 SEG37 SEG38 SEG39 SEG10 SEG41 AVDD AVSS
RE6/SEG26(3) RE7/SEG27(3) RF0/SEG32(3) RF1/SEG33
RF2/SEG34(3) RF3/SEG35(3) RF4/SEG28(3) RF5/SEG29
RF6/SEG30(3) RF7/SEG31(3) RG0/SEG36(3) RG1/SEG37
RG2/SEG38(3) RG3/SEG39(3) RG4/SEG40(3) RG5/SEG41 AVDD(3) AVSS(3) Legend:
Analog power supply microcontroller. Analog ground reference microcontroller. Power supply microcontroller.
Analog input output compatible input High Voltage
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels Power XTAL Crystal
Note
COM3 available PIC16F913/916 PIC16F914/917 PIC16F946. Pins available PIC16F914/917 PIC16F946 only. Pins available PIC16F946 only. Schmitt trigger inputs have special input levels.
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TABLE 1-1: PIC16F91X/946 PINOUT DESCRIPTIONS (CONTINUED)
Function
Analog input output compatible input High Voltage
Name
Legend:
Input Output Type Type
Description
Ground reference microcontroller.
CMOS CMOS compatible input output Open Drain Schmitt Trigger input with CMOS levels Power XTAL Crystal
Note
COM3 available PIC16F913/916 PIC16F914/917 PIC16F946. Pins available PIC16F914/917 PIC16F946 only. Pins available PIC16F946 only. Schmitt trigger inputs have special input levels.
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MEMORY ORGANIZATION
Program Memory Organization
FIGURE 2-2:
PROGRAM MEMORY STACK PIC16F916/917/PIC16F946
pc<12:0>
PIC16F91X/946 13-bit program counter capable addressing program memory space PIC16F913/914 (0000h-0FFFh) program memory space PIC16F916/ PIC16F946 (0000h-1FFFh). Accessing location above memory boundaries PIC16F913 PIC16F914 will cause wrap around within first space. Reset vector 0000h interrupt vector 0004h.
CALL, RETURN RETFIE, RETLW
Stack Level Stack Level Stack Level Reset Vector Interrupt Vector Page 0000h 0004h 0005h 07FFh 0800h 0FFFh 1000h Page 17FFh 1800h 1FFFh
FIGURE 2-1:
PROGRAM MEMORY STACK PIC16F913/914
pc<12:0>
CALL, RETURN RETFIE, RETLW
On-chip Program Memory Page
Stack Level Stack Level Stack Level Reset Vector Interrupt Vector On-chip Program Memory Page Page 07FFh 0800h 0FFFh 1000h 0000h 0004h 0005h
Page
1FFFh
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Data Memory Organization
data memory partitioned into multiple banks which contain General Purpose Registers (GPRs) Special Function Registers (SFRs). Bits bank select bits. Bank selected Bank selected Bank selected Bank selected
Each bank extends (128 bytes). lower locations each bank reserved Special Function Registers. Above Special Function Registers General Purpose Registers, implemented static RAM. implemented banks contain Special Function Registers. Some frequently used Special Function Registers from bank mirrored another bank code reduction quicker access.
2.2.1
GENERAL PURPOSE REGISTER FILE
register file organized bits PIC16F913/914, bits PIC16F916/917 bits PIC16F946. Each register accessed either directly indirectly through File Select Register (FSR) (see Section "Indirect Addressing, INDF Registers").
2.2.2
SPECIAL FUNCTION REGISTERS
Special Function Registers registers used peripheral functions controlling desired operation device (see Tables 2-1, 2-2, 2-4). These registers static RAM. Special Function Registers classified into sets: core peripheral. Special Function Registers associated with "core" described this section. Those related operation peripheral features described section that peripheral feature.
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FIGURE 2-3: PIC16F913/916 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 General Purpose Register Bytes accesses 70h-7Fh Bank File Address Indirect addr. 100h TMR0 101h 102h STATUS 103h 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h 112h LCDDATA3 113h LCDDATA4 114h 115h LCDDATA6 116h LCDDATA7 117h 118h LCDDATA9 119h LCDDATA10 11Ah 11Bh LCDSE0 11Ch LCDSE1 11Dh 11Eh 11Fh 120h General Purpose Register Bytes accesses 70h-7Fh Bank 16Fh 170h 17Fh accesses 70h-7Fh Bank 1EFh 1F0h 1FFh File Address Indirect addr. 180h OPTION_REG 181h 182h STATUS 183h 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh Reserved 18Eh Reserved 18Fh 190h File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG ADRESH ADCON0 General Purpose Register Bytes Bank
General Purpose Register(2) Bytes
Note
Unimplemented data memory locations, read `0'. physical register. PIC16F913, unimplemented data memory locations, read `0'.
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FIGURE 2-4: PIC16F914/917 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 General Purpose Register Bytes accesses 70h-7Fh Bank File Address Indirect addr. 100h TMR0 101h 102h STATUS 103h 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h LCDDATA2 112h LCDDATA3 113h LCDDATA4 114h LCDDATA5 115h LCDDATA6 116h LCDDATA7 117h LCDDATA8 118h LCDDATA9 119h LCDDATA10 11Ah LCDDATA11 11Bh LCDSE0 11Ch LCDSE1 11Dh LCDSE2 11Eh 11Fh 120h General Purpose Register Bytes accesses 70h-7Fh Bank 16Fh 170h 17Fh accesses 70h-7Fh Bank 1EFh 1F0h 1FFh File Address Indirect addr. 180h OPTION_REG 181h 182h STATUS 183h 184h 185h TRISB 186h 187h 188h 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2(1) 18Dh Reserved 18Eh Reserved 18Fh 190h File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 General Purpose Register Bytes Bank
General Purpose Register(2) Bytes
Note
Unimplemented data memory locations, read `0'. physical register. PIC16F914, unimplemented data memory locations, read `0'.
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FIGURE 2-5: PIC16F946 SPECIAL FUNCTION REGISTERS
File Address Indirect addr. OPTION_REG STATUS TRISA TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 General Purpose Register Bytes accesses 70h-7Fh Bank File Address Indirect addr. 100h TMR0 101h 102h STATUS 103h 104h WDTCON 105h PORTB 106h LCDCON 107h LCDPS 108h LVDCON 109h PCLATH 10Ah INTCON 10Bh EEDATL 10Ch EEADRL 10Dh EEDATH 10Eh EEADRH 10Fh LCDDATA0 110h LCDDATA1 111h LCDDATA2 112h LCDDATA3 113h LCDDATA4 114h LCDDATA5 115h LCDDATA6 116h LCDDATA7 117h LCDDATA8 118h LCDDATA9 119h LCDDATA10 11Ah LCDDATA11 11Bh LCDSE0 11Ch LCDSE1 11Dh LCDSE2 11Eh 11Fh 120h General Purpose Register Bytes accesses 70h-7Fh Bank 16Fh 170h 17Fh File Address Indirect addr. 180h OPTION_REG 181h 182h STATUS 183h 184h TRISF 185h TRISB 186h TRISG 187h PORTF 188h PORTG 189h PCLATH 18Ah INTCON 18Bh EECON1 18Ch EECON2 18Dh Reserved 18Eh Reserved 18Fh LCDDATA12 190h LCDDATA13 191h LCDDATA14 192h LCDDATA15 193h LCDDATA16 194h LCDDATA17 195h LCDDATA18 196h LCDDATA19 197h LCDDATA20 198h LCDDATA21 199h LCDDATA22 19Ah LCDDATA23 19Bh LCDSE3 19Ch LCDSE4 19Dh LCDSE5 19Eh 19Fh 1A0h General Purpose Register Bytes accesses 70h-7Fh Bank 1EFh 1F0h 1FFh File Address Indirect addr. TMR0 STATUS PORTA PORTB PORTC PORTD PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 General Purpose Register Bytes Bank
Note
Unimplemented data memory locations, read `0'. physical register.
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TABLE 2-1:
Addr Bank 1Bh(2) 1Ch(2) 1Dh(2) INDF TMR0 STATUS PORTA PORTB PORTC PORTD(2) PORTE PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte RE7(3) EEIF OSFIF RE6(3) PEIE ADIF C2IF RE5(3) T0IE RCIF C1IF RE4(3) INTE TXIF LCDIF RBIE SSPIF RE2(2) T0IF CCP1IF LVDIF RE1(2) INTF TMR2IF RE0(2) RBIF TMR1IF CCP2IF(2) Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 000x 0000 0000 0000 -0-0 xxxx xxxx xxxx xxxx TMR1CS T2CKPS1 SSPM1 TMR1ON T2CKPS0 SSPM0 0000 0000 0000 0000 TOUTPS2 SSPEN TOUTPS1 TOUTPS0 SSPM3 TMR2ON SSPM2 -000 0000 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx CCP1M3 ADDEN CCP1M2 FERR CCP1M1 OERR CCP1M0 RX9D 0000 0000 000x 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CCP2M3 CHS1 CCP2M2 CHS0 CCP2M1 GO/DONE CCP2M0 ADON 0000 xxxx xxxx CHS2 0000 0000 41,226 99,226 40,226 32,226 41,226 44,226 54,226 62,226 71,226 76,226 40,226 34,226 37,226 38,226 102,226 102,226 105,226 107,226 108,226 196,226 195,226 213,226 213,226 212,226 131,226 130,226 128,227 213,227 213,227 212,227 182,227 180,227 Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Write Buffer upper bits Program Counter
Holding Register Least Significant Byte 16-bit TMR1 Holding Register Most Significant Byte 16-bit TMR1 T1GINV WCOL TMR1GE TOUTPS3 SSPOV T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Timer2 Module Register Synchronous Serial Port Receive Buffer/Transmit Register Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) SPEN CCP1X SREN CCP1Y CREN
USART Transmit Data Register USART Receive Data Register Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) ADFM VCFG1 CCP2X VCFG0 CCP2Y Result Register High Byte
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. PIC16F914/917 PIC16F946 only, forced PIC16F913/916. PIC16F946 only, forced PIC16F91X.
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TABLE 2-2:
Addr Bank INDF OPTION_REG STATUS TRISA TRISB TRISC TRISD(3) TRISE PCLATH INTCON PIE1 PIE2 PCON OSCCON OSCTUNE ANSEL SSPADD SSPSTAT WPUB IOCB CMCON1 TXSTA SPBRG CMCON0 VRCON ADRESL ADCON1 Addressing this location uses contents address data memory (not physical register) RBPU TRISA7 TRISB7 TRISC7 TRISD7 EEIE OSFIE ANS7(3) INTEDG TRISA6 TRISB6 TRISC6 TRISD6 PEIE ADIE C2IE IRCF2 ANS6(3) T0CS TRISA5 TRISB5 TRISC5 TRISD5 T0IE RCIE C1IE IRCF1 ANS5(3) T0SE TRISA4 TRISB4 TRISC4 TRISD4 TRISA3 TRISB3 TRISC3 TRISD3 TRISA2 TRISB2 TRISC2 TRISD2 TRISA1 TRISB1 TRISC1 TRISD1 TRISA0 TRISB0 TRISC0 TRISD0 Program Counter's (PC) Least Significant Byte Indirect Data Memory Address Pointer xxxx xxxx 1111 1111 0000 0000 0001 1xxx xxxx xxxx 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 0000 0000 000x 0000 0000 0000 -0-0 -110 q000 0000 1111 1111 1111 1111 0000 0000 WPUB2 BRGH SPBRG2 WPUB1 T1GSS TRMT SPBRG1 WPUB0 C2SYNC TX9D SPBRG0 0000 0000 1111 1111 0000 0000 -010 0000 0000 C2INV ADCS1 C1INV ADCS0 0000 0000 0-0- 0000 xxxx xxxx -000 ADCS2 WPUB5 IOCB5 TXEN SPBRG5 WPUB4 IOCB4 SYNC SPBRG4 WPUB3 SPBRG3 41,226 33,227 40,226 32,226 41,226 44,227 54,227 62,227 71,227 76,227 40,226 34,226 35,227 36,227 39,227 88,227 92,227 43,227 107,227 202,227 194,227 55,227 54,227 117,227 130,227 132,227 116,227 118,227 182,227 181,227 Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
TRISE7(2) TRISE6(2) TRISE5(2) TRISE4(2) TRISE3(5) TRISE2(3) TRISE1(3) TRISE0(3) Write Buffer upper bits Program Counter INTE TXIE LCDIE SBOREN IRCF0 TUN4 ANS4 RBIE SSPIE OSTS(4) TUN3 ANS3 T0IF CCP1IE LVDIE TUN2 ANS2 INTF TMR2IE TUN1 ANS1 RBIF TMR1IE CCP2IE(3) TUN0 ANS0
Timer2 Period Register Synchronous Serial Port (I2C mode) Address Register WPUB7 IOCB7 CSRC SPBRG7 WPUB6 IOCB6 SPBRG6
Unimplemented Unimplemented C2OUT VREN C1OUT
Result Register Byte
Legend: Note
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. PIC16F946 only, forced PIC16F91X. PIC16F914/917 PIC16F946 only, forced PIC16F913/916. value OSTS dependent value Configuration Word (CONFIG) device. Section "Oscillator Control". read-only; TRISE3 always.
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TABLE 2-3:
Addr Bank 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h INDF TMR0 STATUS WDTCON PORTB LCDCON LCDPS LVDCON Addressing this location uses contents address data memory (not physical register) Timer0 Module Register Program Counter's (PC) Least Significant Byte LCDEN EEDATL7 SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SE15 SE23 SLPEN BIASMD PEIE EEDATL6 SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SE14 SE22 WERR LCDA IRVST T0IE EEDATL5 WDTPS3 VLCDEN LVDEN INTE EEDATL4 WDTPS2 RBIE EEDATL3 EEADRL3 EEDATH3 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SE11 SE19 WDTPS1 LVDL2 T0IF EEDATL2 EEADRL2 EEDATH2 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SE10 SE18 WDTPS0 LMUX1 LVDL1 INTF EEDATL1 EEADRL1 EEDATH1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SE17 SWDTEN LMUX0 LVDL0 RBIF EEDATL0 Indirect Data Memory Address Pointer xxxx xxxx xxxx xxxx 0000 0000 0001 1xxx xxxx xxxx 1000 xxxx xxxx 0001 0011 0000 0000 -100 0000 0000 000x 0000 0000 41,226 99,226 40,226 32,226 41,226 235,227 54,226 145,227 146,227 145,228 40,226 34,226 188,228 188,228 188,228 188,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 Name
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
10Ah PCLATH 10Bh INTCON 10Ch EEDATL 10Dh EEADRL 10Eh EEDATH 10Fh EEADRH 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh LCDDATA0 LCDDATA1 LCDDATA2(2) LCDDATA3 LCDDATA4 LCDDATA5(2) LCDDATA6 LCDDATA7 LCDDATA8(2) LCDDATA9 LCDDATA10 LCDDATA11(2)
Write Buffer upper bits Program Counter
EEADRL7 EEADRL6 EEADRL5 EEADRL4 EEDATH5 EEDATH4 SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SE13 SE21 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SE12 SE20
EEADRL0 0000 0000 EEDATH0 0000 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 SE16
EEADRH4 EEADRH3 EEADRH2 EEADRH1 EEADRH0 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
11Ch LCDSE0(3) 11Dh LCDSE1(3) 11Eh 11Fh Legend: Note LCDSE2(2,3)
Unimplemented
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. PIC16F914/917 PIC16F946 only. This register only initialized reset unchanged other Resets.
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TABLE 2-4:
Addr Bank 180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note Addressing this location uses contents address data memory (not physical register) OPTION_REG RBPU INTEDG T0CS T0SE STATUS TRISF(3) TRISB TRISG(3) PORTF(3) PORTG(3) PCLATH INTCON EECON1 EECON2 LCDDATA12(3) LCDDATA13(3) LCDDATA14(3) LCDDATA15(3) LCDDATA16(3) LCDDATA17(3) LCDDATA18(3) LCDDATA19(3) LCDDATA20(3) LCDDATA21(3) LCDDATA22(3) LCDDATA23(3) LCDSE3(2, LCDSE4
PIC16F91X/946 SPECIAL FUNCTION REGISTERS SUMMARY BANK
Value POR, Page
Name
INDF
xxxx xxxx 1111 1111 0000 0000
41,226 33,227 40,226 32,226 41,226 81,228 54,227 84,228 81,228 84,228 40,226 34,226 189,229 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,228 147,229 147,229 147,229
Program Counter (PC) Least Significant Byte TRISF7 TRISB7 EEPGD Reserved Reserved SEG31 COM0 SEG39 COM0 SEG31 COM1 SEG39 COM1 SEG31 COM2 SEG39 COM2 SEG31 COM3 SEG39 COM3 SE31 SE39 SEG30 COM0 SEG38 COM0 SEG30 COM1 SEG38 COM1 SEG30 COM2 SEG38 COM2 SEG30 COM3 SEG38 COM3 SE30 SE38 SEG29 COM0 SEG37 COM0 SEG29 COM1 SEG37 COM1 SEG29 COM2 SEG37 COM2 SEG29 COM3 SEG37 COM3 SE29 SE37 SEG28 COM0 SEG36 COM0 SEG28 COM1 SEG36 COM1 SEG28 COM2 SEG36 COM2 SEG28 COM3 SEG36 COM3 SE28 SE36 SEG27 COM0 SEG35 COM0 SEG27 COM1 SEG35 COM1 SEG27 COM2 SEG35 COM2 SEG27 COM3 SEG35 COM3 SE27 SE35 SEG26 COM0 SEG34 COM0 SEG26 COM1 SEG34 COM1 SEG26 COM2 SEG34 COM2 SEG26 COM3 SEG34 COM3 SE26 SE34 SEG25 COM0 SE33 COM0 SEG41 COM0 SEG25 COM1 SEG33 COM1 SEG41 COM1 SEG25 COM2 SEG33 COM2 SEG41 COM2 SEG25 COM3 SEG33 COM3 SEG41 COM3 SE25 SE33 SE41 SEG24 COM0 SEG32 COM0 SEG40 COM0 SEG24 COM1 SEG32 COM1 SEG40 COM1 SEG24 COM2 SEG32 COM2 SEG40 COM2 SEG24 COM3 SEG32 COM3 SEG40 COM3 SE24 SE32 SE40 TRISF6 TRISB6 PEIE TRISF5 TRISB5 TRISG5 T0IE TRISF4 TRISB4 TRISG4 INTE TRISF3 TRISB3 TRISG3 RBIE WRERR TRISF2 TRISB2 TRISG2 T0IF WREN TRISF1 TRISB1 TRISG1 INTF TRISF0 TRISB0 TRISG0 RBIF Indirect Data Memory Address Pointer
0001 1xxx xxxx xxxx 1111 1111 1111 1111 1111 xxxx xxxx xxxx 0000 0000 000x x000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000
Write Buffer upper bits Program Counter
EEPROM Control Register (not physical register)
LCDSE5(2,
Unimplemented
Unimplemented locations read `0', unchanged, unknown, value depends condition, shaded unimplemented Other (non Power-up) Resets include MCLR Reset Watchdog Timer Reset during normal operation. This register only initialized reset unchanged other Resets. PIC16F946 only.
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2.2.2.1 STATUS Register
STATUS register, shown Register 2-1, contains: arithmetic status Reset status bank select bits data memory (SRAM) STATUS register destination instruction, like other register. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS will clear upper three bits bit. This leaves STATUS register `000u u1uu' (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter STATUS register, because these instructions affect Status bits. other instructions affecting Status bits (see Section 17.0 "Instruction Summary"). Note bits operate Borrow Digit Borrow bits, respectively, subtraction.
REGISTER 2-1:
R/W-0 Legend: Readable Value
STATUS: STATUS REGISTER
R/W-0 R/W-0 R/W-x R/W-x DC(1) R/W-x C(1)
Writable
Unimplemented bit, read cleared unknown
IRP: Register Bank Select (used indirect addressing) Bank (100h-1FFh) Bank (00h-FFh) RP<1:0>: Register Bank Select bits (used direct addressing) Bank (00h-7Fh) Bank (80h-FFh) Bank (100h-17Fh) Bank (180h-1FFh) Time-out After power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit Carry/Borrow (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) carry-out from low-order result occurred carry-out from low-order result Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Borrow, polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high-order low-order source register.
Note
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2.2.2.2 OPTION register
Note: achieve prescaler assignment Timer0, assign prescaler setting OPTION register `1'. Section "Timer1 Prescaler". OPTION register, shown Register 2-2, readable writable register, which contains various control bits configure: Timer0/WDT prescaler External RB0/INT interrupt Timer0 Weak pull-ups PORTB
REGISTER 2-2:
R/W-1 RBPU Legend: Readable Value
OPTION_REG: OPTION REGISTER
R/W-1 INTEDG R/W-1 T0CS R/W-1 T0SE R/W-1 R/W-1 R/W-1 R/W-1
Writable
Unimplemented bit, read cleared unknown
RBPU: PORTB Pull-up Enable PORTB pull-ups disabled PORTB pull-ups enabled individual bits WPUB register INTEDG: Interrupt Edge Select Interrupt rising edge RB0/INT Interrupt falling edge RB0/INT T0CS: Timer0 Clock Source Select Transition RA4/T0CKI Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select Increment high-to-low transition RA4/T0CKI Increment low-to-high transition RA4/T0CKI PSA: Prescaler Assignment Prescaler assigned Prescaler assigned Timer0 module PS<2:0>: Prescaler Rate Select bits
Value Timer0 Rate Rate
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2.2.2.3 INTCON Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. INTCON register readable writable register, which contains various enable flag bits TMR0 register overflow, PORTB change external RB0/INT/SEG0 interrupts.
REGISTER 2-3:
R/W-0 Legend: Readable Value
INTCON: INTERRUPT CONTROL REGISTER
R/W-0 PEIE R/W-0 T0IE R/W-0 INTE R/W-0 RBIE(1) R/W-0 T0IF
R/W-0 INTF
R/W-x RBIF
Writable
Unimplemented bit, read cleared unknown
GIE: Global Interrupt Enable Enables unmasked interrupts Disables interrupts PEIE: Peripheral Interrupt Enable Enables unmasked peripheral interrupts Disables peripheral interrupts T0IE: Timer0 Overflow Interrupt Enable Enables Timer0 interrupt Disables Timer0 interrupt INTE: RB0/INT External Interrupt Enable Enables RB0/INT external interrupt Disables RB0/INT external interrupt RBIE: PORTB Change Interrupt Enable bit(1) Enables PORTB change interrupt Disables PORTB change interrupt T0IF: Timer0 Overflow Interrupt Flag bit(2) TMR0 register overflowed (must cleared software) TMR0 register overflow INTF: RB0/INT External Interrupt Flag RB0/INT external interrupt occurred (must cleared software) RB0/INT external interrupt occur RBIF: PORTB Change Interrupt Flag When least PORTB general purpose pins changed state (must cleared software) None PORTB general purpose pins have changed state appropriate bits IOCB register must also set. T0IF when Timer0 rolls over. Timer0 unchanged Reset should initialized before clearing T0IF bit.
Note
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2.2.2.4 PIE1 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE1 register contains interrupt enable bits, shown Register 2-4.
REGISTER 2-4:
R/W-0 EEIE Legend: Readable Value
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE
Writable
Unimplemented bit, read cleared unknown
EEIE: Write Complete Interrupt Enable Enables write complete interrupt Disables write complete interrupt ADIE: Converter (ADC) Interrupt Enable Enables interrupt Disables interrupt RCIE: USART Receive Interrupt Enable Enables USART receive interrupt Disables USART receive interrupt TXIE: USART Transmit Interrupt Enable Enables USART transmit interrupt Disables USART transmit interrupt SSPIE: Synchronous Serial Port (SSP) Interrupt Enable Enables interrupt Disables interrupt CCP1IE: CCP1 Interrupt Enable Enables CCP1 interrupt Disables CCP1 interrupt TMR2IE: TMR2 Match Interrupt Enable Enables Timer2 match interrupt Disables Timer2 match interrupt TMR1IE: Timer1 Overflow Interrupt Enable Enables Timer1 overflow interrupt Disables Timer1 overflow interrupt
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2.2.2.5 PIE2 Register
Note: PEIE INTCON register must enable peripheral interrupt. PIE2 register contains interrupt enable bits, shown Register 2-5.
REGISTER 2-5:
R/W-0 OSFIE Legend: Readable Value
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER
R/W-0 C2IE R/W-0 C1IE R/W-0 LCDIE R/W-0 LVDIE R/W-0 CCP2IE(1)
Writable
Unimplemented bit, read cleared unknown
OSFIE: Oscillator Fail Interrupt Enable Enables oscillator fail interrupt Disables oscillator fail interrupt C2IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt C1IE: Comparator Interrupt Enable Enables Comparator interrupt Disables Comparator interrupt LCDIE: Module Interrupt Enable Enables interrupt Disables interrupt Unimplemented: Read LVDIE: Voltage Detect Interrupt Enable Enables Interrupt Disables Interrupt Unimplemented: Read CCP2IE: CCP2 Interrupt Enable bit(1) Enables CCP2 interrupt Disables CCP2 interrupt PIC16F914/PIC16F917/PIC16F946 only.
Note
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2.2.2.6 PIR1 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR1 register contains interrupt flag bits, shown Register 2-6.
REGISTER 2-6:
R/W-0 EEIF Legend: Readable Value
PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 ADIF RCIF TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF
Writable
Unimplemented bit, read cleared unknown
EEIF: Write Operation Interrupt Flag write operation completed (must cleared software) write operation completed started ADIF: Converter Interrupt Flag conversion complete (must cleared software) conversion completed been started RCIF: USART Receive Interrupt Flag USART receive buffer full (cleared reading RCREG) USART receive buffer full TXIF: USART Transmit Interrupt Flag USART transmit buffer empty (cleared writing TXREG) USART transmit buffer full SSPIF: Synchronous Serial Port (SSP) Interrupt Flag Transmission/Reception complete (must cleared software) Waiting Transmit/Receive CCP1IF: CCP1 Interrupt Flag Capture mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode Unused this mode TMR2IF: Timer2 Interrupt Flag Timer2 match occurred (must cleared software) Timer2 match occurred TMR1IF: Timer1 Overflow Interrupt Flag TMR1 register overflowed (must cleared software) TMR1 register overflow
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2.2.2.7 PIR2 Register
Note: Interrupt flag bits when interrupt condition occurs, regardless state corresponding enable global enable bit, INTCON register. User software should ensure appropriate interrupt flag bits clear prior enabling interrupt. PIR2 register contains interrupt flag bits, shown Register 2-7.
REGISTER 2-7:
R/W-0 OSFIF Legend: Readable Value
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER
R/W-0 C2IF R/W-0 C1IF R/W-0 LCDIF R/W-0 LVDIF R/W-0 CCP2IF(1)
Writable
Unimplemented bit, read cleared unknown
OSFIF: Oscillator Fail Interrupt Flag System oscillator failed, clock input changed INTOSC (must cleared software) System clock operating C2IF: Comparator Interrupt Flag Comparator output (C2OUT bit) changed (must cleared software) Comparator output (C2OUT bit) changed C1IF: Comparator Interrupt Flag Comparator output (C1OUT bit) changed (must cleared software) Comparator output (C1OUT bit) changed LCDIF: Module Interrupt generated interrupt generated interrupt Unimplemented: Read LVDIF: Voltage Detect Interrupt Flag generated interrupt generated interrupt Unimplemented: Read CCP2IF: CCP2 Interrupt Flag bit(1) Capture Mode: TMR1 register capture occurred (must cleared software) TMR1 register capture occurred Compare Mode: TMR1 register compare match occurred (must cleared software) TMR1 register compare match occurred mode: Unused this mode PIC16F914/PIC16F917/PIC16F946 only.
Note
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2.2.2.8 PCON Register
Power Control (PCON) register contains flag bits (see Table 16-2) differentiate between Power-on Reset (POR) Brown-out Reset (BOR) Watchdog Timer Reset (WDT) External MCLR Reset
PCON register also controls software enable BOR. PCON register bits shown Register 2-8.
REGISTER 2-8:
Legend: Readable Value
PCON: POWER CONTROL REGISTER
R/W-1 SBOREN R/W-0 R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read SBOREN: Software Enable bit(1) enabled disabled Unimplemented: Read POR: Power-on Reset Status Power-on Reset occurred Power-on Reset occurred (must software after Power-on Reset occurs) BOR: Brown-out Reset Status Brown-out Reset occurred Brown-out Reset occurred (must software after Power-on Reset Brown-out Reset occurs) BOREN<1:0> Configuration Word register this control BOR.
Note
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PCLATH
Note There Status bits indicate stack overflow stack underflow conditions. There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, RETURN, RETLW RETFIE instructions vectoring interrupt address. Program Counter (PC) bits wide. byte comes from register, which readable writable register. high byte (PC<12:8>) directly readable writable comes from PCLATH. Reset, cleared. Figure shows situations loading upper example Figure shows loaded write (PCLATH<4:0> PCH). lower example Figure shows loaded during CALL GOTO instruction (PCLATH<4:3> PCH).
Program Memory Paging
FIGURE 2-6:
LOADING DIFFERENT SITUATIONS
Instruction with Destination Result
PCLATH<4:0>
PCLATH PCLATH<4:3> GOTO, CALL OPCODE<10:0>
PIC16F91X/946 devices capable addressing continuous word block program memory. CALL GOTO instructions provide only bits address allow branching within program memory page. When doing CALL GOTO instruction, upper bits address provided PCLATH<4:3>. When doing CALL GOTO instruction, user must ensure that page select bits programmed that desired program memory page addressed. return from CALL instruction interrupt) executed, entire 13-bit POPed stack. Therefore, manipulation PCLATH<4:3> bits required RETURN instructions (which POPs address from stack). Note: contents PCLATH register unchanged after RETURN RETFIE instruction executed. user must rewrite contents PCLATH register subsequent subroutine calls GOTO instructions.
PCLATH
2.3.1
COMPUTED GOTO
computed GOTO accomplished adding offset program counter (ADDWF PCL). When performing table read using computed GOTO method, care should exercised table location crosses memory boundary (each 256-byte block). Refer Application Note AN556, "Implementing Table Read" (DS00556).
Example shows calling subroutine page program memory. This example assumes that PCLATH saved restored Interrupt Service Routine interrupts used).
EXAMPLE 2-1:
CALL SUBROUTINE PAGE FROM PAGE
2.3.2
STACK
500h PCLATH,4 PCLATH,3 CALL SUB1_P1 900h SUB1_P1 RETURN
PIC16F91X/946 family 8-level 13-bit wide hardware stack (see Figures 2-2). stack space part either program data space Stack Pointer readable writable. PUSHed onto stack when CALL instruction executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation. stack operates circular buffer. This means that after stack been PUSHed eight times, ninth PUSH overwrites value that stored from first PUSH. tenth PUSH overwrites second PUSH (and on).
;Select page ;(800h-FFFh) ;Call subroutine ;page (800h-FFFh) ;page (800h-FFFh) ;called subroutine ;page (800h-FFFh) ;return ;Call subroutine page ;(000h-7FFh)
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Indirect Addressing, INDF Registers
EXAMPLE 2-2:
MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE
INDIRECT ADDRESSING
020h 020h INDF FSR,4 NEXT ;initialize pointer ;clear INDF register ;inc pointer ;all done? clear next ;yes continue
INDF register physical register. Addressing INDF register will cause indirect addressing. Indirect addressing possible using INDF register. instruction using INDF register actually accesses data pointed File Select Register (FSR). Reading INDF itself indirectly will produce 00h. Writing INDF register indirectly results operation (although Status bits affected). effective 9-bit address obtained concatenating 8-bit register STATUS register, shown Figure 2-7. simple program clear location 020h-02Fh using indirect addressing shown Example 2-2.
FIGURE 2-7:
DIRECT/INDIRECT ADDRESSING PIC16F91X/946
Indirect Addressing File Select Register
Direct Addressing From Opcode
Bank Select
Location Select
Bank Select 180h
Location Select
Data Memory
Bank Note: Bank Bank Bank
1FFh
memory detail, Figures 2-4.
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NOTES:
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PORTS
ANSEL Register
PIC16F913/914/916/917/946 family devices includes several 8-bit PORT registers along with their corresponding TRIS registers four port: PORTA TRISA PORTB TRISB PORTC TRISC PORTD TRISD(1) PORTE TRISE PORTF TRISF(2) PORTG TRISG(2) Note PIC16F914/917 PIC16F946 only. PIC16F946 only PORTA, PORTB, PORTC RE3/MCLR/VPP implemented devices. PORTD RE<2:0> (PORTE) implemented only PIC16F914/917 PIC16F946. RE<7:4> (PORTE), PORTF PORTG implemented only PIC16F946. ANSEL register (Register 3-1) used configure Input mode analog. Setting appropriate ANSEL high will cause digital reads read allow analog functions operate correctly. state ANSEL bits affect digital output functions. with TRIS clear ANSEL will still operate digital output, Input mode will analog. This cause unexpected behavior when executing read-modify-write instructions affected port.
REGISTER 3-1:
R/W-1 ANS7(2) Legend: Readable Value
ANSEL: ANALOG SELECT REGISTER
R/W-1 ANS6(2) R/W-1 ANS5(2) R/W-1 ANS4 R/W-1 ANS3 R/W-1 ANS2 R/W-1 ANS1 R/W-1 ANS0
Writable
Unimplemented bit, read cleared unknown
ANS<7:0>: Analog Select bits Analog select between analog digital function pins AN<7:0>, respectively. Analog input. assigned analog input(1). Digital I/O. assigned port special function. Setting analog input automatically disables digital input circuitry, weak pull-ups, interrupt-on-change available. corresponding TRIS must Input mode order allow external control voltage pin. PIC16F914/PIC16F917/PIC16F946 only.
Note
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PORTA TRISA Registers
PORTA 8-bit wide, bidirectional port. corresponding data direction register TRISA (Register 3-3). Setting TRISA will make corresponding PORTA input (i.e., corresponding output driver High-Impedance mode). Clearing TRISA will make corresponding PORTA output (i.e., contents output latch selected pin). Example shows initialize PORTA. Five pins PORTA configured analog inputs. These pins, RA<3:0>, configured analog inputs device power-up must reconfigured user used I/O's. This done writing appropriate values CMCON0 ANSEL registers (see Example 3-1). Reading PORTA register (Register 3-2) reads status pins, whereas writing will write PORT latch. write operations read-modify-write operations. Therefore, write port means that port pins read, this value modified then written PORT data latch. TRISA register controls direction PORTA pins, even when they being used analog inputs. user must ensure bits TRISA register maintained when using them analog inputs. pins configured analog inputs always read `0'. Note CMCON0 ANSEL registers must initialized configure analog channel digital input. Pins configured analog inputs will read `0'.
EXAMPLE 3-1:
BANKSEL CLRF BANKSEL MOVLW MOVWF CLRF MOVLW MOVWF PORTA PORTA TRISA CMCON0 ANSEL 0F0h TRISA
INITIALIZING PORTA
;Init PORTA ;Set RA<2:0> ;digital ;Make PORTA digital ;Set RA<7:4> inputs ;and RA<3:0> outputs
REGISTER 3-2:
R/W-x Legend: Readable Value
PORTA: PORTA REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable RA<7:0>: PORTA bits Port >VIH min. Port <VIL max.
Unimplemented bit, read cleared unknown
REGISTER 3-3:
R/W-1 TRISA7 Legend: Readable Value
TRISA: PORTA TRI-STATE REGISTER
R/W-1 TRISA6 R/W-1 TRISA5 R/W-1 TRISA4 R/W-1 TRISA3 R/W-1 TRISA2 R/W-1 TRISA1 R/W-1 TRISA0
Writable TRISA<7:0>: PORTA Tri-State Control bits PORTA configured input (tri-stated) PORTA configured output
Unimplemented bit, read cleared unknown
Note
TRISA<7:6> always reads Oscillator modes.
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3.2.1 DESCRIPTIONS DIAGRAMS
Each PORTA multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions, refer appropriate section this data sheet.
3.2.1.1
RA0/AN0/C1-/SEG12
Figure shows diagram this pin. configurable function following: general purpose analog input analog input Comparator analog output
FIGURE 3-1:
BLOCK DIAGRAM
Data
PORTA
Data Latch TRISA Analog Input SE12 LCDEN TRISA SE12 LCDEN Input Buffer
TRIS Latch
PORTA SEG12 SE12 LCDEN Converter Comparator
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3.2.1.2 RA1/AN1/C2-/SEG7
Figure shows diagram this pin. configurable function following: general purpose analog input analog input Comparator analog output
FIGURE 3-2:
BLOCK DIAGRAM
Data
PORTA
Data Latch TRISA Analog Input LCDEN TRISA LCDEN Input Buffer
TRIS Latch
PORTA SEG7 LCDEN Converter Comparator
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3.2.1.3 RA2/AN2/C2+/VREF-/COM2
Figure shows diagram this pin. configurable function following: general purpose analog input analog input Comparator voltage reference input analog output
FIGURE 3-3:
BLOCK DIAGRAM
Data
PORTA
Data Latch TRISA Analog Input LCDEN LMUX<1:0> LCDEN LMUX<1:0> Input Buffer
TRIS Latch
TRISA
PORTA LCDEN LMUX<1:0>
COM2
Converter Comparator Module VREF- Input
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3.2.1.4 RA3/AN3/C1+/VREF+/COM3/SEG15
Figure shows diagram this pin. configurable function following: general purpose input analog input analog input from Comparator voltage reference input analog outputs
FIGURE 3-4:
BLOCK DIAGRAM
Data PORTA
Data Latch TRISA Analog Input LCDMODE_EN(2) TRISA Input Buffer
TRIS Latch
LCDMODE_EN(2)
PORTA COM3(1) SEG15 LCDMODE_EN(2)
Converter Comparator Module VREF+ Input
Note
PIC16F913/916 only. PIC16F913/916, LCDMODE_EN LCDEN (SE15 LMUX<1:0> 11). PIC16F914/917 PIC16F946, LCDMODE_EN LCDEN SE15.
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3.2.1.5 RA4/C1OUT/T0CKI/SEG4
Figure shows diagram this pin. configurable function following: general purpose digital output from Comparator clock input Timer0 analog output
FIGURE 3-5:
BLOCK DIAGRAM
CM<2:0> C1OUT Data PORTA TRISA LCDEN Input Buffer TRIS Latch Data Latch
TRISA
LCDEN
PORTA Schmitt Trigger T0CKI LCDEN LCDEN
SEG4
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3.2.1.6 RA5/AN4/C2OUT/SS/SEG5
Figure shows diagram this pin. configurable function following: general purpose digital output from Comparator slave select input analog output analog input
FIGURE 3-6:
BLOCK DIAGRAM
CM<2:0> C2OUT Data TRISA Analog Input LCDEN LCDEN Input Buffer TRIS Latch Data Latch
PORTA
TRISA
PORTA Input LCDEN SEG5 Converter
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3.2.1.7 RA6/OSC2/CLKOUT/T1OSO
Figure shows diagram this pin. configurable function following: general purpose crystal/resonator connection clock output Timer1 oscillator connection
FIGURE 3-7:
BLOCK DIAGRAM
FOSC CLKOUT (FOSC/4)
From OSC1 Oscillator Circuit
Data PORTA
Data Latch TRIS Latch FOSC 00x, T1OSCEN Input Buffer TRISA
TRISA FOSC 00x, T1OSCEN
PORTA
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3.2.1.8 RA7/OSC1/CLKIN/T1OSI
Figure shows diagram this pin. configurable function following: general purpose crystal/resonator connection clock input Timer1 oscillator connection
FIGURE 3-8:
BLOCK DIAGRAM
OSC2 Oscillator Circuit
FOSC
Data PORTA
Data Latch TRISA FOSC
FOSC Input Buffer
TRIS Latch
TRISA
PORTA
TABLE 3-1:
Name ADCON0 ANSEL CMCON0 CONFIG(1) OPTION_REG LCDCON LCDSE0 LCDSE1 PORTA SSPCON T1CON TRISA Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH PORTA
ADFM ANS7 C2OUT RBPU LCDEN SE15 WCOL T1GINV TRISA7 VCFG1 ANS6 C1OUT INTEDG SLPEN SE14 SSPOV TMR1GE TRISA6 VCFG0 ANS5 C2INV MCLRE T0CS WERR SE13 SSPEN TRISA5 CHS2 ANS4 C1INV PWRTE T0SE VLCDEN SE12 TRISA4 CHS1 ANS3 WDTE SE11 SSPM3 TRISA3 CHS0 ANS2 FOSC2 SE10 SSPM2 T1SYNC TRISA2 GO/DONE ANS1 FOSC1 LMUX1 SSPM1 TMR1CS TRISA1 ADON ANS0 FOSC0 LMUX0 SSPM0 TMR1ON TRISA0 Value POR, 0000 0000 1111 1111 0000 0000 1111 1111 0001 0011 0000 0000 0000 0000 xxxx xxxx 0000 0000 0000 0000 1111 1111 Value other Resets 0000 0000 1111 1111 0000 0000 1111 1111 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu 1111 1111
T1CKPS1 T1CKPS0 T1OSCEN
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTA. Configuration Word register (CONFIG) operation register bits.
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PORTB TRISB Registers Additional PORTB Functions
PORTB 8-bit bidirectional port. PORTB pins have weak pull-up feature, PORTB<7:4> implements interrupt-on-input change function. PORTB also used Serial Flash programming interface interface. RB<7:6> used data clock signals, respectively, both serial programming in-circuit debugger features device. Also, configured external interrupt input.
3.4.1
WEAK PULL-UPS
EXAMPLE 3-2:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTB PORTB TRISB 0FFh TRISB
INITIALIZING PORTB
;Init PORTB ;Set RB<7:0> inputs
Each PORTB pins individually configurable internal weak pull-up. Control bits WPUB<7:0> enable disable each pull-up. Refer Register 3-7. Each weak pull-up automatically turned when port configured output. pull-ups disabled Power-on Reset RBPU OPTION register.
3.4.2
INTERRUPT-ON-CHANGE
Four PORTB pins individually configurable interrupt-on-change pin. Control bits IOCB<7:4> enable disable interrupt function each pin. Refer Register 3-6. interrupt-on-change feature disabled Power-on Reset. enabled interrupt-on-change pins, values compared with value latched last read PORTB. `mismatch' outputs last read OR'd together PORTB Change Interrupt flag (RBIF) INTCON register (Register 2-3). This interrupt wake device from Sleep. user, Interrupt Service Routine, clears interrupt read write PORTB. This will mismatch condition. Clear flag RBIF.
mismatch condition will continue flag RBIF. Reading writing PORTB will mismatch condition allow flag RBIF cleared. latch holding last read value affected MCLR Brown-out Reset. After these Resets, RBIF flag will continue mismatch present. Note: change should occur when read operation being executed (start cycle), then RBIF interrupt flag set. Furthermore, since read write port affects bits that port, care must taken when using multiple pins Interrupt-on-change mode. Changes seen while servicing changes another pin.
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REGISTER 3-4:
R/W-x Legend: Readable Value Writable Unimplemented bit, read cleared unknown
PORTB: PORTB REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
RB<7:0>: PORTB bits Port >VIH min. Port <VIL max.
REGISTER 3-5:
R/W-1 TRISB7 Legend: Readable Value
TRISB: PORTB TRI-STATE REGISTER
R/W-1 TRISB6 R/W-1 TRISB5 R/W-1 TRISB4 R/W-1 TRISB3 R/W-1 TRISB2 R/W-1 TRISB1 R/W-1 TRISB0
Writable
Unimplemented bit, read cleared unknown
TRISB<7:0>: PORTB Tri-State Control bits PORTB configured input (tri-stated) PORTB configured output
REGISTER 3-6:
R/W-0 IOCB7 Legend: Readable Value
IOCB: PORTB INTERRUPT-ON-CHANGE REGISTER
R/W-0 IOCB6 R/W-0 IOCB5 R/W-0 IOCB4
Writable
Unimplemented bit, read cleared unknown
IOCB<7:4>: Interrupt-on-Change bits Interrupt-on-change enabled Interrupt-on-change disabled Unimplemented: Read
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REGISTER 3-7:
R/W-1 WPUB7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
WPUB: WEAK PULL-UP REGISTER
R/W-1 WPUB6 R/W-1 WPUB5 R/W-1 WPUB4 R/W-1 WPUB3 R/W-1 WPUB2 R/W-1 WPUB1 R/W-1 WPUB0
WPUB<7:0>: Weak Pull-up Register bits Pull-up enabled Pull-up disabled Global RBPU must enabled individual pull-ups enabled. weak pull-up device automatically disabled Output mode (TRISx<7:0>
Note
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3.4.3 DESCRIPTIONS DIAGRAMS 3.4.3.2 RB1/SEG1
Each PORTB multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such interrupts, refer appropriate section this data sheet. Figure shows diagram this pin. configurable function following: general purpose analog output
3.4.3.3
RB2/SEG2
3.4.3.1
RB0/INT/SEG0
Figure shows diagram this pin. configurable function following: general purpose external edge triggered interrupt analog output
Figure shows diagram this pin. configurable function following: general purpose analog output
3.4.3.4
RB3/SEG3
Figure shows diagram this pin. configurable function following: general purpose analog output
FIGURE 3-9:
BLOCK DIAGRAM RB<3:0>
WPUB<3:0> SE<3:0> Weak Pull-up Data Latch
RBPU Data PORTB
TRISB
TRIS Latch SE<3:0> LCDEN Input Buffer
TRISB
PORTB SEG<3:0> SE<3:0> LCDEN
Schmitt Trigger INT(1) LCDEN
Note
only.
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3.4.3.5 RB4/COM0
Figure 3-10 shows diagram this pin. configurable function following: general purpose analog output
FIGURE 3-10:
BLOCK DIAGRAM
WPUB<4> RBPU Data PORTB Data Latch TRISB TRIS Latch TRISB LCDEN
LCDEN
Weak Pull-up
Input Buffer
PORTB
Interrupt-onChange RBIF Write RBIF LCDEN From other RB<7:4> pins LCDEN
PORTB
COM0
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3.4.3.6 RB5/COM1
Figure 3-11 shows diagram this pin. configurable function following: general purpose analog output
FIGURE 3-11:
BLOCK DIAGRAM
WPUB<5> RBPU Data PORTB Data Latch TRISB TRIS Latch TRISB LCDEN LMUX<1:0> LCDEN LMUX<1:0>
Weak Pull-up
Input Buffer
PORTB LCDEN LMUX<1:0>
Interrupt-onChange RBIF Write RBIF From other RB<7:4> pins
PORTB
COM1
LCDEN LMUX<1:0>
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3.4.3.7 RB6/ICSPCLK/ICDCK/SEG14
Figure 3-12 shows diagram this pin. configurable function following: general purpose In-Circuit Serial Programmingclock clock input analog output
FIGURE 3-12:
BLOCK DIAGRAM
Program Mode/ICD Mode WPUB<6> RBPU SE14 LCDEN Data PORTB Data Latch TRISB TRIS Latch TRISB PORTB SE14 LCDEN Input Buffer Weak Pull-up
RBIF Interrupt-onChange Write RBIF Schmitt Trigger ICSPCLK From other RB<7:4> pins Program Mode/ICD
PORTB
Program Mode Mode (SE14 LCDEN)
SEG14
SE14 LCDEN
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3.4.3.8 RB7/ICSPDAT/ICDDAT/SEG13
Figure 3-13 shows diagram this pin. configurable function following: general purpose In-Circuit Serial ProgrammingI/O data analog output
FIGURE 3-13:
BLOCK DIAGRAM
PORT/Program Mode/ICD ICSPDAT
RBPU SE13 LCDEN
Weak Pull-up
Data PORTB
Data Latch
TRISB DRVEN
TRIS Latch SE13 LCDEN Input Buffer
TRISB PORTB
Program Mode/ICD
Interrupt-onChange
RBIF From other RB<7:4> pins
PORTB
Write RBIF Schmitt Trigger ICSPDAT/ICDDAT Program Mode Mode (SE13 LCDEN)
SEG13
SE13 LCDEN
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TABLE 3-2:
Name INTCON IOCB LCDCON LCDSE0 LCDSE1 OPTION_REG PORTB TRISB WPUB Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH PORTB
IOCB7 LCDEN SE15 RBPU TRISB7 WPUB7 PEIE IOCB6 SLPEN SE14 INTEDG TRISB6 WPUB6 T0IE IOCB5 WERR SE13 T0CS TRISB5 WPUB5 INTE IOCB4 VLCDEN SE12 T0SE TRISB4 WPUB4 RBIE SE11 TRISB3 WPUB3 T0IF SE10 TRISB2 WPUB2 INTF LMUX1 TRISB1 WPUB1 RBIF LMUX0 TRISB0 WPUB0 Value POR, 0000 000x 0000 -0001 0011 0000 0000 0000 0000 1111 1111 xxxx xxxx 1111 1111 1111 1111 Value other Resets 0000 000x 0000 -0001 0011 uuuu uuuu uuuu uuuu 1111 1111 uuuu uuuu 1111 1111 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTB. This register only initialized reset unchanged other Resets. Configuration Word register DEBUG <12> also associated with PORTB. Register 16-1 more details.
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PORTC TRISC Registers
EXAMPLE 3-3:
BANKSEL CLRF BANKSEL MOVLW MOVWF BANKSEL CLRF PORTC PORTC TRISC 0FFh TRISC LCDCON LCDCON
INITIALIZING PORTC
;Init PORTC ;Set RC<7:0> inputs ;Disable VLCD<3:1> ;inputs RC<2:0>
PORTC 8-bit bidirectional port. PORTC multiplexed with several peripheral functions. PORTC pins have Schmitt Trigger input buffers. PORTC pins have latch bits (PORTC register). They will modify contents PORTC latch (when written); thus, modifying value driven corresponding TRISC configured output.
REGISTER 3-8:
R/W-x Legend: Readable Value
PORTC: PORTC REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RC<7:0>: PORTC bits Port >VIH min. Port <VIL max.
REGISTER 3-9:
R/W-1 TRISC7 Legend: Readable Value
TRISC: PORTC TRI-STATE REGISTER
R/W-1 TRISC6 R/W-1 TRISC5 R/W-1 TRISC4 R/W-1 TRISC3 R/W-1 TRISC2 R/W-1 TRISC1 R/W-1 TRISC0
Writable
Unimplemented bit, read cleared unknown
TRISC<7:0>: PORTC Tri-State Control bits PORTC configured input (tri-stated) PORTC configured output
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3.5.1 DESCRIPTIONS DIAGRAMS 3.5.1.3 RC2/VLCD3
Each PORTC multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such SSP, refer appropriate section this data sheet. Figure 3-16 shows diagram this pin. configurable function following: general purpose analog input bias voltage
3.5.1.1
RC0/VLCD1
Figure 3-14 shows diagram this pin. configurable function following: general purpose analog input bias voltage
3.5.1.2
RC1/VLCD2
Figure 3-15 shows diagram this pin. configurable function following: general purpose analog input bias voltage
FIGURE 3-14:
Data PORTC
BLOCK DIAGRAM
Data Latch
TRISC
TRIS Latch (VLCDEN LMUX<1:0> TRISC Schmitt Trigger PORTC (LCDEN LMUX<1:0>
VLCD1
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FIGURE 3-15: BLOCK DIAGRAM
Data PORTC
Data Latch
TRISC
TRIS Latch (VLCDEN LMUX<1:0> Schmitt Trigger PORTC (LCDEN LMUX<1:0>
TRISC
VLCD2
FIGURE 3-16:
BLOCK DIAGRAM
Data PORTC
Data Latch
TRISC
TRIS Latch
VLCDEN TRISC Schmitt Trigger PORTC LCDEN
VLCD3
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3.5.1.4 RC3/SEG6
Figure 3-17 shows diagram this pin. configurable function following: general purpose analog output
FIGURE 3-17:
BLOCK DIAGRAM
Data PORTC
Data Latch
TRISC
TRIS Latch
LCDEN TRISC Schmitt Trigger PORTC LCDEN
SEG6 LCDEN
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3.5.1.5 RC4/T1G/SDO/SEG11
Figure 3-18 shows diagram this pin. RC4pin configurable function following: general purpose Timer1 gate input serial data output analog output
FIGURE 3-18:
BLOCK DIAGRAM
PORT/SDO Select
Data PORTC
Data Latch TRIS Latch
TRISC
TRISC
SE11 LCDEN
Schmitt Trigger
PORTC Timer1 Gate SEG11 SE11 LCDEN
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3.5.1.6 RC5/T1CKI/CCP1/SEG10
Figure 3-19 shows diagram this pin. configurable function following: general purpose Timer1 clock input Capture input, Compare output output analog output
FIGURE 3-19:
BLOCK DIAGRAM
(PORT/CCP1 Select) CCPMX CCP1 Data Data PORTC TRISC TRIS Latch Data Latch
TRISC
SE10 LCDEN
Schmitt Trigger
PORTC Timer1 Clock Input SEG10 SE10 LCDEN
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3.5.1.7 RC6/TX/CK/SCK/SCL/SEG9
Figure 3-20 shows diagram this pin. configurable function following: general purpose asynchronous serial output synchronous clock clock data analog output
FIGURE 3-20:
BLOCK DIAGRAM
PORT/USART/SSP Mode Select(1) I2CData TX/CK Data Data Data PORTC TRISC TRIS Latch Data Latch
USART I2CDrive
TRISC
LCDEN
Schmitt Trigger
PORTC CK/SCL/SCK Input SEG9 LCDEN
Note
three data output sources enabled, following priority order will used: USART data (highest) data PORT data (lowest)
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3.5.1.8 RC7/RX/DT/SDI/SDA/SEG8
Figure 3-21 shows diagram this pin. configurable function following: general purpose asynchronous serial input synchronous serial data data input data analog output
FIGURE 3-21:
BLOCK DIAGRAM
USART/I2CMode Select(1) Data I2CData
PORT/(USART I2CTM) Select Data PORTC
Data Latch
TRISC
LCDEN
TRIS Latch Schmitt Trigger
I2CDrive SCEN Drive
TRISC
PORTC RX/SDI Input SEG8 Note LCDEN
three data output sources enabled, following priority order will used: USART data (highest) data PORT data (lowest)
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TABLE 3-3:
Name CCP1CON LCDCON LCDSE0 LCDSE1 PORTC RCSTA SSPCON T1CON TRISC Legend:
SUMMARY REGISTERS ASSOCIATED WITH PORTC
LCDEN SE15 SPEN WCOL T1GINV TRISC7 SLPEN SE14 SSPOV TMR1GE TRISC6 CCP1X WERR SE13 SREN SSPEN T1CKPS1 TRISC5 CCP1Y VLCDEN SE12 CREN T1CKPS0 TRISC4 CCP1M3 SE11 ADDEN SSPM3 T1OSCEN TRISC3 CCP1M2 SE10 FERR SSPM2 T1SYNC TRISC2 CCP1M1 LMUX1 OERR SSPM1 TMR1CS TRISC1 CCP1M0 LMUX0 RX9D SSPM0 TMR1ON TRISC0 Value POR, 0000 0001 0011 0000 0000 0000 0000 xxxx xxxx 0000 000x 0000 0000 0000 0000 1111 1111 Value other Resets 0000 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 0000 000x 0000 0000 uuuu uuuu 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTC.
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PORTD TRISD Registers
EXAMPLE 3-4:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTD PORTD TRISD TRISD
INITIALIZING PORTD
;Init PORTD ;Set RD<7:0> inputs
PORTD 8-bit port with Schmitt Trigger input buffers. Each individually configured input output. PORTD only available PIC16F914/917 PIC16F946.
REGISTER 3-10:
R/W-x Legend: Readable Value
PORTD: PORTD REGISTER
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RD<7:0>: PORTD bits Port >VIH min. Port <VIL max.
REGISTER 3-11:
R/W-1 TRISD7 Legend: Readable Value
TRISD: PORTD TRI-STATE REGISTER
R/W-1 R/W-1 TRISD5 R/W-1 TRISD4 R/W-1 TRISD3 R/W-1 TRISD2 R/W-1 TRISD1 R/W-1 TRISD0
TRISD6
Writable
Unimplemented bit, read cleared unknown
TRISD<7:0>: PORTD Tri-State Control bits PORTD configured input (tri-stated) PORTD configured output
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3.6.1 DESCRIPTIONS DIAGRAMS 3.6.1.7 RD6/SEG19
Each PORTD multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such Comparator ADC, refer appropriate section this data sheet. Figure 3-25 shows diagram this pin. configurable function following: general purpose analog output
3.6.1.8
RD7/SEG20
3.6.1.1
RD0/COM3
Figure 3-22 shows diagram this pin. configurable function following: general purpose analog output
Figure 3-25 shows diagram this pin. configurable function following: general purpose analog output
3.6.1.2
Figure 3-23 shows diagram this pin. configurable function following: general purpose
3.6.1.3
RD2/CCP2
Figure 3-24 shows diagram this pin. configurable function following: general purpose Capture input, Compare output output
3.6.1.4
RD3/SEG16
Figure 3-25 shows diagram this pin. configurable function following: general purpose analog output
3.6.1.5
RD4/SEG17
Figure 3-25 shows diagram this pin. configurable function following: general purpose analog output
3.6.1.6
RD5/SEG18
Figure 3-25 shows diagram this pin. configurable function following: general purpose analog output
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FIGURE 3-22: BLOCK DIAGRAM
Data PORTD
Data Latch TRISD
TRIS Latch
TRISD
LCDEN LMUX<1:0> Schmitt Trigger
PORTD LCDEN LMUX<1:0>
COM3
FIGURE 3-23:
BLOCK DIAGRAM
Data PORTD
Data Latch TRISD
TRIS Latch Schmitt Trigger
TRISD
PORTD
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FIGURE 3-24: BLOCK DIAGRAM
(PORT/CCP2 Select) CCPMX CCP2 Data Data PORTD
Data Latch
TRISD
TRIS Latch
Schmitt Trigger
TRISD
PORTD CCP2 Input
FIGURE 3-25:
BLOCK DIAGRAM RD<7:3>
Data PORTD
Data Latch TRISD
TRIS Latch SE<20:16> LCDEN TRISD
Schmitt Trigger
PORTD SE<20:16> LCDEN
SEG<20:16>
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TABLE 3-4:
Name CCP2CON(1) LCDCON LCDSE2(1) PORTD(1) TRISD(1) Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH PORTD(1)
LCDEN SE23 TRISD7 SLPEN SE22 TRISD6 CCP2X WERR SE21 TRISD5 CCP2Y VLCDEN SE20 TRISD4 CCP2M3 SE19 TRISD3 CCP2M2 SE18 TRISD2 CCP2M1 LMUX1 SE17 TRISD1 CCP2M0 LMUX0 SE16 TRISD0 Value POR, 0000 0001 0011 0000 0000 xxxx xxxx 1111 1111 Value other Resets 0000 0001 0011 uuuu uuuu uuuu uuuu 1111 1111
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTD. PIC16F914/917 PIC16F946 only.
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PORTE TRISE Registers
EXAMPLE 3-5:
BANKSEL CLRF BANKSEL MOVLW MOVWF CLRF PORTE PORTE TRISE TRISE ANSEL
INITIALIZING PORTE
;Init PORTE ;Set RE<3:0> inputs ;Make RE<2:0> I/O's
PORTE 1-bit, 4-bit 8-bit port with Schmitt Trigger input buffers. RE<7:4, 2:0> individually configured inputs outputs only available input MCLRE Configuration Word (Register 16-1). RE<2:0> only available PIC16F914/917 PIC16F946. RE<7:4> only available PIC16F946.
REGISTER 3-12:
R/W-x RE7(1,3) Legend: Readable Value
PORTE: PORTE REGISTER
R/W-x R/W-x RE5(1,3) R/W-x RE4(1,3) R/W-x RE2(2,4) R/W-x RE1(2,4) R/W-x RE0(2,4)
RE6(1,3)
Writable
Unimplemented bit, read cleared unknown
RE<7:0>: PORTE bits Port >VIH min. Port <VIL max. PIC16F946 only. PIC16F914/917 PIC16F946 only. PIC16F91X, Read `0'. PIC16F913/916, Read `0'.
Note
REGISTER 3-13:
R/W-1 TRISE7(1,3) Legend: Readable Value
TRISE: PORTE TRI-STATE REGISTER
R/W-1 R/W-1 TRISE5(1,3) R/W-1 TRISE4(1,3) TRISE3 R/W-1 TRISE2(2,4) R/W-1 TRISE1(2,4) R/W-1 TRISE0(2,4)
TRISE6(1,3)
Writable
Unimplemented bit, read cleared unknown
TRISE<7:0>: PORTE Tri-State Control bits PORTE configured input (tri-stated) PORTE configured output PIC16F946 only. PIC16F914/917 PIC16F946 only. PIC16F91X, Read `0'. PIC16F913/916, Read `0'.
Note
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3.7.1 DESCRIPTIONS DIAGRAMS 3.7.1.7 RE6/SEG26(2)
Each PORTE multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions such Comparator ADC, refer appropriate section this data sheet. Figure 3-28 shows diagram this pin. RE6/SEG26 configurable function following: general purpose analog output
3.7.1.1
RE0/AN5/SEG21(1)
3.7.1.8
RE7/SEG27(2)
Figure 3-26 shows diagram this pin. configurable function following: general purpose analog input analog output
Figure 3-28 shows diagram this pin. RE7/SEG27 configurable function following: general purpose analog output Note available PIC16F914/917 PIC16F946 only. available PIC16F946 only.
3.7.1.2
RE1/AN6/SEG22(1)
Figure 3-26 shows diagram this pin. configurable function following: general purpose analog input analog output
3.7.1.3
RE2/AN7/SEG23(1)
Figure 3-26 shows diagram this pin. configurable function following: general purpose analog input analog output
3.7.1.4
RE3/MCLR/VPP
Figure 3-27 shows diagram this pin. configurable function following: digital input only Master Clear Reset with weak pull-up programming voltage reference input
3.7.1.5
RE4/SEG24(2)
Figure 3-28 shows diagram this pin. RE4/SEG24 configurable function following: general purpose analog output
3.7.1.6
RE5/SEG25(2)
Figure 3-28 shows diagram this pin. RE5/SEG25 configurable function following: general purpose analog output
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FIGURE 3-26: BLOCK DIAGRAM RE<2:0> (PIC16F914/917 PIC16F946 ONLY)
Data PORTE
Data Latch TRISE Analog Mode TRISE SEG<23:21> LCDEN Schmitt LCDEN Trigger
TRIS Latch
PORTE SEG<23:21> AN<7:5> SEG<23:21> LCDEN
FIGURE 3-27:
BLOCK DIAGRAM
Schmitt Trigger Buffer
MCLR circuit
MCLR Filter
Programming mode
Detect MCLRE Input Schmitt Trigger Buffer
Data TRISE
PORTE
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FIGURE 3-28: BLOCK DIAGRAM RE<7:4> (PIC16F946 ONLY)
Data PORTE
Data Latch TRISE Analog Mode TRISE SEG<27:24> LCDEN Schmitt Trigger
TRIS Latch
PORTE SEG<27:24> AN<7:5> SEG<27:24> LCDEN
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TABLE 3-5:
Name ADCON0 ANSEL LCDCON LCDSE2(1,2) LCDSE3(1, PORTE TRISE Legend: Note
SUMMARY REGISTERS ASSOCIATED WITH PORTE
ADFM ANS7 LCDEN SE23 SE31 RE7(3) VCFG1 ANS6 SLPEN SE22 SE30 RE6(3) TRISE6(3) VCFG0 ANS5 WERR SE21 SE29 RE5(3) TRISE5(3) CHS2 ANS4 VLCDEN SE20 SE28 RE4(3) TRISE4(3) CHS1 ANS3 SE19 SE27 TRISE3(4) CHS0 ANS2 SE18 SE26 RE2(2) TRISE2(2) GO/DONE ANS1 LMUX1 SE17 SE25 RE1(2) TRISE1(2) ADON ANS0 LMUX0 SE16 SE24 RE0(2) TRISE0(2) Value POR, 0000 0000 1111 1111 0001 0011 0000 0000 0000 0000 xxxx xxxx 1111 1111 Value other Resets 0000 0000 1111 1111 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111
TRISE7(3)
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTC. This register only initialized reset unchanged other Resets. PIC16F914/917 PIC16F946 only. PIC16F946 only. read-only; TRISE always.
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PORTF TRISF Registers
EXAMPLE 3-6:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTF PORTF TRISF 0FFh TRISF
INITIALIZING PORTF
;Init PORTF ;Set RF<7:0> inputs
PORTF 8-bit port with Schmitt Trigger input buffers. RF<7:0> individually configured inputs outputs, depending state port direction. port bits also multiplexed with segment functions. PORTF available PIC16F946 only.
REGISTER 3-14:
R/W-x Legend: Readable Value
PORTF: PORTF REGISTER(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
RF<7:0>: PORTF bits Port >VIH min. Port <VIL max. PIC16F946 only.
Note
REGISTER 3-15:
R/W-1 TRISF7 Legend: Readable Value
TRISF: PORTF TRI-STATE REGISTER(1)
R/W-1 R/W-1 TRISF5 R/W-1 TRISF4 R/W-1 TRISF3 R/W-1 TRISF2 R/W-1 TRISF1 R/W-1 TRISF0
TRISF6
Writable
Unimplemented bit, read cleared unknown
TRISF<7:0>: PORTF Tri-State Control bits PORTF configured input (tri-stated) PORTF configured output PIC16F946 only.
Note
2007 Microchip Technology Inc.
DS41250F-page
PIC16F913/914/916/917/946
3.8.1 DESCRIPTIONS DIAGRAMS 3.8.1.7 RF6/SEG30
Each PORTF multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions, refer appropriate section this data sheet. Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.1
RF0/SEG32
3.8.1.8
RF7/SEG31
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.2
RF1/SEG33
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.3
RF2/SEG34
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.4
RF3/SEG35
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.5
RF4/SEG28
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
3.8.1.6
RF5/SEG29
Figure 3-29 shows diagram this pin. configurable function following: general purpose analog output
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
FIGURE 3-29: BLOCK DIAGRAM RF<7:0>
Data PORTF
Data Latch TRISF
TRIS Latch
TRISF
SE<35:28> LCDEN
Schmitt Trigger
PORTF SEG<35:28> SE<35:28> LCDEN
TABLE 3-6:
Name LCDCON LCDSE3
SUMMARY REGISTERS ASSOCIATED WITH PORTF(1)
SLPEN SE30 SE38 TRISF6 WERR SE29 SE37 TRISF5 VLCDEN SE28 SE36 TRISF4 SE27 SE35 TRISF3 SE26 SE34 TRISF2 LMUX1 SE25 SE33 TRISF1 LMUX0 SE24 SE32 TRISF0 Value POR, 0001 0011 0000 0000 0000 0000 xxxx xxxx 1111 1111 Value other Resets 0001 0011 uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111
LCDEN SE31 SE39 TRISF7
LCDSE4(1) PORTF(1) TRISF(1) Legend: Note
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTF. PIC16F946 only.
2007 Microchip Technology Inc.
DS41250F-page
PIC16F913/914/916/917/946
PORTG TRISG Registers
EXAMPLE 3-7:
BANKSEL CLRF BANKSEL MOVLW MOVWF PORTG PORTG TRISG TRISG
INITIALIZING PORTG
;Init PORTG ;Set RG<5:0> inputs
PORTG 8-bit port with Schmitt Trigger input buffers. RG<5:0> individually configured inputs outputs, depending state port direction. port bits also multiplexed with segment functions. PORTG available PIC16F946 only.
REGISTER 3-16:
Legend: Readable Value
PORTG: PORTG REGISTER(1)
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read RG<5:0>: PORTG bits Port >VIH min. Port <VIL max. PIC16F946 only.
Note
REGISTER 3-17:
Legend: Readable Value
TRISG: PORTG TRI-STATE REGISTER(1)
R/W-1 TRISG5 R/W-1 TRISG4 R/W-1 TRISG3 R/W-1 TRISG2 R/W-1 TRISG1 R/W-1 TRISG0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read TRISF<5:0>: PORTG Tri-State Control bits PORTG configured input (tri-stated) PORTG configured output PIC16F946 only.
Note
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
3.9.1 DESCRIPTIONS DIAGRAMS 3.9.1.4 RG3/SEG39
Each PORTG multiplexed with other functions. pins their combined functions briefly described here. specific information about individual functions, refer appropriate section this data sheet. Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
3.9.1.1
RG0/SEG36
3.9.1.5
RG4/SEG40
Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
3.9.1.2
RG1/SEG37
3.9.1.6
RG5/SEG41
Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
3.9.1.3
RG2/SEG38
Figure 3-30 shows diagram this pin. configurable function following: general purpose analog output
FIGURE 3-30:
BLOCK DIAGRAM RG<5:0>
Data PORTG
Data Latch TRISG
TRIS Latch
TRISG
SE<41:36> LCDEN
Schmitt Trigger
PORTG SEG<41:36> SE<41:36> LCDEN
2007 Microchip Technology Inc.
DS41250F-page
PIC16F913/914/916/917/946
TABLE 3-7:
Name LCDCON LCDSE4(1) LCDSE5(1) PORTG(1) TRISG
SUMMARY REGISTERS ASSOCIATED WITH PORTG(1)
SLPEN SE38 WERR SE37 TRISG5 VLCDEN SE36 TRISG4 SE35 TRISG3 SE34 TRISG2 LMUX1 SE33 SE41 TRISG1 LMUX0 SE32 SE40 TRISG0 Value POR, 0001 0011 0000 0000 xxxx 1111 Value other Resets 0001 0011 uuuu uuuu uuuu 1111
LCDEN SE39
Legend: Note
unknown, unchanged, unimplemented locations read `0'. Shaded cells used PORTG. PIC16F946 only.
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR)
Overview
Oscillator module configured eight clock modes. External clock with OSC2/CLKOUT. Low-Power Crystal mode. Medium Gain Crystal Ceramic Resonator Oscillator mode. High Gain Crystal Ceramic Resonator mode. External Resistor-Capacitor (RC) with FOSC/4 output OSC2/CLKOUT. RCIO External Resistor-Capacitor (RC) with OSC2/CLKOUT. INTOSC Internal oscillator with FOSC/4 output OSC2 OSC1/CLKIN. INTOSCIO Internal oscillator with OSC1/CLKIN OSC2/CLKOUT.
Oscillator module wide variety clock sources selection features that allow used wide range applications while maximizing performance minimizing power consumption. Figure illustrates block diagram Oscillator module. Clock sources configured from external oscillators, quartz crystal resonators, ceramic resonators Resistor-Capacitor (RC) circuits. addition, system clock source configured from internal oscillators, with choice speeds selectable software. Additional clock features include: Selectable system clock source between external internal software. Two-Speed Start-up mode, which minimizes latency between external oscillator start-up code execution. Fail-Safe Clock Monitor (FSCM) designed detect failure external clock source (LP, modes) switch automatically internal oscillator.
Clock Source modes configured FOSC<2:0> bits Configuration Word register (CONFIG). internal clock generated from internal oscillators. HFINTOSC calibrated high-frequency oscillator. LFINTOSC uncalibrated low-frequency oscillator.
FIGURE 4-1:
SIMPLIFIED PIC® CLOCK SOURCE BLOCK DIAGRAM
FOSC<2:0> (Configuration Word Register) SCS<0> (OSCCON Register)
External Oscillator OSC2 Sleep OSC1
RCIO, INTOSC
IRCF<2:0> (OSCCON Register) Internal Oscillator Postscaler HFINTOSC LFINTOSC
System Clock (CPU Peripherals)
Power-up Timer (PWRT) Watchdog Timer (WDT) Fail-Safe Clock Monitor (FSCM)
2007 Microchip Technology Inc.
DS41250F-page
PIC16F913/914/916/917/946
Oscillator Control
Oscillator Control (OSCCON) register (Figure 4-1) controls system clock frequency selection options. OSCCON register contains following bits: Frequency selection bits (IRCF) Frequency Status bits (HTS, LTS) System clock control bits (OSTS, SCS)
REGISTER 4-1:
Legend: Readable Value
OSCCON: OSCILLATOR CONTROL REGISTER
R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 OSTS(1) R/W-0
Writable
Unimplemented bit, read cleared unknown
Unimplemented: Read IRCF<2:0>: Internal Oscillator Frequency Select bits (default) (LFINTOSC) OSTS: Oscillator Start-up Time-out Status bit(1) Device running from clock defined FOSC<2:0> Configuration Word Device running from internal oscillator (HFINTOSC LFINTOSC) HTS: HFINTOSC Status (High Frequency kHz) HFINTOSC stable HFINTOSC stable LTS: LFINTOSC Stable (Low Frequency kHz) LFINTOSC stable LFINTOSC stable SCS: System Clock Select Internal oscillator used system clock Clock source defined FOSC<2:0> Configuration Word resets with Two-Speed Start-up selected Oscillator mode Fail-Safe mode enabled.
Note
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
Clock Source Modes
4.4.1
External Clock Modes
OSCILLATOR START-UP TIMER (OST)
Clock Source modes classified external internal. External Clock modes rely external circuitry clock source. Examples are: Oscillator modules mode), quartz crystal resonators ceramic resonators (LP, modes) Resistor-Capacitor (RC) mode circuits. Internal clock sources contained internally within Oscillator module. Oscillator module internal oscillators: High-Frequency Internal Oscillator (HFINTOSC) Low-Frequency Internal Oscillator (LFINTOSC). system clock selected between external internal clock sources System Clock Select (SCS) OSCCON register. Section "Clock Switching" additional information.
Oscillator module configured modes, Oscillator Start-up Timer (OST) counts 1024 oscillations from OSC1. This occurs following Power-on Reset (POR) when Power-up Timer (PWRT) expired configured), wake-up from Sleep. During this time, program counter does increment program execution suspended. ensures that oscillator circuit, using quartz crystal resonator ceramic resonator, started providing stable system clock Oscillator module. When switching between clock sources, delay required allow clock stabilize. These oscillator delays shown Table 4-1. order minimize latency between external oscillator start-up code execution, Two-Speed Clock Start-up mode selected (see Section "Two-Speed Clock Start-up Mode").
TABLE 4-1:
OSCILLATOR DELAY EXAMPLES
Switch LFINTOSC HFINTOSC HFINTOSC Frequency Oscillator Delay Oscillator Warm-Up Delay (TWARM) instruction cycles cycle each 1024 Clock Cycles (OST) (approx.)
Switch From Sleep/POR Sleep/POR LFINTOSC kHz) Sleep/POR LFINTOSC kHz)
4.4.2
MODE
FIGURE 4-2:
External Clock (EC) mode allows externally generated logic level system clock source. When operating this mode, external clock source connected OSC1 input OSC2 available general purpose I/O. Figure shows connections mode. Oscillator Start-up Timer (OST) disabled when mode selected. Therefore, there delay operation after Power-on Reset (POR) wake-up from Sleep. Because PIC® design fully static, stopping external clock input will have effect halting device while leaving data intact. Upon restarting external clock, device will resume operation time elapsed.
EXTERNAL CLOCK (EC) MODE OPERATION
OSC1/CLKIN PIC® OSC2/CLKOUT(1)
Clock from Ext. System
Note
Alternate functions listed Section "Device Overview".
2007 Microchip Technology Inc.
DS41250F-page
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4.4.3 MODES
modes support quartz crystal resonators ceramic resonators connected OSC1 OSC2 (Figure 4-3). mode selects low, medium high gain setting internal inverter-amplifier support various resonator types speed. Oscillator mode selects lowest gain setting internal inverter-amplifier. mode current consumption least three modes. This mode designed drive only 32.768 tuning-fork type crystals (watch crystals). Oscillator mode selects intermediate gain setting internal inverter-amplifier. mode current consumption medium three modes. This mode best suited drive resonators with medium drive level specification. Oscillator mode selects highest gain setting internal inverter-amplifier. mode current consumption highest three modes. This mode best suited resonators that require high drive setting. Figure Figure show typical circuits quartz crystal ceramic resonators, respectively. Note Quartz crystal characteristics vary according type, package manufacturer. user should consult manufacturer data sheets specifications recommended application. Always verify oscillator performance over temperature range that expected application. oscillator design assistance, reference following Microchip Applications Notes: AN826, "Crystal Oscillator Basics Crystal Selection rfPIC® PIC® Devices" (DS00826) AN849, "Basic PIC® Oscillator Design" (DS00849) AN943, "Practical PIC® Oscillator Analysis Design" (DS00943) AN949, "Making Your Oscillator Work" (DS00949)
FIGURE 4-4:
CERAMIC RESONATOR OPERATION MODE)
PIC®
OSC1/CLKIN
FIGURE 4-3:
QUARTZ CRYSTAL OPERATION (LP, MODE)
PIC®
OSC1/CLKIN
Internal Logic RP(3) RF(2) Sleep
Quartz Crystal RF(2)
Internal Logic Sleep Ceramic RS(1) Resonator OSC2/CLKOUT
RS(1)
OSC2/CLKOUT
Note series resistor (RS) required ceramic resonators with drive level. value varies with Oscillator mode selected (typically between additional parallel feedback resistor (RP) required proper ceramic resonator operation.
Note
series resistor (RS) required quartz crystals with drive level. value varies with Oscillator mode selected (typically between
DS41250F-page
2007 Microchip Technology Inc.
PIC16F913/914/916/917/946
4.4.4 EXTERNAL MODES
Internal Clock Modes
external Resistor-Capacitor (RC) modes support external circuit. This allows designer maximum flexibility frequency choice while keeping costs minimum when clock accuracy required. There modes: RCIO. mode, circuit connects OSC1. OSC2/CLKOUT outputs oscillator frequency divided This signal used provide clock external circuitry, synchronization, calibration, test other application requirements. Figure shows external mode connections.
Oscillator module independent, internal oscillators that configured selected system clock source. HFINTOSC (High-Frequency Internal Oscillator) factory calibrated operates MHz. frequency HFINTOSC user-adjusted software using OSCTUNE register (Register 4-2). LFINTOSC (Low-Frequency Internal Oscillator) uncalibrated operates kHz.
FIGURE 4-5:
REXT
EXTERNAL MODES
PIC®
system clock speed selected software using Internal Oscillator Frequency Select bits IRCF<2:0> OSCCON register. system clock selected between external internal clock sources System Clock Selection (SCS) OSCCON register. Section "Clock Switching" more information.
OSC1/CLKIN CEXT FOSC/4 I/O(2) OSC2/CLKOUT(1)
Internal Clock
4.5.1
INTOSC INTOSCIO MODES
Recommended values: REXT REXT 3-5V CEXT 2-5V Note Alternate functions listed Section "Device Overview". Output depends upon RCIO clock mode.
INTOSC INTOSCIO modes configure internal oscillators system clock source when device programmed using oscillator selection FOSC<2:0> bits Configuration Word register (CONFIG). Section 16.0 "Special Features CPU" more information. INTOSC mode, OSC1/CLKIN available general purpose I/O. OSC2/CLKOUT outputs selected internal oscillator frequency divided CLKOUT signal used provide clock external circuitry, synchronization, calibration, test other application requirements. INTOSCIO mode, OSC1/CLKIN OSC2/CLKOUT available general purpose I/O.
RCIO mode, circuit connected OSC1. OSC2 becomes additional general purpose pin. oscillator frequency function supply voltage, resistor (REXT) capacitor (CEXT) values operating temperature. Other factors affecting oscillator frequency are: threshold voltage variation component tolerances packaging variations capacitance user also needs take into account variation tolerance external components used.
4.5.2
HFINTOSC
High-Frequency Internal Oscillator (HFINTOSC) factory calibrated internal clock source. frequency HFINTOSC altered software using OSCTUNE register (Register 4-2)
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