Mode Supplies Gate External Battery Reverse Protection NMOS Regul

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Mode Supplies Gate External Battery Reverse Protection NMOS Regul

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Direction-controlled Driving Four Externally Powered NMOS Transistors Internal Charge Pump Provides Gate Voltages High-side Drivers Permanent
Mode Supplies Gate External Battery Reverse Protection NMOS
Regulator With External Power Device (NPN) Current Limitation Function Reset Derived From Regulator Output Voltage Sleep Mode With Supply Current Typical Wake-up Signal
Interface (Pin /DATA) Window Watchdog; Watchdog Time Programmable Choosing Certain Value External Watchdog Capacitor CCWD External Watchdog Resistor RCWD Battery Overvoltage Protection Battery Undervoltage Management Overtemperature Protection Transceiver (Operating Differential Single-ended Mode) Battery Voltage Level Digital Control Block With Control Pins DIR, Internal Low-power Regulator With Low-power Band (Trimmed With Four Bits) Guarantee Power Dissipation Sleep Mode Guarantee Parameters Wake-up
H-bridge Motor Driver ATA6026
Description
ATA6026 used drive continuous-current motor full H-bridge configuration. external microcontroller controls driving function ATA6026 providing signal direction signal, allows usage ATA6026 windshield wiper application, example. ATA6026 supports direction-controlled driving four external power MOSFETs with external bootstrap capacitors. control performed high-side switch. opposite low-side switch permanently driving phase. Motor braking performed using low-side switches. programmable dead time included prevent peak currents within H-bridge. maximum frequency kHz.
Rev. 4865C-AUTO-01/06
Figure 1-1.
Block Diagram
RGATE VBATSW
RGATE
RGATE
RGATE
Driver
Driver
Bootstrap
Bootstrap
Driver
Driver
VINT Vint Regulator
Charge Pump
Regulator
Band
Oscillator
VBAT
VRefCC
Regulator VSHUNT VREG VBAT Bias VREF
Logic Control
Supervisor
PGND
VBAT VBAT Vint Watchdog VBAT DATA Reset
/DATA
/RESET
RSEM
Battery
Microcontroller
ATA6026
4865C-AUTO-01/06
ATA6026
Configuration
Figure 2-1. Pinning QFN32
VINT VREF VBAT_SWITCH VREG VSHUNT DATA /DATA VBAT PGND Atmel ATA6026 ZZZZZ-AL /RESET
Note:
ATA6026 ZZZZZ
Date code Year above 2000, week number) Product name Wafer number Assembly sub-lot number
Table 2-1.
Description
Symbol VINT VREF VBAT_SWITCH /RESET Function Supply Analog Analog (HV) Digital input-PU Digital input (HV) Digital input (HV) Digital input (HV) Digital output Digital output Open drain-PU Digital output-PU Digital input-PU Digital input Analog in/out Description Output internal voltage regulator (external blocking capacitor) Ground, substrate ATA6026 Reference resistor reference current Connected with VBAT ATA6026-internal switch Control mode (Single-ended Mode) Enable control input control input Direction control input Status output Status output Reset output, active Data output interface Transmit control input interface Watchdog trigger input Capacitor definition watchdog timer Protection Open drain diode diode from Diode PGND Open drain diode Diodes VBAT/GND Diodes GND/VCC Open drain diode Open drain diode Open drain diode Diodes GND/VCC Diodes GND/VCC Diodes GND/VCC Diodes GND/VCC Diodes GND/VCC Diodes GND/VCC Diodes GND/VCC
4865C-AUTO-01/06
Table 2-1.
Description (Continued)
Symbol PGND VBAT /DATA DATA VSHUNT VREG Function Analog Analog (HV) Analog in/out (HV) Analog in/out (HV) Analog in/out (HV) Analog in/out (HV) Analog (HV) Analog (HV) Analog (HV) Analog (HV) Supply (HV) Analog in/out (HV) Analog in/out (HV) Supply Analog Analog Description Cross conduction time definition Gate external high-side NMOS Source external high-side NMOS Boost capacitor voltage input Boost capacitor voltage input Source external high-side NMOS Gate external high-side NMOS Gate external low-side NMOS Gate external low-side NMOS Power ground (used drivers power devices charge pump) Charge pump output Battery voltage behind reverse protection element Inverse data signal Data signal (high voltage modulation) Feedback regulated main supply voltage part ATA6026 Sense input current limitation regulator Base external regulator pass device (NPN) Protection Diodes GND/VCC Floating open drain diode Floating open drain diode Open drain diode Open drain diode Floating open drain diode Floating open drain diode Open drain diode Open drain diode Diode Open drain diode from VBAT diode Open drain diode diode Floating open drain Floating open drain Open drain diode Diodes Open drain diode
ATA6026
4865C-AUTO-01/06
ATA6026
Functional Description
3.1.1
Power Supply Unit
Power Supply ATA6026 supplied reverse-protected battery voltage. prevent damage proper external protection circuitry must added. capacitor combination storage capacitors behind reverse protection circuitry closed VBAT ATA6026 (Figure page recommended. fully-internal low-power low-drop regulator with voltage cleaned external blocking capacitor provides necessary low-voltage supply needed wake-up process. low-power band trimmed OTPDC also used regulator. following blocks supplied internal regulator: Enable input comparator Band Wake-up part interface Digital control complete ATA6026 OTPDC regulator external) internal supply voltage VINT must used other supply reasons! remaining blocks supplied regulator (5V). detection reasons microcontroller, there high-voltage switch which brings battery voltage VBAT_SWITCH. This switch VthRES.
Sleep Mode
Sleep mode exists guarantee quiescent current inactive ATA6026. Sleep mode possible wake using pins /DATA. following blocks active Sleep mode: Band Internal regulator with external blocking capacitor Input structure detecting threshold Wake-up block receive part
4865C-AUTO-01/06
Wake-up Sleep Mode Strategy
ATA6026 modes: Sleep Active. change between modes, procedures implemented described here. default state after power-on Active mode. Sleep HIGH transition followed time tgotosleep (typically ms), switches ATA6026 Sleep mode. internal supply VINT, input structure, certain part receiver permanently active ensure proper startup system. Active activating input structure consists comparator with built-in hysteresis. input comparator protected against voltages VBATmax. Pulling HIGH time longer than twakeEN (typically will switch ATA6026 Active mode. Active interface second possibility waking part transceiver. Sleep mode receiver partially active works single-ended mode, independent status SEM. wake-up requires steps: voltage /DATA below value V/DATwake (about VVBAT 2V), receive part interface active (not confused with Active mode whole IC). active receive part able detect valid /DATA pin. /DATA filter time twakeSCI (typically ms), will change Active mode. short change back HIGH during filter time will reset filter. After entering Active mode, this information stored latch.
When interface used switch Active mode, remain without disturbing Active mode status. Figure page illustrates wake-up SCI.
ATA6026
4865C-AUTO-01/06
ATA6026
Figure 3-1. Wake-up SCI, /DATA
/DATA VBAT Level activating PREWAKE
REC_SCI
twakeSCI
twakeSCI STATUS Active
twakeSCI
tdelON_EN
tgotosleep
Sleep
status PREWAKE characterized activated receive block activated comparator input. After going Active, regulator starts working. Sleep" possible valid HIGH transition (remaining longer than tgotosleep), previously valid HIGH state (HIGH longer than tdelON_EN).
Regulator
regulator on-chip, using external power element. reason behind using external pass device prevent large power dissipation within ATA6026. battery voltage level between regulated output voltage ±10%; above VVBAT regulated output voltage ±3%. prevent destruction external ATA6026, sense resistor used detect current delivered regulator. case overcurrent, regulator limits current specified level. This means that characteristic voltage regulator changes characteristic current regulator, delivered voltage will break down. function correctly, regulator requires external transistor with minimum
4865C-AUTO-01/06
Figure 3-2.
Principal Function Regulator with External Pass Device
Battery
VBAT VREG VSHUNT RSENSE RESR CELKO
Reset Watchdog Management
reset watchdog management block controls /RESET influences behavior internal circuitry. /RESET active with internal pull-up resistor VCC. Static reset dependent level reset will active VtHRESx. level VtHRESx realized with hysteresis (HYSRESth).
Figure 3-3.
Static Reset Behavior
VtHRESH VtHRESL
/RESET
tdelayRESH
tdelayRESL
tdelayRESH
Dynamic reset dependent watchdog behavior
ATA6026
4865C-AUTO-01/06
ATA6026
Figure shows principal behavior watchdog. oscillator composed external elements RCWD CCWD defines timing base watchdog (referred here t(µs) tdis(µs) RCWD(k) [CCWD(nF) Cparasitic(nF)] tdis 1.83 (Cparasitic assumed (pad capacitance wiring capacitance PCB)) watchdog realized window watchdog will triggered microcontroller HIGH transition during open window. watchdog detects window error trigger open window wrong trigger closed window), reset pulse length tres will generated. relieve watchdog trigger after power-on, first open window longer factor about compared following windows. (open window) (closed window) tOW1 (first open window after power-on) tres (reset pulse length) Figure 3-4. Principal Behavior Watchdog
tres /RESET tow1 tow1 tres
Figure 3-5.
External Elements Watchdog
RCWD CCWD
4865C-AUTO-01/06
Table 3-1.
Examples Watchdog Oscillator Period (µs) Function CCWD RCWD
CCWD (pF) RCWD 3300 366.0 296.9 275.1 249.6 227.8 206.0 187.8 173.3 158.7 144.2 133.3 122.4 111.4 100.5 89.6 82.4 75.1 67.8 60.5 56.9 49.6 46.0 38.7 2200 245.1 199.0 184.4 167.4 152.9 138.3 126.2 116.5 106.8 97.0 89.8 82.5 75.2 67.9 60.6 55.8 50.9 46.1 41.2 38.8 33.9 31.5 26.6 1000 113.3 92.2 85.6 77.8 71.1 64.5 58.9 54.5 50.1 45.6 42.3 39.0 35.6 32.3 29.0 26.8 24.5 22.3 20.1 19.0 16.8 15.7 13.4 92.4 75.3 69.9 63.6 58.2 52.8 48.3 44.7 41.1 37.5 34.8 32.1 29.4 26.7 24.0 22.2 20.4 18.6 16.8 15.9 14.1 13.2 11.4 78.2 63.8 59.2 53.9 49.3 44.8 41.0 38.0 34.9 31.9 29.6 27.4 25.1 22.8 20.5 19.0 17.5 16.0 14.5 13.7 12.2 11.4 65.0 53.1 49.3 44.9 41.2 37.4 34.3 31.8 29.3 26.8 24.9 23.0 21.1 19.3 17.4 16.1 14.9 13.6 12.4 11.7 10.5 14.4 12.1 11.4 10.6
capacitors greater than less than resistors less than greater than apply periods shorter than 11.5 used) typical application with will following values: tres 2.77 11.9 tow1 53.66 internal tolerance 6.5%; tolerances external elements have included into period calculation.
ATA6026
4865C-AUTO-01/06
ATA6026
Transceiver
transceiver differential device which also work single-ended mode. singleended mode levels currents compatible with interface, faster timing. necessary define differential mode externally pulling down SEM. Single-ended mode default left open. this case, /DATA active. typical external elements DATA also recommended single-ended mode (SEM mode). driver DATA passive single-ended mode. digital input with internal pull-up resistor VCC. Sleep mode current will flow through pull-up resistor affect Sleep mode supply current, regulator down while Sleep mode. Figure 3-6. Principal Function
ACTIVE
SCIREC
VBAT
/DATA
wake_SCI SCI_Rx
LINM ACTIVE DATA
SCI_Tx
Switches SW1, SW2, control signals HIGH
both resistors provide VVBAT/2
Definition symbols Figure 3-6: ACTIVE: SCIREC: VCC: wake_SCI: SCI_Rx: SEM: VVBAT: ATA6026 Active mode Receive part working voltage (pin VCC) Wake-up performed (for more information filter time twakeSCI, see"Wake-up Sleep Mode Strategy" page output Single-ended mode when HIGH (SEM "Single-ended Mode") Voltage VBAT (not battery!)
4865C-AUTO-01/06
Figure 3-7.
Timing (Differential Mode)
tSCf tSCL Vhdiff 0.05 VBAT -0.05 VBAT Vldiff tRxL tRxH tSCH tSCr
/DATA DATA
Vhdiff VVBAT (SCI driver passive, recessive mode) Vldiff VT/DATAL VTDATAH (VT/DATAL output voltage /DATA) Figure 3-8. Timing (Single-ended Mode)
tSCf tSCL Vhdiff 0.05 VBAT -0.05 VBAT Vldiff tRxL tRxH tSCH tSCr
/DATA DATA
VT/DATAL output voltage /DATA
ATA6026
4865C-AUTO-01/06
ATA6026
When HIGH (single-ended mode), reference receive comparator will switched from signal DATA VVBAT necessary this external ATA6026; signal HIGH signals this request ATA6026. recommended, necessary, external connections DATA /DATA both differential mode single-ended mode specified Figure page DATA also kept open single-ended mode programmed.
Control Inputs DIR,
enable used activate ATA6026 with HIGH. This input uses voltage levels withstand voltage 40V. internal pull-down resistor included. DIR: Logical input control direction external motor. internal pull-down resistor included. test mode entered when this pulled voltage above 10V. PWM: Logical input information delivered external microcontroller. Duty cycle frequency switching choosen this pin. internal pull-down resistor included. test mode entered when this pulled voltage above 10V.
Table 3-2.
Status ATA6026 Depending Control Inputs Detected Failures Means Don't Care)
Device Status Driver Stage External Power /PWM /PWM Diagnostic Outputs Standby mode Thermal shutdown(1) Overvoltage(1) Undervoltage(1) Short circuit(1) Motor forward Motor backward Motor brake Motor full forward Motor full backward Comments
Control Inputs Note:
section "Diagnosis" page explanation
Thermal shutdown Overvoltage VBAT Undervoltage VBAT Short circuit
4865C-AUTO-01/06
Diagnosis
Table 3-3.
Event
Table Events Detected ATA6026
Description Undervoltage (VBAT VTHUV) VBAT increasing above VTHUV Overvoltage (VBAT VTHOV) VBAT increasing above VTHOV Short circuit source-drain voltage switched external NMOS short circuit detected) Short circuit condition disappears Thermal shutdown (junction temperature 165oC ±hysteresis) Thermal shutdown (junction temperature 165oC ±hysteresis) Additional reaction ATA6026 Switch Switch according PWM/DIR status Switch Switch according PWM/DIR status Timing after detection After HIGH transition after detection After HIGH transition
Release
Release
Switch
after detection
Release
Switch according PWM/DIR status
After HIGH transition
Switch DATA, Directly after /DATA detection Switch according PWM/DIR status After HIGH transition
Release
Switch DATA, /DATA according Directly after status detection
Note:
After power-on, undervoltage status latched. switch drivers HIGH transition required.
3.8.1
Overvoltage This block protects external power transistors against overvoltage battery. Function: case overvoltage alarm THOV), external NMOS transistors will switched off, event will signalled switching (see Table 3-3). overvoltage condition disappears, after next HIGH transition PWM, drivers external power transistors will switch back status defined control will cleared there other event signalled. drivers influenced voltage supervisor. comparator includes hysteresis.
ATA6026
4865C-AUTO-01/06
ATA6026
3.8.2 Undervoltage This block switches external power transistors case undervoltage battery. Function: case undervoltage alarm (VTHuV), external NMOS transistors will switched event will signalled switching (see Table page 14). undervoltage condition disappears, after next HIGH transition drivers external power transistors will switch back status defined control DIR, will cleared there other event signalled. drivers influenced voltage supervisor. comparator includes hysteresis. 3.8.3 Temperature Supervisor There temperature sensor integrated on-chip prevent overheating ATA6026 protect external NMOSFETS from failure external circuitry. case detected overtemperature (150°C 180°C), drivers including drivers will switched immediately both diagnostic pins will switched HIGH signal this event processor. status thermal shutdown (TS) will stored latch: After next HIGH transition PWM, drivers external power transistors will switch back status defined control DIR, pins will cleared there other event signalled, drivers immediately will switch status defined control hysteresis built prevent fast oscillations. Attention: With HIGH, short circuit signalled well overtemperature. 3.8.4 Short Circuit Detection detect short H-bridge circuitry, internal comparators detect voltage difference between source drain external power NMOS. transistors switched source drain voltage difference higher than value with tolerances) time greater than tSC, signal (short circuit) will set, external power transistors will switched immediately, pins will switched HIGH signal this event processor. With next programmed HIGH transition PWM, bits will cleared corresponding drivers will switch back status defined control DIR; pins will switch back short circuit condition cleared.
Behavior Bridge Drivers Case RESET
case RESET (/RESET LOW), high-side drivers will switched low-side drivers will remain status defined DIR. case overvoltage (OV), undervoltage (UV), thermal shutdown (TS), short circuit (SC), drivers will switched off, independent status /RESET pin.
4865C-AUTO-01/06
3.10
Charge Pump
fully-integrated charge pump needed supply gates external power MOSFETs drivers case permanent (100% PWM, bootstrap function available). addition, gate external power NMOS used reverse battery protection supplied charge pump output. charge pump fully integrated, including oscillator with typical frequency MHz, works pumping regulated three times above battery. addition, charge pump output supplied action bootstrap capacitors. switched (Sleep mode), charge pump function disabled, charge pump output voltage will diode threshold below VBAT.
3.11
H-bridge Driver
includes push-pull drivers control external power NMOS used high-side drivers, push-pull drivers control external power NMOS used low-side drivers. drivers used with either standard logic-level power NMOS. drivers high-side control external bootstrap capacitors supply gates with voltage above battery voltage level. bootstrap capacitor greater than equal GATE, where CGATE capacitance external switching NMOS. Smaller values bootstrap capacitor will reduce dynamic gate voltage external switching NMOS. also possible control external load (motor) reverse direction (see Table page 14). duty cycle 100% both directions possible, using charge pump supply gates high-side drivers. output voltage drivers low-side control limited level less than 16V, clamped active.
3.11.1
Cross Conduction Time prevent high peak currents H-bridge, non-overlapping phase switching external power NMOS realized. external combination defines cross conduction time following way: (µs) 0.36 (nF) (tolerance: ±0.15 combination charged switching level internal comparator start level. time measurement triggered signal crossing level.
ATA6026
4865C-AUTO-01/06
ATA6026
Figure 3-9. Timing Drivers
tLxHL tLxf tLxLH tLxr
tHxLH tHxr tHxHL tHxf
delays tHxLH tLxLH include cross conduction time tCC.
4865C-AUTO-01/06
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Description Ground Power ground Reverse-protected battery voltage VBAT behind internal switch Digital output Digital output Analog input (LV) output, external blocking capacitor Base external regulator Cross conduction time capacitor/resistor combination Digital input coming from microcontroller Watchdog timing resistor Digital input direction control Digital input control test mode Digital input enable control Digital input mode control regulator output Sense regulator current Digital output Digital input data data Bootstrap capacitor Source external high-side NMOS Gates external low-side NMOS Gates external high-side NMOS Charge pump Power dissipation Storage temperature Soldering temperature (10s) Notes: VVBAT 13.5V additionally limited external thermal resistance Name PGND VBAT VBAT_SWITCH /RESET DG1, VREF VINT VREG VSHUNT DATA /DATA CBI, Ptot STORE SOLDERING -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3
+0.3 VVBAT VVCC VVCC VVCC VVCC VVCC VVCC VVCC VVCC VVCC VVBAT VVBAT VVBAT 0.5(2) +150
Unit
-0.3 VPGND -0.3
ATA6026
4865C-AUTO-01/06
ATA6026
Operating Range
operating conditions define limits functional operation parametric characteristics device. Functionality outside these limits implied unless otherwise stated explicitly. Parameters Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Operating supply voltage Note:
Symbol VVBAT1 VVBAT1_a VVBAT2 VVBAT3 VVBAT4 VVBAT5 ambient
+125
Unit
Ambient temperature range under bias Full functionality (jump start)
H-bridge drivers switched (undervoltage detection) H-bridge drivers switched off, regulator charge pump with reduced parameters, RESET works correctly H-bridge drivers switched off, regulator charge pump working, RESET correct H-bridge drivers switched off, load dump
Temperature Conditions
Junction Temperature/°C +150 Status Normal functionality Drivers DATA, /DATA switched OFF, (DG1 will HIGH this case), parameters depart from specified values Drivers DATA, /DATA switched will HIGH signal overtemperature), parameters depart from specified values. 180°C maximum switch-off temperature
4865C-AUTO-01/06
Electrical Characteristics
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 1.10 1.11 1.12 Parameters Test Conditions Symbol Unit Type* Power Supply Supervisor Functions (This Block Supplies Parts ATA6026 Used Startup Supervises VBAT Voltage (Battery Voltage Behind Reverse Battery Protection Device)) Current consumption VBAT Current consumption VBAT, standby mode Internal power supply Overvoltage threshold VBAT Delay time overvoltage Overvoltage threshold hysteresis VBAT Undervoltage threshold VBAT Delay time undervoltage Undervoltage threshold hysteresis VBAT resistance VBAT switch Resistor defining internal bias currents used internal timings, regardless watchdog timing Measured during qualification only VVBAT 13.5V Measured during qualification only VVBAT 13.5V(1) IVBAT1 IVCC IVBAT2 VINT VTHOV VTOVhys VTHUV VTUVhys RON_VBATSW 4.75 1.21 1.26 5.25 1.33
Current consumption VVCC 5V(1) VVBAT 13.5V(3) VVBAT 5.2V
Buffered band-gap voltage VVBAT 5V(2)
1.13
Tolerance:
RVREF
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
ATA6026
4865C-AUTO-01/06
ATA6026
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 2.10 Parameters 2.2V-5V Regulator Regulated output voltage Regulated output voltage Line regulation Load regulation VVBAT Iload VVBAT Iload Iload VVBAT Iload
Test Conditions
Symbol
Unit
Type*
VCC1 VCC2 linereg loadreg IOS1 IOS2 IVREG RESR
4.85
5.15
Output current limitation(4) VVBAT Output current limitation Output current VREG value used blocking capacitor Blocking capacitor Current gain external Reset Watchdog threshold voltage level /RESET threshold voltage level /RESET Hysteresis /RESET level Length pulse /RESET /RESET pulse triggered watchdog, CCWD RCWD Combination with capacitor VVBAT VVREG VVCC VVBAT
CVCC
VtHRESH VtHRESL HYSRESth
0.4(5)
4.15
tRES
2.58
2.96
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
4865C-AUTO-01/06
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). Parameters Delay time release /RESET after exceeding VtHRESH Test Conditions CCWD RCWD k(6) Symbol tdelayRESH tdelayRESL tdelayRESH tow1 RCWD CCWD VILWD VIHWD VhysWD tWpL tWpH tWDr tWDf 1000 VVCC 2.58 2.96 Unit Type*
Time VtHRESL Independent CCWD before activating /RESET RCWD Watchdog oscillator period CCWD RCWD k(6)
60.4
68.8
CCWD Time VtHRESH before release /RESET RCWD k(6) First open watchdog window width after power- RCWD k(6) Open watchdog window width CCWD RCWD k(6)
50.2
57.2
3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19
11.2 11.2
12.7 12.7 3300 VVCC
Closed watchdog window CCWD width RCWD k(6) External watchdog resistor External watchdog capacitor Watchdog input voltage threshold Watchdog input high voltage threshold Hysteresis watchdog input voltage threshold Pulse length watchdog Measured between pulse proper triggering levels Rise time watchdog trigger pulse Fall time watchdog trigger pulse
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
ATA6026
4865C-AUTO-01/06
ATA6026
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 3.20 3.21 3.22 Parameters Output voltage /RESET Internal pull-up resistor /RESET Leakage current Transceiver output voltage HIGH VRxH RRXH RRXL tRxH tRxL VTxL VTxH
Test Conditions IOLRES
Symbol VOLRES RPURES
Unit
Type*
IleakWD
Internal pull-up resistance driver HIGH RDS_ON low-side driver transistor output Output HIGH delay time Driver Figure Figure page 12(7) Figure Figure page
Output delay time input level input HIGH level Input hysteresis Internal pull-up resistance Input high voltage difference between DATA /DATA Input voltage difference between DATA /DATA Hysteresis between VDATH VDATL
VVCC VVCC VVBAT VVBAT VVBAT
VhysTx RTXH
4.10
VRDATH
4.11
VRDATL VDAThys
4.12
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
4865C-AUTO-01/06
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 Parameters Output HIGH voltage DATA Output HIGH voltage DATA Output voltage /DATA Output voltage /DATA Short-circuit current /DATA Short-circuit current DATA input level input HIGH level Input hysteresis Internal pull-up resistance Transmit delay HIGH LOW(10) Transmit fall time(10) Transmit delay HIGH(10) Transmit rise time(10) Activation voltage /DATA receive part Input current DATA VDATA passive transmit VVBAT Filter time wake-up Input current DATA VDATA VVBAT passive transmit VVBAT 13.5V VVBAT 13.5V VVBAT 13.5V VVBAT 13.5V
Test Conditions LOW, IDATA LOW, IDATA LOW, I/DATA LOW, I/DATA
Symbol VTDATAH1 VTDATAH2 VT/DATAL1 VT/DATAL2 I/DATASC IDATASC VSEML VSEMH VhysSEM RSEM tSCL tSCf tSCH tSCr V/DATwake IDATA1 twakeSCI IDATA2
VVBAT VVBAT
Unit
Type*
-150 VVCC VVCC VVBAT
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
ATA6026
4865C-AUTO-01/06
ATA6026
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 4.31 4.32 5.10 5.11 5.12 5.13 5.14 Parameters Test Conditions Symbol I/DATA VSYM Unit Type* Input current /DATA V/DATA VVBAT passive transmit Symmetry DATA /DATA during transmit Enable input low-voltage threshold Enable input high-voltage threshold Hysteresis switching level Pull-down resisistor Enable input low-voltage threshold input high-voltage threshold Hysteresis switching level Pull-down resisistor input low-voltage threshold input high-voltage threshold Hysteresis switching level Pull-down resisistor Rise/fall time, Rise/fall time, Tested during characterization only Tested during characterization only Tested during characterization only VVBAT 13.5V(9)
Control Inputs DIR, VILEN VIHEN HYSENth RPDEN VILDIR VIHDIR HYSDIRth RPDDIR VILPWM VIHPWM HYSPWMth RPDPWM trf_EN trf_PWM VVCC VVCC VVCC VVCC
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
4865C-AUTO-01/06
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 5.15 5.16 5.17 Parameters Rise/fall time, Delay time Active" Enable Delay time Sleep" Enable Charge Pump Charge pump voltage Charge pump voltage Charge pump current driving capability under valid parameters 6.1/6.2 Charge pump oscillator frequency Serial resistance between charge pump gate external reverse battery protection NMOS Charge pump voltage case H-bridge Driver Low-side driver HIGH output voltage Low-side driver HIGH output voltage resistance sink stage pins resistance source stage pins Related VVBAT VVBAT (with VVBAT drivers switched off) VLxH1 VLxH2 RDSON_LxL, RDSON_LxH, VVBAT (Sleep mode) VVBAT VVBAT VVBAT VVBAT VVBAT VVBAT Test Conditions Symbol trf_DIR tdelON_EN tgotosleep Unit Type*
fcposc
VCPsleep
VVBAT 0.7V
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
ATA6026
4865C-AUTO-01/06
ATA6026
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). Parameters Output peak current pins switched Output peak current pins switched HIGH Pull-down resistance pins resistance sink stage pins resistance source stage pins Related CBx, VVBAT Test Conditions Symbol ILxL, ILxH, RPDLx, RDSON_HxL, RDSON_HxH, IHxL, Unit Type*
-100
7.10
VVBAT 13.5V Output peak current VVBAT pins switched VCBx VVBAT VVBAT VVBAT 13.5V Output peak current VVBAT pins switched HIGH VCBx VVBAT VVBAT Static high-side switch output low-voltage pins Static high-side switch output high-voltage pins Static high-side switch output high-voltage pins Sink resistance between Ground Sleep mode (PWM static) VVBAT (PWM static) VVBAT (with VVBAT 25V, drivers switched off)
7.11
IHxH, VHxL, VHxHstat1 (supplied VVBAT charge pump) VHxHstat1 (supplied VVBAT charge pump)
-100
7.12
VVBAT
7.13
7.14
VVBAT
7.15
RHxsleep
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
4865C-AUTO-01/06
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 7.16 7.17 7.18 7.19 7.20 7.21 7.22 7.23 7.24 Parameters Test Conditions Symbol VSxOFF VCB1 VCB1 VCB1 VCB1 VCB2 VCB2 VCB2 VCB2 Unit Type* Voltage open both switched voltage VVBAT voltage VVBAT voltage VVBAT voltage VVBAT voltage VVBAT voltage VVBAT voltage VVBAT voltage VVBAT Dynamic Parameters Dynamic high-side switch output high-voltage pins (bootstrap voltage) Dynamic high-side switch output high-voltage pins (bootstrap voltage) Dynamic high-side switch output high-voltage pins (bootstrap voltage) CCBx fPWM VVBAT CCBx fPWM VVBAT CCBx fPWM VVBAT VVBAT VVBAT
7.14
VHxHdyn1
7.15
VHxHdyn2
VVBAT
VVBAT
7.16
VHxHdyn3
VVBAT
VVBAT
7.17
Propagation delay time VVBAT 13.5V low-side driver from HIGH CCBx Figure page Propagation delay time low-side driver from HIGH Fall time low-side driver VVBAT 13.5V
tLxHL
7.18
tLxLH tLxf
7.19
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
ATA6026
4865C-AUTO-01/06
ATA6026
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). 7.20 Parameters Rise time low-side driver Propagation delay time VVBAT 13.5V high-side driver from CCBx HIGH Figure page Propagation delay time high-side driver from HIGH Fall time high-side driver Rise time high-side driver Cross conduction time External resistor External capacitor switching transistor Switching level comparator Short circuit detection voltage Voltage between source-drain external switching transistor active case "Cross Conduction Time" page VVBAT 13.5V Test Conditions Symbol tLxr tHxHL Unit Type*
7.21
7.22
tHxLH tHxf tHxr RONCC Vswtcc VVCC VVCC
7.23 7.24 7.25 7.26 7.27 7.28 7.29
VVCC
7.30
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
4865C-AUTO-01/06
Electrical Characteristics (Continued)
parameters given valid VBAT -40°C ambient 125°C unless stated otherwise. Conditions: HIGH (single-ended mode SCI). Parameters Short circuit detection time Test Conditions switch-on time tsc, short circuit message will never generated Time (plus cross conduction time inductive load applied), this time limits ratio values about used Symbol Unit Type*
7.31
7.32
Charging time bootstrap capacitors
tCHBOOT
7.33
Maximum frequency
fPWMmax
Type: 100% tested, 100% correlation tested, Characterized samples, Design parameter Notes: DIR, HIGH Internal band-gap voltage valid VBAT (not testable) Valid -40°C +90°C RSHUNT Tested during qualification only timing, formula "Reset Watchdog Management" page times depend external elements CCWD RCWD, tolerances these elements have added given tolerances above table External parasitic capacitive load together with pull-up resistor defines time tRxH single-ended mode used (SEM HIGH): DATA used VBAT instead DATA internal reference parameters 4.10 4.11 Maximum voltage difference arises during slope, Figure page Parameters 4.16 4.19 based transmit voltage slopes DATA /DATA 4V/µs ±50%
Figure 7-1.
Principal Dynamic Behavior SCI, VSYM Symmetry DATA /DATA VBAT
VBAT DATA
VBAT/2
/DATA
VSYM (VBAT /DATA) DATA, ideally should always
ATA6026
4865C-AUTO-01/06
ATA6026
Latch-up Requirements
device withstands pulses when tested according S5.1-1998: Constant voltage pulse polarity samples, failures Electrical post-stress testing room temperature Static latch-up tested according AEC-Q100-004 JESD78. samples, failures Electrical post-stress testing room temperature test, voltage pins VBAT, DATA, /DATA, VBAT_SWITCH, must exceed case being able drive specified current; pins voltage must exceed 25V.
4865C-AUTO-01/06
Ordering Information
Extended Type Number ATA6026-PHQW Package QFN32, Remarks Pb-free
Package Information
Thermal resistance junction ambient: airflow LFPM), valid JEDEC Standard Four-layer Thermal Test Board with Thermal Matrix (100 Drill Hole, Filled Vias).
ATA6026
4865C-AUTO-01/06
ATA6026
Table Contents
Features Description Configuration Functional Description
Power Supply Unit Sleep Mode Wake-up Sleep Mode Strategy Regulator Reset Watchdog Management Transceiver Control Inputs DIR, Diagnosis Behavior Bridge Drivers Case RESET 3.10 Charge Pump 3.11 H-bridge Driver
Absolute Maximum Ratings Operating Range Temperature Conditions Electrical Characteristics Latch-up Requirements Ordering Information
Package Information
4865C-AUTO-01/06
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4865C-AUTO-01/06

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