Low-current Microcontroller Watchdog Function ATA6020N Descriptio
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Low-current Microcontroller Watchdog Function ATA6020N
Description
ATA6020N member Atmel's 4-bit single-chip microcontroller family. contains ROM, RAM, parallel ports, 8-bit programmable multifunction timer/counter with modulator function, voltage supervisor, interval timer with watchdog function sophisticated on-chip clock generation with external clock input integrated RC-oscillators. Figure 1-1. Block Diagram
OSC1
Brown-out protect RESET Voltage monitor External input
oscillators
External clock input UTCM Timer interval- watchdog timer
Clock management
Timer 8/12-bit timer with modulator
Data direction
BP20/NTE Port BP21 BP22 BP23
MARC4
4-bit core
Serial interface
Data direction alternate function Port
Data direction interrupt control Port
BP42 BP40 INT3 BP41 BP43 INT3
BP50 INT6
BP52 INT1 BP53 INT1
BP51 INT6
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Configuration
Figure 2-1. Pinning SSO20 Package
BP40/INT3/SC BP53/INT1 BP52/INT1 BP51/INT6 BP50/INT6 OSC1
BP43/INT3/SD BP42/T2O BP41/VMI/T2I BP23 BP22 BP21 BP20/NTE
ATA6020N
Table 2-1.
Name BP20 BP21 BP22 BP23 BP40 BP41 BP42 BP43 BP50 BP51 BP52 BP53 OSC1
Description
Type Function Supply voltage Circuit ground connected connected Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port Bi-directional line Port connected connected connected Oscillator input Alternate Function test mode enable, also section ''Master Reset'' serial clock INT3 external interrupt input voltage monitor input external clock input Timer Timer output serial data INT3 external interrupt input INT6 external interrupt input INT6 external interrupt input INT1 external interrupt input INT1 external interrupt input External clock input external trimming resistor input Number SS020 Reset State Input Input Input Input Input Input Input Input Input Input Input Input Input
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Introduction
ATA6020N member Atmel's 4-bit single-chip microcontroller family. contains ROM, RAM, parallel ports, 8-bit programmable multifunction timer/counter, voltage supervisor, interval timer with watchdog function sophisticated on-chip clock generation with integrated RC-oscillators.
MARC4 Architecture General Description
MARC4 microcontroller consists advanced stack-based, 4-bit core on-chip peripherals. based HARVARD architecture with physically separated program memory (ROM) data memory (RAM). Three independent buses, instruction bus, memory bus, used parallel communication between ROM, peripherals. This enhances program execution speed allowing both instruction prefetching, simultaneous communication on-chip peripheral circuitry. extremely powerful integrated interrupt controller with associated eight prioritized interrupt levels supports fast efficient processing hardware events. MARC4 designed high-level programming language qFORTH. core includes both, expression return stack. This architecture enables high-level language programming without loss efficiency code density. Figure 4-1. MARC4 Core
MARC4 CORE
Reset
Program memory
4-bit
Reset Clock
Instruction Memory Instruction decoder
System clock
Sleep
Interrupt controller
On-chip peripheral modules
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Components MARC4 Core
core contains ROM, RAM, ALU, program counter, address registers, instruction decoder interrupt controller. following sections describe each functional block more detail:
4.1.1
program memory (ROM) mask programmed with customer application program during fabrication microcontroller. addressed 12-bit wide program counter, thus predefining maximum program bank size Kbytes. additional 1-Kbyte exists, which reserved quality control self-test software lowest user address segment taken 512-byte Zero page which contains predefined start addresses interrupt service routines special subroutines accessible with single byte instructions (SCALL). corresponding memory shown Figure 4-2. Look-up tables constants also held accessed MARC4's built-in TABLE instruction. Figure 4-2.
7FFh
ATA6020N
1F8h 1F0h 1E8h 1E0h
1E0h 180h
SCALL addresses
bit)
page
140h 100h 080h
1FFh
Zero page
000h
018h 010h 008h
040h
008h 000h
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4.1.2 ATA6020N contains 4-bit wide static random access memory (RAM), which used expression stack. return stack data memory used variables arrays. addressed four 8-bit wide address registers Figure 4-3.
(256 4-bit) Autosleep Global variables
Expression stack
TOS-1 TOS-2 4-bit Expression stack Return stack
address register
TOS-1
Return stack
Global variables 12-bit
4.1.2.1
Expression Stack 4-bit wide expression stack addressed with expression stack pointer (SP). arithmetic, memory reference operations take their operands, return their results expression stack. MARC4 performs operations with stack items (TOS TOS-1). register contains element expression stack works same accumulator. This stack also used passing parameters between subroutines scratch area temporary storage data. Return Stack 12-bit wide return stack addressed return stack pointer (RP). used storing return addresses subroutines, interrupt routines keeping loop index counts. return stack also used temporary storage area. MARC4 instruction supports exchange data between elements expression stack return stack. stacks within have user definable location maximum depth.
4.1.2.2
4.1.3
Registers MARC4 controller seven programmable registers condition code register. They shown following programming model.
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4.1.3.1
Program Counter (PC) program counter 12-bit register which contains address next instruction fetched from ROM. Instructions currently being executed decoded instruction decoder determine internal micro-operations. linear code calls branches) program counter incremented with every instruction cycle. branch-, call-, return-instruction interrupt executed, program counter loaded with address. program counter also used with TABLE instruction fetch 8-bit wide constants. Programming Model
Figure 4-4.
Program counter
Return stack pointer
Expression stack pointer
address register
address register
stack register
Condition code register
Interrupt enable Branch Reserved Carry/borrow
4.1.3.2
Address Registers addressed with four 8-bit wide address registers: These registers allow access nibbles. Expression Stack Pointer (SP) stack pointer contains address next-to-top 4-bit item (TOS-1) expression stack. pointer automatically pre-incremented nibble moved onto stack postdecremented nibble removed from stack. Every post-decrement operation moves item (TOS-1) register before decremented. After reset, stack pointer initialized with allocate start address expression stack area. Return Stack Pointer (RP) return stack pointer points element 12-bit wide return stack. pointer automatically pre-increments element moved onto stack, post-decrements element removed from stack. return stack pointer increments decrements steps This means that every time 12-bit element stacked, 4-bit location left unwritten. This location used qFORTH compiler allocate 4-bit variables. After reset return stack pointer initialized FCh.
4.1.3.3
4.1.3.4
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4.1.3.5 Address Registers registers used address 4-bit item RAM. fetch operation moves addressed nibble onto TOS. store operation moves addressed location. using either pre-increment post-decrement addressing mode arrays compared, filled moved. Stack (TOS) stack register accumulator MARC4. arithmetic/logic, memory reference operations this register. register receives data from ALU, ROM, bus. Condition Code Register (CCR) 4-bit wide condition code register contains branch, carry interrupt enable flag. These bits indicate current state CPU. flags reset operations. instructions SET_BCF, TOG_BF, CCR! allow direct manipulation condition code register. Carry/Borrow carry/borrow flag indicates that borrowing carrying arithmetic logic unit (ALU) occurred during last arithmetic operation. During shift rotate operations, this used fifth bit. Boolean operations have effect C-flag. Branch branch flag controls conditional program branching. Should branch flag been previous instruction conditional branch will cause jump. This flag affected arithmetic, logic, shift, rotate operations. 4.1.3.10 Interrupt Enable interrupt enable flag globally enables disables triggering interrupt routines with exception non-maskable reset. After reset executing instruction, interrupt enable flag reset thus disabling interrupts. core will accept further interrupt requests until interrupt enable flag been again either executing SLEEP instruction.
4.1.3.6
4.1.3.7
4.1.3.8
4.1.3.9
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4.1.4
4-bit performs arithmetic, logical, shift rotate operations with elements expression stack (TOS TOS-1) returns result TOS. operations affects carry/borrow branch flag condition code register (CCR). Figure 4-5. Zero-address Operations
TOS-1 TOS-2 TOS-3 TOS-4
4.1.5
ports registers peripheral modules mapped. communication between core on-chip peripherals take place associated control. With MARC4 instructions, allows direct read write access primary addresses. More about access on-chip peripherals described section "Peripheral Modules" page internal accessible customer final microcontroller device, used interface MARC4 emulation (see section "Emulation").
4.1.6
Instruction MARC4 instruction optimized high level programming language qFORTH. Many MARC4 instructions qFORTH words. This enables compiler generate fast compact program code. instruction pipeline allowing controller prefetch instruction from same time present instruction being executed. MARC4 zero address machine, instructions containing only operation performed source destination address fields. operations implicitly performed data placed stack. There one- two-byte instructions which executed within machine cycles. MARC4 machine cycle made system clock cycles (SYSCL). Most instructions only byte long executed single machine cycle. more information refer "MARC4 Programmer's Guide".
4.1.7
Interrupt Structure MARC4 handle interrupts with eight different priority levels. They generated from internal external interrupt sources software interrupt from itself. Each interrupt level hard-wired priority associated vector service routine (see Table page 10). programmer postpone processing interrupts resetting interrupt enable flag CCR. interrupt occurrence will still registered, interrupt routine only starts after I-flag set. interrupts masked, priority individually software configured programming appropriate control register interrupting module (see section "Peripheral Modules" page 20).
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Figure 4-6. Interrupt Handling
INT7
Priority Level
Main Autosleep INT3 INT5
INT7 active
INT5 active
INT2 INT3 active INT2 pending INT2 active SWI0
INT0 pending
INT0 active Main Autosleep
Time
4.1.7.1
Interrupt Processing order process eight interrupt levels, MARC4 includes interrupt controller with 8-bit wide interrupt pending interrupt active registers. interrupt controller samples interrupt requests during every non-I/O instruction cycle latches these interrupt pending register. higher priority interrupt present interrupt active register, signals interrupt current program execution. interrupt enable set, processor enters interrupt acknowledge cycle. During this cycle short call (SCALL) instruction service routine executed current saved return stack. interrupt service routine completed with instruction. This instruction resets corresponding bits interrupt pending/active register fetches return address from return stack program counter. When interrupt enable flag reset (triggering interrupt routines disabled), execution interrupt service routines inhibited logging interrupt requests interrupt pending register. execution interrupt delayed until interrupt enable flag again. Note that interrupts only lost interrupt request occurs while corresponding pending register still (i.e., interrupt service routine finished). should noted that automatic stacking carried hardware banking used, must stacked expression stack application program restored before RTI. After master reset (power-on, brown-out watchdog reset), interrupt enable flag interrupt pending interrupt active register reset.
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4.1.7.2
Interrupt Latency interrupt latency time from occurrence interrupt interrupt service routine being activated. This extremely short (taking between machine cycles depending state core).
Table 4-1.
INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Interrupt Priority Table
Priority lowest highest Address 040h 080h 0C0h 100h 140h 180h 1C0h 1E0h Interrupt Opcode (SCALL 040h) (SCALL 080h) (SCALL 0C0h) (SCALL 100h) (SCALL 140h) (SCALL 180h) (SCALL 1C0h) (SCALL 1E0h) Function Software interrupt (SWI0) External hardware interrupt, edge BP52 BP53 Timer interrupt interrupt external hardware interrupt BP40 BP43 Timer interrupt Software interrupt (SW15) External hardware interrupt, edge BP50 BP51 Voltage monitor (VM) interrupt
Interrupt
Table 4-2.
Hardware Interrupts
Interrupt Mask
Register
Interrupt INT1 INT2 INT3 INT4 INT6 INT7
Interrupt Source edge BP52 edge BP53 Timer buffer full/empty BP40/BP43 interrupt Timer compare match/overflow edge BP50 edge BP51 External/internal voltage monitoring
P5CR SISC T2CM P5CR
P52M1, P52M2 P53M1, P53M2 T1IM T2IM P50M1, P50M2 P51M1, P51M2
4.1.7.3
Software Interrupts programmer generate interrupts using software interrupt instruction (SWI), which supported qFORTH predefined macros named SWI0.SWI7. software triggered interrupt operates exactly like hardware triggered interrupt. instruction takes elements from expression stack writes corresponding bits interrupt pending register. Therefore, using instruction, interrupts re-prioritized lower priority processes scheduled later execution. Hardware Interrupts ATA6020N, there eleven hardware interrupt sources with seven different levels. Each source masked individually mask bits corresponding control registers. overview possible hardware configurations shown Table page
4.1.7.4
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Master Reset
master reset forces into well-defined condition. unmaskable activated independent current program state. triggered either initial supply power-up, short collapse power supply, brown-out detection circuitry, watchdog time-out, external input clock supervisor stage (see Figure 4-7). master reset activation will reset interrupt enable flag, interrupt pending register interrupt active register. During power-on reset phase, control signals reset mode, thereby, initializing on-chip peripherals. bi-directional ports input mode. Attention: During reset phase, BP20/NTE input driven towards additional internal strong pull-up transistor. This must pulled down during reset external circuitry representing resistor less than Releasing reset results short call instruction (opcode C1h) address 008h. This activates initialization routine $RESET which turn initialize necessary variables, stack pointers peripheral configuration registers. Figure 4-7. Reset Configuration
Pull-up NRST Reset Reset timer timer Internal Internal reset reset
CL=SYSCL/4 CL=SYSCL/4 Power-on Power-on reset reset
Brown-out Brown-out detection detection
WatchWatchdog
Ext. clock Ext. clock supervisor supervisor
ExIn ExIn
4.2.1
Power-on Reset Brown-out Detection ATA6020N fully integrated power-on reset brown-out detection circuitry. reset generation external components needed. These circuits ensure that core held reset state until minimum operating supply voltage been reached. reset condition will also generated should supply voltage drop momentarily below minimum operating level except when power-down mode activated (the core SLEEP mode peripheral clock stopped). this power-down mode brown-out detection disabled. values brown-out voltage threshold programmable SC-register.
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power-on reset pulse generated rise across default voltage level (3.0 brown-out reset pulse generated when falls below brown-out voltage threshold. values brown-out voltage threshold programmable BOT-bit SC-register. When controller runs upper supply voltage range with high system clock frequency, high threshold must used. When runs with lower system clock frequency, threshold wider supply voltage range chosen. further details, electrical specification SC-register description programming. Figure 4-8.
Brown-out Detection
Reset Reset (typically)
brown-out voltage threshold. (3.0V reset value). high brown-out voltage threshold (4.0V). 4.2.2 Watchdog Reset watchdog's function enabled WDC-register triggers reset with every watchdog counter overflow. suppress watchdog reset, watchdog counter must regularly reset reading watchdog register address (CWD). reacts exactly same manner reset stimulus from above sources. External Clock Supervisor external input clock supervisor function enabled external input clock selected within SC-registers clock module. reacts exactly same manner reset stimulus from above sources.
4.2.3
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Voltage Monitor
voltage monitor consists comparator with internal voltage reference. used supervise supply voltage external voltage pin. comparator supply voltage internal programmable thresholds: lower threshold (4.0V) higher threshold (5.0V). external voltages pin, comparator threshold 1.25V. VMS-bit indicates supervised voltage below (VMS above (VMS this threshold. interrupt generated when VMS-bit reset detect rising falling slope. voltage monitor interrupt (INT7) enabled when interrupt mask (VIM) reset VMC-register. Figure 4-9. Voltage Monitor
Voltage monitor BP41/ INT7
VMST
4.3.1
Voltage Monitor Control/Status Register
Primary register address: 'F'hex VMC: Write VMST: Read reserved Reset value: 1111b Reset value: xx11b
VM2: Voltage monitor Mode VM1: Voltage monitor Mode VM0: Voltage monitor Mode
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Table 4-3.
Voltage Monitor Modes
Function Disable voltage monitor External (VIM input), internal reference threshold (1.25V), interrupt with negative slope allowed External (VMI input), internal reference threshold (1.25V), interrupt with positive slope Internal (supply voltage), high threshold (5.0V), interrupt with negative slope allowed Internal (supply voltage), threshold (4.0V), interrupt with negative slope allowed
Voltage Interrupt Mask voltage monitor interrupt enabled voltage monitor interrupt disabled Voltage Monitor Status voltage comparator input below VRef voltage comparator input above VRef Figure 4-10. Internal Supply Voltage Supervisor
threshold High threshold
threshold High threshold
Figure 4-11. External Input Voltage Supervisor
Internal reference level Negative slope 1.25 Positive slope Interrupt negative slope Interrupt positive slope
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4.4.1
Clock Generation
Clock Module ATA6020N contains clock module with different internal RC-oscillator types. OSC1 used input external clocks connect external trimming resistor RC-oscillator necessary circuitry, except trimming resistor, integrated on-chip. these oscillator types external input clock selected generate system clock (SYSCL). applications that require exact timing, possible fully integrated RC-oscillator without external components. RC-oscillator center frequency tolerance better than ±50%. RC-oscillator trimmable oscillator whereby oscillator frequency trimmed with external resistor attached between OSC1 GND. this configuration, RC-oscillator frequency maintained stable within tolerance ±15% over full operating temperature voltage range. clock module programmable software with clock management register (CM) system configuration register (SC). required oscillator configuration selected with OS1-bit OS0-bit SC-register. programmable 4-bit divider stage allows adjustment system clock speed. special feature clock management that external oscillator used switched port power-down mode. Before external clock switched off, internal RC-oscillator must selected with CCS-bit then SLEEP mode activated. this state interrupt wake controller with RC-oscillator, external oscillator activated selected software. synchronization stage avoids clock periods that short clock source clock speed changed. external input clock selected, supervisor circuit monitors external input generates hardware reset external clock source fails drops below more than
Figure 4-12. Clock Module
OSC1 Oscin
oscillator Ext. clock
ExIn ExOut Stop Stop RCOut1 Control Divider
SYSCL
oscillator2
RTrim RCOut2 Stop Sleep NSTOP CSS1 CSS0 Cin/16
Osc-Stop
SUBCL
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Table 4-4.
Mode
Clock Modes
Clock Source SYSCL RC-oscillator (internal) RC-oscillator (internal) External input clock RC-oscillator with external trimming resistor Clock Source SUBCL Cin/16 Cin/16
clock module generates output clocks. system clock (SYSCL) other periphery (SUBCL). SYSCL supply core peripherals SUBCL supply only peripherals with clocks. modes clock sources programmable with OS1-bit OS0-bit SC-register CCS-bit CM-register. 4.4.2 Oscillator Circuits External Clock Input Stage ATA6020N consists different internal RC-oscillators external clock input stage. RC-oscillator Fully Integrated timing insensitive applications, possible fully integrated RC-oscillator operates without external components saves additional costs. RC-oscillator center frequency tolerance better than ±50% over full temperature voltage range. basic center frequency RC-oscillator RC-oscillator selected default after power-on reset. Figure 4-13. RC-oscillator
4.4.2.1
RC-oscillator RcOut1 Stop RcOut1 Osc-Stop
Control
4.4.2.2
External Input Clock OSC1 driven external clock source provided meets specified duty cycle, rise fall times input levels. Additionally, external clock stage contains supervisory circuit input clock. supervisor function controlled OS1, OS0-bit SC-register CCS-bit CM-register. external input clock fails CM-register, supervisory circuit generates hardware reset. input clock failed frequency less than more than
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Figure 4-14. External Input Clock
Ext. input clock Ext. Clock OSC1 ExIn Stop ExOut
RcOut1 Osc-Stop
Clock monitor
Table 4-5.
Supervisor Function Control Bits
Supervisor Reset Output (Res) Enable Disable Disable
4.4.2.3
RC-oscillator with External Trimming Resistor RC-oscillator high resolution trimmable oscillator whereby oscillator frequency trimmed with external resistor between OSC1 VDD. this configuration, RC-oscillator frequency maintained stable within tolerance ±10% over full operating temperature voltage range from 3.5V 5.5V. example: output frequency RC-oscillator MHz, obtained connecting resistor Rext (see Figure 4-15). Figure 4-15. RC-oscillator
RC-oscillator OSC1 Rext RcOut2 RTrim Stop RcOut2 Osc-Stop
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4.4.3
Clock Management clock management register controls system clock divider synchronization stage. Writing this register triggers synchronization cycle. Clock Management Register (CM)
Auxiliary register address: '3'hex NSTOP CSS1 CSS0 Reset value: 1111b
4.4.3.1
NSTOP
STOP peripheral clock NSTOP stops peripheral clock while core SLEEP mode NSTOP enables peripheral clock while core SLEEP mode Core Clock Select internal RC-oscillator generates SYSCL external clock source RC-oscillator with external resistor OSC1 generates SYSCL dependent setting system configuration register Core Speed Select Core Speed Select
CSS1 CSS0
Table 4-6.
CSS1
Core Speed Select
CSS0 Divider Note Reset value
4.4.3.2
System Configuration Register (SC)
Primary register address: '3'hex write Reset value: 1x11b
Brown-Out Threshold brown-out voltage threshold (3.0 high brown-out voltage threshold (4.0 Oscillator Select Oscillator Select
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Table 4-7.
Mode Note:
Oscillator Select
Input SUBCL Cin/16 Cin/16 Selected Oscillators RC-oscillator external input clock RC-oscillator RC-oscillator
CM-register, RC-oscillator always stops.
Power-down Modes
sleep mode shut-down condition which used reduce average system power consumption applications where microcontroller fully utilized. this mode, system clock stopped. sleep mode entered SLEEP instruction. This instruction sets interrupt enable condition code register enable interrupts stops core. During sleep mode peripheral modules remain active able generate interrupts. microcontroller exits sleep mode carrying interrupt reset. sleep mode only kept when none interrupt pending active register bits set. application $AUTOSLEEP routine ensures correct function sleep mode. total power consumption directly proportional active time microcontroller. rough estimation expected average system current consumption, following formula should used: Itotal (VDD,fsyscl) ISleep (IDD tactive/ttotal) depends fsyscl ATA6020N various power-down modes. During sleep mode clock MARC4 core stopped. With NSTOP-bit clock management register (CM), programmable clock on-chip peripherals active stopped during sleep mode. clock core peripherals stopped selected oscillator switched off.
Table 4-8.
Mode Active Power-down SLEEP Note:
Power-down Modes
Core SLEEP SLEEP Osc-Stop(1) Brown-out Function Active Active STOP RC-oscillator RC-oscillator STOP External Input Clock STOP
Osc-Stop SLEEP NSTOP
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Peripheral Modules
Addressing Peripherals
Accessing peripheral modules takes place (see Figure 5-1). instructions allow direct addressing modules. dual register addressing scheme been adopted enable direct addressing primary register. address auxiliary register, access must switched with auxiliary switching module. Thus, single OUT) module address will read write into) modules primary register. Accessing auxiliary register performed with same instruction preceded writing module address into auxiliary switching module. Byte wide registers accessed multiple OUT) instructions. more complex peripheral modules, with larger number registers, extended addressing used. this case, bank subport registers indirectly addressed with subport address. first OUT-instruction writes subport address sub-address register, second instruction reads data from writes data addressed subport. Figure 5-1.
Module
Example Addressing
Module
(Address Pointer) Subaddress Reg. Bank Primary Regs. Subport Subport
Module
Aux. Reg.
Module
Auxiliary Switch Module
Primary Reg.
Subport Subport Primary Reg.
Primary Reg.
other modules
Indirect Subport Access
Dual Register Access (Primary Register Write)
Single Register Access (Primary Register Write)
(Subport Register Write)
Addr. (SPort) Addr. (M1) SPort_Data Addr. (M1)
Prim._Data Addr. (M2) (Auxiliary Register Write)
Prim._Data Addr. (M3) (Primary Register Read)
(Subport Register Read) Addr. (SPort) Addr. (M1) Addr. (M1) (Subport Register Write Byte)
Addr. (M2) Addr. (ASW) Aux._Data Addr. (M2) (Primary Register Read)
Addr. (M3)
Example qFORTH Program Code
Addr. (M2) (Auxiliary Register Read
Addr. (SPort) Addr. (M1) SPort_Data (lo) Addr. (M1) SPort_Data (hi) Addr. (M1) (Subport Register Read Byte)
Addr. (M2) Addr. (ASW) Addr. (M2) (Auxiliary Register Write Byte)
Addr. (SPort) Addr. (M1) Addr. (M1) (hi) Addr. (M1) (lo)
Addr. (M2) Addr. (ASW) Aux._Data (lo) Addr. (M2) Aux._Data (hi) Addr. (M2)
Addr. (ASW) Auxililiary Switch Module Address Addr. (Mx) Module Address Addr. (SPort) Subport Address Prim._Data Data written into Primary Register Aux._Data Data written into Auxiliary Register Aux._Data (lo) Data written into Auxiliary Register (low nibble)
Aux._Data (hi) Data written into Auxiliary Register (high nibble) SPort_Data (lo) Data written into Subport (low nibble) SPort_Data (hi) Data written into Subport (high nibble) (lo) SPort_Data (low nibble) (hi) SPort_Data (high nibble)
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Table 5-1.
Port Address Aux. Aux. Aux. Aux.
Peripheral Addresses
Name P2DAT P2CR P4DAT P4CR P5DAT P5CR T12SUB 0000b 1111b 1111b 0000b 1111b 1111 1111b 1111b x111b 1111b 1111b xxxx xxxxb xxxx xxxxb 1111b 1x11b 1111b Write/Read Reset Value Register Function 1111b 1111b 1x11b xxxxb 1111b 1111b 1111 1111b 1111b 1111 1111b Port data register/pin data Port control register Port system configuration register Watchdog reset Port clock management register Port data register/pin data Port control register (byte) Port data register/pin data Port control register (byte) Reserved Data Timer subport Timer control register Timer mode register Timer mode register Timer compare mode register Timer compare register Timer compare register (byte) Reserved Reserved Timer control register Timer control register Watchdog control register Reserved Auxiliary/switch register Serial transmit buffer (byte) Serial receive buffer (byte) Serial interface control register Serial interface status/control register Serial interface control register Reserved Reserved 0000b 1111b xx11b bank switch register Reserved Voltage monitor control register Voltage monitor status register Module Type Page
Support address Aux. Aux. T2M1 T2M2 T2CM T2CO1 T2CO2 T1C1 T1C2
SIC1 SISC SIC2 VMST
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Bi-directional Ports
Ports bits wide. ports used data input output. ports equipped with Schmitt trigger inputs variety mask options open-drain, open-source, full-complementary outputs, pull-up pull-down transistors. Port Data Registers (PxDAT) mapped primary address register respective port address Port Control Register (PxCR), corresponding auxiliary register. There three different directional ports available: Port Port Port 4-bit wide bitwise-programmable port. 4-bit wide bitwise-programmable bi-directional port with optional static pull-ups programmable interrupt logic. 4-bit wide bitwise-programmable bi-directional port also provides interface Timer SSI, voltage monitor input external interrupt input.
5.2.1
Bi-directional Port This, other bi-directional ports include bitwise-programmable Control Register (P2CR), which enables individual programming each port input output. also opens possibility reading condition when output mode. This useful feature selftesting serial applications. Port however, increased drive capability additional resistance pull-up/-down transistor mask option. Care should taken connecting external components BP20/NTE. During reset phase, BP20/NTE input driven towards additional internal strong pull-up transistor. This must pulled down (active passive) during reset external circuitry representing resistor less than This prevents circuit from unintended switching test mode enable through application circuitry BP20/NTE. Resistors less than might lead undefined state internal test logic thus disabling application firmware. avoid conflict with optional internal pull-down transistors, BP20 handles pull-down options different than other ports. BP20 only port that switches pulldown transistors during reset.
Figure 5-2.
Bi-directional Port
Pull-up
Static Pull-up
(Data out) Master reset P2DATy
BP2y
P2CRy
Static Pull-down
Pull-down (Direction)
Mask
options
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5.2.1.1 Port Data Register (P2DAT)
Primary register address: '2'hex P2DAT P2DAT3 P2DAT2 P2DAT1 P2DAT0 Reset value: 1111b
MSB, 5.2.1.2 Port Control Register (P2CR)
Auxiliary register address: '2'hex P2CR P2CR3 P2CR2 P2CR1 P2CR0 Reset value: 1111b
Value: 1111b means pins input mode
Table 5-2.
Code 3210 xxx1 xxx0 xx1x xx0x x1xx x0xx 1xxx 0xxx
Port Control Register
Function BP20 input mode BP20 output mode BP21 input mode BP21 output mode BP22 input mode BP22 output mode BP23 input mode BP23 output mode
5.2.2
Bi-directional Port This, other bi-directional ports include bitwise-programmable Control Register (P5CR), which allows individual programming each port input output. also opens possibility reading condition when output mode. This useful feature self testing serial applications. port pins also used external interrupt inputs (see Figure page Figure page 24). interrupts (INT1 INT6) masked independently configured trigger either edge. interrupt configuration port direction controlled Port Control Register (P5CR). additional resistance pull-up/-down transistor mask option provides internal pull-up serial applications. Port Data Register (P5DAT) mapped primary address register address '5'h Port Control Register (P5CR) corresponding auxiliary register. P5CR byte-wide register configured writing first nibble then high nibble (see section "Addressing Peripherals" page 20).
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Figure 5-3.
Bi-directional Port
Pull-up
Static pull-up
(Data out) P5DATy Master reset enable
BP5y
Static pull-down
Mask options
Pull-down
Figure 5-4.
Port External Interrupts
INT1
Data
BP52
INT6
Data Bi-directional Port IN_Enable
BP51
Bi-directional Port IN_Enable
I/O-bus
I/O-bus
Data
BP53
Data Bi-directional Port IN_Enable
Decoder Decoder Decoder Decoder BP50
Bi-directional Port IN_Enable
P5CR
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
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5.2.2.1 Port Data Register (P5DAT)
Primary register address:'5'hex P5DAT P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b
5.2.2.2
Port Control Register (P5CR) Byte Write
Auxiliary register address:'5'hex P5CR First write cycle Second write cycle P51M2 P53M2 P51M1 P53M1 P50M2 P52M2 P50M1 P52M1 Reset value: 1111b Reset value: 1111b
P5xM2, P5xM1 Port Interrupt Mode/Direction Code
Table 5-3.
Port Control Register
First Write Cycle Second Write Cycle Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function BP52 input mode interrupt disabled BP52 input mode rising edge interrupt BP52 input mode falling edge interrupt BP52 output mode interrupt disabled BP53 input mode interrupt disabled BP53 input mode rising edge interrupt BP53 input mode falling edge interrupt BP53 output mode interrupt disabled
Auxiliary Address:'5'hex Code 3210 xx11 xx01 xx10 xx00 11xx 01xx 10xx 00xx Function
BP50 input mode interrupt disabled BP50 input mode rising edge interrupt BP50 input mode falling edge interrupt BP50 output mode interrupt disabled BP51 input mode interrupt disabled BP51 input mode rising edge interrupt BP51 input mode falling edge interrupt BP51 output mode interrupt disabled
5.2.3
Bi-directional Port bi-directional Port both bitwise configurable port provides external pins Timer voltage monitor input (VMI). normal port, performs exactly same bi-directional Port (see Figure page 22). additional multiplexes allow data port direction control passed over other internal modules (Timer SSI). I/O-pins lines have additional mode generate SSI-interrupt. four Port pins individually switched P4CR-register. Figure page shows internal interfaces bi-directional Port
4708D-4BMCU-09/05
Figure 5-5.
Bi-directional Port
Intx PxMRy
Static pull-up
POut PxDATy Master reset
Pull-up
BPxy
(Direction) Pull-down
Static pull-down
PxCRy PDir
Mask
options
5.2.3.1
Port Data Register (P4DAT)
Primary register address: '4'hex P4DAT P4DAT3 P4DAT2 P4DAT1 P4DAT0 Reset value: 1111b
5.2.3.2
Port Control Register (P4CR) Byte Write
Auxiliary register address: '4'hex P4CR First write cycle Second write cycle P41M2 P43M2 P41M1 P43M1 P40M2 P42M2 P40M1 P42M1 Reset value: 1111b Reset value: 1111b
P4xM2, P4xM1 Port Interrupt Mode/Direction Code Table 5-4.
Code 3210 xx11 xx10 xx01 xx00 11xx 10xx 01xx 00xx
Port Control Register
First Write Cycle Second Write Cycle Code 3210 xx11 xx10 xx0x 11xx 10xx 01xx 00xx Function BP42 input mode BP42 output mode BP42 enable alternate function (T2O Timer BP43 input mode BP43 output mode BP43 enable alternate function SSI) BP43 enable alternate function (falling edge interrupt input INT3)
Auxiliary Address: '4'hex Function
BP40 input mode BP40 output mode BP40 enable alternate function SSI) BP40 enable alternate function (falling edge interrupt input INT3) BP41 input mode BP41 output mode BP41 enable alternate function (VMI voltage monitor input) BP41 enable alternate function (T2I external clock input Timer
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5.2.4 Universal Timer/Counter/ Communication Module (UTCM) Universal Timer/counter/Communication Module (UTCM) consists Timer Timer Synchronous Serial Interface (SSI). Timer interval timer that used generate periodical interrupts prescaler Timer serial interface watchdog function. Timer 8/12-bit timer with external clock input (T2I) output (T2O). operates two-wire serial interface shift register modulation. modulator units work together with timers shift data bits shift register. There multitude modes which timers serial interface work together. Figure 5-6. UTCM Block Diagram
SYSCL SUBCL Interval/Prescaler T1OUT Compare POUT Compare Control 8-bit Counter INT4 from clock module
Timer
Watchdog NRST INT2
Timer
4-bit Counter Modulator
TOG2
Receive-buffer 8-bit Shift-register Transmit-buffer
Control INT3
5.2.5
Timer Timer interval timer which used generate periodic interrupts prescaler Timer Timer serial interface watchdog function. Timer consists programmable 14-stage divider that driven either SUBCL SYSCL. timer output signal used prescaler clock SUBCL source Timer interrupt. Because other system requirements Timer output T1OUT synchronized with SYSCL. Therefore, power-down mode SLEEP (CPU core sleep OSC-Stop yes) output T1OUT stopped (T1OUT Nevertheless, Timer active SLEEP generate Timer interrupts. interrupt maskable T1IM SUBCL bypassed T1BP T1C2 register. time interval timer output programmed Timer control register T1C1. This timer starts running automatically after power-on reset! watchdog function activated, timer restarted writing into T1C1 register with T1RM
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Timer also used watchdog timer prevent system from stalling. watchdog timer 3-bit counter that supplied separate output Timer generates system reset when 3-bit counter overflows. avoid this, 3-bit counter must reset before overflows. application software accomplish this reading register. After power-on reset watchdog must activated software $RESET initialization routine. There watchdog modes, mode watchdog switched software, other mode watchdog active locked. This mode only stopped carrying system reset. watchdog timer operation mode time interval watchdog reset programmed watchdog control register (WDC). Figure 5-7. Timer Module
SYSCL SUBCL WDCL
14-bit Prescaler
4-bit Watchdog
NRST
INT2 T1CS T1MUX T1BP T1IM T1OUT
Figure 5-8.
Timer Watchdog
T1C1 T1RM T1C2 T1C1 T1C0 T1C2 T1BP T1IM
Write T1C1 register
T1MUX
T1IM=0 INT2 T1IM=1 T1OUT
Decoder
interval timer
SUBCL Watchdog Divider/8
Decoder
watchdog timer WDCL
Read register Divider RESET RESET (NRST)
WDT1 WDT0
Watchdog mode control
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5.2.5.1 Timer Control Register (T1C1)
Address: '7'hex Subaddress: '8'hex T1C1 T1RM T1C2 T1C1 T1C0 Reset value: 1111b
MSB,
T1RM T1C2 T1C1 T1C0
T1RM write access without Timer restart T1RM write access with Timer restart Note: Timer restart impossible Timer Control Timer Control Timer Control
Timer Restart Mode
three bits T1C[2:0] select divider Timer resulting time interval depends this divider timer input clock source. timer input supplied system clock clock management. clock management generates SUBCL, selected input clock from oscillator external clock divided
Table 5-5.
T1C2 Note:
Timer Control Bits
T1C1 T1C0 Divider 2048 16384 Time Interval with SUBCL from Time Interval with SYSCL Clock Management 4096 32768 262144 µs/2 µs/4 µs/8 µs/16 µs/32 µs/256 1024 µs/2048 8192 µs/16384
Tin: input clock period 1/Cin (see Figure 4-12 page
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5.2.5.2
Timer Control Register (T1C2)
Address: '7'hex Subaddress: '9'hex T1C2 T1BP T1CS T1IM Reset value: x111b
MSB,
T1BP
Timer SUBCL ByPassed T1BP TIOUT T1MUX T1BP T1OUT SUBCL Timer input Clock Select T1CS SUBCL (see Figure 5-11 page T1CS SYSCL (see Figure 5-11 page Timer Interrupt Mask T1IM disables Timer interrupt T1IM enables Timer interrupt
T1CS
T1IM
5.2.5.3
Watchdog Control Register (WDC)
Address: '7'hex Subaddress: 'A'hex WDT1 WDT0 Reset value: 1111b
MSB,
WatchDog Lock mode watchdog enabled disabled using WDR-bit watchdog enabled locked. this mode WDR-bit effect. After WDL-bit cleared, watchdog active until system reset power-on reset occurs. WatchDog stop mode watchdog stopped/disabled watchdog active/enabled WatchDog Time WatchDog Time
WDT1 WDT0
Both these bits control time interval watchdog reset
Table 5-6.
WDT1 Note:
Watchdog Time Control Bits
WDT0 Divider 2048 16384 131072 Delay Time Reset with 1/(2/1 MHz) 0.256 ms/0.512 1.024 ms/2.048 ms/16.4 65.5 ms/131
tin: input clock period 1/Cin (see Figure 4-12 page
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5.2.6 Timer 8-/12 Timer for:
Interrupt, square-wave, pulse duty cycle generation Baud rate generation internal shift register Manchester Bi-phase modulation together with Carrier frequency generation modulation together with Timer used interval timer interrupt generation, signal generator baud rate generator modulator serial interface. consists 4-bit 8-bit counter stage which both have compare registers. 4-bit counter stages Timer cascadable 12-bit timer 8-bit timer with 4-bit prescaler. timer also configured 8-bit timer separate 4-bit prescaler. Timer input supplied system clock, external input clock (T2I), Timer output clock shift clock serial interface. external input clock synchronized with SYSCL. Therefore, possible Timer with higher clock speed than SYSCL. Furthermore; with that input clock Timer operates power-down mode SLEEP (CPU core sleep OSC-Stop yes) well POWER-DOWN (CPU core sleep OSC-Stop no). other clock sources supplied clock signal SLEEP. 4-bit counter stages Timer have additional clock output (POUT). output modulator stage that allows generation pulses well generation modulation carrier frequencies. Timer output modulate with shift register internal data output generate Bi-phase- Manchester-code. serial interface used modulate bit-stream, 4-bit stage Timer special task. shift register only handle bit-stream lengths divisible other lengths, 4-bit counter stage used stop modulator after right bit-count shifted out. timer used carrier frequency modulation, 4-bit stage works together with additional 2-bit duty cycle generator like 6-bit prescaler generate carrier frequency duty cycle. 8-bit counter used enable disable modulator output programmable count pulses. timer 4-bit 8-bit compare register programming time interval, programming timer function, four mode control registers. comparator output stage controlled special compare mode register (T2CM). This register contains mask bits actions (counter reset, output toggle, timer interrupt) which triggered compare match event counter overflow. This architecture enables timer function various modes. Timer compare data values. Timer 4-bit compare register (T2CO1) 8-bit compare register (T2CO2). Both these compare registers cascadable 12-bit compare register, 8-bit compare register 4-bit compare register. 12-bit compare data value: 8-bit compare data value: 4-bit compare data value: 4095
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Figure 5-9.
Timer
I/O-bus
P4CR
T2M1
T2M2
DCGO
SYSCL T1OUT CL2/1
4-bit Counter
OVF1 POUT
CL2/2
8-bit Counter
OVF2 TOG2
OUTPUT
MOUT
Compare
Control
Compare
INT4
Modulator
T2CO1
POUT
T2CM
T2CO2
Bi-phase Manchester Modulator
Timer modulator output-stage
I/O-bus
Control
5.2.6.1
Timer Modes Mode 12-bit Compare Counter
4-bit stage 8-bit stage work together 12-bit compare counter. compare match signal 4-bit 8-bit stage generates signal counter reset, toggle flip-flop interrupt. compare action programmable compare mode register (T2CM). 4bit counter overflow (OVF1) supplies clock output (POUT) with clocks. duty cycle generator (DCG) bypassed this mode.
Figure 5-10. 12-bit Compare Counter
POUT (CL2/1 /16) CL2/1 OVF2 TOG2 INT4
4-bit counter
8-bit counter
4-bit compare
8-bit compare
Timer output mode T2OTM-bit
4-bit register
T2D1,
8-bit register
T2RM
T2O
T2IM
T2C
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Mode 8-bit Compare Counter with 4-bit Programmable Prescaler
4-bit stage used programmable prescaler 8-bit counter stage. this mode, duty cycle stage also available. This stage used additional 2-bit prescaler generating duty cycles 25%, 50%. 4-bit compare output (CM1) supplies clock output (POUT) with clocks.
Figure 5-11. 8-bit Compare Counter
DCGO POUT CL2/1 OVF2 TOG2 INT4
4-bit counter
8-bit counter
4-bit compare
8-bit compare
Timer output mode T2OTM-bit
4-bit register
T2D1,
8-bit register
T2RM
T2O
T2IM
T2C
Mode 3/4: 8-bit Compare Counter 4-bit Programmable Prescaler
these modes 4-bit 8-bit counter stages work independently 4-bit prescaler 8-bit timer with 2-bit prescaler duty cycle generator. Only mode mode 8-bit counter supplied external clock input (T2I) which selected P4CR register. 4-bit prescaler started activating mode stopped reset mode Changing mode effect 8-bit timer stage. 4-bit stage used prescaler generate stop signal modulator
Figure 5-12. 4-/8-bit Compare Counter
DCGO SYSCL CL2/2
8-bit counter
OVF2 TOG2
INT4 Timer output mode T2OTM-bit P4CR P41M2, T2D1,
8-bit compare
8-bit register
T2RM
T2O
T2IM
T2C
T1OUT SYSCL
CL2/1
4-bit counter
POUT
4-bit compare
T2CS1,
4-bit register
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5.2.6.2
Timer Output Modes signal timer output generated Modulator toggle mode, compare match event toggles output T2O. high resolution duty cycle modulation bits bits used toggle output. duty cycle burst modulator modes output connected switched either toggle flipflop output serial data line SSI. Modulator also modes output content serial interface Biphase Manchester code.
modulator output stage configured output control bits T2M2 register. modulator started with start shift register (SIR stopped either carrying shift register stop (SIR compare match event stage (CM1) Timer this task, Timer mode must used prescaler supplied with internal shift clock (SCL).
Figure 5-13. Timer Modulator Output Stage
DCGO TOG2 Bi-phase/ Manchester modulator Toggle RES/SET
CONTROL
OMSK T2M2 T2OS2, T2TOP
5.2.6.3
Timer Output Signals Timer Output Mode Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 5-14. Interrupt Timer/Square Wave Generator Output Toggles with Each Edge Compare Match Event
Input Counter
Counter INT4
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Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 5-15. Pulse Generator Timer Output Toggles with Timer Start T2TS-Bit
Input Counter
4095/
Counter INT4
Toggle start
Timer Output Mode Toggle Mode Timer compare match toggles output flip-flop (M2) Figure 5-16. Pulse Generator Timer Toggles with Timer Overflow Compare Match
Input Counter
4095/
Counter OVF2 INT4
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Timer Output Mode
Duty Cycle Burst Generator output signal (DCGO) given output, gated output flip-flop (M2)
Figure 5-17. Carrier Frequency Burst Modulation with Timer Toggle Flip-Flop Output
DCGO
Counter TOG2
Counter compare register (=2)
Timer Output Mode
Duty Cycle Burst Generator output signal (DCGO) given output, gated internal data output (SO)
Figure 5-18. Carrier Frequency Burst Modulation with Data Output
DCGO
Counter
Counter compare register (=2)
TOG2
Timer Output Mode Bi-phase Modulator: Timer modulates internal data output (SO) Bi-phase code. Figure 5-19. Bi-phase Modulation
TOG2
8-bit SR-Data
Data: 00110101
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Timer Output Mode
Manchester Modulator: Timer modulates internal data output (SO) Manchester code.
Figure 5-20. Manchester Modulation
TOG2
8-bit SR-Data
Data: 00110101
Timer Output Mode Mode: Pulse-width modulation output Timer output (T2O)
this mode timer overflow defines period compare register defines duty cycle. During period only first compare match occurrence used toggle timer output flip-flop, until overflow occur further compare match ignored. This avoids situation that changing compare register causes occurrence several compare match during period. resolution pulse-width modulation Timer mode 12-bit other Timer modes 8-bit.
Figure 5-21. Modulation
Input clock Counter
Counter OVF2 INT4
load next compare value T2CO2=150 load load
5.2.6.4
Timer Registers Timer control registers configure timer mode, time interval, input clock output function. registers indirectly addressed using extended addressing described section "Addressing Peripherals" page alternate functions Ports BP41 BP42 must selected with Port control register P4CR, Timer modes require input T2I/BP41 output T2O/BP42.
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5.2.6.5
Timer Control Register (T2C)
Address: '7'hex Subaddress: '0'hex T2CS1 T2CS0 T2TS Reset value: 0000b
T2CS1 T2CS0
Timer Clock Select Timer Clock Select
Table 5-7.
T2CS1
Timer Clock Select Bits
T2CS0 Input Clock 2/1) Counter Stage System clock (SYSCL) Output signal Timer (T1OUT) Internal shift clock (SCL) Reserved
T2TS
Timer Toggle with Start T2TS output flip-flop Timer toggled with timer start T2TS output flip-flop Timer toggled when timer started with Timer Timer stop reset Timer
5.2.6.6
Timer Mode Register (T2M1)
Address: '7'hex Subaddress: '1'hex T2M1 T2D1 T2D0 T2MS1 T2MS0 Reset value: 1111b
T2D1 T2D0
Timer Duty cycle Timer Duty cycle
Table 5-8.
T2D1
Timer Duty Cycle Bits
T2D0 Function Duty Cycle Generator (DCG) Bypassed (DCGO0) Duty cycle (DCGO1) Duty cycle (DCGO2) Additional Divider Effect
T2MS1 T2MS0
Timer Mode Select Timer Mode Select
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Table 5-9.
Mode
Timer Mode Select Bits
T2MS1 T2MS0 Clock Output (POUT) 4-bit counter overflow (OVF1) Timer Modes 12-bit compare counter, have bypassed this mode 8-bit compare counter with 4-bit programmable prescaler duty cycle generator 8-bit compare counter clocked SYSCL external clock input T2I, 4-bit prescaler run, counter starts after writing mode 8-bit compare counter clocked SYSCL external clock input T2I, 4-bit prescaler stop resets
4-bit compare output (CM1)
4-bit compare output (CM1)
4-bit compare output (CM1)
5.2.6.7
Duty Cycle Generator duty cycle generator generates duty cycles from 25%, 50%. frequency duty cycle generator output depends duty cycle Timer prescaler setting. DCG-stage also used additional programmable prescaler Timer Figure 5-22. Output Signals
DCGIN DCGO0 DCGO1 DCGO2 DCGO3
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5.2.6.8
Timer Mode Register (T2M2)
Address: '7'hex Subaddress: '2'hex T2M2 T2TOP T2OS2 T2OS1 T2OS0 Reset value: 1111b
T2TOP
Timer Toggle Output Preset This allows programmer preset Timer output T2O. T2TOP resets toggle outputs with write cycle T2TOP sets toggle outputs with write cycle Note: output preset possible Timer Output Select Timer Output Select Timer Output Select
T2OS2 T2OS1 T2OS0
Table 5-10.
Output Mode
Timer Output Select Bits
T2OS2 T2MS1 T2MS0 Clock Output (POUT) Toggle mode: Timer compare match toggles output flip-flop (M2) Duty cycle burst generator output signal (DCG0) given output gated output flip-flop (M2) Duty cycle burst generator output signal (DCGO) given output gated internal data output (SO) Bi-phase modulator: Timer modulates internal data output (SO) Bi-phase code Manchester modulator: Timer modulates internal data output (SO) Manchester code output: used directly internal data output (SO) mode: 8/12-bit mode allowed
Note:
these output modes used alternate function Port must also activated.
5.2.6.9
Timer Compare Compare Mode Registers Timer separate compare registers, T2CO1 4-bit stage T2CO2 8-bit stage Timer timer compares contents compare register current counter value matches generates output signal. Depending timer mode, this signal used generate timer interrupt, toggle output flip-flop clock clock next counter stage.
12-bit timer mode, T2CO1 contains bits T2CO2 bits 12-bit compare value. other modes, compare registers work independently 4-bit 8-bit compare register. When assigned compare register compare event will suppressed.
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5.2.6.10 Timer Compare Mode Register (T2CM)
Address: '7'hex Subaddress: '3'hex T2CM T2OBit T2CBit T2RM T2IM Reset value: 0000b
T2O
Timer Overflow Toggle Mask T2O= disable overflow toggle T2O= enable overflow toggle, counter overflow (OVF2) toggles output flip-flop (TOG2). T2OTM-bit set, only counter overflow generate interrupt except Timer output mode Timer Compare Toggle Mask T2C= disable compare toggle T2C= enable compare toggle, match counter with compare register toggles output flip-flop (TOG2). Timer output mode when T2CTM-bit set, only match counter with compare register generate interrupt. Timer Reset Mask T2RM disable counter reset T2RM enable counter reset, match counter with compare register resets counter Timer Interrupt Mask T2IM disable Timer interrupt T2IM enable Timer interrupt
T2C
T2RM
T2IM
Table 5-11.
Timer Toggle Mask Bits
T2O0 T2Cx Timer Interrupt Source Compare match (CM2) Overflow (OVF2) Compare match (CM2)
Timer Output Mode
5.2.6.11
Timer COmpare Register (T2CO1)
Address: '7'hex Subaddress: '4'hex T2CO1 Write cycle Reset value: 1111b
prescaler mode clock bypassed compare register T2CO1 contains
5.2.6.12
Timer COmpare Register (T2CO2) Byte Write
Address: '7'hex Subaddress: '5'hex T2CO2 First write cycle Second write cycle
Reset value: 1111b Reset value: 1111b
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5.2.7 5.2.7.1
Synchronous Serial Interface (SSI) Features
3-wire 2-wire mode With Timer Bi-phase modulation Manchester modulation Pulse-width demodulation Burst modulation
5.2.7.2
Peripheral Configuration synchronous serial interface (SSI) used either serial communication with external devices such EEPROMs, shift registers, display drivers, other microcontrollers, means generating capturing on-chip serial streams data. External data communication takes place Port (BP4) multi-functional port which software configured writing appropriate control word into P4CR register. configured following ways:
2-wire external interface bi-directional data communication with data terminal shift clock. uses Port BP43 bi-directional serial data line (SD) BP40 shift clock line (SC). 3-wire external interface simultaneous input output serial data, with serial input data terminal (SI), serial output data terminal (SO) shift clock (SC). uses BP40 shift clock (SC), while serial data input (SI) applied BP43 (configured P4CR input). Serial output data (SO) this case passed through BP42 (configured P4CR T2O) Timer output stage (T2M2 configured mode Timer/SSI combined modes used together with Timer capable performing variety data modulation functions (see section "Timer page 27). modulating data converted into continuous serial stream data which turn modulated timer functional blocks.
Figure 5-23. Block Diagram Synchronous Serial Interface
I/O-bus Timer SIC1 SIC2 SISC Control SSI-Control Output 8-bit Shift Register INT3
TOG2 POUT T1OUT SYSCL
Shift_CL
Transmit Buffer I/O-bus
Receive Buffer
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5.2.7.3 General Operation comprised essentially 8-bit shift register with associated 8-bit buffers receive buffer (SRB) capturing incoming serial data transmit buffer (STB) intermediate storage data serially output. Both buffers directly accessable software. Transferring parallel buffer data into shift register controlled automatically control, that both single byte transfers continuous streams supported.
generate shift clock (SC) either from several on-chip clock sources accept external clock. external shift clock output applied Port BP40. Selection external clock source performed Serial Clock Direction control (SCD). combinational modes, required clock selected corresponding timer mode. operate three data transfer modes synchronous 8-bit shift mode, 9-bit MultiChip Link mode (MCL), containing 8-bit data 1-bit acknowledge, corresponding 8-bit mode without acknowledge. both modes data transmission begins after valid start condition ends with valid stop condition. External clocking supported these modes. should thus generate have full control over shift clock that always regarded MCL-bus master device. directional control external data port used handled automatically dependent transmission direction Serial Data Direction (SDD) control bit. This control defines whether currently operating transmit (TX) mode receive (RX) mode. Serial data organized 8-bit telegrams which shifted with most significant first. 9-bit mode, additional acknowledge appended telegram handshaking purposes (see "MCL protocol"). beginning every telegram, control loads transmit buffer into shift register proceeds immediately shift data serially out. same time, incoming data shifted into shift register input. This incoming data automatically loaded into receive buffer when complete telegram been received. Data can, required thus simultaneously received transmitted. Before data transferred, must first activated. This performed means reset control (SIR) bit. further operation then depends data directional mode (TX/RX) present status buffer registers shown Serial Interface Ready Status Flag (SRDY). This SRDY flag indicates (empty/full) status either transmit buffer mode), receive buffer mode). control logic ensures that data shifting temporarily halted time, appropriate receive/transmit buffer ready (SRDY SRDY status will then automatically back data shifting resumed soon application software loads data into transmit register mode) frees shift register reading into receive buffer mode). further activity status (ACT) indicates present status serial communication. remains high duration serial telegram stop start conditions currently being generated. Both current SRDY status read status register. deactivate SSI, must high.
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5.2.7.4
8-bit Synchronous Mode Figure 5-24. 8-bit Synchronous Mode
(rising edge) (falling edge) DATA SD/TO2 Data: 00110101
8-bit synchronous mode, operate either 3-wire interface (see section "SSI Peripheral Configuration" page 42). serial data (SD) received transmitted format, synchronized either rising falling edge shift clock (SC). choice clock edge defined Serial Mode Control bits (SM0, SM1). should noted that transmission edge refers clock edge with which changes. avoid clock skew problems, incoming serial input data shifted with opposite edge. When used together with timer modulator demodulator stages, must 8-bit synchronous mode mode, soon activated (SIR shift clocks generated incoming serial data shifted into shift register. This first telegram automatically transferred into receive buffer SRDY flag indicating that receive buffer contains valid data. same time interrupt enabled) generated. then continues shifting following 8-bit telegram. during this time first telegram been read controller, second telegram will also transferred same into receive buffer will continue clocking next telegram. Should, however, first telegram have been read (SRDY then will stop, temporarily holding second telegram shift register until certain point time when controller able service receive buffer. this data lost overwritten. Deactivating (SIR mid-telegram will immediately stop shift clock latch present contents shift register into receive buffer. This used clocking data telegram less than bits length. Care should taken read final complete 8-bit data telegram multiple word message before deactivating (SIR terminating reception. After termination, shift register contents will overwrite receive buffer.
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Figure 5-25. Example 8-bit Synchronous Transmit Operation
data
data
data
SRDY
Interrupt (IFN Interrupt (IFN Write data Write data Write data
Figure 5-26. Example 8-bit Synchronous Receive Operation
data data
data
SRDY
Interrupt (IFN Interrupt (IFN Read data Read data Read data
5.2.7.5
9-bit Shift Mode 9-bit shift mode, able handle protocol (described below). always operates master device, i.e., always generated output SSI. Both start stop conditions automatically generated whenever activated deactivated SIR-bit. accordance with protocol, output data always changed clock phase shifted high phase.
Before activating (SIR commencing dialog, appropriate data direction first word must using control bit. state this controls direction data port (BP43 MCL_SD). Once started, data bits are, depending selected direction, either clocked into shift register. During clock period, port direction automatically switched over that corresponding acknowledge shifted read transmit mode, acknowledge received from device captured Status Register (TACK) where read controller. receive mode, state acknowledge returned device predetermined Status Register (RACK).
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Changing directional mode (TX/RX) should performed during transfer telegram. should wait until telegram which detected using interrupt (IFN interrogating status. 9-bit telegram, once started will always completion will prematurely terminated bit. SIR-bit with telegram, will complete current transfer terminate dialog with stop condition.
Figure 5-27. Example Transmit Dialog
Start Stop
data
data
SRDY
Interrupt (IFN Interrupt (IFN Write data Write data
Figure 5-28. Example Receive Dialog
Start Stop
data
data
SRDY
Interrupt (IFN Interrupt (IFN
Write data
Read data
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5.2.7.6 8-bit Pseudo Mode this mode, exhibits typical operational features except acknowledge-bit which never expected transmitted. Protocol protocol constitutes simple 2-wire bi-directional communication highway which devices communicate control data information. Although protocol support multi-master configurations, SSI, mode intended purely master controller single master system. reference multiple control contention will omitted this point.
data packaged into 8-bit telegrams plus trailing handshaking acknowledge-bit. Normally communication channel opened with so-called start condition, which initializes devices connected bus. This then followed data telegram, transmitted master controller device. This telegram usually contains 8-bit address code activate single slave device connected onto bus. Each slave receives this address compares with unique address. addressed slave device, ready receive data will respond pulling line during clock pulse. This represents so-called acknowledge. controller detecting this affirmative acknowledge then opens connection required slave. Data then passed back forth master controller, each 8-bit telegram being acknowledged respective recipient. communication finally closed master device slave device back into standby applying stop condition onto bus.
5.2.7.7
Figure 5-29. Protocol
Start condition
Data valid
Data change
Data valid
Stop condition
busy Start data transfer Stop data transfer Data valid
Both data clock lines remain HIGH. HIGH transition line while clock (SC) HIGH defines START condition. HIGH transition line while clock (SC) HIGH defines STOP condition. state data line represents valid data when, after START condition, data line stable duration HIGH period clock signal.
4708D-4BMCU-09/05
Acknowledge
address data words serially transmitted from device eight-bit words. receiving device returns zero data line during ninth clock cycle acknowledge word receipt.
Figure 5-30. Protocol
Start
Stop
5.2.7.8
Interrupt
interrupt INT3 generated either buffer register status (i.e., transmit buffer empty receive buffer full) data telegram falling edge SC/SD pins Port (see P4CR). interrupt selection performed Interrupt Function control (IFN). interrupt usually used synchronize software control inform controller present status. Port interrupts used together with itself required, additional external interrupt sources. either case this interrupt capable waking controller sleep mode. enable select relevant interrupts interrupt mask (SIM) Interrupt Function (IFN) while Port interrupts enabled setting appropriate control bits P4CR register.
5.2.7.9
Modulation
shift register used together with Timer modulation purposes, 8-bit synchronous mode must used. this case, unused Port pins used conventional bi-directional ports. modulation stage, enabled, operates soon activated (SIR ceases when deactivated (SIR byte-orientated data control, (when running normally) generates serial bitstreams which submultiples bits. However, output masking (OMSK) function permits, however, generation bit-streams length. OMSK signal derived indirectly from 4-bit prescaler Timer masks programmable number unrequired trailing data bits during shifting final data word stream. number non-masked data bits defined value pre-programmed prescaler compare register. output masking, modulator stop mode (MSM) must before programming final data word into transmit buffer. This turn, enables shift clocks prescaler when this final word shifted out. reaching compare value, prescaler triggers OMSK signal following data bits blanked.
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Figure 5-31. Output Masking Function
Timer
CL2/1 Compare OMSK Control SSI-control Output TOG2 POUT T1OUT SYSCL Shift_CL 8-bit shift register
4-bit counter
5.2.7.10 5.2.7.11
Serial Interface Registers Serial Interface Control Register (SIC1)
Auxiliary register address: '9'hex SIC1 SCS1 SCS0 Reset value: 1111b
Serial Interface Reset inactive active Serial Clock Direction line used output line used input Note: This during mode
SCS1 SCS0
Serial Clock source Select Serial Clock source Select Note: with bits SCS1 SCS0 insignificant
Table 5-12.
SCS1
Serial Clock Source Select Bits
SCS0 Internal Clock SYSCL/2 T1OUT/2 POUT/2 TOG2/2
4708D-4BMCU-09/05
transmit mode (SDD shifting starts only transmit buffer been loaded (SRDY Setting SIR-bit loads contents shift register into receive buffer (synchronous 8-bit mode only). modes, writing generates start condition writing generates stop condition.
5.2.7.12
Serial Interface Control Register (SIC2)
Auxiliary register address: 'A'hex SIC2 Reset value: 1111b
Modular Stop Mode modulator stop mode disabled (output masking off) modulator stop mode enabled (output masking used modulation modes generating streams which sub-multiples bit.
Serial Mode control Serial Mode control
Table 5-13.
Mode
Serial Mode Control Bits
Mode 8-bit NRZ-Data changes with rising edge 8-bit NRZ-Data changes with falling edge 9-bit two-wire compatible 8-bit two-wire pseudo compatible acknowledge)
Serial Data Direction transmit mode line used output (transmit data). SRDY transmit buffer write access receive mode line used input (receive data). SRDY receive buffer read access
controls port directional control defines reset function SRDY-flag
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5.2.7.13 Serial Interface Status Control Register (SISC)
Primary register address: 'A'hex SISC SISC write read RACK TACK SRDY Reset value: 1111b Reset value: xxxxb
RACK
Receive ACKnowledge status/control mode RACK transmit acknowledge next receive telegram RACK transmit acknowledge last receive telegram Transmit ACKnowledge status/control mode TACK acknowledge received last transmit telegram TACK acknowledge received last transmit telegram Serial Interrupt Mask disable interrupts enable serial interrupt. interrupt generated. Interrupt FuNction serial interrupt generated telegram serial interrupt generated when SRDY goes (i.e., buffer becomes empty/full transmit/receive mode) Serial interface buffer ReaDY status flag SRDY receive mode: receive buffer empty transmit mode: transmit buffer full SRDY receive mode: receive buffer full transmit mode: transmit buffer empty Transmission ACTive status flag transmission active, i.e., serial data transfer. Stop start conditions currently progress. transmission inactive
TACK
SRDY
5.2.7.14
Serial Transmit Buffer (STB) Byte Write
Primary register address: '9'hex First write cycle Second write cycle Reset value: xxxxb Reset value: xxxxb
transmit buffer SSI. transfers transmit buffer into shift register starts shifting with most significant bit.
5.2.7.15
Serial Receive Buffer (SRB) Byte Read
Primary register address: '9'hex First read cycle Second read cycle Reset value: xxxxb Reset value: xxxxb
receive buffer SSI. shift register clocks serial data (most significant first) loads content into receive buffer when complete telegram been received.
4708D-4BMCU-09/05
5.2.8
Combination Modes UTCM consists timer (Timer serial interface. There multitude modes which timers serial interface work together. 8-bit wide serial interface operates shift register modulation. modulator units work together with timers shift data bits into shift register. Combination Mode Timer
5.2.8.1
Figure 5-32. Combination Timer
I/O-bus
P4CR
T2M1
T2M2
DCGO SYSCL T1OUT reserved CL2/1 4-bit Counter OVF1 POUT CL2/2
8-bit Counter OVF2 TOG2
OUTPUT
Compare
POUT
Timer control
Compare
INT4
MOUT Bi-phase Manchester Modulator
T2CO1
TOG2
T2CM
T2CO2
Timer modulator output-stage
Control
I/O-bus
SIC1
TOG2 POUT T1OUT SYSCL SCLI
SIC2
SISC
Control INT3
SSI-control
Output
Shift_CL
8-bit shift register
Transmit buffer I/O-bus
Receive buffer
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ATA6020N
Combination Mode Burst Modulation
mode Timer mode Timer output mode 8-bit internal data output Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler Duty cycle burst generator
Figure 5-33. Carrier Frequency Burst Modulation with Internal Data Output
DCGO
Counter
Counter compare register (=2)
TOG2
Combination Mode Bi-phase Modulation
mode Timer mode Timer output mode 8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler Modulator Timer modulates internal data Bi-phase code
Figure 5-34. Bi-phase Modulation
TOG2
8-bit SR-data
Data: 00110101
4708D-4BMCU-09/05
Combination Mode Manchester Modulation
mode Timer mode Timer output mode 8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter with 4-bit programmable prescaler Modulator Timer modulates internal data Manchester code
Figure 5-35. Manchester Modulation
TOG2
8-bit SR-data
Data: 00110101
Combination Mode Manchester Modulation
mode Timer mode Timer output mode 8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter 4-bit prescaler Modulator Timer modulates data output Manchester code
4-bit stage used prescaler generate stop signal modulator special mode supply prescaler with shift-clock. control output signal (OMSK) used stop signal modulator. Figure 5-36 example 12-bit Manchester telegram.
Figure 5-36. Manchester Modulation
SCLI Buffer full Timer Mode Counter OMSK Counter Compare Register
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ATA6020N
Combination Mode Bi-phase Modulation
mode Timer mode Timer output mode 8-bit shift register internal data output (SO) Timer modulator stage 8-bit compare counter 4-bit prescaler modulator Timer modulates data output Bi-phase code
4-bit stage used prescaler generate stop signal Modulator special mode supply prescaler shift-clock. control output signal (OMSK) used stop signal modulator. Figure 5-37 example 13-bit Bi-phase telegram.
Figure 5-37. Bi-phase Modulation
SCLI Buffer full Timer Mode OMSK Counter Compare Register
4708D-4BMCU-09/05
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. inputs outputs protected against high electrostatic voltages electric fields. However, precautions minimize build-up electrostatic charges during handling recommended. Reliability operation enhanced unused inputs connected appropriate logic voltage level (e.g., VDD). Voltages given relative Parameters Supply voltage Input voltage pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (SSO20) Soldering temperature 10s) Symbol tshort Tamb Tstg RthJA Tsld Value -0.3 +6.5 -0.3 +0.3 Indefinite +130 Unit
Operating Characteristics
Tamb -40°C +85°C unless otherwise specified Parameters Power supply Active current active Rext fSYSCL fRCext fSYSCL fRCext Rext fSYSCL fRCext fSYSCL fRCext fSYSCL fRCext 6.5V Test Conditions Symbol Min. Typ. Max. Unit
Power down current (CPU sleep, RC-oscillator active) Sleep current (CPU sleep, RC-oscillator inactive)
ISleep
5.5V, Tamb -40°C +85°C unless otherwise specified. Parameters Active current active Test Conditions Rext fSYSCL fRCext/2 fSYSCL fRCext/4 Rext fSYSCL fRCext/2 fSYSCL fRCext/4 fSYSCL fRCext/16 Symbol Min. Typ. Max. Unit
Power down current (CPU sleep, oscillator active)
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ATA6020N
Tamb 25°C unless otherwise specified. Parameters Power-on Reset Threshold Voltage threshold voltage threshold voltage hysteresis Voltage Monitor Threshold Voltage high threshold voltage high threshold voltage threshold voltage threshold voltage External Input Voltage VBG, VBG, VVMI VVMI 1.25 1.25 VMThh VMThh VMThl VMThl VPOR VPOR VPOR Test Conditions Symbol Min. Typ. Max. Unit
Bi-directional Ports
Tamb -40°C +85°C unless otherwise specified. Parameters Input voltage Input voltage HIGH Input current (dynamic pull-up) Input HIGH current (dynamic pull-down) Input current (static pull-up) Input current (static pull-down) Output current Test Conditions 3.5V 6.5V 3.5V 6.5V 3.5V, 6.5V 3.5V, 6.5V 3.5V, 6.5V 3.5V, 6.5V 0.2VDD 3.5V, 6.5V 0.8VDD 3.5V, 6.5V Symbol Min. -120 -300 -100 -250 -600 Typ. Max. -200 -500 -1200 1200 Unit
Output HIGH current Note:
BP20/NTE static pull-up resistor during reset-phase microcontroller:
4708D-4BMCU-09/05
Characteristics
Parameters System clock cycle Test Conditions 2.5V 6.5V Tamb -40° +85° Symbol tSYSCL Min. 0.25 Typ. Max. Unit
Operation Cycle Time
Supply voltage 2.5V 6.5V, Tamb 25°C unless otherwise specified. Parameters Timer Input Timing Timer input clock Timer input time Timer input HIGH time Interrupt Request Input Timing Interrupt request time Interrupt request HIGH time External System Clock EXSCL OSC1 input EXSCL OSC1 input Input HIGH time Reset Timing Power-on reset time RC-oscillator Frequency Stability Stabilization time Frequency Stability Stabilization time External resistor 3.5V 5.5V Tamb -40° +85° 3.5V 5.5V Rext 3.5V 5.5V Tamb -40° +85° 3.5V 5.5V fRcOut1 fRcOut2 Rext >VPOR tPOR Rise/fall time Rise/fall time Rise/fall time fEXSCL fEXSCL 0.02 Rise/fall time Rise/fall time tIRL tIRH Rise/fall time Rise/fall time fT2I tT2IL tT2IH Test Conditions Symbol Min. Typ. Max. Unit
RC-oscillator External Resistor
ATA6020N
4708D-4BMCU-09/05
ATA6020N
Figure 8-1.
Active Supply Current versus Frequency
2.000 1.800 1.600 Tamb 25°C
IDDact (mA)
1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.000 1000 1500 2000 2500 3000 3500
4000
System Clock (kHz)
Figure 8-2.
Power-down Supply Current versus Frequency
Tamb 25°C
(µA)
1000
1200
1400
1600
1800
2000
System Clock (kHz)
Figure 8-3.
Active Supply Current versus
0.600 fSYSCLK 0.500
Tamb 85°C
IDDact (mA)
0.400
0.300
25°C -40°C
0.200
0.100
0.000
4708D-4BMCU-09/05
Figure 8-4.
Power-down Supply Current versus
90.0 80.0 70.0 60.0 fSYSCL Tamb 25°C
(µA)
50.0 40.0 30.0 20.0 10.0
Figure 8-5.
Internal Frequency versus
5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00
fRC_INT (MHz)
Tamb -40°C
85°C 25°C
Figure 8-6.
External Frequency versus
1.730 1.710 Rext Tamb -40°C
fRC_EXT (MHz)
1.690 1.670 1.650 1.630 1.610 1.590 1.570 85°C
25°C
ATA6020N
4708D-4BMCU-09/05
ATA6020N
Figure 8-7.
Maximum System Clock versus
12.00
fSYSCLK (MHz)
10.00
8.00
6.00
4.00
2.00
0.00
Figure 8-8.
Internal Frequency versus Tamb
5.60 5.40 5.20 5.00 4.80 4.60 4.40 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 2.00
fRC_INT (MHz)
Tamb (°C)
Figure 8-9.
External Frequency versus Tamb
1.730 1.710 Rext
fRC_EXT (MHz)
1.690 1.670 1.650 1.630 1.610 1.590 1.570
Tamb (°C)
4708D-4BMCU-09/05
Figure 8-10. External Frequency versus Rext
5500 4500 Tamb 25°C
fRC_EXT (kHz)
3500
2500
typ.
1500
Rext
Figure 8-11. Pull-up Resistor versus
1000.0
Tamb 85°C
25°C
100.0
-40°C
10.0
Figure 8-12. Strong Pull-up Resistor versus
100.0
RSPU
Tamb 85°C 25°C
-40°C 10.0
ATA6020N
4708D-4BMCU-09/05
ATA6020N
Figure 8-13. Output High Current versus Output High Voltage
-5.0 -10.0 -15.0
(mA)
-20.0 -25.0
Tamb 25°C
-30.0 -35.0 -40.0
Figure 8-14. Pull-down Resistor versus
1000
Tamb 85°C -40°C
25°C
Figure 8-15. Strong Pull-down Resistor versus
100.0
RSPD
Tamb 85°C
25°C
-40°C 10.0
4708D-4BMCU-09/05
Figure 8-16. Output Current versus Output Voltage
Tamb 25°C
(mA)
Figure 8-17. Output High Current versus Tamb 25°C, 6.5V,
min.
(mA)
typ.
max.
Tamb (°C)
Figure 8-18. Output Current versus Tamb, 6.5V,
max.
typ.
(mA)
min.
Tamb (°C)
ATA6020N
4708D-4BMCU-09/05
ATA6020N
Emulation
basic function emulation test evaluate customer's program hardware real time. This therefore enables analysis timing, hardware software problem. emulation purposes, MARC4 controllers include special emulation mode. this mode, internal core inactive buses available Port Port allow external access on-chip peripherals. MARC4 emulator uses this mode control peripherals MARC4 controller (target chip) emulates lost ports application. MARC4 emulator stop restart program specified points during execution, making possible applications engineer view memory contents those various registers during program execution. designer also gains ability analyze executed instruction sequences activities.
Figure 8-19. MARC4 Emulation
MARC4 emulator Program memory MARC4 emulation-CPU
Emulator target board
MARC4 target chip
Port
control
Port
Trace memory
CORE
CORE (inactive) Peripherals
Port Control logic
Port
Emulation control
SYSCL/ TCL, NRST Application-specific hardware
Personal computer
4708D-4BMCU-09/05
Option Settings Ordering
Please select option settings from list below insert CRC.
Output Port BP20 CMOS Open drain Open drain BP21 CMOS Open drain Open drain Port BP40 CMOS Open drain Open drain BP41 CMOS Open drain Open drain BP42 CMOS Open drain Open drain BP43 CMOS Open drain Open drain Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Watchdog Softlock Hardlock Used oscillator Ext. Ext. clock (External Clock Monitor) Enable Disable BP53 CMOS Open drain Open drain Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static BP52 CMOS Open drain Open drain BP51 CMOS Open drain Open drain Input Port BP50 CMOS Open drain Open drain Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Pull-up Pull-down Pull-up static Pull-down static Output Input
Please attach this page approval form.
Date:
Signature: Company:
ATA6020N
4708D-4BMCU-09/05
ATA6020N
Ordering Information
Extended Type Number(1) ATA6020x-yyy-TKQY Note: Program Memory Data-EEPROM Package SSO20, Pb-free Delivery Taped reeled
Hardware revision Customer specific ROM-version
Package Information
Package SSO20
Dimensions
6.75 6.50
1.30 0.25 0.65 5.85 0.15 0.05 0.15
technical drawings according specifications
4708D-4BMCU-09/05
Revision History
Please note that following page numbers referred this section refer specific revision mentioned, this document. Revision 4708D-4BMCU-09/05 History datasheet template Pb-free Logo page added Ordering Information page changed Figure "ROM MAP" page changed. Figure Figure page page added. datasheet template. Figure "RAM MAP" page changed. Table "Peripheral Addresses" page changed. heading rows Table "Absolute Maximum Ratings" page added. Section "Emulation" page added. Table "Ordering Information" page added. Table name page changed.
4708C-4BMCU-02/04
4708B-4BMCU-12/03
ATA6020N
4708D-4BMCU-09/05
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