Strength Indicator) Output Minimal External Circuitry Requirements, Co

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Strength Indicator) Output Minimal External Circuitry Requirements, Co

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Distinguishes Signal Strength Several Transmitters RSSI (Received Signal
Strength Indicator) Output Minimal External Circuitry Requirements, Components Board Except Matching Receiver Antenna High Sensitivity, Especially Data Rates Sensitivity Reduction Possible Even While Receiving Fully Integrated Power Consumption Configurable Self-polling With Programmable Time Frame Check Supply Voltage 4.5V 5.5V Operating Temperature Range -40°C +105°C Single-ended Input Easy Adaptation Antenna Printed Antenna Low-cost Solution High Integration Level Protection According MIL-STD. HBM) High Image Frequency Suppression Conjunction With Front-end Filter Achievable With Newer SAWs) Communication Microcontroller Possible Single, Bi-directional Data Line Power Management (Polling) also Possible Means Separate Microcontroller
ASK/FSK Receiver ATA3742
Description
ATA3742 multi-chip receiver device supplied SO20 package. been specially developed demands low-cost data transmission systems with data rates from kBaud kBaud kBaud kBaud FSK) Manchester Bi-phase code. receiver well-suited operate with Atmel's transmitter U2741B. main applications area wireless control telemetering, security technology, tire-pressure monitoring keyless-entry systems. used frequency receiving range data transmission. statements made this datasheet refer both 433.92 applications.
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Figure 1-1.
System Block Diagram
ASK/FSK Remote control transmitter ASK/FSK Remote control receiver ATA3742 Demod Encoder ATARx9x Antenna Antenna Control
cell U2741B
Keys
Power amp.
Figure 1-2.
Block Diagram
Dem_out
FSK/ASK CDEM RSSI SENS
FSK/ASK Demodulator data filter RSSI
DATA
Limiter
ENABLE Sensitivity reduction Polling circuit control logic TEST
AVCC AGND DGND Order
MODE DVCC
MIXVCC
Standby logic LFGND
LNAGND
LFVCC
LNA_IN
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Configuration
Figure 2-1. Pinning SO20
SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN DATA ENABLE TEST RSSI MODE DVCC LFGND LFVCC
Table 2-1.
Description
Symbol SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN LFVCC LFGND DVCC MODE RSSI TEST ENABLE DATA Function Sensitivity-control resistor Selecting FSK/ASK Low: FSK, High: Lower cut-off frequency data filter Analog power supply Analog ground Digital ground Power supply mixer High-frequency ground mixer input connected Power supply Loop filter Ground Crystal oscillator Digital power supply Selecting 433.92 MHz/315 Low: 4.90625 (USA) High: 6.76438 (Europe) Output RSSI amplifier Test pin, during operation Enables polling mode Low: polling mode (sleep mode) High: polling mode (active mode) Data output/configuration input
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Front
front receiver heterodyne configuration that converts input signal into signal. seen Figure page front consists (low noise amplifier), (local oscillator), mixer amplifier. generates carrier frequency mixer synthesizer. (crystal oscillator) generates reference frequency fXTO. (voltage-controlled oscillator) generates drive voltage frequency mixer. dependent voltage divided factor divided frequency compared fXTO phase frequency detector. current output phase frequency detector connected passive loop filter thereby generates control voltage VCO. means that configuration, controlled that equal fXTO. determined, fXTO calculated using following formula: fXTO one-pin oscillator that operates series resonance quartz crystal. crystal should connected capacitor according Figure 3-1. value that capacitor recommended crystal supplier. value should optimized individual board layout achieve exact value fXTO hereby fLO. When designing system terms receiving bandwidth, accuracy crystal must considered. Figure 3-1. Peripherals
DVCC
LFGND
LFVCC
passive loop filter connected designed loop bandwidth BLoop kHz. This value BLoop exhibits best possible noise performance Figure shows appropriate loop filter components achieve desired loop bandwidth. filter components changed reason, please note that maximum capacitive load limited. capacitive load exceeded, check longer possible since cannot settle time before check starts evaluate incoming data stream. that case, self-polling will also work. determined input frequency frequency using following formula:
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determine fLO, construction filter must considered this point. nominal frequency MHz. achieve good accuracy filter's corner frequencies, filter tuned crystal frequency fXTO. This means that there fixed relation between that depends logic level MODE. This described following formulas:
MODE (USA) -314 MODE (Europe) -432.92
relation designed achieve nominal frequency most applications. applications where MHz, MODE must "0". case 433.92 MHz, MODE must "1". other frequencies, equal MHz. then dependent logical level MODE fRF. Table summarizes different conditions. input either from antenna from generator must transformed input LNA_IN. input impedance that provided electrical parameters. parasitic board inductances capacitances also influence input matching. receiver ATA3742 exhibits highest sensitivity best signal-to-noise ratio LNA. Hence, noise matching best choice designing transformation network. good practice when designing network start with power matching. From that starting point, values components varied some extent achieve best sensitivity. implemented into input network, mirror frequency suppression PRef achieved. There SAWs available that exhibit notch MHz. These SAWs work best intermediate frequency MHz. selectivity receiver also improved using SAW. typical automotive applications, used. Figure page shows typical input matching network 433.92 using SAW. Figure page illustrates input matching without SAW. input matching networks shown Figure page reference networks parameters given "Electrical Characteristics" page
Table 3-1.
Conditions
Calculation Frequency
Local Oscillator Frequency 432.92 -314 -432.92 Intermediate Frequency -314
MHz, MODE 433.92 MHz, MODE
MHz, MODE
MHz, MODE
-432.92
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Figure 3-2.
Input Matching Network With Filter
LNAGND
LNAGND
ATA3742
LNA_IN
ATA3742
LNA_IN
100p
8.2p
TOKO LL2012 F27NJ
100p
TOKO LL2012
47NJ
433.92
RFIN 8.2p
TOKO LL2012 F33NJ
TOKO LL2012 F82NJ
OUT_GND IN_GND CASE_GND
B3555
RFIN
OUT_GND IN_GND CASE_GND
B3551
Figure 3-3.
Input Matching Network Without Filter
433.92
LNAGND
LNAGND
ATA3742
LNA_IN
ATA3742
LNA_IN
RFIN 3.3p 100p TOKO LL2012 F22NJ
3.3p 100p TOKO LL2012 F39NJ
Please note that coupling conditions (see Figure Figure 3-3), bond wire inductivity ground compensated. forms series resonance circuit together with bond wire. feed inductor establish path. value critical must large enough detune series resonance circuit. cost reduction, this inductor easily printed PCB. This configuration improves sensitivity receiver about
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Analog Signal Processing
Amplifier
signals coming from front filtered fully integrated 4th-order filter. center frequency applications where 433.92 used. other input frequencies, Table page determine center frequency. receiver ATA3742-M3 employs bandwidth used together with U2741B mode.
RSSI Amplifier
subsequent RSSI amplifier enhances output signal amplifier before into demodulator. dynamic range this amplifier RRSSI RSSI amplifier operated within linear range, best signal-to-noise ratio (SNR) maintained mode. dynamic range exceeded transmitter signal, defined ratio maximum RSSI output voltage RSSI output voltage disturber. dynamic range RSSI amplifier exceeded input signal about higher compared input signal full sensitivity. mode, affected dynamic range RSSI amplifier. output voltage RSSI amplifier internally compared threshold voltage VTh_red. VTh_red determined value external resistor RSense. RSense connected between SENS output comparator into digital control logic. this means, possible operate receiver lower sensitivity.
RSSI
output voltage RSSI amplifier (VRSSI) available RSSI. Using RSSI output signal, signal strength different transmitters distinguished. usable input-power range PRef -100 dBm. temperature coefficient VRSSI typically -2.2 mV/K. gain tolerance, possible find absolute level each transmitter, level differences used distinguish several transmitters. illustrated Figure page RSSI output voltage constant over temperature range. Figure illustrates application that realizes temperature compensation VRSSI.
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Figure 4-1.
Temperature Compensation VRSSI
VRSSI_temp_comp. Ig(VLNA_IN) 180k RSSI Bmin VRSSI
ATA3742
Figure 4-2.
RSSI Characteristic
VRSSI
-110 -100 105°C -40°C 25°C
PRef (dBm)
RSense connected receiver operates lower sensitivity. reduced sensitivity defined value RSense, maximum sensitivity signal-to-noise ratio input. reduced sensitivity dependent signal strength output RSSI amplifier. Since different input networks exhibit slightly different values gain, sensitivity values given electrical characteristics refer specific input matching. This matching illustrated Figure page exhibits best possible sensitivity.
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RSense connected microcontroller. receiver switched from full sensitivity reduced sensitivity vice versa time. polling mode, receiver will wake input signal does exceed selected sensitivity. receiver already active, data stream DATA will disappear when input signal lower than defined reduced sensitivity. Instead data stream, pattern shown Figure issued DATA indicate that receiver still active. Figure 4-3. Steady State Limited DATA Output Pattern
DATA
tmin2
tDATA_L_max
FSK/ASK Demodulator Data Filter
signal coming from RSSI amplifier converted into data signal ASK/FSK demodulator. operating mode demodulator ASK/FSK. Logic sets demodulator mode; logic sets into mode. mode, automatic threshold control circuit (ATC) employed detection reference voltage value where good signal-to-noise ratio achieved. This circuit also implies effective suppression kind inband noise signals competing transmitters. exceeds data signal detected properly. demodulator intended used deviation kHz. Lower values used, sensitivity receiver will reduced. minimum usable deviation dependent selected baud rate. mode, only BR_Range0 BR_Range1 available. mode, data signal detected exceeds output signal demodulator filtered data filter before into digital signal processing circuit. data filter improves pass band adopted characteristics data signal. data filter consists 1st-order high-pass 1storder low-pass filter. high-pass filter cut-off frequency defined external capacitor connected CDEM. cut-off frequency high-pass filter defined following formula:
cu_DF CDEM
self-polling mode, data filter must settle very rapidly achieve current consumption. Therefore, CDEM cannot increased very high values self-polling used. other hand, CDEM must large enough meet data filter requirements according data signal. Recommended values CDEM given "Electrical Characteristics" page values slightly different mode. cut-off frequency low-pass filter defined selected baud rate range (BR_Range). BR_Range defined OPMODE register (refer Section "Configuration Receiver" page 20). BR_Range must accordance used baud rate. ATA3742 designed operate with data coding where level data signal 50%. This valid Manchester Bi-phase coding. other modulation schemes used, level should always remain within range VDC_min VDC_max 66%. sensitivity reduced that condition.
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Each BR_Range also defined minimum maximum edge-to-edge time (tee_sig). These limits defined electrical characteristics. They should exceeded maintain full sensitivity receiver.
Receiving Characteristics
receiver ATA3742 operated with without front-end filter. typical automotive application, filter used achieve better selectivity. selectivity with without front-end filter illustrated Figure page This example relates mode. mode exhibits similar behavior. Note that mirror frequency reduced plots printed relatively maximum sensitivity. filter used, insertion loss about must considered. When designing system terms receiving bandwidth, deviation must considered also determines center frequency. total deviation calculated deviation crystal deviation ATA3742. Low-cost crystals specified within ±100 ppm. deviation ATA3742 additional deviation circuit. This deviation specified ppm. crystal ±100 used, total deviation ±130 ppm. Note that receiving bandwidth IF-filter bandwidth equivalent mode mode. Figure 4-4. Receiving Frequency Response
without
(dB)
-100 with
(MHz)
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Polling Circuit Control Logic
receiver designed consume less than while being sensitive signals from corresponding transmitter. This achieved polling circuit. This circuit enables signal path periodically short time. During this time, check logic verifies presence valid transmitter signal. Only valid signal detected does receiver remain active transfer data connected microcontroller. there valid signal present, receiver sleep mode most time, resulting current consumption. This condition called polling mode. connected microcontroller disabled during that time. relevant parameters polling logic configured connected microcontroller. This flexibility enables user meet specifications terms current consumption, system response time, data rate, etc. Regarding number connection wires microcontroller, receiver very flexible. either operated single bi-directional line save ports connected microcontroller, operated three uni-directional ports.
Basic Clock Cycle Digital Circuitry
complete timing digital circuitry analog filtering derived from clock. According Figure page this clock cycle TClk derived from crystal oscillator (XTO) combination with divider. division factor controlled logical state MODE. described Section Front End" page frequency crystal oscillator (fXTO) defined input signal (fRFin), which also defines operating frequency local oscillator (fLO). Figure 5-1. Generation Basic Clock Cycle
TCLK MODE Divider :14/:10 fXTO USA(:10) Europe(:14)
DVCC
MODE accordance with desired clock cycle TClk. TClk controls following application-relevant parameters: Timing polling circuit including check Timing analog digital signal processing Timing register programming Frequency reset marker filter center frequency (fIF0)
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Most applications dominated transmission frequencies: fSend mainly used USA, fSend 433.92 Europe. order ease usage TClk-dependent parameters, electrical characteristics display three conditions each parameter. Application (fXTO 4.90625 MHz, MODE TClk 2.0383 Application Europe (fXTO 6.76438 MHz, MODE TClk 2.0697 Other applications (TClk dependent fXTO logical state MODE. electrical characteristic given function TClk). clock cycle some function blocks depends selected baud rate range (BR_Range) which defined OPMODE register. This clock cycle TXClk defined following formulas further reference:
BR_Range
BR_Range0: BR_Range1: BR_Range2: BR_Range3:
TXClk TClk TXClk TClk TXClk TClk TXClk TClk
Polling Mode
seen Figure page receiver stays polling mode continuous cycle three different modes. sleep mode, signal processing circuitry disabled time period TSleep while consuming current ISoff. During start-up period, TStartup, signal processing circuits enabled settled. following bit-check mode, incoming data stream analyzed bit, looking valid transmitter signal. valid signal present, receiver back sleep mode after period TBitcheck. This period varies check check statistical process. average value TBitcheck given electrical characteristics. During TStartup TBitcheck current consumption ISon. average current consumption polling mode dependent duty cycle active mode calculated
Soff Sleep Startup Bitcheck Spoll Sleep Startup Bitcheck
During TSleep TStartup, receiver sensitive transmitter signal. guarantee reception transmitted command, transmitter must start telegram with adequate preburst. required length preburst dependent polling parameters TSleep, TStartup, TBitcheck startup time connected microcontroller (TStart,microcontroller). TBitcheck thus depends actual rate number bits (NBitcheck) tested. following formula indicates calculate preburst length. TPreburst TSleep TStartup TBitcheck TStart_microcontroller
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5.2.1 Sleep Mode length period TSleep defined 5-bit word Sleep OPMODE register, extension factor Sleep according Table page basic clock cycle calculated TSleep Sleep XSleep 1024 TClk European applications, maximum value TSleep about XSleep "1". time resolution about that case. sleep time extended almost half second setting XSleep XSleep XSleepStd XSleepTemp, resulting different mode action described below: XSleepStd implies standard extension factor. sleep time always extended. XSleepTemp implies temporary extension factor. extended sleep time used long every check check fails once, this back "0", automatically resulting regular sleep time. This functionality used save current presence modulated disturber similar expected transmitter signal. connected microcontroller rarely activated that condition. disturber disappears, receiver switches back regular polling again sensitive appropriate transmitter signals. highest register value Sleep sets receiver into permanent sleep condition (see Table page 22). receiver remains that condition until another value Sleep programmed into OPMODE register. This function desirable where several devices share single data line. 5.2.2 Bit-check Mode bit-check mode, incoming data stream examined distinguish between valid signal from corresponding transmitter signals noise. This done subsequent time frame checks where distances between signal edges continuously compared programmable time window. maximum count these edge-to-edge tests, before receiver switches receiving mode, also programmable. Configuring Check Assuming modulation scheme that contains edges bit, time frame checks verify bit. This valid Manchester, bi-phase most other modulation schemes. maximum count bits checked bits variable NBitcheck OPMODE register. This implies edge-to-edge checks respectively. NBitcheck higher value, receiver less likely switch receiving mode noise. presence valid transmitter signal, check takes less time NBitcheck lower value. polling mode, check time dependent NBitcheck. Figure page shows example where bits tested successfully data signal transferred DATA. According Figure 5-2, time window check defined separate time limits. edge-to-edge time between lower check limit TLim_min upper check limit TLim_max, check will continued. smaller than TLim_min exceeds TLim_max, check will terminated receiver switches sleep mode.
5.2.3
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Figure 5-2.
Valid Time Window Check
1/fSig Dem_out
TLim_min TLim_max
best noise immunity recommended span between TLim_min TLim_max. This achieved using fixed frequency duty cycle transmitter preburst. "11111." "10101." sequence Manchester bi-phase good choice given this recommendation. good compromise between receiver sensitivity susceptibility noise time window ±25% regarding expected edge-to-edge time tee. Using preburst patterns that contain various edge-to-edge time periods, check limits must programmed according required span. check limits determined means formula below: TLim_min Lim_min TXClk TLim_max (Lim_max TXClk Lim_min Lim_max defined 5-bit word each within LIMIT register. Using above formulas, Lim_min Lim_max determined according required TLim_min, TLim_max TXClk. time resolution when defining TLim_min TLim_max TXClk. minimum edge-to-edge time (tDATA_L_min, tDATA_H_min) defined according Section "Receiving Mode" page this, lower limit should Lim_min maximum value upper limit Lim_max
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Figure 5-3. Polling Mode Flow Chart
Sleep Mode: circuits signal processing disabled. Only polling logic enabled. ISOFF TSleep Sleep XSleep 1024 TClk
Sleep:
5-bit word defined Sleep0 Sleep4 OPMODE register Extension factor defined XSleepTemp according Table Basic clock cycle defined fXTO MODE defined selected baud-rate range TClk. baud-rate range defined Baud0 Baud1 OPMODE register. Depends result check. check TBitcheck depends number bits checked Bitcheck utilized data rate. check fails, average time period that check depends selected baud-rate range TClk. baud-rate range defined Baud0 Baud1 OPMODE register.
XSleep: TClk: TStartup:
Start-up Mode: signal processing circuits enabled. After start-up time (TStartup) circuits stable condition ready receive. ISON TStartup
TBit-check: Bit-check Mode: incoming data stream analyzed. timing indicates valid transmitter signal, receiver receiving mode. Otherwise Sleep mode. ISON TBitcheck check
Receiving Mode: receiver turned permanently passes data stream connected microcontroller. Sleep mode through command DATA ENABLE ISON command
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Figure 5-4.
Timing Diagram Complete Successful Check
Number Checked Bits: Enable check
check Dem_out DATA Startup mode
check mode
Receiving mode
Figure 5-5.
Timing Diagram During Check
Lim_min Lim_max Enable TStartup check Dem_out check counter 11121314 151617 1011121314 check check
TXCLK
Figure 5-6.
Timing Diagram Failed Check (Condition: CV_Lim Lim_min)
Lim_min Lim_max Enable check failed (CV_Lim Lim_min)
check Dem_out check counter
1112
Startup mode
check mode
Sleep mode
Figure 5-7.
Timing Diagram Failed Check (Condition: CV_Lim Lim_max)
Lim_min Lim_max Enable check failed (CV_Lim Lim_max
check Dem_out check counter Startup mode
1112 13141516171819 21222324 check mode
Sleep mode
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Figure page Figure illustrate check default check limits Lim_min Lim_max When enabled, signal processing circuits enabled during TStartup. output ASK/FSK demodulator (Dem_out) undefined during that period. When check becomes active, check counter clocked with cycle TXClk. Figure page shows check proceeds check counter value CV_Lim within limits defined Lim_min Lim_max occurrence signal edge. Figure page check fails value CV_lim lower than limit Lim_min. check also fails CV_Lim reaches Lim_max. This illustrated Figure 5-7. 5.2.4 Duration Check transmitter signal present during check, output ASK/FSK demodulator delivers random signals. check statistical process TBitcheck varies each check. Therefore, average value Bitcheck given electrical characteristics. Bitcheck depends selected baud rate range TClk. higher baud rate range causes lower value TBitcheck resulting lower current consumption polling mode. presence valid transmitter signal, TBitcheck dependent frequency that signal, fSig, count checked bits, NBitcheck. higher value NBitcheck thereby results longer period TBitcheck requiring higher value transmitter preburst TPreburst.
Receiving Mode
check successful bits specified NBitcheck, receiver switches receiving mode. shown Figure page internal data signal switched DATA that case. connected microcontroller woken negative edge DATA. receiver stays that condition until switched back polling mode explicitly.
5.3.1
Digital Signal Processing data from ASK/FSK demodulator (Dem_out) digitally processed different ways result converted into output signal data. This processing depends selected baud rate range (BR_Range). Figure page illustrates Dem_out synchronized extended clock cycle TXClk. This clock also used check counter. Data change state only after TXClk elapses. edge-to-edge time period data signal result always integral multiple TXClk. minimum time period between edges data signal limited TDATA_min. This implies efficient suppression spikes DATA output. same time, limits maximum frequency edges DATA. This eases interrupt handling connected microcontroller. TDATA_min some extent affected preceding edge-to-edge time interval illustrated Figure 5-9. between specified check limits, following level frozen time period TDATA_min tmin1, case being outside that check limits TDATA_min tmin2 relevant stable time period. maximum time period DATA limited TDATA_L_max. This function ensures finite response time during programming switching receiver DATA. TDATA_L_max thereby longer than maximum time period indicated transmitter data stream. Figure 5-10 gives example where Dem_out remains after receiver receiving mode.
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Figure 5-8.
Synchronization Demodulator Output
TXClk
Clock check Counter
Dem_out
DATA
Figure 5-9.
Debouncing Demodulator Output
Dem_out
DATA Lim_min CV_Lim Lim_max CV_Lim Lim_min CV_Lim Lim_max tmin2 tmin1
Figure 5-10. Steady State Limited DATA Output Pattern after Transmission
Enable
check Dem_out
DATA Startup mode check mode Receiving mode tmin2 tDATA_L_max
After data transmission, receiver remains active random noise pulses appear DATA. edge-to-edge time period majority these noise pulses equal slightly higher than TDATA_min.
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5.3.2 Switching Receiver Back Sleep Mode receiver back polling mode DATA ENABLE. When using DATA, this must pulled period connected microcontroller. Figure 5-11 illustrates timing command (see also Figure 5-15 page 24). minimum value depends BR_Range. maximum value limited recommended exceed specified value prevent erasing reset marker. This item explained more detail Section "Configuration Receiver" page Setting receiver sleep mode DATA achieved programming OPMODE register "1". Only sync pulse (t3) issued. duration command determined t10. After command, sleep time TSleep elapses. Note that capacitive load DATA limited. resulting time constant together with optional external pull-up resistor exceeded ensure proper operation. receiver polling mode ENABLE, pulse (TDoze) must issued that pin. Figure 5-12 page illustrates timing that command. After positive edge this pulse, sleep time TSleep elapses. receiver remains sleep mode long ENABLE held "L". receiver polled exclusively microcontroller, TSleep programmed enable instantaneous response time. This command faster option than DATA, cost additional connection microcontroller. Figure 5-11. Timing Diagram Command DATA
Out1 (microcontroller)
DATA (ATA3742)
Serial bi-directional data line
("1") (Startbit) TSleep command Startup mode
Receiving mode
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Figure 5-12. Timing Diagram Command ENABLE
TDoze TSleep
toff
ENABLE
DATA (ATA3742)
Serial bi-directional data line
Receiving mode
Startup mode
Configuration Receiver
ATA3742 receiver configured 12-bit registers called OPMODE LIMIT. registers programmed means bi-directional DATA port. register contents have changed voltage drop, this condition indicated certain output pattern called reset marker (RM). receiver must reprogrammed that case. After power-on reset (POR), registers default mode. receiver operated default mode, there need program registers. Table page shows structure registers. Refering Table 5-1, defines receiver back polling mode command (see Section "Receiving Mode" page 17), programmed. represents register address. selects appropriate register programmed.
Table 5-1.
Effect Programming Registers
Action receiver back polling mode (OFF command) OPMODE register programmed LIMIT register programmed
Table page following illustrate effect individual configuration words. default configuration highlighted each word. BR_Range sets appropriate baud rate range. same time defines XLim. XLim used define check limits TLim_min TLim_max shown Table page
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Table 5-2.
Command OPMODE Register BR_Range Baud1 Baud0 NBitcheck BitChk1 BitChk0 VPOUT POUT Sleep4 Sleep3 Sleep Sleep2 Sleep1 Sleep0 XSleep XSleep XSleep Temp
Effect Configuration Words Within Registers
(Default) LIMIT Register
Lim_min
Lim_max
Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
(Default)
Table 5-3.
Baud1
Effect Configuration Word BR_Range
BR_Range Baud0 Baud Rate Range/Extension Factor Check Limits (XLim) BR_Range0 (application USA/Europe: BR_Range0 kBaud kBaud) (Default) XLim (Default) BR_Range1 (application USA/Europe: BR_Range1 kBaud kBaud) XLim BR_Range2 (application USA/Europe: BR_Range2 kBaud kBaud) XLim BR_Range3 (application USA/Europe: BR_Range3 kBaud kBaud) XLim
Table 5-4.
Effect Configuration Word NBitcheck
NBitcheck BitChk1 BitChk0 Number Bits Checked (Default)
Table 5-5.
Effect Configuration Reserved
Reserved Function (Reserved Future Use) (Default)
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Table 5-6.
Sleep4
Effect Configuration Word Sleep
Sleep Sleep3 Sleep2 Sleep1 Sleep0 Start Value Sleep Counter (TSleep Sleep XSleep 1024 TClk) (Receiver continuously polling until valid signal occurs) (TSleep XSleep US/European applications) (USA: TSleep 22.96 Europe: TSleep 23.31 (Default) (Permanent sleep mode)
Table 5-7.
Effect Configuration Word XSleep
XSleep XSleepTemp Extension Factor Sleep Time (TSleep Sleep XSleep 1024 TClk) (Default) (XSleep reset check fails once) (XSleep permanently) (XSleep permanently)
XSleepStd
Table 5-8.
Effect Configuration Word Lim_min
Lim_min Lim_min applicable Lower Limit Value Check (TLim_min Lim_min XLim TClk) (Default) (USA: TLim_min Europe: TLim_min
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Table 5-9. Effect Configuration Word Lim_max
Lim_max Lim_max applicable Upper Limit Value Check (TLim_max (Lim_max XLim TClk) (Default) (USA: TLim_max Europe: TLim_max
5.4.1
Conservation Register Information ATA3742 integrated power-on reset (POR) brown-out detection circuitry provide mechanism preserve register information. According Figure 5-13, power-on reset generated supply voltage drops below threshold voltage VThReset. default parameters programmed into configuration registers that condition. Once exceeds VThReset, canceled after minimum reset period tRst. also generated when supply voltage receiver turned indicate that condition, receiver displays reset marker (RM) DATA after reset. represented fixed frequency duty cycle. canceled pulse DATA. implies following characteristics: lower than lowest feasible frequency data signal. This means, cannot misinterpreted connected microcontroller. receiver back polling mode DATA, cannot cancelled accident applied according proposal Section "Programming Configuration Register" page means that mechanism, receiver cannot lose register information without communicating that condition reset marker
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Figure 5-13. Generation Power-on Reset
VThReset tRst DATA (ATA3742)
1/fRM
Figure 5-14. Timing Register Programming
Out1 (microcontroller) TSleep
DATA (ATA3742)
Serial bi-directional data line
("0") (Startbit) ("1") (Registerselect) Programming frame ("0") (Poll8) ("1") (Poll8R) Startup mode
Receiving mode
5.4.2
Programming Configuration Register configuration registers programmed serially bi-directional data line according Figure 5-14 Figure 5-15. Figure 5-15. One-wire Connection Microcontroller
ATA3742 Internal pull-up resistor Microcontroller Bi-directional data line DATA
Data (ATA3742)
(microcontroller)
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start programming, serial data line DATA pulled time period microcontroller. When DATA been released, receiver becomes master device. When programming delay period elapsed, emits subsequent synchronization pulses with pulse length After each these pulses, programming window occurs. delay until program window starts determined duration defined Within programming window, individual bits set. microcontroller pulls down DATA time period during "0". programming pulse issued, this "1". bits subsequently programmed this way. time frame program defined followed equivalent time window During this window, equivalent acknowledge pulse (E_Ack) occurs just-programmed mode word equivalent mode word that already stored that register. E_Ack should used verify that mode word correctly transferred register. register must programmed twice that case. Programming register possible both during sleep active mode receiver. During programming, LNA, low-pass filter, amplifier FSK/ASK Manchester demodulator disabled. programming start pulse initiates programming configuration registers. "1", represents command receiver back polling mode same time. length programming start pulse following convention should considered: t1(min) 1535 TClk: [t1(min) minimum specified value relevant BR_Range] Programming command) initiated receiver reset mode. receiver reset mode, programming command) initiated, reset marker (RM) still present DATA. This period generally used switch receiver polling mode. reset condition, canceled accident. 5632 TClk Programming command) initiated case. canceled present. This period used connected microcontroller detected configuration register programmed, this time period generally used. Note that capacitive load DATA limited. resulting time constant together with optional external pull-up resistor exceeded ensure proper operation.
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Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Parameters Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched Symbol Ptot Tstg Tamb Pin_max Min. Max. +125 +105 Unit
Thermal Resistance
Parameters Junction ambient Symbol RthJA Value Unit
Electrical Characteristics
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C)
6.76438 Oscillator (Mode Parameter Test Condition Symbol Min. Typ. Max. 4.90625 Oscillator (Mode Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit
Basic Clock Cycle Digital Circuitry Basic clock cycle Extended basic clock cycle Polling Mode Sleep XSleep defined OPMODE register BR_Range0 BR_Range1 BR_Range2 BR_Range3 Average bit-check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 Bit-check time valid input signal fSig NBitcheck NBitcheck NBitcheck NBitcheck Sleep XSleep 1024 2.0697 1855 1061 1061 Sleep XSleep 1024 2.0383 1827 1045 1045 Sleep XSleep 1024 TClk 896.5 512.5 512.5 320.5 TClk MODE (USA) MODE (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk 2.0383 2.0697 16.6 16.3 (fXTO (fXTO TClk TClk TClk TClk
TXClk
Sleep time
TSleep
Start-up time
TStartup
TBitcheck
Time Check
0.45 0.24 0.14 0.14
0.47 0.26 0.16 0.15
TBitcheck
fSig fSig fSig
fSig fSig fSig fSig fSig fSig
fSig fSig fSig
TXClk fSig fSig fSig
TXClk fSig fSig fSig
ATA3742
4900A-RKE-11/05
ATA3742
Electrical Characteristics (Continued)
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C)
6.76438 Oscillator (Mode Parameter Test Condition Symbol Min. Typ. Max. 4.90625 Oscillator (Mode Min. Typ. Max. Min. Variable Oscillator Typ. fXTO fXTO 432.92 10.0 36.7 44.8 18.3 22.4 2136 1068 BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk TClk TClk TClk Max. Unit
Receiving Mode Intermediate frequency Baud-rate range MODE=0 (USA) MODE=1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range0 BR_Range1 BR_Range2 BR_Range3 37.3 45.5 18.6 22.8 2169 1085 10.0 kBaud kBaud kBaud kBaud
BR_Range
Minimum time period between edges DATA (Figure page Maximum period DATA (Figure 5-10 page command ENABLE (Figure 5-12 page
TDATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2
TXClk TXClk TXClk TXClk TXClk TXClk TXClk TXClk TXClk TXClk TXClk TXClk
BR_Range0 BR_Range1 BR_Range2 BR_Range3
TDATA_L_max
tDoze
3.05
TClk
Configuration Receiver Frequency reset marker (Figure 5-13 page BR_Range0 Programming BR_Range1 start pulse BR_Range2 (Figure 5-11 page Figure 5-14 BR_Range3 page after Programming delay period (Figure 5-11 page Figure 5-14 page -4096
117.9
119.8
2188 1104 11656
3176 3176 3176 3176
2155 1087 11479
3128 3128 3128 3128
1057 TClk TClk TClk TClk 5632 TClk
1535 TClk 1535 TClk 1535 TClk 1535 TClk
384.5 TClk
385.5 TClk
4900A-RKE-11/05
Electrical Characteristics (Continued)
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C)
6.76438 Oscillator (Mode Parameter Synchronization pulse (Figure 5-11 page Figure 5-14 page Delay until program window starts (Figure 5-11 page Figure 5-14 page Programming window (Figure 5-11 page Figure 5-14 page Time frame (Figure 5-14 page Programming pulse (Figure 5-11 page Figure page Equivalent acknowledge pulse: E_Ack (Figure 5-14 page Equivalent time window (Figure 5-14 page OFF-bit programming window (Figure 5-11 page Test Condition Symbol Min. Typ. Max. 4.90625 Oscillator (Mode Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit
TClk
63.5 TClk
TClk
1060
1044
TClk
TClk
TClk
TClk
TClk
449.5 TClk
ATA3742
4900A-RKE-11/05
ATA3742
Electrical Characteristics
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C) Parameters Test Conditions Sleep mode (XTO polling logic active) Current consumption active (start check, receiving mode) DATA LNA/mixer/IF amplifier input matched according Figure page Input matched according Figure page required according I-ETS 300220 Input matching according Figure page 433.92 Input matched according Figure page referred RFin Input matched according Figure page 10-3, mode Symbol ISoff ISon Min. Typ. Max. Unit
Mixer Third-order intercept point IIP3
spurious emission RFIn Noise figure mixer (DSB) LNA_IN input impedance compression point (LNA, mixer, amplifier)
ISLORF ZiLNA_IN IP1db
1.56
Maximum input level
Pin_max
Local Oscillator Operating frequency range Phase noise VCO/LO Spurious gain best noise (design parameter) capacitive load limited check used. limitation therefore also applies self-polling. crystal frequency, appropriate load capacitance must connected XTAL 6.764375 4.90625 Series resonance resistor crystal fXTO 6.764 4.906 fosc 432.92 ±fXTO KVCO fVCO (fm) -113 -110 dBC/Hz dBC/Hz MHz/V
Loop bandwidth
BLoop
Capacitive load
CLF_tot
operating frequency
fXTO
6.764375 6.764375 6.764375 4.90625 4.90625 4.90625
4900A-RKE-11/05
Electrical Characteristics (Continued)
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C) Parameters Static capacitance crystal Analog Signal Processing Input matched according Figure page (level carrier) 10-3, 433.92 MHz/315 25°C, BR_Range0 Input sensitivity BR_Range1 BR_Range2 BR_Range3 Sensitivity variation full operating range compared Tamb 25°C, Sensitivity variation full operating range including filter compared Tamb 25°C, 433.92 MHz/315 PASK PRef_ASK PRef 433.92 MHz/315 0.79 1.21 0.73 1.27 PASK PRef_ASK PRef Input matched according Figure page 10-3, 433.92 MHz/315 25°C, BR_Range0 BR_Range1 433.92 MHz/315 PFSK PRef_FSK PRef 433.92 MHz/315 0.86 1.14 0.82 1.18 PFSK PRef_FSK PRef sensitivity receiver higher higher values fFSK BR_Range0 BR_Range1 BR_Range2 BR_Range3 suitable operation mode mode PRef PRef Test Conditions Symbol Cxto Min. Typ. Max. Unit
Input sensitivity
PRef_ASK
-108 -106.5 -106 -104 +2.5
-110 -108.5 -108 -106
-112 -110.5 -110 -108 -1.5
PRef
+5.5 +7.5
-1.5 -1.5
Input sensitivity
PRef_FSK
Input sensitivity
-95.5 -96.5 -94.5 -95.5 +2.5
-97.5 -98.5 -96.5 -97.5
-99.5 -100.5 -98.5 -99.5 -1.5
Sensitivity variation full operating range compared Tamb 25°C, Sensitivity variation full operating range including filter compared Tamb 25°C,
PRef
+5.5 +7.5
-1.5 -1.5
frequency deviation
fFSK
suppress inband noise signals Dynamic range RSSI amplifier
SNRASK SNRFSK RRSSI
ATA3742
4900A-RKE-11/05
ATA3742
Electrical Characteristics (Continued)
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C) Parameters Lower cut-off frequency data filter Test Conditions cu_DF CDEM mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 suitable operation Symbol fcu_DF Min. 0.11 Typ. 0.16 Max. 0.20 Unit
Recommended CDEM best performance
CDEM
Recommended CDEM best performance
CDEM
BR_Range0 (Default) Maximum edge-to-edge time period BR_Range1 input data signal full sensitivity BR_Range2 BR_Range3 Upper cut-off frequency programmable ranges serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3
tee_sig
1000
Upper cut-off frequency data filter
13.6
17.0
11.4 20.4
(peak level)
BR_Range0 (Default) Minimum edge-to-edge time period BR_Range1 input data signal full sensitivity BR_Range2 BR_Range3 Reduced sensitivity RSense connected from Sens input matched according Figure page Tamb 25°C) RSense 433.92 MHz, Reduced sensitivity RSense 433.92 RSense RSense Reduced sensitivity variation over full operating range RSense RSense PRed PRef_Red PRed Values relative RSense RSense RSense RSense RSense RSense RSense PRed PRef_Red PRed
tee_sig
PRef_Red PRed
Reduced sensitivity variation different values RSense
PRed
-3.5 -6.0 -9.0 -11.0 -13.5
4900A-RKE-11/05
Electrical Characteristics (Continued)
parameters refer GND, Tamb -40°C +105°C, 4.5V 5.5V, 433.92 MHz, unless otherwise specified. Tamb 25°C) Parameters Threshold voltage reset Digital Ports Data output Saturation voltage Internal pull-up resistor Maximum time constant Maximum capacitive load FSK/ASK input Low-level input voltage High-level input voltage ENABLE input Low-level input voltage High-level input voltage MODE input Low-level input voltage High-level input voltage TEST input Low-level input voltage (Rpup//RExt) without external pull-up resistor Rext selected selected Idle mode Active mode Division factor Division factor Test input must always RPup 0.08 Test Conditions Symbol VThRESET Min. 1.95 Typ. Max. 3.75 Unit
ATA3742
4900A-RKE-11/05
ATA3742
Ordering Information
Extended Type Number ATA3742P3-TGSY ATA3742P3-TGQY Package SO20 SO20 Remarks Tube, Pb-free Taped reeled, Pb-free
Package Information
Package SO20
Dimensions
12.95 12.70 9.15 8.65
2.35 0.25 10.50 10.20
1.27 11.43
0.25 0.10
technical drawings according specifications
4900A-RKE-11/05
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4900A-RKE-11/05

Strength Indicator) Output Minimal External Circuitry Requirements, Co

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