1.8V, 3.3V 10/100BASETX/FX Physical Layer Transceiver DATASHEET 1.01 G
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KS8001
1.8V, 3.3V 10/100BASETX/FX Physical Layer Transceiver DATASHEET 1.01 General Description
KS8001 10BASE-T/100BASE-TX/FX Physical Layer Transceiver, operating core volts meet voltage power requirements. solution provides MII/RMII/SMII interfaces transmit receive data. unique mixed-signal design extends signaling distance while reducing power consumption. Auto MDI/MDI-X provides most robust solution eliminating need differentiate between crossover straight-through cables. Featuring LinkMD cable diagnostics, which allows detection common cabling plant problems such open short circuits, KS8001 represents level features performance ideal choice physical layer transceiver 100BASE-TX/10BASET/100BASE-FX applications.
Single chip 100BASE-TX/100BASE-FX/10BASE-T physical layer solution 1.8V CMOS design, power consumption Robust (130m+) operation over standard cables Supports Media Independent Interface (MII), Reduced (RMII), Serial (SMII) LinkMD feature determine cable length diagnose faulty cables with accuracy Supports MDI/MDI-X auto crossover Supports power down mode power saving mode MDC/MDIO 12.5 rapid configuration Fully compliant IEEE 802.3u standard Supports auto-negotiation manual selection 10/100Mbps speed full half-duplex mode
Functional Diagram
NRZ/NRZI MLT3 ENCODER 4B/5B ENCODER SCRAMBLER PARALLEL/SERIAL
TRANSMITTER
10/100 PULSE SHAPER
PARALLEL/SERIAL MANCHESTER ENCODER
ADAPTIVE BASELINE WANDER CORRECTION MLT3 DECODER NRZI/NRZ
CLOCK RECOVERY
4B/5B DECODER DESCRAMBLER SERIAL/PARALLEL
MII/RMII/SMII REGISTERS CONTROLLER INTERFACE
AUTO NEGOTIATION
10BASE-T RECEIVER
MANCHESTER DECODER SERIAL/PARALLEL
TXD3 TXD2 TXD1 TXD0 TXER TXEN MDIO RXD3 RXD2 RXD1 RXD0 RXER RXDV
POWER DOWN/ POWER SAVING
LINK
DRIVER
PWRDWN
Micrel, Inc. 1849 Fortune Drive Jose, 95131 (408) 944-0800 (408) 944-0970 http://www.micrel.com
2005
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Features (continued)
Configurable through serial management ports external control pins Programmable outputs link, activity, full/half duplex, collision speed On-chip built-in analog front filtering both 100BASE-TX 10BASE-T Supports back back, media converter applications Single 3.3V power supply with built-in 1.8V regulator (`L' parts) LQFP, SSOP, (targeted)
Ordering Information
Part Number KS8001L KSZ8001L KS8001LI KS8001S KSZ8001S Temp. Range 0o-70o 0o-70o 40o-85o 0o-70o 0o-70o Package 48-LQFP 48-LQFP 48-LQFP 48-SSOP 48-SSOP Lead Finish Standard Lead-free Standard Standard Lead-free
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Revision History
Revision Date
2004 2004 Updated (VDDRCV) definition 3.3V Corrected configuration diagrams reflect pins Updated crystal tolerance Updated series resistance crystal specification LinkMD distance coefficient changed 0.39 Interrupt register status bits RO/SC Recommended reset circuit added RMII timing added Added lead-free part numbers Changed REXT value 6.65 Removed preliminary status Added KS8001S ordering information
Summary Changes
PRELIMINARY
0.81 0.82
2004 2005
1.00 1.01
2005 2005
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Table Contents
Description Strapping Options Configuration Functional Description. 100BASE-TX Transmit 100BASE-TX Receive Clock Synthesizer Scrambler/De-scrambler (100BASE-TX only). 10BASE-T Transmit. 10BASE-T Receive. Jabber Function (10BASE-T only) Auto-Negotiation. Management Interface. Data Interface RMII (Reduced MII) Data Interface. RMII Signal Definition Reference Clock (REF_CLK). Carrier Sense/Receive Data Valid (CRS_DV) Receive Data [1:0] (RXD[1:0]) Transmit Enable (TX_EN) Transmit Data [1:0] (TXD[1:0]). Collision Detection. RX_ER RMII Characteristics RMII Transmit Timing RMII Receive Timing SMII Signal Definition. SMII Signals Receive Path Receive Sequence Diagram Transmit Path Transmit Sequence Diagram Collision Detection. Specification Timing Specification Auto Crossover (Auto MDI/MDI-X) Auto MDI/MDI-X Cross-Over Transformer Connection. Power Management. 100BT Mode. Media converter operation. LinkMD Cable Diagnostics. Reference Clock Connection Options Register Register Basic Control Register Basic Status Register Identifier Register Identifier Register Auto-Negotiation Advertisement.
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Register Auto-Negotiation Link Partner Ability. Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability. Register RXER Counter. Register Interrupt Control/Status Register Register LinkMD Control/Status Register Register Control Register 100BASE-TX Controller Absolute Maximum Rating (Note Operating Range (Note Package Thermal Resistance (JA)(Note Electrical Characteristics (Note4) Timing Diagrams Reset Timing Diagram. Reset Timing Parameters Reset Circuit Diagram Reference Circuit Strapping Option Configuration. Selection Isolation Transformers Selection Reference Crystal. Package Information
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Description
Number Name MDIO RXD3/ PHYAD1 RXD2/ PHYAD2 RXD1/ RXD[1]/ PHYAD3 RXD0/ RXD[0]/ PHYAD4 VDDIO RXDV/ CRSDV/
PCS_LPBK
Type Ipd/O
(Note
Ipd/O
Ipd/O
Ipd/O
Ipd/O
RXC/
SMII_SELECT
Ipd/O
RXER/ RX_ER/ VDDC TXER TXC/ REFCLK/ CLOCK TXEN TXD0/ TXD[0]/
Ipd/O
Function Management Interface (MII) Data This requires external pull-up resistor. Management Interface (MII) Clock Input This synchronous MDIO data interface Mode: Receive Data Output[3]2 Configuration Mode: pull-up/pull-down value latched PHYADDR[1] during reset. "Strapping Options" section details. Mode: Receive Data Output[2] Configuration Mode: pull-up/pull-down value latched PHYADDR[2] during reset. "Strapping Options" section details. Mode: Receive Data Output[1]2 RMII Mode: Receive Data Output[1]3 Configuration Mode: pull-up/pull-down value latched PHYADDR[3] during reset. "Strapping Options" section details. Mode: Receive Data Output[0]2 RMII Mode: Receive Data Output[0]3 SMII Mode: Receive Data Control4 Configuration Mode: pull-up/pull-down value latched PHYADDR[4] during reset. "Strapping Options" section details. Digital /3.3V tolerance power supply. Ground Mode: Receive Data Valid Output RMII Mode: Carrier Sense/Receive Data Valid Configuration Mode: pull-up/pull-down value latched pcs_lpbk during reset. "Strapping Options" section details. Receive Clock Output Operating Mbps Mbps Configuration Mode: pull-up/pull-down value latched SMII during reset. "Strapping Options" section details. Mode: Receive Error Output RMII Mode: Receive Error Configuration Mode: pull-up/pull-down value latched ISOLATE during reset. "Strapping Options" section details. Ground Digital core only power supply Transmit Error Input Mode: Transmit Clock Output RMII Mode: Reference Clock Input SMII Mode: Synchronization Clock Input Transmit Enable Input Mode: Transmit Data Input[0] RMII Mode: Transmit Data Input[0] SMII Mode: Transmit Data Control
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KS8001 Number Name TXD1/ TXD[1]/ SYNC TXD2 TXD3
RMII_SELECT
Micrel Type (Note Function Mode: Transmit Data Input[1] RMII Mode: Transmit Data Input[1] SMII Mode: SYNC Transmit Data Input[2] Transmit Data Input[3] Collision Detect Output Configuration Mode: pull-up/pull-down value latched RMII select during reset. "Strapping Options" section details. Carrier Sense Output Configuration Mode: pull-up/pull-down value latched RMII Loopback during reset when RMII mode selected. "Strapping Options section" details. Ground Digital 3.3V tolerance power supply Management Interface (MII) Interrupt Out. Configuration Mode: Latched PHYAD[0] during power reset. "Strapping Options" section details. Programmable Output Configuration Mode: external pull down enable test mode only used tfactory test. Active Low. LED0 also programmable register 1eh. mode Link/Act Link Link Activity mode Link Link Link mode 10Mbps Link Link State Definition State Definition State Definition Toggle
Ipd/O
CRS/ RMII_BTB
Ipd/O
VDDIO INT#/ PHYAD0 LED0/ TEST
Ipu/O
Ipu/O
LED1 SPD100/ noFEF
Ipu/O
Link Programmable Output Configuration Mode: Latched SPEED (Register during power reset. "Strapping Options" Section details. Active Low. LED1 also programmable register 1eh. mode Speed 10BT 100BT mode Speed 10BT 100BT State Definition State Definition
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KS8001 Number Name Type (Note Function mode 100Mbps Link Link LED2/ DUPLEX Ipu/O State Definition
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Link Programmable Output Configuration Mode: Latched DUPLEX (register during power reset. "Strapping Options" Section details. Active Low. LED2 also programmable register 1eh. mode Duplex Half Full mode Full Duplex/Col Half Full Collision mode Duplex Half State Definition State Definition Toggle State Definition
LED3/ NWAYEN
Ipu/O
Full Programmable Output Configuration Mode: Latched ANEG_EN (register during power reset. "Strapping Options" Section details. Active Low. LED3 also programmable register 1eh. mode Collision Collision Collision mode Activity Activity mode Activity State Definition Activity Toggle Power Down. 1=Normal operation, 0=Power down, Active State Definition Toggle State Definition
VDDRX RXRX+ FXSD/ FXEN
Ipd/O
Analog power supply
Receive Input Differential receive input pins 100BASE-TX 10BASE-T Receive Input Differential receive input 100BASE-TX 10BASE-T Fiber Mode Enable Signal Detect Fiber Mode FXEN=0, mode disable. default "0". "100BT Mode" section more details. Ground
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KS8001 Number Name REXT VDDRCV TXTX+ VDDPLL RST# Type (Note Function Ground External resistor (6.65K connects REXT GNDRX
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Analog power supply (See "Circuit design power supply" section details)
Ground Transmit Outputs Differential transmit output 100BASE-TX/FX 10BASE-T Transmit Outputs Differential transmit output 100BASE-TX/FX 10BASE-T Connect Connect Ground XTAL feedback Used with Xtal application. Crystal Oscillator Input Input crystal external clock Analog power supply Chip Reset Active low, minimum pulse required
Note power supply; ground; input; output; bi-directional input internal pull input internal pull down; Note
Ipu/O input internal pull during reset, output otherwise; Ipd/O input internal pull down during reset, output otherwise; strap pull down; strap pull
Mode: RXD[3.0] bits synchronous with RXCLK. When RXDV asserted, [3.0] presents valid data through MII. [3.0] invalid when RXDV de-asserted. Note RMII Mode: RXD[1.0] bits synchronous with REF_CLK. each clock period which CRS_DV asserted, bits recovered data sent from PHY. Note SMII Mode: Receive data control information sent segments. 100MBit mode, each segment represents byte data. 10MBit mode, each segment repeated times; therefore, every segments represents byte data. sample every segments 10MBit mode. Note Mode: TXD[3.0] bits synchronous with TXCLK. When TXEN asserted, [3.0] presents valid data from through MII. [3.0] effect when TXEN de-asserted. Note RMII Mode: TXD[1.0] bits synchronous with REF_CLK. each clock period which TX_EN asserted, bits recovered data recovered PHY. Note SMII Mode: Transmit data control information received segments. 100MBit mode, each segment represents byte data. 10MBit mode, each segment repeated times; therefore, every segments represents byte data. sample every segments 10MBit mode. 2005 SPECIFICATIONS SUBJECT CHANGE WITHOUT NOTICE KS8001
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Strapping Options
Number 6,5, Name PHYAD[4:1] RXD[0:3] PHYAD0/ INT# PCS_LPBK/ RXDV SMII_SELECT Type (Note Ipd/O Description Address latched power-up reset. default address 00001.
Ipu/O
Ipd/O
Enables PCS_LPBK mode power-up reset. (default) Disable, Enable
Enables SMII mode power-up reset. (default) Disable, Enable RXER Ipd/O Enables ISOLATE mode power-up /reset. (default) Disable, Enable Ipd/O Enables RMII mode power-up reset. RMII_SELECT (default) Disable, Enable Ipd/O Enable RMII_BTB mode power-up reset. RMII_BTB/ (default) Disable, Enable Ipu/O Latched into Register during power-up reset. SPD100 10Mb/s, (default) 100Mb/s. LED1 SPD100 asserted during power-up reset, this also latched Speed Support register FXEN pulled latched value means _End _Fault.) Ipu/O Latched into Register during power-up reset. DUPLEX/ LED2 Half Duplex, (default) Full duplex. Duplex pulled during reset, this also latched Duplex support register Ipu/O Nway (auto-=Negotiation) Enable NWAYEN/ LED3 Latched into Register during power-up reset. Disable Auto-Negotiation, (default) Enable AutoNegotiation Power Down Enable (default) Normal operation, Power down mode Note: Strap-in latched during power reset. some systems, pins drive high times causing strap-in latched high during power system reset. this case, recommended strong pull down 1kohm resistor RXDV, RXC, RXER pins. Otherwise, stay Isolate loop back modes.
Ipd/O
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Configuration
View SSOP
MDIO RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO RXDV/PCS_LPBK RXER/ISO VDDC TXER TXC/REF_CLK TXEN TXD0 TXD1 TXD2 TXD3 COL/RMII CRS/RMII_BTB VDDIO
RST# VDDPLL TXGND
RST#
VDDPLL
VDDRCV
MDIO RXD3/PHYAD1 RXD2/PHYAD2 RXD1/PHYAD3 RXD0/PHYAD4 VDDIO RXDV/PCS_LPBK CRS/RMII_BTB TXC/REF_CLK RXER/ISO VDDC TXER
REXT FXSD/FXEN VDDRX LED0/TEST
View LQFP
KS8001S
VDDRCV REXT FXSD/FXEN RXVDDRX
KS8001L
LED3/NWAYEN LED2/DUPLEX LED1/SPD100
LED3/NWAYEN LED2/DUPLEX LED1/SPD100 LED0/TEST INT#/PHYAD0
COL/RMII
INT#/PHYAD0 VDDIO
TXEN
TXD0
TXD1
TXD2
TXD3
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Functional Description
100BASE-TX Transmit
100BASE-TX transmit function performs parallel-to-serial conversion, NRZI conversion, MLT-3 encoding transmission. circuitry starts with parallel-to-serial conversion, which converts MHz, 4-bit nibbles into serial stream. incoming data clocked positive edge signal. serialized data further converted from NRZI format, then transmitted MLT3 current output. output current external 6.65 resistor transformer ratio. typical rise/fall times complies with ANSI TP-PMD standard regarding amplitude balance, overshoot timing jitter. wave-shaped 10BASE-T output driver also incorporated into 100BASE-TX driver.
100BASE-TX Receive
100BASE-TX receive function performs adaptive equalization, restoration, MLT-3 NRZI conversion, data clock recovery, NRZI conversion, serial-to-parallel conversion. receiving side starts with equalization filter compensate inter-symbol interference (ISI) over twisted pair cable. Since amplitude loss phase distortion function length cable, equalizer adjust characteristic optimize performance. this design, variable equalizer will make initial estimation based upon comparisons incoming signal strength against some known cable characteristics, then tunes itself optimization. This ongoing process self adjust against environmental changes such temperature variations. equalized signal then goes through restoration data conversion block. restoration circuit used compensate effects base line wander improve dynamic range. differential data conversion circuit converts MLT3 format back NRZI. slicing threshold also adaptive. clock recovery circuit extracts clock from edges NRZI signal. This recovered clock then used convert NRZI signal into format. Finally, serial data converted 4-bit parallel nibbles. synchronized generated that nibbles clocked negative edge RCK25 valid receiver positive edge. When valid data present, clock recovery circuit locked reference clock both clocks continue run.
Clock Synthesizer
KS8001 generates clocks system timing. internal crystal oscillator circuit provides reference clock synthesizer.
Scrambler/De-scrambler (100BASE-TX only)
purpose scrambler spread power spectrum signal order reduce baseline wander.
10BASE-T Transmit
When TXEN (transmit enable) goes high, data encoding transmission will begin. KS8001 will continue encode transmit data long TXEN remains high. data transmission will when TXEN goes low. last transition occurs boundary cell last zero, center cell last one. output driver incorporated into 100BASE- driver allow transmission with same magnetics. They internally wave-shaped pre-emphasized into outputs with typical amplitude. harmonic contents least below fundamental when driven all-ones Manchester-encoded signal.
10BASE-T Receive
receive side, input buffer level detecting squelch circuits employed. differential input receiver circuit performs decoding function. Manchester-encoded data stream separated into clock signal data. squelch circuit rejects signals with levels less than with short pulse widths order prevent noises input from falsely trigger decoder. When input exceeds squelch limit, locks onto incoming signal KS8001 decodes data frame. This activates carrier sense (CRS) RXDV signals makes receive data (RXD) available. receive clock maintained active during idle periods between data reception.
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Jabber Function (10BASE-T only)
10BASE-T operation, short pulse will after each packet transmitted. This required test 10BASE-T transmit/receive path called test. 10BASE-T transmitter will disabled will high TXEN High more than (Jabbering). TXEN then goes more than 10BASE-T transmitter will re-enabled will Low.
Auto-Negotiation
KS8001 performs auto-negotiation hardware strapping option (pin software (Register 0.12). will automatically choose mode operation advertising abilities comparing them with those received from link partner whenever autonegotiation enabled. also configured advertise 100BASE-TX 10BASE-T either full- half-duplex mode. Autonegotiation disabled mode. During auto-negotiation, contents Register coded Fast Link Pulse (FLP), will sent link partner under conditions power-on, link-loss re-start. same time, KS8001 will monitor incoming data determine mode operation. Parallel detection circuit will enabled soon either 10BASE-T (Normal Link Pulse) 100BASE-TX idle detected. operation mode configured based following priority: Priority 100BASE-TX, full-duplex Priority 100BASE-TX, half-duplex Priority 10BASE-T, full-duplex Priority 10BASE-T, half-duplex
When KS8001 receives burst from link partner with identical link code words (ignoring acknowledge bit), will store these code words Register wait next identical code words. Once KS8001 detects second code words, then configures itself according above-mentioned priority. addition, KS8001 also checks 100BASE-TX idle 10BASE-T symbols. either detected, KS8001 automatically configures match detected operating speed.
Management Interface
KS8001 supports IEEE 802.3 Management Interface, also known Management Data Input Output (MDIO) Interface. This interface allows upper-layer devices monitor control state KS8001. MDIO interface consists following: physical connection including data line (MDIO), clock line (MDC) optional interrupt line (INTRPT) specific protocol that runs across above-mentioned physical connection also allows controller communicate with multiple KS8001 devices. Each KS8001 assigned address between PHYAD inputs. internal addressable fourteen 16-bit MDIO registers. Register [0:6] required their functions specified IEEE 802.3 specifications. Additional registers provided expanded functionality.
INTPRT functions management data interrupt MII. active High this indicates status change KS8001 based upon 1fh.9 level control. Register bits 1bh[15:8] interrupt enable bits. Register bits 1bh[7:0] interrupt condition bits. This interrupt cleared reading Register 1bh.
Data Interface
data interface consists separate channels transmitting data from 10/100 802.3 compliant Media Access Controller (MAC) KS8001, receiving data from line. Normal data transmission implemented Nibble Mode (4-bit wide nibbles). Transmit Clock (TXC): transmit clock normally generated KS8001 from external 25MHz reference source input. transmit data control signals must always synchronized MAC. KS8001 normally samples these signals rising edge TXC.
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Receive Clock (RXC): 100BASE-TX links, receive clock continuously recovered from line. link goes down, auto-negotiation disabled, receive clock then operates master input clock TXC). 10BASE-T links, receive clock recovered from line while carrier active, operates from master input clock when line idle. KS8001 synchronizes receive data control signals falling edge order stabilize signals rising edge clock with 10ns setup hold times. Transmit Enable: must assert TXEN same time first nibble preamble, de-assert TXEN after last packet. Receive Data Valid: KS8001 asserts RXDV when receives valid packet. Line operating speed mode will determine timing changes following way: 100BASE-TX link with mode, RXDV asserted from first nibble preamble last nibble data packet. 10BASE-T links, entire preamble truncated. RXDV asserted with first nibble remains asserted until packet.
Error Signals: Whenever KS8001 receives error symbol from network, asserts RXER drives "1110" (4B) pins. When asserts TXER, KS8001 will drive symbols Transmit Error define IEEE 802.3 4B/5B code group) line force signaling errors. Carrier Sense (CRS): 100TX links, start-of-stream delimiter, /J/K symbol pair causes assertion Carrier Sense (CRS). end-of-stream delimiter,or /T/R symbol pair causes de-assertion CRS. layer will also de-assert IDLE symbols received without /T/R, this case RXER will asserted clock cycle when de-asserted. links, assertion based reception valid preamble, de-assertion reception end-of-frame (EOF) marker. Collision: Whenever line state half-duplex transmitter receiver active same time, then KS8001 asserts collision signal, which asynchronous clock.
RMII (Reduced MII) Data Interface
RMII interface specifies count (Reduced) Media Independent Interface (RMII) intended between Ethernet PHYs Switch Repeater ASICs. fully compliant with IEEE 802.3u [2]. This interface following characteristics: capable supporting 10Mb/s 100Mb/s data rates single clock reference sourced from from external source) provides independent wide (di-bit) transmit receive data paths uses signal levels, compatible with common digital CMOS ASIC processes
RMII Signal Definition
Signal Name REF_CLK CRS_DV RXD[1:0] TX_EN TXD[1:0] Direction (with respect PHY) Input Output Output Input Input Direction (with respect MAC) Input Output Synchronous clock reference receive, transmit control interface Carrier Sense/Receive Data Valid Receive Data Transit Enable Transit Data
Input Input Output Output Input Receive Error RX_ER Output (Not Required) Note: Unused signals, TXD[3:2], TXER need tied when RMII used
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Reference Clock (REF_CLK)
REF_CLK continuous clock that provides timing reference CRS_DV, RXD[1:0], TX_EN, TXD[1:0], RX_ER. REF_CLK sourced external source. Switch implementations choose provide REF_CLK input output depending whether they provide REF_CLK output rely external clock distribution device. Each device shall have input corresponding this clock single clock input multiple PHYs implemented single
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV asserted asynchronously detection carrier criteria relevant operating mode. That 10BASE-T mode, when squelch passed 100BASE-X mode when non-contiguous zeroes bits detected carrier said detected. Loss carrier shall result de-assertion CRS_DV synchronous REF_CLK. long carrier criteria being met, CRS_DV shall remain asserted continuously from first recovered di-bit frame through final recovered di-bit shall negated prior first REF_CLK that follows final di-bit. data RXD[1:0] considered valid once CRS_DV asserted. However, since assertion CRS_DV asynchronous relative REF_CLK, data RXD[1:0] shall "00" until proper receive signal decoding takes place (see definition RXD[1:0] behavior).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] shall transition synchronously REF_CLK. each clock period which CRS_DV asserted, RXD[1:0] transfers bits recovered data from PHY. some cases (e.g. before data recovery during error conditions) pre-determined value RXD[1:0] transferred instead recovered data. RXD[1:0] shall "00" indicate idle when CRS_DV de-asserted. Values RXD[1:0] other than "00" when CRS_DV de-asserted reserved out-of-band signaling defined). Values other than "00" RXD[1:0] while CRS_DV de-asserted shall ignored MAC/repeater. Upon assertion CRS_DV, shall ensure that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that presenting di-bits TXD[1:0] RMII trans-mission. TX_EN shall asserted synchronously with first nibble preamble shall remain asserted while di-bits transmitted presented RMII. TX_EN shall negated prior first REF_CLK following final di-bit frame. TX_EN shall transition synchronously with respect REF_CLK.
Transmit Data [1:0] (TXD[1:0])
Transmit Data TXD[1:0] shall transition synchronously with respect REF_CLK. When TX_EN asserted, TXD[1:0] accepted transmission PHY. TXD[1:0] shall "00" indicate idle when TX_EN de-asserted. Values TXD[1:0] other than "00" when TX_EN de-asserted reserved out-of-band signaling defined). Values other than "00" TXD[1:0] while TX_EN disserted shall ignored PHY.
Collision Detection
Since definition CRS_DV TX_EN both contain accurate indication start frame, reliably regenerate signal Ending TX_EN CRS_DV. During time following successful transmission frame, signal asserted some transceivers self-test. Signal Quality Error (SQE) function will supported reduced lack signal. Historically, present indicate that transceiver located physically remote from functioning. Since reduced only supports chip-to-chip connections PCB, functionality required.
RX_ER
shall provide RX_ER output according rules specified IEEE 802.3u (see Clause Figure 24-11 Receive State Diagram). RX_ER shall asserted more REF_CLK periods indicate that error (e.g. coding error error that capable detecting, that otherwise undetectable sublayer) detected somewhere frame presently being transferred from PHY. RX_ER shall transition synchronously with respect REF_CLK. While CRS_DV de-asserted, RX_ER shall have effect MAC.
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RMII Characteristics RMII Transmit Timing
20ns
REF_CLK
TXD[1:0] TXEN TXER
Parameter REF_CLK Frequency TXEN, TXD[1:0], TX_EN, Data Setup REF_CLK rising edge TXEN, TXD[1:0], TX_EN, Data hold from REF_CLK rising edge
Units
RMII Receive Timing
20ns
REF_CLK
RXD[1:0] RXDV RXER
Parameter REF_CLK Frequency RXD[1:0], CRS_DV, RX_ER Output delay from REF_CLK rising edge Units
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SMII Signal Definition
SMII composed signals port, global synchronization signal, global 125MHz reference clock. signals synchronous clock. SMII uses common 125MHz reference clock SYNC signals that synchronous reference clock. There signals SMII from MAC-to-PHY each port (TXD TxSYNC), signal port from PHY-to-MAC (RXD). Serial Media Independent Interface (SMII) designed satisfy following requirements: Convey complete information between 10/100 with pins port. Allow multi-port MAC/PHY communication with system clock. Operate both half full duplex. packet switching between 10Mbit 100Mbit data rates. Allow direct communication.
SMII Signals
Signal Name SYNC Clock From System MAC&PHY Receive Data Control Transmit Data Control Synchronization Synchronization
Receive Path
Receive data control information signaled segments. 100Mbit mode, each segment represents byte data. 10Mbit mode, each segment repeated times; therefore, every segments represent byte data. simply every segment 10Mbit mode. Segment boundaries delimited SYNC. continuously generates pulse SYNC every clocks.
Receive Sequence Diagram
X_SYN
RX_DV
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
contains information found receive path standard MII. Bits Purpose Carrier Sense identical MII, except that asynchronous signal RX_DV Receive Data Valid identical RXD7-0 Encoded Data, RXD0-7 Encoding table Description RXD7-0 used convey packet data, RX_ER, status. infer meaning segment-by-basis encoding control bits.
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KS8001 RX_DV RXD0 RX_ER from previous frame RXD1 Speed 0=10Mbit 1=100Mbit RXD2 Duplex 0=Half 1=Full RXD3 Link 0=Down 1=Up RXD4 Jabber 0=OK 1=Error RXD5 Upper Nibble 0=invalid 1=valid RXD6 False Carrier Detected
Micrel RXD7
Data Byte (Two Data Nibble)
TXD7 Encoding Inter-frame status RXD5 conveys validity upper nibble byte previous frame. Inter-frame status RXD0 indicates whether detected error somewhere previous frame. Both these bits should valid segment immediately following frame, should stay valid until first data segment next frame begins. When asserted, inter-frame status RXD6 indicates that detected false carrier event. order send receive data synchronous reference clock, must pass data through elasticity FIFO handle difference between reference clock rate clock packet source. Ethernet specification calls packet data referenced clock with frequency tolerance 100ppm (0.01%); however, uncommon encounter Ethernet stations with clocks that have frequency errors 0.1%. Therefore, elasticity FIFO should least bits long, filling half-way point before beginning valid data transfer RX_ER should asserted during reception frame, this fifo overflows underflows. Only RX_DV should passed through elasticity FIFO. should passed through elasticity FIFO. Instead, should asserted time `wire' busy receiving frame.
Transmit Path
Transmit data control information signaled segments, just like receive path. 100Mbit mode, each segment represents anew byte data. 10Mbit mode each segment repeated times; therefore, every segments represents byte data. sample every segments 10Mbit mode. Segment boundaries delimited SYNC. continuously generates pulse SYNC every clocks.
Transmit Sequence Diagram
TX_CLK
TX_SYNC
TX_ER
TX_EN
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
Bits TX_EN TX_ER TXD7-0 Description
Purpose Transmit Enable identical Transmit Error identical Encoded Data TXD7-0 Encoding Table
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concerned, TXD7-0 used convey only packet data. allow direct connection, uses TXD7-0 signal `status' between frames. TX_ER TX_EN TXD0 force error direct connection TXD1 100MBit TXD2 Full Duplex TXD3 Link TXD4 Jabber TXD7-5
TXD7 Encoding
Data Byte (Two Data Nibbles)
Collision Detection
Collisions occur when TX_EN simultaneously asserted. this work, must ensure that affected transmit path.
Specification
Parameter Input High Voltage Input Voltage Input High Current Input Current Symbol Units Volts Volts
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Timing Specification
Parameter Input Setup Input Hold Output Delay Units
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Auto Crossover (Auto MDI/MDI-X)
Automatic MDI/MDI-X configuration intended eliminate need crossover cables between similar devices. assignment pin-outs 10/100 BASE-T crossover function cable shown below. This feature eliminate confusion real applications allowing both straight cable crossover cables. This feature controlled register 1f:13, "Register 1fh" section details.
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Auto MDI/MDI-X Cross-Over Transformer Connection
KS8001 features Auto MDI/MDI-X crossover requires symmetric transformers that support Auto MDI/MDI-X. Selection Isolation Transformers list transformers that support Auto MDI/MDI-X.
Power Management
KS8001 offers following modes power management: Power Down Mode: This mode achieved writing Register 0.11 pulling Low. power down state, KS8061 disables internal functions drives output pins logic zero, except serial management interface. Power Saving Mode: writing register 1fh.10 disable this mode. KS8001 will then turn everything except Energy Detect circuits when cable installed. other words, KS8001 will shutdown most internal circuits save power there link. Power Saving mode will this most effective state when AutoNegotiation Mode enabled.
100BT Mode
100BT mode activated when FXSD/FXEN higher than 0.6V (This default pull down). Under this mode, autonegotiation auto-MDIX features disabled. fiber operation FXSD should connect (signal detect) output fiber module. internal threshold FXSD around (2.2V 0.05V 3.3V). Above this level, considered Fiber signal detected, operation summarized following table: FXSD/FXEN Less than 0.6V Less than 2.15V, greater than 0.6V Greater than 2.25V Condition 100TX mode mode signal detected generated mode Signal detected
ensure proper operation, swing fiber module should cover threshold variation. resistive voltage divider recommended adjust voltage range. (Far Fault), repetition special pattern, which consists 84-ones 1-zero, generated under mode with signal detected". purpose notify sender faulty link. When receiving FEF, LINK will down indicate fault, even with fiber signal detected. transmitter affected receiving still sends normal transmit pattern from MAC. disabled strapping pin27 low, please refer "Strapping Options" section.
Media converter operation
KS8001 capable performing media conversion with parts back-to-back RMII mode indicated diagram. Both parts RMII mode with RMII_BTB asserted (pin21 strapped high). part operating mode other mode. Both parts share common 50MHz oscillator. Under this operation, auto-Negotiation side will prohibit 10BASE-T link Additional options implemented under this operation. Disable transmitter tri-state controlling high TXD2 pin. order this, RXD2 TXD2 pins need connected inverter. When TXD2 high both copper fiber operation, disables transmit. Meanwhile, RXD2 copper side serves energy detect indicate line signal detected. TXD3 should tied RXD3 float. Please contact your local Micrel Media Converter reference design.
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+/TxC/ Ref_CLK
TxC/ Ref_CLK
KS8001
(Fiber Mode) Fiber Module
LinkMD Cable Diagnostics
KS8001 utilizes time domain reflectometry (TDR) analyze cabling plant common cabling problems such open circuits, short circuits impedance mismatches. LinkMD works sending pulse known amplitude duration down MDIX pairs analyzing shape reflected signal. Timing duration gives indication distance cabling fault with maximum distance accuracy Cable diagnostics only valid copper connections support fiber optic operation. LinkMD used accessing register 1dh, LinkMD Control/Status register conjunction with register 1fh, 100BASE-TX Controller register. LinkMD, Auto-MDIX disabled writing 1f:13 enable manual control over which pair used transmit LinkMD pulse. self-clearing Cable diagnostic test enable bit, 1d.15 start test this pair. When 1d.15 returns `0', test complete. test result returned 1d.14:13 distance returned 1d.8:0. cable diagnostic test results follows: Valid test, normal condition Valid test, open circuit cable Valid test, short circuit cable Invalid test, LinkMD failed
`11' case, Invalid test, occurs when possible KS8001 shut down link partner. this case, test run, since would possible KS8001 determine detected signal reflection signal generated signal from another source. Cable length determined multiplying contents 1d.8:0 0.39. This constant calibrated different cabling conditions, including cables with velocity propagation that varies significantly from norm.
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Reference Clock Connection Options
KS8001 capable performing three different kinds clock speed options connecting external reference clock depends upon different interface using MII/RMII/SMII. figures below illustrate recommended connection using different interface options. Please selection reference crystal table specifications.
25MHz 100ppm
25MHz Oscillator Reference Clock Connection Diagram
22pF 22pF 22pF 22pF 25MHz Xtal 100ppm
25MHz Crystal Reference Clock Connection Diagram
50/125MHz 100ppm
REF_CLK
50/125MHz Oscillator Reference Clock Connection RMII/SMII Mode Diagram
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Register
Register 9h-14h Address 0.15 0.14 0.13 Name Reset Loop-back Speed Select (LSB) Description Basic Control Register Basic Status Register Identifier Identifier Auto-Negotiation Advertisement Register Auto-Negotiation Link Partner Ability Register Auto-Negotiation Expansion Register Auto-Negotiation Next Page Register Link Partner Next Page Ability Reserved RXER Counter Register Reserved Interrupt Control/Status Register Reserved LinkMD Control/Status Register Control Register 100BASE-TX Control Register Description software reset. self-clearing loop-back mode normal operation 100Mb/s 10Mb/s Ignored Auto-Negotiation enabled (0.12 enable auto-negotiation process (override 0.13 0.8) disable auto-negotiation process power down mode normal operation electrical isolation from TX+/TX0 normal operation restart auto-negotiation process normal operation. self-clearing full duplex half duplex enable test disable test enable transmitter disable transmitter Mode Default SPD100
Register Basic Control
0.12
AutoNegotiation Enable Power Down
NWAYEN
0.11
0.10
Isolate
0.6:1
Restart AutoNegotiation Duplex Mode Collision Test Reserved Disable Transmitter
DUPLEX
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KS8001 Address 1.15 1.14 1.13 1.12 1.11 Name 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX Half Duplex 10BASE-T Full Duplex 10BASE-T Half Duplex Reserved Preamble AutoNegotiation Complete Remote Fault AutoNegotiation Ability Link Status Jabber Detect Extended Capability Number Description capable capable capable 100BASE-X full duplex capable 100BASE-X full duplex capable 100BASE-X half duplex capable 100BASE-X half duplex 10Mbps with full duplex 10Mbps with full duplex capability 10Mbps with half duplex 10Mbps with half duplex capability Mode Default
Micrel
Register Basic Status
1.10:7
preamble suppression normal preamble auto-negotiation process completed auto-negotiation process completed remote fault remote fault capable perform auto-negotiation unable perform auto-negotiation link link down jabber detected jabber detected. Default supports extended capabilities registers
RO/LH
RO/LL RO/LH
Register Identifier
2.15:0
Assigned through bits Organizationally Unique Identifier (OUI). Kendin Communication's 0010A1 (hex)
0022h
Register Identifier
3.15:10 Number Model Number Revision Number Next Page Reserved Remote Fault Reserved
Assigned through bits Organizationally Unique Identifier (OUI). Kendin Communication's 0010A1 (hex) manufacturer's model number Four manufacturer's model number
000101
3.9:4 3.3:0
100001 1010
Register Auto-Negotiation Advertisement
4.15 4.14 4.13 4.12 next page capable next page capability. remote fault supported remote fault
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KS8001 Address 4.10 4.4:0 Name Pause 100BASE-T4 100BASE-TX Full Duplex 100BASE-TX 10BASE-T Full Duplex 10BASE-T Selector Field Description pause function supported pause function capable capability with full duplex full duplex capability capable capability 10Mbps with full duplex 10Mbps full duplex capability 10Mbps capable 10Mbps capability [00001] IEEE 802.3 Mode Default
Micrel
SPD100 DUPLEX SPD100 DUPLEX 00001
Register Auto-Negotiation Link Partner Ability
5.15 5.14 5.13 5.12 5.11:10 Next Page Acknowledge Remote Fault Reserved Pause 5.10 PAUSE Asymmetric PAUSE (link partner) Symmetric PAUSE Symmetric Asymmetric PAUSE (local device) capable capability with full duplex full duplex capability capable capability 10Mbps with full duplex 10Mbps full duplex capability 10Mbps capable 10Mbps capability [00001] IEEE 802.3 next page capable next page capability link code word received from partner link code word received remote fault detected remote fault
5.4:0
BASE-T4 100BASE-TX Full Duplex 100BASE-TX 10BASE-T Full Duplex 10BASE-T Selector Field
00001
Register Auto-Negotiation Expansion
6.15:5 Reserved
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KS8001 Address Name Parallel Detection Fault Link Partner Next Page Able Next Page Able Page Received Link Partner AutoNegotiation Able Description fault detected parallel detection fault detected parallel detection. link partner next page capability link partner does have next page capability local device next page capability local device does have next page capability page received page received link partner auto-negotiation capability link partner does have auto-negotiation capability Mode Default
Micrel
Register Auto-Negotiation Next Page
7.15 7.14 7.13 7.12 7.11 Next Page Reserved Message Page Acknowledge2 Toggle message page unformatted page will comply with message cannot comply with message previous value transmitted link code word equaled logic logic Zero 11-bit wide field encode 2048 messages additional next page(s) will follow last page
7.10:0
Message Field
Register Link Partner Next Page Ability
8.15 8.14 8.13 8.12 Next Page Acknowledge Message Page Acknowledge2 additional Next Page(s) will follow last page successful receipt link word successful receipt link word Message Page Unformatted Page able information able information previous value transmitted Link Code Word equal logic zero previous value transmitted Link Code Word equal logic
8.11
Toggle
8.10:0
Message Field
Register RXER Counter
15.15:0 RXER Counter Error counter RX_ER each package 0000
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KS8001 Address Name Description Mode Default
Micrel
Register Interrupt Control/Status Register
1b.15 Jabber Interrupt Enable Receive Error Interrupt Enable Page Received Interrupt Enable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Enable Remote Fault Interrupt Enable Link Interrupt Enable Jabber Interrupt Receive Error Interrupt Page Receive Interrupt Parallel Detect Fault Interrupt Link Partner Acknowledge Interrupt Link Down Interrupt Remote Fault Interrupt Link Interrupt 1=Enable Jabber Interrupt 0=Disable Jabber Interrupt 1=Enable Receive Error Interrupt 0=Disable Receive Error Interrupt 1=Enable Page Received Interrupt 0=Disable Page Received Interrupt Enable Parallel Detect Fault Interrupt Disable Parallel Detect Fault Interrupt Enable Link Partner Acknowledge Interrupt Disable Link Partner Acknowledge Interrupt Enable Link Down Interrupt Disable Link Down Interrupt Enable Remote Fault Interrupt Disable Remote Fault Interrupt Enable Link Interrupt Disable Link Interrupt Jabber Interrupt Occurred Jabber Interrupt Does Occurred Receive Error Occurred Receive Error Does Occurred Page Receive Occurred Page Receive Does Occurred Parallel Detect Fault Occurred Parallel Detect Fault Does Occurred Link Partner Acknowledge Occurred Link Partner Acknowledge Does Occurred Link Down Occurred Link Down Does Occurred Remote Fault Occurred Remote Fault Does Occurred Link Interrupt Occurred Link Interrupt Does Occurred
1b.14
1b.13
1b.12
1b.11
1b.10
1b.9
1b.8
1b.7 1b.6 1b.5 1b.4 1b.3
RO/SC RO/SC RO/SC RO/SC RO/SC
1b.2 1b.1 1b.0
RO/SC RO/SC RO/SC
Register LinkMD Control/Status Register
1d.15 Cable diagnostic test enable Indicates cable diagnostic test completed status information valid read. cable diagnostic test activated. This self-clearing.
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KS8001 Address 1d.14:13 Name Cable diagnostic test result Description [00] normal condition [01] open condition been detected cable [10] short condition been detected cable [11] cable diagnostic test failed Mode Default
Micrel
1d.12:9 1d.8:0
Reserved Cable fault counter Distance fault, approximately 0.39m*cabfaultcnt value
Register Control
1e:15:14 mode [00] LED3 collision LED2 full duplex LED1 speed LED0 link/activity [01] LED3 activity LED2 full duplex/collision LED1 speed LED0 link [10] LED3 activity LED2 full duplex LED1 100Mbps link LED0 10Mbps link [11] reserved Polarity reversed Polarity reversed fault detected fault detected MDIX
1e.13 1e.12 1e.11 1e:10:8 1e:7 1e:6:0
Polarity fault detect MDIX/MDI state Reserved Remote loopback Reserved
normal mode remote (analog) loop back enable
Register 100BASE-TX Controller
1f:15 Reserved
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KS8001 Address 1f:14 Name Mdi/mdix select when auto mdi/mdix disable Pairswap disable Energy detect Description transmit pair (TPFINn/TPFIPn) receive pair (TPFONn/TPFOPn). transmit pair (TPFONn/TPFOPn) receive pair (TPFINn/TPFIPn). disable MDI/MDIX enable MDI/MDIX presence signal RX+/- analog wire pair signal detected RX+/1 force link pass normal link operation This bypasses control logic allow transmitter send pattern even there link. enable power saving disable interrupt active high active enable jabber counter disable auto-negotiation complete complete flow control capable flow control isolate mode isolated [000] still auto-negotiation [001] 10BASE-T half duplex [010] 100BASE-TX half duplex [011] default [101] 10BASE-T full duplex [110] 100BASE-TX full duplex [111] PHY/MII isolate enable test disable disable scrambler enable Mode Default
Micrel
1f:13 1f.12
1f.11
Force link
1f.10 1f.9 1f.8 1f.7
Power Saving Interrupt Level Enable Jabber AutoNegotiation Complete Enable Pause (Flow-Control Result) Isolate Operation Mode Indication
1f.6
1f.5 1f.4:2
1f.1 1f.0
Enable test Disable Data Scrambling
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Absolute Maximum Rating (Note
Storage Temperature (TS) -55°C +150°C Supply Referenced GND. .-0.5V +4.0 pins .-0.5V +4.0 Important: Please read Notes bottom page.
Operating Range (Note
Supply Voltage (VDD_PLL, VDD_TX, VDD_RXC, VDDC).1.8V (VDD_RCV, VDDIO).3.3V Ambient Temperature Commercial (TA).0°C +70°C Ambient Temperature Industrial (TA).-40°C +85°C
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Package Thermal Resistance (JA)(Note
Thermal Resistance Airflow Velocity (m/s) LQFP SSOP 83.56 75.19 77.08 68.20 72.36 66.20 46.93
Electrical Characteristics (Note4)
VDD=3.3V ±10%
Symbol IDD1 IDD2 IDD3 IDD4 IDD5
Parameter
Condition
(Note
Units
Total Supply Current (including output drive current)
Normal 100BASE-TX Normal 10BASE-T Power Saving Mode Power Down Mode (software power down) Power down (PD#)
Including 40mA output current
Including 90mA output current, indepdendent utilization
Auto-negotiation Enabled
Inputs Input High Voltage Input Voltage Input Current (I/O)
Outputs Output High Voltage Output Voltage Output Tri-State Leakage Peak Differential Ouput Voltage Output Voltage Imbalance Rise/Fall Time Rise/Fall Time Imbalance Duty Cycle Distortion Overshoot VSET Refernce Voltage ISET Propagation Delay Jitter 10BASE-T Transmit (measured differentially after transformer) 0.75 -4mA (I/O)
100BASE-TX Transmit (measured differentially after transformer) VIMB from each output from each output 0.95 1.05 ±0.5 ns(pk-pk)
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KS8001 Peak Differential Ouput Voltage Output Voltage Imbalance Rise/Fall Time Crystal Oscillator Receive Clock, 100TX Receive Clock, Receive Clock Jitter TXC100 TXC10 Transmit Clock, 100TX Transmit Clock, Transmit Clock Jitter
Note Note Note Note Note
Micrel
VIMB RXC100 RXC10
from each output from each output
±3.5
ns(pk-pk) ns(pk-pk)
Clock Outputs
Exceeding absolute rating(s) cause permanent damage device. Operating maximum conditions extended periods affect device reliability. This device guaranteed operate beyond specified operating rating. Unused inputs must always tied appropriate logic voltage level (Ground VDD). (heat spreader) package. Specification packaged product only. 100% data transmission full-duplex mode minimum with 130-meter cable.
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Timing Diagrams
TXEN
TXEN
etup etup after after asserted latency e-asserted latency latency) elay after e-asserted ulse uratio
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100BaseTX Transmit Timing
tSU2
TXEN
tHD2 tHD1
tSU1
TXD[3:0], TXER Data
tCRS1 tLAT
tCRS2
TX+/TX-
Symbol
min. tSU1 tSU2 tHD1 tHD2 tHD3 tCRS1 tCRS2 tLAT TXD[3:0] Setup High TX_ER Setup High TXD[3:0] Hold after High TXER Hold after High TXEN Hold after High TXEN High asserted latency TXEN de-asserted latency TXEN High TX+/TX- output latency) 10ns 10ns
typ.
max.
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100BaseTX Receive Timing
RX+/RX-
Start Stream
Stream
tCRS1
tCRS2 tRLAT
RXDV
RXD[3:0] RXER
min. tRLAT tCRS1 tCRS2 period pulse width pulse width RXD[3:0], RXER, RXDV setup rising edge RXD[3:0], RXER, RXDV hold from rising edge latency, aligned "Start Stream" asserted "End Stream" de-asserted
typ. 40ns
max.
20ns 20ns 20ns 20ns 140ns 170ns
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Auto Negotiation Fast Link Pulse Timing
Burst Burst
TX+/TX-
tFLPW tBTB
Clock Pulse TX+/TX-
Data Pulse
Clock Pulse
Data Pulse
tCTD
tCTC
min. tBTB tFLPW tCTD tCTC burst burst burst width Clock/Data pulse width Clock pulse data pulse Clock pulse clock pulse Number Clock/Data pulses burst
typ. 16ms 100ns 69us 136us
max. 24ms
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Serial Management Interface Timing
tMD1
MDIO (Into Chip) MDIO (Out Chip)
tMD2
Valid Data Valid Data Valid Data
tMD3
min. tMD1 tMD2 tMD3 period MDIO Setup (MDIO input) MDIO Hold after (MDIO input) MDIO Valid (MDIO output)
typ.
max.
10ns 10ns 222ns
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Reset Timing Diagram
Supply Voltage
RST_N
Strap-In Value
Reset Timing Parameters
Parameter Description Stable supply voltages reset high Units
Reset Circuit Diagram
Micrel recommends following discrete reset circuit shown Figure when powering KS8001 device. application where reset circuit signal comes from another device (e.g., CPU, FPGA, etc), recommend reset circuit shown Figure
KS8001
CPU/FPGA
RST_OUT_n
10uF
1N4148
Recommended Reset Circuit
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1N4148
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10uF
Recommended Circuit Interfacing with CPU/FPGA Reset
power-on-reset, provide necessary ramp rise time reset Micrel device. reset from CPU/FPGA provides warm reset after power also recommend power core voltage earlier than VDDIO voltage. worst case, both core VDDIO voltages should come same time.
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Reference Circuit Strapping Option Configuration
Figure shows reference circuit strapping option pins
Pull
KS8001
Pull Down
KS8001
Reference circuits anaged program through ports
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Selection Isolation Transformers
isolation transformer required line interface. isolation transformer with integrated common-mode choke recommended exceeding requirements. following table gives recommended transformer characteristics. Parameter Turns Ratio Open-Circuit Inductance (min.) Leakage Inductance (max.) Inter-Winding Capacitance (max.) D.C. Resistance (max.) Insertion Loss (max.) HIPOT (min.) Transformer Selection Criteria Value Ohms 1500 Vrms Magnetic Vendor Selection Lists Single Port Magnetic manufacturer Pulse Fuse Fuse Fuse Transpower Delta LanKom Test Condition kHz, (min.)
0-65
Part number H1102 S558-5999-U7 SI-46001 SI-50170 PT163020 HB726 LF8505 LF-H41S
AUTO MDIX
Number port
Selection Reference Crystal
oscillator crystal with following typical characteristics recommended. Charateristics Frequency Frequency Tolerance(max) Load Capacitance (max) Series Resistance Value 25.00000 Units
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Package Information
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