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8-bit Microcontroller Compatible with MCS®51 Products Enhanced 8051 Architecture
Single Clock Cycle Byte Fetch MIPS Throughput Clock Frequency Fully Static Operation: On-chip 2-cycle Hardware Multiplier Internal 4-level Interrupt Priority Nonvolatile Program Memory Bytes In-System Programmable (ISP) Flash Memory Endurance: Minimum 10,000 Write/Erase Cycles Data Retention: Minimum Years Serial Interface Program Downloading 32-byte Fast Page Programming Mode 64-byte User Signature Array 2-level Program Memory Lock Software Security Peripheral Features 16-bit Enhanced Timer/Counters 8-bit Outputs (AT89LP213 only) Enhanced UART with Automatic Address Recognition Framing Error Detection (AT89LP214 only) Enhanced Master/Slave with Double-buffered Send/Receive Programmable Watchdog Timer with Software Reset Analog Comparator with Selectable Interrupt Debouncing General-purpose Interrupt Pins Special Microcontroller Features Two-wire On-chip Debug Interface Brown-out Detection Power-on Reset with Power-off Flag Internal Oscillator Power Idle Power-down Modes Interrupt Recovery from Power-down Mode Packages Programmable Lines Configurable with Quasi-bidirectional, Input, Push-pull Output, Open-drain Modes Tolerant 14-lead TSSOP PDIP Operating Conditions 2.4V 5.5V Voltage Range -40° 85°C Temperature Range
8-bit Microcontroller with Bytes Flash AT89LP213 AT89LP214 Preliminary
Description
AT89LP213/214 low-power, high-performance CMOS 8-bit microcontroller with bytes In-System Programmable Flash memory. device manufactured using Atmel's high-density nonvolatile memory technology compatible with industry-standard MCS-51 instruction set. AT89LP213/214 built around enhanced core that fetch single byte from memory every clock cycle. classic 8051 architecture, each fetch requires clock cycles, forcing instructions execute clock cycles. AT89LP213/214 CPU, instructions need only clock cycles providing times more throughput than standard 8051. Seventy percent instructions need only many clock cycles they
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have bytes execute, most remaining instructions require only additional clock. enhanced core capable MIPS throughput whereas classic 8051 deliver only MIPS same current consumption. Conversely, same throughput classic 8051, core runs much lower speed thereby greatly reduces power consumption. AT89LP213/214 provides following standard features: bytes In-System Programmable Flash memory, bytes RAM, lines, 16-bit timer/counters, outputs (AT89LP213 only), programmable watchdog timer, full duplex serial port (AT89LP214 only), serial peripheral interface, internal oscillator, on-chip crystal oscillator, four-level, six-vector interrupt system. timer/counters AT89LP213/214 enhanced with modes. Mode configured variable 16-bit timer/counter Mode configured 16-bit auto-reload timer/counter. addition, timer/counters AT89LP213 independently drive pulse width modulation output. ports AT89LP213/214 independently configured four operating modes. quasi-bidirectional mode, ports operate classic 8051. input mode, ports tristated. Push-pull output mode provides full CMOS drivers open-drain mode provides just pull-down. addition, pins Port configured generate interrupt using general-purpose interrupt interface. pins AT89LP213/214 tolerate voltages higher than device's power supply, 5.5V. When device supplied 2.4V ports receive 5.5V, total back flowing current I/Os less than
Configuration
AT89LP213: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI5/RST) P1.3 (GPI2) P1.2 (T0) P3.4 (INT0/XTAL1) P3.2
P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) P3.5 (T1) P3.3 (XTAL2/CLKOUT/INT1)
AT89LP214: 14-lead TSSOP/PDIP
(GPI5/MOSI) P1.5 (GPI7/SCK) P1.7 (GPI5/RST) P1.3 (GPI2) P1.2 (RxD) P3.0 (INT0/XTAL1) P3.2
P1.6 (MISO/GPI6) P1.4 (SS/GPI4) P1.1 (AIN1/GPI1) P1.0 (AIN0/GPI0) P3.1 (TxD) P3.3 (XTAL2/CLKOUT/INT1)
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Description
Table 3-1.
AT89LP213 Description
Type Description P1.5: User-configurable Port MOSI: master-out/slave-in. When configured master, this output. When configured slave, this input. GPI5: General-purpose Interrupt input P1.7: User-configurable Port SCK: Clock. When configured master, this output. When configured slave, this input. GPI7: General-purpose Interrupt input P1.3: User-configurable Port Reset Fuse disabled). RST: External Active-Low Reset input Reset Fuse enabled. "External Reset" page 15). GPI3: General-purpose Interrupt input DCL: Serial Clock input On-chip Debug Interface when enabled. Ground P1.2: User-configurable Port GPI2: General-purpose Interrupt input P3.4: User-configurable Port Timer/Counter External Input Output. P3.2: User-configurable Port XTAL1: Input inverting oscillator amplifier internal clock generation circuits. used port internal oscillator selected clock source. DDA: Serial Data input/output On-chip Debug Interface when enabled internal oscillator selected clock source. P3.3: User-configurable Port XTAL2: Output from inverting oscillator amplifier. used port internal oscillator selected clock source. CLKOUT: When internal oscillator selected clock source, used output internal clock divided DDA: Serial Data input/output On-chip Debug Interface when enabled external clock selected clock source. P3.5: User-configurable Port Timer/Counter External input output. Supply Voltage P1.0: User-configurable Port AIN0: Analog Comparator Positive input. GPI0: General-purpose Interrupt input P1.1: User-configurable Port AIN1: Analog Comparator Negative input. GPI1: General-purpose Interrupt input P1.4: User-configurable Port slave select input. GPI4: General-purpose Interrupt input P1.6: User-configurable Port MISO: master-in/slave-out. When configured master, this input. When configured slave, this output. GPI6: General-purpose Interrupt input
Symbol
P1.5
P1.7
P1.3
P1.2 P3.4
P3.2
P3.3
P3.5 P1.0
P1.1
P1.4
P1.6
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Table 3-2.
AT89LP214 Description
Type Description P1.5: User-configurable Port MOSI: master-out/slave-in. When configured master, this output. When configured slave, this input. GPI5: General-purpose Interrupt input P1.7: User-configurable Port SCK: Clock. When configured master, this output. When configured slave, this input. GPI7: General-purpose Interrupt input P1.3: User-configurable Port Reset Fuse disabled). RST: External Active-Low Reset input Reset Fuse enabled. "External Reset" page 15). GPI3: General-purpose Interrupt input DCL: Serial Clock input On-chip Debug Interface. Ground P1.2: User-configurable Port GPI2: General-purpose Interrupt input P3.0: User-configurable Port RXD: Serial Port Receiver input. P3.2: User-configurable Port XTAL1: Input inverting oscillator amplifier internal clock generation circuits. used port internal oscillator selected clock source. DDA: Serial Data input/output On-chip Debug Interface when enabled internal oscillator selected clock source. P3.3: User-configurable Port XTAL2: Output from inverting oscillator amplifier. used port internal oscillator selected clock source. CLKOUT: When internal oscillator selected clock source, used output internal clock divided DDA: Serial Data input/output On-chip Debug Interface when enabled external clock selected clock source.\ P3.1: User-configurable Port TXD: Serial Port Transmitter output. Supply Voltage P1.0: User-configurable Port AIN0: Analog Comparator Positive input. GPI0: General-purpose Interrupt input P1.1: User-configurable Port AIN1: Analog Comparator Negative input. GPI1: General-purpose Interrupt input P1.4: User-configurable Port slave select input. GPI4: General-purpose Interrupt input P1.6: User-configurable Port MISO: master-in/slave-out. When configured master, this input. When configured slave, this output. GPI6: General-purpose Interrupt input
Symbol
P1.5
P1.7
P1.3
P1.2 P3.0
P3.2
P3.3
P3.1 P1.0
P1.1
P1.4
P1.6
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Block Diagram
Figure 4-1. AT89LP213 Block Diagram
Single Cycle 8051
Flash
Timer Timer
Bytes
Analog Comparator
Port Configurable
Watchdog Timer
Port Configurable
On-Chip Oscillator
General-purpose Interrupt
Clock
Configurable Oscillator
Crystal Resonator
Figure 4-2.
AT89LP214 Block Diagram
Single Cycle 8051
UART
Flash
Bytes
Timer Timer
Port Configurable
Analog Comparator
Port Configurable
Watchdog Timer
General-purpose Interrupt
On-Chip Oscillator
Clock
Configurable Oscillator
Crystal Resonator
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Comparison Standard 8051
AT89LP213/214 part family devices with enhanced features that fully binary compatible with MCS-51 instruction set. addition, most addresses, assignments, alternate functions identical Atmel's existing standard 8051 products. However, high performance nature device, some system behaviors different from those Atmel's standard 8051 products such AT89S52 AT89S2051. differences from standard 8051 outlined following paragraphs.
System Clock
clock frequency equals external XTAL1 frequency. oscillator longer divided provide internal clock, mode supported.
Instruction Execution with Single-cycle Fetch
fetches code byte from memory every clock cycle instead every clock cycles. This greatly increases throughput CPU. consequence, longer executes instructions clock cycles. Each instruction executes only clock cycles. "Instruction Summary" page more details.
Interrupt Handling
interrupt controller polls interrupt flags during last clock cycle instruction. order interrupt serviced instruction, flag needs have been latched active during next last clock cycle instruction, last clock cycle previous instruction current instruction executes only single clock cycle. external interrupt pins, INT0 INT1, sampled every clock cycle instead once every clock cycles. Coupled with shorter instruction timing faster interrupt response, this leads higher maximum rate incidence external interrupts.
Timer/Counters
default Timer/Counters incremented rate once clock cycle. This compares once every clocks standard 8051. common prescaler available divide time base timers reduce increment rate. bits CLKREG control prescaler (Table page 13). Setting 1011B will cause timers count once every clocks. external Timer/Counter pins, sampled every clock cycle instead once every clock cycles. This increases maximum rate which Counter modules function.
Serial Port
baud rate UART Mode clock frequency, compared 1/12 clock frequency standard 8051; output data only stable around rising edge serial clock. should also noted that when using Timer generate baud rate Mode Mode timer counts clock frequency 1/12 clock frequency. maintain same baud rate AT89LP214 while running same frequency standard 8051, time-out period must times longer. Mode Timer supports 16-bit auto-reload facilitate longer time-out periods generating baud rates.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Watchdog Timer
Watchdog Timer AT89LP213/214 counts rate once clock cycle. This compares once every clocks standard 8051. common prescaler available divide time base timers reduce counting rate.
Ports
ports AT89LP213/214 configured four different modes. default ports revert input-only (tristated) mode power-up reset. standard 8051, ports weakly pulled high during power-up reset. enable 8051-like ports, ports must into quasi-bidirectional mode clearing P1M0 P3M0 SFRs. user also configure ports start quasi-bidirectional mode disabling Tristate-Port User Fuse. When this fuse disabled, P1M0 P3M0 will reset instead ports will weakly pulled high.
Reset
AT89LP213/214 active-low compared with active high reset standard 8051. addition, sampled every clock cycle must held minimum clock cycles, instead clock cycles, recognized valid reset.
Memory Organization
AT89LP213/214 uses Harvard Architecture with separate address spaces program data memory. program memory regular linear address space with support bytes directly addressable application code. data memory bytes internal bytes Special Function Register space. AT89LP213/214 does support external data memory external program memory.
Program Memory
AT89LP213/214 contains bytes on-chip In-System Programmable Flash memory program storage. Flash memory endurance least 10,000 write/erase cycles minimum data retention time years. reset interrupt vectors located within first bytes program memory (refer Table 12-1 page 19). Constant tables allocated within entire program memory address space access MOVC instruction. AT89LP213/214 does support external program memory. Figure 6-1. Program Memory
007F
User Signature Array
0040 001F
Atmel Signature Array
0000 07FF
Program Memory
0000
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AT89LP213/214 program memory shown Figure 6-1. addition code space from 0000h 07FFh, AT89LP213/214 also supports 64-byte User Signature Array 32-byte Atmel Signature Array that accessible read-only fashion. order read from signature arrays, SIGEN AUXR1 must set. While SIGEN one, MOVC A,@A+DPTR will access signature arrays. User Signature Array mapped addresses 0040h 007Fh Atmel Signature Array mapped addresses 0000h 001Fh. SIGEN must cleared before using MOVC access code memory. Atmel Signature Array initialized with Device factory. User Signature Array available user identification codes constant parameter data. Data stored signature array secure. Security bits will disable writes array; however, reads always allowed. Table 6-1.
AUXR1 Auxiliary Register Reset Value XXXX 0XXXB
AUXR1 Addressable SIGEN
Data Memory
AT89LP213/214 contains bytes general SRAM data memory plus bytes memory mapped into single 8-bit address space. bytes data memory accessed through both direct indirect addressing lower byte addresses. bytes memory reside upper byte address space (Figure 6-2). memory only accessed through direct addressing contains Special Function Registers (SFRs). Indirect accesses upper byte addresses will return invalid data. lowest bytes data memory grouped into banks registers each. bits (PSW.3 PSW.4) select which register bank use. Instructions using register addressing will only access currently specified bank. AT89LP213/214 does support external data memory. Figure 6-2. Data Memory
Accessible Direct Addressing Only Special Function Registers Accessible Direct Indirect Addressing Only
UPPER
Ports Status Control Bits Timers Registers Stack Pointer Accumulator (Etc.)
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Special Function Registers
on-chip memory area called Special Function Register (SFR) space shown Table 7-1. Note that addresses occupied, unoccupied addresses implemented chip. Read accesses these addresses will general return random data, write accesses will have indeterminate effect. User software should write these unlisted locations, since they used future products invoke features. Table 7-1. AT89LP213/214 Reset Values
0F8H 0F0H 0E8H 0E0H 0D8H 0D0H 0C8H P1M0(2) x000 0000 xx11 1111 0000 0000 SADDR 0000 0000 AUXR1 xxxx 0xxx SCON 0000 0000 1111 1111 TCON 0000 0000 SBUF xxxx xxxx TCONB 0010 0100 TMOD 0000 0000 0000 0111 Notes: GPMOD 0000 0000 0000 0000 0000 0000 0000 0000 GPLS 0000 0000 0000 0000 0000 0000 0000 0000 GPIEN 0000 0000 0000 0000 0000 0000 GPIF 0000 0000 0000 0000 0000 0000 ACSR xx00 0000 CLKREG 0000 x000 PCON 0000 0000 WDTRST (write-only) WDTCON 0000 x000 SADEN 0000 0000 x000 0000 P1M1 xx00 0000 P3M0(2) P3M1 xx00 0000 0000 0000 0000 0000 SPSR 000x x000 0000 0000 SPCR 0000 0000 SPDR xxxx xxxx 0FFH 0F7H 0EFH 0E7H 0DFH 0D7H 0CFH 0C7H 0BFH 0B7H 0AFH 0A7H
0C0H 0B8H 0B0H 0A8H 0A0H
SFRs left-most column bit-addressable. Reset value xx11 1111B when Tristate-Port Fuse enabled xx00 0000B when disabled.
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Enhanced
AT89LP213/214 uses enhanced 8051 that runs times speed standard 8051 devices times speed 8051 devices). increase performance factors. First, fetches instruction byte from code memory every clock cycle. Second, uses simple two-stage pipeline fetch execute instructions parallel. This basic pipelining concept allows obtain MIPS MHz. simple example shown Figure 8-1. MCS-51 instruction allows instructions variable length from bytes. single-clock-per-byte-fetch system this means each instruction takes least many clocks bytes execute. majority instructions AT89LP213/214 follow this rule: instruction execution time clock cycles equals number bytes instruction with exceptions. Branches Calls require additional cycle compute target address some other complex instructions require multiple cycles. "Instruction Summary" page more detailed information individual instructions. Figures show examples 2-byte instructions. Figure 8-1. Parallel Instruction Fetches Executions
System Clock
Tn+1
Tn+2
Instruction
Fetch
Execute
(n+1)th Instruction
Fetch
Execute
(n+2)th Instruction
Fetch
Figure 8-2.
Single-cycle Operation (Example:
System Clock Total Execution Time Register Operand Fetch Operation Execute Result Write Back Fetch Next Instruction
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Figure 8-3. Two-cycle Operation (Example: #data)
System Clock Total Execution Time Fetch Immediate Operand Operation Execute Result Write Back Fetch Next Instruction
Restrictions Certain Instructions
AT89LP213/214 economical cost-effective member Atmel's growing family microcontrollers. contains bytes Flash program memory. fully compatible with MCS-51 architecture, programmed using MCS-51 instruction set. However, there considerations must keep mind when utilizing certain instructions program this device. instructions related jumping branching should restricted such that destination address falls within physical program memory space device, which AT89LP213/214. This should responsibility software programmer. example, LJMP 7E0H would valid instruction, whereas LJMP 900H would not.
8.1.1
Branching Instructions LCALL, LJMP, ACALL, AJMP, SJMP, @A+DPTR unconditional branching instructions will execute correctly long programmer keeps mind that destination branching address must fall within physical boundaries program memory size (locations 000H 7FFH AT89LP213/214). Violating physical space limits cause unknown program behavior. With CJNE [.], DJNZ [.], JNB, JNC, JBC, conditional branching instructions, same previous rule applies. Again, violating memory boundaries cause erratic execution. applications involving interrupts normal interrupt service routine address locations 8051 family architecture have been preserved. MOVX-related Instructions, Data Memory AT89LP213/214 contains bytes internal data memory. accesses addresses above will return invalid data. Furthermore, stack depth limited bytes, amount available RAM. Stack Pointer should allowed point locations above 7FH. External DATA memory access supported this device, external PROGRAM memory execution. Therefore, MOVX instructions should included program. typical 8051 assembler will still assemble instructions, even they written violation restrictions mentioned above. responsibility user know physical features limitations device being used adjust instructions used accordingly.
8.1.2
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System Clock
system clock generated directly from three selectable clock sources. three sources on-chip crystal oscillator, external clock source, internal oscillator. clock source selected Clock Source User Fuses shown Table 9-1. internal clock division used generate clock from system clock. "User Configuration Fuses" page Table 9-1. Clock Source Settings
Clock Source Fuse Selected Clock Source Crystal Oscillator Reserved External Clock XTAL1 Internal Oscillator Clock Source Fuse
Crystal Oscillator
When enabled, internal inverting oscillator amplifier connected between XTAL1 XTAL2 connection external quartz crystal ceramic resonator. When using crystal oscillator, P3.2 P3.3 will have their inputs outputs disabled. When using crystal oscillator, XTAL2 should used drive board-level clock without buffer.
External Clock Source
external clock option disables oscillator amplifier allows XTAL1 driven directly clock source. XTAL2 left unconnected, used P3.3 I/O, configured output divided version system clock.
Internal Oscillator
AT89LP213/214 internal oscillator tuned ±2.5%. When enabled clock source, XTAL1 XTAL2 used P3.2 P3.3 respectively. XTAL2 also configured output divided version system clock. frequency oscillator adjusted changing Adjust Fuses. (See "User Configuration Fuses" page 71).
System Clock
When AT89LP213/214 configured either external clock internal oscillator, divided version system clock output XTAL2 (P3.3). Clock feature enabled setting CLKREG. bits determine clock divide ratio. example, setting CDIV "00" when using internal oscillator will result 3.950 (±5%) clock output P3.3. P3.3 must configured output order clock feature.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 9-2.
CLKREG Clock Control Register Reset Value 0000 0000B
CLKREG Addressable TPS3 TPS2 TPS1 TPS0 CDV1
CDV0
Symbol TPS3 TPS2 TPS1 TPS0
Function Timer Prescaler. Timer Prescaler selects time base Timer Timer Watchdog Timer. prescaler implemented 4-bit binary down counter. When counter reaches zero reloaded with value stored bits give division ratio between default timers will count every clock cycles (TPS 0000B). configure timers count standard 8051 rate once every clock cycles, should 1011B. Clock Division. Determines frequency clock output relative system clock. CDIV1 CDIV0 Clock Frequency f/16
CDV1 CDV0
Clock Enable. output divided version system clock XTAL2 (P3.3). internal oscillator external clock source must selected order this feature.
Reset
During reset, Registers their initial values, port pins tristated, program starts execution from Reset Vector, 0000H. AT89LP213/214 five sources reset: power-on reset, brown-out reset, external reset, watchdog reset, software reset.
10.1
Power-on Reset
Power-on Reset (POR) generated on-chip detection circuit. detection level nominally 1.4V. activated whenever below detection level. circuit used trigger start-up reset detect supply voltage failure devices without brown-out detector. circuit ensures that device reset from power-on. power-on sequence shown Figure 10-1 page When reaches Power-on Reset threshold voltage VPOR, initialization sequence lasting tPOR started. When initialization sequence completes, start-up timer determines long device kept after rise. signal activated again, without delay, when falls below threshold level. Power-on Reset (i.e. cold reset) will flag PCON. internally generated reset extended beyond power-on period holding longer than time-out.
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Figure 10-1. Power-on Reset Sequence (BOD Disabled)
TIME-OUT
VPOR tPOR tSUT
VPOR
INTERNAL RESET INTERNAL RESET
(RST Tied VCC)
(RST Controlled Externally)
tRHD
Brown-out Detector (BOD) also enabled, start-up timer does begin counting until after reaches threshold voltage VBOD shown Figure 10-2. However, this event occurs prior initialization sequence, timer must first wait that sequence complete before counting. Figure 10-2. Power-on Reset Sequence (BOD Enabled)
VBOD
TIME-OUT
VPOR tPOR tSUT
INTERNAL RESET INTERNAL RESET
(RST Tied VCC)
(RST Controlled Externally)
tRHD
Note:
tPOR approximately
start-up timer delay user configurable with Start-up Time User Fuses depends clock source (Table 10-1). start-up delay should selected provide enough settling time selected clock source. Start-Up Time fuses also control length start-up time after Brown-out Reset when waking from Power-down during internally timed mode.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 10-1.
Fuse
Start-up Timer Settings
Fuse Crystal Oscillator Internal RC/External Clock 1024 2048 1024 4096 4096 16384 Clock Source Internal RC/External Clock tSUT
Crystal Oscillator Internal RC/External Clock
Crystal Oscillator Internal RC/External Clock
Crystal Oscillator
10.2
Brown-out Reset
AT89LP213/214 on-chip Brown-out Detection (BOD) circuit monitoring level during operation comparing fixed trigger level. trigger level nominally 2.2V. purpose ensure that fails dips while executing speed, system will gracefully enter reset without possibility errors induced incorrect execution. sequence shown Figure 10-3. When decreases value below trigger level VBOD, internal reset immediately activated. When increases above trigger level, start-up timer releases internal reset after specified time-out period expired (Table 10-1). Brown-out Detector must enabled setting Enable Fuse. (See "User Configuration Fuses" page 71). Figure 10-3. Brown-out Detector Reset
TIME-OUT INTERNAL RESET
VPOR
VBOD tSUT
10.3
External Reset
P1.3/RST function either active-LOW reset input digital general purpose I/O, P1.3. Reset Enable Fuse, when "1", enables external reset input function P1.3. (See "User Configuration Fuses" page 71). When cleared, P1.3 used input output pin. When configured reset input, must held least clock cycles trigger internal reset.
Note: During power-up sequence, fuse selection always overridden therefore will always function reset input. external circuit connected this should hold this during power-on sequence this will keep device reset until transitions high. After power-up delay, this input will function either external reset input digital input defined fuse bit. Only power-up reset will temporarily override selection defined reset fuse bit. Other sources reset will override reset fuse bit. P1.3/RST also serves In-System Programming (ISP) enable. enabled when external reset held low. When reset disabled fuse, only entered pulling P1.3 during power-up.
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10.4
Watchdog Reset
When Watchdog times out, will generate internal reset pulse lasting clock cycles. Watchdog reset will also WDTOVF flag WDTCON. prevent Watchdog reset, watchdog reset sequence 1EH/E1H must written WDTRST before Watchdog times out. "Programmable Watchdog Timer" page details operation Watchdog.
10.5
Software Reset
generate internal 16-clock cycle reset pulse writing software reset sequence 5AH/A5H WDRST register. software reset will SWRST WDTCON. "Software Reset" page more information software reset.
Power Saving Modes
AT89LP213/214 supports different power-reducing modes: Idle Power-down. These modes accessed through PCON register.
11.1
Idle Mode
Setting PCON enters idle mode. Idle mode halts internal clock. state preserved entirety, including RAM, stack pointer, program counter, program status word, accumulator. Port pins hold logic states they time that Idle activated. Idle mode leaves peripherals running order allow them wake when interrupt generated. timers, UART, SPI, blocks continue function during Idle. comparator watchdog selectively enabled disabled during Idle. enabled interrupt source reset terminate Idle mode. When exiting Idle mode with interrupt, interrupt will immediately serviced, following RETI next instruction executed will following instruction that device into Idle.
11.2
Power-down Mode
Setting Power-down (PD) PCON enters Power-down mode. Power-down mode stops oscillator powers down Flash memory order minimize power consumption. Only power-on circuitry will continue draw power during Power-down. During Power-down, power supply voltage reduced keep-alive voltage. contents will retained, contents guaranteed once been reduced. Power-down exited external reset, power-on reset, certain interrupts.
11.2.1
Interrupt Recovery from Power-down Three external interrupts configured terminate Power-down mode. XTAL1 XTAL2, when used crystal oscillator external clock, used exit Power-down through external interrupts INT0 (P3.2) INT1 (P3.3). wake external interrupt INT0 INT1, that interrupt must enabled configured level-sensitive operation. General purpose interrupt (GPI3) also wake device when disabled. GPI3 must enabled configured level detection order terminate Power-down. When terminating Power-down interrupt, different wake-up modes available. When PWDEX PCON zero, wake-up period internally timed shown Figure 11-1. falling edge interrupt pin, Power-down exited, oscillator restarted, internal timer begins counting. internal clock will allowed propagate until after timer timed out. After time-out period interrupt service routine will
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
begin. time-out period controlled Start-up Timer Fuses (see Table 10-1 page 15). interrupt need remain entire time-out period. Figure 11-1. Interrupt Recovery from Power-down (PWDEX
XTAL1
tSUT
INT1 INTERNAL CLOCK
When PWDEX "1", wake-up period controlled externally interrupt. Again, falling edge interrupt pin, power-down exited oscillator restarted. However, internal clock will propagate until rising edge interrupt shown Figure 11-2. interrupt should held long enough selected clock source stabilize. After rising edge interrupt service routine will executed. Figure 11-2. Interrupt Recovery from Power-down (PWDEX
XTAL1
INT1 INTERNAL CLOCK
11.2.2 Reset Recovery from Power-down wake-up from Power-down through external reset similar interrupt with PWDEX "0". falling edge RST, Power-down exited, oscillator restarted, internal timer begins counting shown Figure 11-3. internal clock will allowed propagate until after timer timed out. time-out period controlled Start-up Timer Fuses. (See Table 10-1 page 15). returns high before time-out, clock cycle internal reset generated when internal clock restarts. Otherwise device will remain reset until brought high.
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Figure 11-3. Reset Recovery from Power-down.
XTAL1
tSUT
INTERNAL CLOCK INTERNAL RESET
Table 11-1.
PCON Power Control Register Reset Value 000X 0000B
PCON Addressable SMOD1 Symbol SMOD1 SMOD0 PWDEX GF1, Function Double Baud Rate bit. Doubles baud rate UART Modes SMOD0 PWDEX
Frame Error Select. When SMOD0 SCON.7 SM0. When SMOD0 SCON.7 Note that will after frame error regardless state SMOD0. Power-down Exit Mode. When PWDEX wake from Power-down externally controlled. When PWDEX wake from Power-down internally timed. Power Flag. during power (i.e. cold reset). reset under software control affected (i.e. warm resets). General-purpose Flags Power-down bit. Setting this activates power-down operation. Idle Mode bit. Setting this activates Idle mode operation
Interrupts
AT89LP213/214 provides interrupt sources: external interrupts, timer interrupts, serial port interrupt, general-purpose interrupt, analog comparator interrupt. These interrupts system reset each have separate program vector start program memory space. Each interrupt source individually enabled disabled setting clearing interrupt enable register register also contains global disable bit, which disables interrupts. Each interrupt source (except analog comparator) individually programmed four priority levels setting clearing bits interrupt priority registers IPH. analog comparator fixed lowest priority level. interrupt service routine progress interrupted higher priority interrupt, another interrupt same lower priority. highest priority interrupt cannot interrupted other interrupt source. requests different priority levels pending instruction, request higher priority level serviced. requests same priority level pending
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
instruction, internal polling sequence determines which request serviced. polling sequence based vector address; interrupt with lower vector address higher priority than interrupt with higher vector address. Note that polling sequence only used resolve pending requests same priority level. External Interrupts INT0 INT1 each either level-activated edge-activated, depending bits Register TCON. flags that actually generate these interrupts bits TCON. When service routine vectored hardware clears flag that generated external interrupt only interrupt edge-activated. interrupt level activated, then external requesting source (rather than on-chip hardware) controls request flag. Timer Timer Interrupts generated TF1, which rollover their respective Timer/Counter registers (except Timer Mode When timer interrupt generated, on-chip hardware clears flag that generated when service routine vectored Serial Port Interrupt generated logic SCON plus SPIF SPSR. None these flags cleared hardware when service routine vectored fact, service routine normally must determine whether SPIF generated interrupt, must cleared software. logic eight flags GPIF register causes general-purpose interrupt. None these flags cleared hardware when service routine vectored service routine must determine which generated interrupt, must cleared software. interrupt level activated, then external requesting source must de-assert interrupt before flag cleared software. ACSR generates Comparator Interrupt. flag cleared hardware when service routine vectored must cleared software. Most bits that generate interrupts cleared software, with same result though they been cleared hardware. That interrupts generated pending interrupts canceled software. exceptions interrupt flag SPIF general-purpose interrupt flags GPIF. These flags only hardware only cleared software.
Table 12-1.
Interrupt System Reset
Interrupt Vector Addresses
Source SPIF GPIF Vector Address 0000H 0003H 000BH 0013H 001BH 0023H 002BH 0033H
External Interrupt Timer Overflow External Interrupt Timer Overflow Serial Port General-purpose Interrupt Analog Comparator
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12.1
Interrupt Response Time
interrupt flags their hardware clock cycle. interrupt controller polls flags last clock cycle instruction progress. flags preceding cycle, polling cycle will find interrupt system will generate LCALL appropriate service routine next instruction, provided that interrupt blocked following conditions: interrupt equal higher priority level already progress; instruction progress RETI write registers. Either these conditions will block generation LCALL interrupt service routine. second condition ensures that instruction progress RETI access IPH, then least more instruction will executed before interrupt vectored polling cycle repeated last cycle each instruction, values polled values that were present previous clock cycle. active interrupt flag being serviced because above conditions longer active when blocking condition removed, denied interrupt will serviced. other words, fact that interrupt flag once active serviced remembered. Every polling cycle new. request active conditions acknowledged, hardware subroutine call requested service routine will next instruction executed. call itself takes four cycles. Thus, minimum five complete clock cycles elapsed between activation interrupt request beginning execution first instruction service routine. longer response time results request blocked previously listed conditions. interrupt equal higher priority level already progress, additional wait time depends nature other interrupt's service routine. instruction progress final clock cycle, additional wait time cannot more than cycles, since longest only cycles long. instruction progress RETI access additional wait time cannot more than cycles maximum three more cycles complete instruction progress, plus maximum cycles complete next instruction). Thus, single-interrupt system, response time always more than clock cycles less than clock cycles. Figure 12-1 Figure 12-2. Figure 12-1. Minimum Interrupt Response Time
Clock Cycles INT0 Instruction
Ack.
Cur. Instr.
LCALL
Instr.
Figure 12-2. Maximum Interrupt Response Time
Clock Cycles INT0 Instruction RETI
Ack.
Cyc. Instr.
LCALL
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 12-2.
Addressable Symbol
Interrupt Enable Register Reset Value 0000 0000B
Function
Global enable/disable. interrupts disabled when When each interrupt source enabled/disabled setting /clearing enable bit. Comparator Interrupt Enable General-purpose Interrupt Enable Serial Port Interrupt Enable Timer Interrupt Enable External Interrupt Enable Timer Interrupt Enable External Interrupt Enable Interrupt Priority Register Reset Value X000 0000B
Table 12-3.
Addressable
Symbol Function
General-purpose Interrupt Priority Serial Port Interrupt Priority Timer Interrupt Priority External Interrupt Priority Timer Interrupt Priority External Interrupt Priority
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Table 12-4.
Interrupt Priority High Register Reset Value X000 0000B
Addressable
Symbol PT1H PX1H PT0H PX0H Function
PT1H
PX1H
PT0H
PX0H
General-purpose Interrupt Priority High Serial Port Interrupt Priority High Timer Interrupt Priority High External Interrupt Priority High Timer Interrupt Priority High External Interrupt Priority High
Ports
AT89LP213/214 configured between pins. exact number pins available depends clock reset options shown Table 13-1. port pins tolerant, that they pulled driven 5.5V even when operating lower such Table 13-1.
Clock Source External Crystal Resonator external reset External External Clock external reset External Internal Oscillator external reset
Configurations
Reset Option External Number Pins
13.1
Port Configuration
port pins AT89LP213/214 configured four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, input-only. Port modes assigned software pin-by-pin basis shown Table 13-2. Tristate-Port User Fuse determines default state port pins. When fuse enabled, port pins default input-only mode after reset. When fuse disabled, port pins, with exception P1.0 P1.1, default quasi-bidirectional mode after reset weakly pulled high. Each port also Schmitt-triggered input improved input noise rejection. During Power-down Schmitt-triggered inputs disabled with exception P1.3, P3.2 P3.3, which used wake device. Therefore P1.3, P3.2 P3.3 should left floating during Power-down
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 13-2.
PxM0.y
Configuration Modes Port
PxM1.y Port Mode Quasi-bidirectional Push-pull Output Input Only (High Impedance) Open-drain Output
13.1.1
Quasi-bidirectional Output Port pins quasi-bidirectional output mode function similar standard 8051 port pins. Quasibidirectional port used both input output without need reconfigure port. This possible because when port outputs logic high, weakly driven, allowing external device pull low. When driven low, driven strongly able sink large current. There three pull-up transistors quasi-bidirectional output that serve different purposes. these pull-ups, called "very weak" pull-up, turned whenever port latch contains logic "1". This very weak pull-up sources very small current that will pull high left floating. second pull-up, called "weak" pull-up, turned when port latch contains logic itself also logic level. This pull-up provides primary source current quasi-bidirectional that outputting "1". this pulled external device, this weak pull-up turns off, only very weak pull-up remains order pull under these conditions, external device sink enough current overpower weak pull-up pull port below input threshold voltage. third pull-up referred "strong" pull-up. This pull-up used speed low-tohigh transitions quasi-bidirectional port when port latch changes from logic logic "1". When this occurs, strong pull-up turns clocks quickly pulling port high. quasi-bidirectional port configuration shown Figure 13-1. input circuitry P1.3, P3.2 P3.3 disabled during Power-down (see Figure 13-3). Figure 13-1. Quasi-bidirectional Output
Clock Delay Flip-Flop)
Strong
Very Weak
Weak Port
From Port Register Input Data
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13.1.2
Input-only Mode input only port configuration shown Figure 13-2. output drivers tristated. input includes Schmitt-triggered input improved input noise rejection. input circuitry P1.3, P3.2 P3.3 disabled during Power-down (see Figure 13-3). Input pins safely driven 5.5V even when operating lower levels; however, input threshold Schmitt trigger will level must taken into consideration. Figure 13-2. Input Only
Input Data
Figure 13-3. Input Only P1.3, P3.2 P3.3
Port
Input Data
13.1.3
Port
Open-drain Output open-drain output configuration turns pull-ups only drives pull-down transistor port when port latch contains logic "0". used logic output, port configured this manner must have external pull-up, typically resistor tied VCC. pulldown this mode same quasi-bidirectional mode. open-drain port configuration shown Figure 13-4.The input circuitry P1.3, P3.2 P3.3 disabled during Power-down (see Figure 13-3). Open-drain pins safely pulled high 5.5V even when operating lower levels; however, input threshold Schmitt trigger will level must taken into consideration. Figure 13-4. Open-drain Output
Port
From Port Register Input Data
13.1.4 Push-pull Output push-pull output configuration same pull-down structure both open-drain quasi-bidirectional output modes, provides continuous strong pull-up when port latch contains logic "1". push-pull mode used when more source current needed from port output. push-pull port configuration shown Figure 13-5. input circuitry P1.3, P3.2 P3.3 disabled during Power-down (see Figure 13-3).
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Figure 13-5. Push-pull Output
Port
From Port Register Input Data
13.2
Port Analog Functions
AT89LP213/214 incorporates analog comparator. order give best analog performance minimize power consumption, pins that being used analog functions must have both their digital outputs digital inputs disabled. Digital outputs disabled putting port pins into input-only mode described "Port Configuration" page Digital inputs P1.0 P1.1 disabled whenever Analog Comparator enabled setting ACSR. forces input P1.0 P1.1 low, thereby disabling Schmitt trigger circuitry. P1.0 P1.1 will always default input-only mode after reset regardless state Tristate-Port Fuse.
13.3
Port Read-modify-write
read from port will read either state pins state port register depending which instruction used. Simple read instructions will always access port pins directly. Read-modify-write instructions, which read value, possibly modify then write back, will always access port register. This includes write instructions such SETB they actually read entire port, modify single bit, then write data back entire port. Table 13-3 complete list Read-modify-write instruction which access ports. Table 13-3.
Mnemonic DJNZ PX.Y, PX.Y SETB PX.Y
Port Read-modify-write Instructions
Instruction Logical Logical Logical EX-OR Jump clear Complement Increment Decrement Decrement jump zero Move carry Port Clear Port Port Example P3.0, LABEL P3.1 DJNZ LABEL P1.0, P1.1 SETB P3.2
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13.4
Port Alternate Functions
Most general-purpose digital pins AT89LP213/214 share functionality with various I/Os needed peripheral units. Table 13-5 lists alternate functions port pins. Alternate functions connected pins logic fashion. order enable alternate function port pin, that must have corresponding port register bit, otherwise input/output will always "0". Furthermore, each must configured correct input/output mode required peripheral before used such. Table 13-4 shows configure generic with alternate function. Table 13-4.
PxM0.y
Alternate Function Configurations Port
PxM1.y Px.y Mode bidirectional (internal pull-up) output input bidirectional (external pull-up)
Table 13-5.
Port Alternate Functions
Configuration Bits Alternate Function AIN0 GPI0 AIN1 GPI1 GPI2 GPI3 GPI4 MOSI GPI5 MISO GPI6 GPI7 INT0 INT1 CLKOUT CMPOUT AT89LP214 Only Internal Oscillator Only Internal Oscillator External Clock Source Only AT89LP213 Only tied comparator output must disabled input-only
Port P1.0
PxM0.y P1M0.0
PxM1.y P1M1.0
Notes input-only
P1.1 P1.2 P1.3 P1.4
P1M0.1 P1M0.2 P1M0.3 P1M0.4
P1M1.1 P1M1.2 P1M1.3 P1M1.4
P1.5
P1M0.5
P1M1.5
P1.6
P1M0.6
P1M1.6
P1.7 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6
P1M0.7 P3M0.0 P3M0.1 P3M0.2 P3M0.3 P3M0.4 P3M0.5
P1M1.7 P3M1.0 P3M1.1 P3M1.2 P3M1.3 P3M1.4 P3M1.5
configurable
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Enhanced Timer/Counters
AT89LP213/214 16-bit Timer/Counter registers: Timer Timer Timer, register increase every clock cycle default. Thus, register counts clock cycles. Since clock cycle consists oscillator period, count rate equal oscillator frequency. timer rate prescaled value between using Timer Prescaler (see Table page 13). Both Timers share same prescaler. Counter, register incremented response l-to-0 transition corresponding input pin, external input sampled every clock cycle. When samples show high cycle next cycle, count incremented. count value appears register during cycle following which transition detected. Since clock cycles required recognize l-to-0 transition, maximum count rate oscillator frequency. There restrictions duty cycle input signal, should held least full clock cycle ensure that given level sampled least once before changes. AT89LP214, inputs available pins. However, inputs exercised software toggling P3.4 P3.5 bits Port register. Furthermore, Timer Counter functions Timer Timer have four operating modes: variable width timer, 16-bit auto-reload timer, 8-bit auto-reload timer, split timer. control bits Special Function Register TMOD select Timer Counter function. pairs (M1, TMOD select operating modes.
14.1
Mode Variable Width Timer/Counter
Both Timers Mode 8-bit Counters with variable prescaler. prescaler vary from bits depending bits TCONB, giving timer range bits. default timer configured 13-bit timer compatible Mode standard 8051. Figure 14-1 shows Mode operation applies Timer 13-bit mode. count rolls over from "1"s "0"s, sets Timer interrupt flag TF1. counter input enabled Timer when either GATE INT1 Setting GATE allows Timer controlled external input INT1, facilitate pulse width measurements. control Special Function Register TCON. GATE TMOD. 13-bit register consists bits lower bits TL1. upper bits indeterminate should ignored. Setting flag (TR1) does clear registers. Mode Time-out Period Oscillator Frequency
Note:
RH1/RL1 required Timer during Mode used temporary storage registers.
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Figure 14-1. Timer/Counter Mode Variable Width Counter
÷TPS
Bits)
Control PSC1
GATE Bits)
Interrupt
INT1
Mode operation same Timer Timer except that TR0, INT0 replace corresponding Timer signals Figure 14-1. There different GATE bits, Timer (TMOD.7) Timer (TMOD.3). INT0 INT1 pins shared with XTAL oscillator. They only used GATE function when using internal oscillator system clock.
14.2
Mode 16-bit Auto-Reload Timer/Counter
Mode Timers configured 16-bit auto-reload. Timer register with bits. 16-bit reload value stored high reload registers (RH1/RL1). clock applied combined high timer registers (TH1/TL1). clock pulses received, timer counts 0000H, 0001H, 0002H, etc. overflow occurs FFFFH-to0000H transition, upon which timer register reloaded with value from RH1/RL1 overflow flag TCON set. Figure 14-2. reload registers default 0000H, which gives full 16-bit timer period compatible with standard 8051. Mode operation same Timer/Counter Mode 65536 Time-out Period Oscillator Frequency
Figure 14-2. Timer/Counter Mode 16-bit Auto-reload
Bits)
÷TPS Reload
Bits)
Bits)
Bits)
Interrupt
Control
GATE
INT1
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
14.3 Mode 8-bit Auto-reload Timer/Counter
Mode configures Timer register 8-bit Counter (TL1) with automatic reload, shown Figure 14-3. Overflow from only sets TF1, also reloads with contents TH1, which preset software. reload leaves unchanged. Mode operation same Timer/Counter Mode Time-out Period Oscillator Frequency
Figure 14-3. Timer/Counter Mode 8-bit Auto-reload
÷TPS
Bits) Interrupt
GATE
Control
Reload Bits)
INT0
Note:
RH1/RL1 required Timer during Mode used temporary storage registers.
14.4
Mode 8-bit Split Timer
Timer Mode simply holds count. effect same setting Timer Mode establishes separate counters. logic Mode Timer shown Figure 14-4. uses Timer control bits: C/T, GATE, TR0, INT0, TF0. locked into timer function (counting machine cycles) takes over from Timer Thus, controls Timer interrupt. While Timer Mode Timer will still obey settings TMOD cannot generate interrupt. Mode applications requiring extra 8-bit timer counter. With Timer Mode AT89LP213/214 appear have three Timer/Counters. When Timer Mode Timer turned switching into Mode this case, Timer still used serial port baud rate generator application requiring interrupt. Figure 14-4. Timer/Counter Mode 8-bit Counters
÷TPS
Control
Bits)
Interrupt
GATE INT0
÷TPS Control
Bits)
Interrupt
Note:
RH0/RL0 required Timer during Mode used temporary storage registers.
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Table 14-1.
TCON Timer/Counter Control Register Reset Value 0000 0000B
TCON Addressable Symbol Function
Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine. Timer control bit. Set/cleared software turn Timer/Counter on/off. Timer overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine. Timer control bit. Set/cleared software turn Timer/Counter on/off. Interrupt edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt type control bit. Set/cleared software specify falling edge/low level triggered external interrupts. Interrupt edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt type control bit. Set/cleared software specify falling edge/low level triggered external interrupts.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 14-2. TMOD: Timer/Counter Mode Control Register
Reset Value 0000 0000B
TMOD Addressable
GATE Timer1 Gate Gating control when set. Timer/Counter enabled only while INTx high control set. When cleared, Timer enabled whenever control set. Timer Counter Selector cleared Timer operation (input from internal system clock). Counter operation (input from input pin). Timer Mode Timer Mode GATE
Timer0
Timer gate
Timer counter/timer select
Timer Timer
Mode
Operating Mode Variable 16-bit Timer mode. 8-bit Timer/Counter with 8-bit prescaler. 16-bit auto-reload mode. 16-bit Timer/Counters cascaded; there prescaler. 8-bit auto reload. 8-bit auto-reload Timer/Counter holds value which reloaded into each time overflows. Split Timer mode. (Timer 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only controlled Timer control bits. (Timer Timer/Counter stopped.
Timer TCON TMOD TCONB
Purpose Control Mode Timer low-byte Timer low-byte Timer high-byte Timer high-byte Mode Timer reload low-byte Timer reload low-byte Timer reload high-byte Timer reload high-byte
Address
Bit-Addressable
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Table 14-3.
TCONB Timer/Counter Control Register Reset Value 0010 0100B
TCONB Addressable PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02
PSC01
PSC00
Symbol PWM1EN PWM0EN PSC12 PSC11 PSC10 PSC02 PSC01 PSC00
Function Configures Timer Pulse Width Modulation output (P3.5). Configures Timer Pulse Width Modulation output (P3.4). Prescaler Timer Mode number active bits equals PSC1 After reset PSC1 100B which enables bits compatibility with 13-bit Mode AT89S2051. Prescaler Timer Mode number active bits equals PSC0 After reset PSC0 100B which enables bits compatibility with 13-bit Mode AT89C52.
14.5
Pulse Width Modulation
AT89LP213, Timer Timer independently configured 8-bit asymmetrical (edge-aligned) pulse width modulators (PWM) setting PWM0EN PWM1EN bits TCONB, respectively. Mode generated waveform output timer's input pin, Therefore, must when mode. (P3.4) (P3.5) must configured output mode. Timer Overflow Flags Interrupts will continue function while Mode Timer still generate baud rate UART. Each channel four modes selected mode bits TMOD. example waveform Timer Mode shown Figure 14-5. acts 8-bit counter while stores 8-bit compare value. When output high. When count reaches value stored output low. Therefore, pulse width proportional value RH0. prevent glitches, writes only take effect overflow TH0. Setting will keep output low. Figure 14-5. Asymmetrical Pulse Width Modulation
Counter Value (TH0)
Compare Value (RH0)
Output (T0)
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
14.5.1 Mode 8-bit with 8-bit Logarithmic Prescaler Mode acts logarithmic prescaler driving 8-bit counter (see Figure 14-6). PSCx bits TCONB control prescaler value. overflow, duty cycle value transferred OCRx output high. When count matches OCRx, output cleared low. following formulas give output frequency duty cycle Timer Mode Timer Mode identical Timer
Mode
Oscillator Frequency -PSC Duty Cycle -256
Mode
Figure 14-6. Timer/Counter Mode
Bits)
÷TPS Control
Bits)
OCR1
PSC1
GATE Bits)
INT1
14.5.2
Mode 8-bit with 8-bit Linear Prescaler Mode provides linear prescaling with 8-bit auto-reload from (see Figure 14-7). overflow, loaded with value RLx. acts 8-bit counter. overflow, duty cycle value transferred OCRx output high. When count matches OCRx, output cleared low. following formulas give output frequency duty cycle Timer Mode Timer Mode identical Timer
Mode
Oscillator Frequency -256
Mode
Duty Cycle -256
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Figure 14-7. Timer/Counter Mode
Bits)
Bits)
OCR1
÷TPS Control
Bits)
Bits)
GATE
INT1
14.5.3
Mode 8-bit Frequency Generator Timer Mode functions 8-bit auto-reload timer, same normal Mode with exception that output toggled every overflow (see Figure 14-8). Timer Mode identical Timer Mode used output square wave varying frequency. acts 8-bit counter. following formula gives output frequency Timer Mode Mode Oscillator Frequency
Figure 14-8. Timer/Counter Mode
Bits)
÷TPS Control
Bits)
GATE
INT1
Note:
{RH0 RL0}/{RH1 RL1} required Timer 0/Timer during Mode used temporary storage registers.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
14.5.4 Mode Split 8-bit Timer Mode simply holds count. effect same setting Timer Mode establishes separate counters manner similar normal Mode Mode Timer shown Figure 14-9. Only Timer Prescaler available change output frequency during Mode Timer control bits: GATE, TR0, INT0, PWM0EN TF0. locked into timer function uses TR1, PWM1EN TF1. provides duty cycle provides duty cycle TH0. Mode applications requiring single channel timers, channels extra timer counter. With Timer Mode AT89LP213 appear have three Timer/Counters. When Timer Mode Timer turned switching into Mode this case, Timer still used serial port baud rate generator application requiring interrupt. following formulas give output frequency duty cycle Timer Mode Mode Oscillator Frequency -256
Mode
Duty Cycle -256 Duty Cycle -256
Mode
Figure 14-9. Timer/Counter Mode
Bits)
OCR0
÷TPS Control
Bits)
GATE
Bits)
OCR1 INT1
÷TPS
Bits)
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External Interrupts
When AT89LP213/214 configured internal Oscillator, XTAL1 XTAL2 used INT0 INT1 external interrupt sources. external interrupts programmed level-activated transition-activated setting clearing Register TCON. external interrupt triggered detected INTx pin. external interrupt edge-triggered. this mode successive samples INTx show high cycle next cycle, interrupt request flag TCON set. Flag then requests interrupt. Since external interrupt pins sampled once each clock cycle, input high should hold least oscillator periods ensure sampling. external interrupt transition-activated, external source hold request high least clock cycles, then hold least clock cycles ensure that transition seen that interrupt request flag will set. will automatically cleared when service routine called generated edge-triggered mode. external interrupt level-activated, external source hold request active until requested interrupt actually generated. Then external source must deactivate request before interrupt service routine completed, else another interrupt will generated.
General-purpose Interrupts
General-purpose Interrupt (GPI) function provides configurable external interrupts Port Each port detect high/low levels positive/negative edges. GPIEN register select which bits Port enabled generate interrupt. GPMOD GPLS registers determine mode each individual pin. GPMOD selects between level-sensitive edge-triggered mode. GPLS selects between high/low level mode positive/negative edge mode. pins Port sampled every clock cycle. level-sensitive mode, valid level must appear successive samples before generating interrupt. edge-triggered mode, transition will detected value changes from sample next. When interrupt condition detected, that enabled, appropriate flag GPIF register set. flags GPIF must cleared software.
Table 16-1.
GPMOD General-purpose Interrupt Mode Register Reset Value 0000 0000B
GPMOD Addressable GPMOD7 GPMOD6 GPMOD5 GPMOD4 GPMOD3 GPMOD2
GPMOD1
GPMOD0
GPMOD.x
level-sensitive interrupt P1.x edge-triggered interrupt P1.x
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Table 16-2.
GPLS General-purpose Interrupt Level Select Register Reset Value 0000 0000B
GPLS Addressable GPLS7 GPLS6 GPLS5 GPLS4 GPLS3 GPLS2
GPLS1
GPLS0
GPMOD.x
detect level negative edge P1.x detect high level positive edge P1.x
Table 16-3.
GPIEN General-purpose Interrupt Enable Register Reset Value 0000 0000B
GPIEN Addressable GPIEN7 GPIEN6 GPIEN5 GPIEN4 GPIEN3 GPIEN2
GPIEN1
GPIEN0
GPIEN.x
interrupt P1.x disabled interrupt P1.x enabled
Table 16-4.
GPIF General-purpose Interrupt Flag Register Reset Value 0000 0000B
GPIF Addressable GPIF7 GPIF6 GPIF5 GPIF4 GPIF3 GPIF2
GPIF1
GPIF0
GPIF.x
interrupt P1.x inactive interrupt P1.x active. Must cleared software.
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Serial Interface
serial interface AT89LP214 implements Universal Asynchronous Receiver/Transmitter (UART). UART following features: Full Duplex Operation Data Bits Framing Error Detection Multiprocessor Communication Mode with Automatic Address Recognition Baud Rate Generator Using Timer Interrupt Receive Buffer Full Transmission Complete serial interface full duplex, which means transmit receive simultaneously. also receive-buffered, which means begin receiving second byte before previously received byte been read from receive register. (However, first byte still been read when reception second byte complete, bytes will lost.) serial port receive transmit registers both accessed Special Function Register SBUF. Writing SBUF loads transmit register, reading SBUF accesses physically separate receive register. serial port operate following four modes. Mode Serial data enters exits through RXD. outputs shift clock. Eight data bits transmitted/received, with first. baud rate fixed oscillator frequency. Mode bits transmitted (through TXD) received (through RXD): start (0), data bits (LSB first), stop (1). receive, stop goes into Special Function Register SCON. baud rate variable based Timer Mode bits transmitted (through TXD) received (through RXD): start (0), data bits (LSB first), programmable data bit, stop (1). transmit, data (TB8 SCON) assigned value "1". example, parity PSW) moved into TB8. receive, data goes into Special Function Register SCON, while stop ignored. baud rate programmable either 1/16 1/32 oscillator frequency. Mode bits transmitted (through TXD) received (through RXD): start (0), data bits (LSB first), programmable data bit, stop (1). fact, Mode same Mode respects except baud rate, which variable based Timer Mode four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated Mode condition Reception initiated other modes incoming start
17.1
Multiprocessor Communications
Modes have special provision multiprocessor communications. these modes, data bits received, followed stop bit. goes into RB8. Then comes stop bit. port programmed such that when stop received, serial port interrupt activated only This feature enabled setting SCON. following example shows serial interrupt multiprocessor communications. When master processor must transmit block data several slaves, first sends address byte that identifies target slave. address byte differs from data byte that address byte data byte. With slave interrupted data byte. address byte, however, interrupts slaves. Each slave examine received byte being addressed. addressed slave clears
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
prepares receive data bytes that follows. slaves that addressed their bits ignore data bytes. effect Mode used check validity stop Mode Mode reception, receive interrupt activated unless valid stop received. Table 17-1. SCON Serial Port Control Register
Reset Value 0000 0000B
SCON Address Addressable SM0/FE (SMOD0 0/1) Symbol
Function Framing error bit. This receiver when invalid stop detected. cleared valid frames must cleared software. SMOD0 must enable access bit. will regardless state SMOD0. Serial Port Mode (SMOD0 must access SM0) Serial Port Mode
Mode Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate(2) fosc/2 variable (Timer fosc/32 fosc/16 variable (Timer
Enables Automatic Address Recognition feature Modes then will unless received data (RB8) indicating address, received byte Given Broadcast Address. Mode then will activated unless valid stop received, received byte Given Broadcast Address. Mode should Enables serial reception. software enable reception. Clear software disable reception. data that will transmitted Modes clear software desired. Modes data that received. Mode stop that received. Mode used. Transmit interrupt flag. hardware time Mode beginning stop other modes, serial transmission. Must cleared software. Receive interrupt flag. hardware time Mode halfway through stop time other modes, serial reception (except SM2). Must cleared software. SMOD0 located PCON.6. fosc oscillator frequency.
Notes:
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17.2
Baud Rates
baud rate Mode fixed shown following equation: Oscillator Frequency Mode Baud Rate baud rate Mode depends value SMOD1 Special Function Register PCON.7. SMOD1 (the value reset), baud rate 1/32 oscillator frequency. SMOD1 baud rate 1/16 oscillator frequency, shown following equation: Mode Baud Rate (Oscillator Frequency)
SMOD1
17.2.1
Using Timer Generate Baud Rates Timer overflow rate determines baud rates Modes When Timer baud rate generator, baud rates determined Timer overflow rate value SMOD1 according following equation: Modes (Timer Overflow Rate) Baud Rate
SMOD1
Timer interrupt should disabled this application. Timer itself configured either timer counter operation running modes. most typical applications, configured timer operation auto-reload mode (high nibble TMOD 0010B). this case, baud rate given following formula: Modes Oscillator Frequency Baud Rate
SMOD1
Programmers achieve very baud rates with Timer configuring Timer 16-bit auto-reload timer (high nibble TMOD 0001B). this case, baud rate given following formula. Modes Oscillator Frequency H1,RL1 Baud Rate
SMOD1
Table 17-2 lists commonly used baud rates they obtained from Timer Table 17-2.
Baud Rate Mode Mode 375K 62.5K 19.2K 9.6K 4.8K 2.4K 1.2K 137.5
Commonly Used Baud Rates Generated Timer (TPS 0000B)
Timer fOSC (MHz) 11.059 11.059 11.059 11.059 11.059 11.986 SMOD1 Mode Reload Value FEE0H F55CH F958H F304H
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AT89LP213/214 [Preliminary]
17.3 More About Mode
Serial data enters exits through RXD. outputs shift clock. Eight data bits transmitted/received, with first. baud rate fixed oscillator frequency. Figure 17-1 page shows simplified functional diagram serial port Mode associated timing. Transmission initiated instruction that uses SBUF destination register. "write SBUF" signal also loads into position transmit shift register tells Control Block begin transmission. internal timing such that full machine cycle will elapse between "write SBUF" activation SEND. SEND transfers output shift register alternate output function line P3.0, also transfers Shift Clock alternate output function line P3.1. falling edge Shift Clock contents transmit shift register shifted position right. data bits shift right, "0"s come from left. When data byte output position shift register, that initially loaded into position just left MSB, positions left that contain "0"s. This condition flags Control block last shift, then deactivate SEND Reception initiated condition next clock cycle, Control unit writes bits 11111110 receive shift register activates RECEIVE next clock phase. RECEIVE enables Shift Clock alternate output function line P3.1. falling edge Shift Clock contents receive shift register shifted position left. value that comes from right value that sampled P3.0 rising edge Shift Clock. data bits come from right, "1"s shift left. When that initially loaded into right-most position arrives left-most position shift register, flags Control block last shift load SBUF. Then RECEIVE cleared set.
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Figure 17-1. Serial Port Mode
INTERNAL
fosc
INTERNAL
WRITE SBUF SEND SHIFT (DATA OUT) (SHIFT CLOCK)
WRITE SCON (CLEAR RECEIVE SHIFT (DATA (SHIFT CLOCK)
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
17.4 More About Mode
bits transmitted (through TXD), received (through RXD): start (0), data bits (LSB first), stop (1). receive, stop goes into SCON. AT89LP214, baud rate determined Timer overflow rate. Figure 17-2 shows simplified functional diagram serial port Mode associated timings transmit receive. Transmission initiated instruction that uses SBUF destination register. "write SBUF" signal also loads into position transmit shift register flags Control unit that transmission requested. Transmission actually commences S1P1 machine cycle following next rollover divide-by-16 counter. Thus, times synchronized divide-by-16 counter, "write SBUF" signal. transmission begins when SEND activated, which puts start TXD. time later, DATA activated, which enables output transmit shift register TXD. first shift pulse occurs time after that. data bits shift right, "0"s clocked from left. When data byte output position shift register, that initially loaded into position just left MSB, positions left that contain "0"s. This condition flags Control unit last shift, then deactivate SEND This occurs tenth divide-by-16 rollover after "write SBUF." Reception initiated 1-to-0 transition detected RXD. this purpose, sampled rate times established baud rate. When transition detected, divide-by-16 counter immediately reset, 1FFH written into input shift register. Resetting divide-by-16 counter aligns roll-overs with boundaries incoming times. states counter divide each time into 16ths. 7th, 8th, counter states each time, detector samples value RXD. value accepted value that seen least samples. This done reject noise. order reject false bits, value accepted during first time receive circuits reset unit continues looking another l-to-0 transition. start valid, shifted into input shift register, reception rest frame proceeds. data bits come from right, "1"s shift left. When start arrives leftmost position shift register, (which 9-bit register Mode flags Control block last shift, load SBUF RB8, signal load SBUF generated only following conditions time final shift pulse generated. Either received stop either these conditions met, received frame irretrievably lost. both conditions met, stop goes into RB8, data bits into SBUF, activated. this time, whether above conditions met, unit continues looking 1-to-0 transition RXD.
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Figure 17-2. Serial Port Mode
TIMER OVERFLOW
INTERNAL
SMOD1 SMOD1
WRITE SBUF
SBUF ZERO DETECTOR
START
SHIFT DATA CONTROL
SEND
SERIAL PORT INTERRUPT
CLOCK
SAMPLE 1-TO-0 TRANSITION DETECTOR CLOCK START CONTROL LOAD SBUF SHIFT 1FFH
DETECTOR INPUT SHIFT REG. BITS) LOAD SBUF SHIFT
SBUF
READ SBUF
INTERNAL
CLOCK WRITE SBUF SEND DATA SHIFT
START
CLOCK
STOP
RESET
RECEIVE
START
STOP
DETECTOR SAMPLE TIMES
SHIFT
AT89LP213/214 [Preliminary]
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TRANSMIT
AT89LP213/214 [Preliminary]
17.5 More About Modes
Eleven bits transmitted (through TXD), received (through RXD): start (0), data bits (LSB first), programmable data bit, stop (1). transmit, data (TB8) assigned value "1". receive, data goes into SCON. baud rate programmable either 1/16 1/32 oscillator frequency Mode Mode have variable baud rate generated from Timer Figures 17-3 17-4 show functional diagram serial port Modes receive portion exactly same Mode transmit portion differs from Mode only transmit shift register. Transmission initiated instruction that uses SBUF destination register. "write SBUF" signal also loads into position transmit shift register flags Control unit that transmission requested. Transmission commences S1P1 machine cycle following next rollover divide-by-16 counter. Thus, times synchronized divide-by-16 counter, "write SBUF" signal. transmission begins when SEND activated, which puts start TXD. time later, DATA activated, which enables output transmit shift register TXD. first shift pulse occurs time after that. first shift clocks (the stop bit) into position shift register. Thereafter, only "0"s clocked Thus, data bits shift right, "0"s clocked from left. When output position shift register, then stop just left TB8, positions left that contain "0"s. This condition flags Control unit last shift, then deactivate SEND This occurs 11th divide-by-16 rollover after "write SBUF." Reception initiated 1-to-0 transition detected RXD. this purpose, sampled rate times established baud rate. When transition detected, divide-by-16 counter immediately reset, 1FFH written input shift register. 7th, counter states each time, detector samples value RXD. value accepted value that seen least samples. value accepted during first time receive circuits reset unit continues looking another l-to-0 transition. start proves valid, shifted into input shift register, reception rest frame proceeds. data bits come from right, "1"s shift left. When start arrives leftmost position shift register (which Modes 9-bit register), flags Control block last shift, load SBUF RB8, signal load SBUF generated only following conditions time final shift pulse generated: Either received data either these conditions met, received frame irretrievably lost, set. both conditions met, received data goes into RB8, first data bits into SBUF. time later, whether above conditions were not, unit continues looking 1-to-0 transition input. Note that value received stop irrelevant SBUF, RB8,
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Figure 17-3. Serial Port Mode
INTERNAL
CLOCK
SMOD1
SMOD1
INTERNAL
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Figure 17-4. Serial Port Mode
TIMER OVERFLOW
INTERNAL
SMOD1 SMOD1
WRITE SBUF
SBUF ZERO DETECTOR
SERIAL PORT INTERRUPT
SHIFT DATA START STOP CONTROL CLOCK SEND
SAMPLE 1-TO-0 TRANSITION DETECTOR CLOCK START CONTROL LOAD SBUF SHIFT 1FFH
DETECTOR INPUT SHIFT REG. BITS) LOAD SBUF SHIFT
SBUF
READ SBUF
CLOCK WRITE SBUF SEND DATA SHIFT
INTERNAL
START
STOP
STOP
CLOCK RECEIVE RESET
START
DETECTOR SAMPLE TIMES SHIFT
STOP
TRANSMIT
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17.6
Framing Error Detection
addition usual modes, UART perform framing error detection looking missing stop bits, automatic address recognition. When used framing error detect, UART looks missing stop bits communication. missing will SCON register. shares SCON.7 with function SCON.7 determined PCON.6 (SMOD0). SMOD0 then SCON.7 functions SCON.7 functions when SMOD0 cleared. When used SCON.7 only cleared software.
17.7
Automatic Address Recognition
Automatic Address Recognition feature which allows UART recognize certain addresses serial stream using hardware make comparisons. This feature saves great deal software overhead eliminating need software examine every serial address which passes serial port. This feature enabled setting SCON. UART modes, Mode Mode Receive Interrupt flag (RI) will automatically when received byte contains either "Given" address "Broadcast" address. mode requires that information indicate that received information address data. mode called Mode this mode flag will enabled information received valid stop following address bits information either Given Broadcast address. Mode Shift Register mode ignored. Using Automatic Address Recognition feature allows master selectively communicate with more slaves invoking given slave address addresses. slaves contacted using Broadcast address. special Function Registers used define slave's address, SADDR, address mask, SADEN. SADEN used define which bits SADDR used which bits "don't care". SADEN mask logically ANDed with SADDR create "Given" address which master will addressing each slaves. Given address allows multiple slaves recognized while excluding others. following examples show versatility this scheme: Slave SADDR 1100 0000 SADEN 1111 1101 Given 1100 00X0
Slave
SADDR 1100 0000 SADEN 1111 1110 Given 1100 000X
previous example, SADDR same SADEN data used differentiate between slaves. Slave requires ignores Slave requires ignored. unique address slave would 1100 0010 since slave requires unique address slave would 1100 0001 since will exclude slave Both slaves selected same time address which (for slave (for slave Thus, both could addressed with 1100 0000.
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AT89LP213/214 [Preliminary]
more complex system, following could used select slaves while excluding slave Slave SADDR 1100 0000 SADEN 1111 1001 Given 1100 0XX0
Slave
SADDR 1110 0000 SADEN 1111 1010 Given 1110 0X0X
Slave
SADDR 1110 0000 SADEN 1111 1100 Given 1110 00XX
above example, differentiation among slaves lower address bits. Slave requires that uniquely addressed 1110 0110. Slave requires that uniquely addressed 1110 0101. Slave requires that unique address 1110 0011. select Slaves exclude Slave address 1110 0100, since necessary make exclude slave Broadcast Address each slave created taking logic SADDR SADEN. Zeros this result trended don't cares. most cases, interpreting don't cares ones, broadcast address will hexadecimal. Upon reset SADDR (SFR address 0A9H) SADEN (SFR address 0B9H) loaded with "0"s. This produces given address "don't cares" well Broadcast address "don't cares". This effectively disables Automatic Addressing mode allows microcontroller standard 80C51-type UART drivers which make this feature.
Serial Peripheral Interface
serial peripheral interface (SPI) allows high-speed synchronous data transfer between AT89LP213/214 peripheral devices between multiple AT89LP213/214 devices. features include following: Full-duplex, 3-wire Synchronous Data Transfer Master Slave Operation Maximum Frequency fOSC/4 First First Data Transfer Four Programmable Rates Master Mode Transmission Interrupt Flag Write Collision Flag Protection Double-buffered Receive Double-buffered Transmit (Enhanced Mode Only) Wake from Idle Mode (Slave Mode Only)
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interconnection between master slave CPUs with shown Figure 18-1. four pins interface Master-In/Slave-Out (MISO), Master-Out/Slave-In (MOSI), Shift Clock (SCK), Slave Select (SS). clock output master mode, clock input slave mode. MSTR SPCR determines directions MISO MOSI. Also notice that MOSI connects MOSI MISO MISO. master mode, SS/P1.4 ignored used general-purpose input output. slave mode, must driven select individual device slave. When driven high, slave's port deactivated MOSI/P1.5 used general-purpose input. Figure 18-1. Master-slave Interconnection
Master
MISO MISO
Slave
8-Bit Shift Register
MOSI MOSI
8-Bit Shift Register
Clock Generator
modes operation: normal (non-buffered write) enhanced (buffered write). normal mode, writing data register (SPDR) master starts clock generator data written shifts MOSI into MOSI slave CPU. Transmission start after initial delay while clock generator waits next full slot specified baud rate. After shifting byte, clock generator stops, setting transmission flag (SPIF) transferring received byte read buffer (SPDR). both interrupt enable (SPIE) serial port interrupt enable (ES) set, interrupt requested. Note that SPDR refers either write data buffer read data buffer, depending whether access write read. normal mode, because write buffer transparent (and write access SPDR will directed shift buffer), attempt write SPDR while transmission progress will result write collision with WCOL set. However, transmission will still complete normally, byte will ignored write access SPDR will necessary. Enhanced mode similar normal mode except that write buffer holds next byte transmitted. Writing SPDR loads write buffer sets WCOL signify that buffer full further writes will overwrite buffer. WCOL cleared hardware when buffered byte loaded into shift register transmission begins. master currently idle, i.e. this first byte, then after loading SPDR, transmission byte starts WCOL cleared immediately. While this byte transmitting, next byte written SPDR. Load Enable flag (LDEN) SPSR used determine when transmission started. LDEN asserted during first four slots transfer. master should first check that LDEN that WCOL cleared before loading next byte. enhanced mode, WCOL when transfer completes, i.e. next byte available, then immediately loads buffered byte into shift register, resets WCOL, continues transmission without stopping restarting clock generator. long keep write buffer full this manner, multiple bytes transferred with minimal latency between bytes.
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AT89LP213/214 [Preliminary]
Table 18-1. SPCR Control Register
Reset Value 0000 0000B
SPCR Address Addressable
SPIE Symbol SPIE DORD MSTR CPOL CPHA Function
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
interrupt enable. This bit, conjunction with register, enables interrupts: SPIE enable interrupts. SPIE disables interrupts. enable. enables channel connects MOSI, MISO pins P1.4, P1.5, P1.6, P1.7. disables channel. Data order. DORD selects first data transmission. DORD selects first data transmission. Master/slave select. MSTR selects Master mode. MSTR selects slave mode. Clock polarity. When CPOL high when idle. When CPOL master device when transmitting. Please refer figure clock phase polarity control. Clock phase. CPHA together with CPOL controls clock data relationship between master slave. Please refer figure clock phase polarity control. clock rate select. These bits control rate device configured master. SPR1 SPR0 have effect slave. relationship between oscillator frequency, FOSC., follows: SPR1 SPR0 fOSC/4 fOSC/8 fOSC/32 fOSC/64
SPR0 SPR1
Notes:
clock mode before enabling SPI: bits needed SPCR except bit, then SPE. Enable master prior slave device. Slave echoes master next loaded with data.
Table 18-2.
SPDR Data Register
Reset Value (after cold reset) unchanged (after warm reset)
SPDR Address Addressable
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
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Table 18-3.
SPSR Status Register
Reset Value 000X X000B
SPSR Address Addressable
SPIF Symbol SPIF Function
WCOL
LDEN
SSIG
DISSO
interrupt flag. When serial transfer complete, SPIF interrupt generated SPIE SPIF cleared reading status register followed reading/writing data register. When Write collision flag. WCOL data register written during data transfer. During data transfer, result reading SPDR register incorrect, writing effect. WCOL (and SPIF bit) cleared reading status register followed reading/writing data register. When WCOL works Enhanced mode Buffer Full. Writing during WCOL enhanced mode will overwrite waiting data already present Buffer. this mode, WCOL longer reset SPIF reset reset when write buffer been unloaded into serial shift register. Load enable buffer enhanced mode. When set, safe load Buffer while LDEN WCOL LDEN high during bits during bits serial byte transmission time frame. Slave Select Ignore. SSIG will only operate slave mode (P1.4) pulled low. When SSIG ignores slave mode active whenever (SPCR.6) set. P1.4 used regular when SSIG Disable slave output bit. When set, this causes MISO tri-stated more than slave device share same interface with single master. Normally, first byte transmission could slave address only selected slave should clear DISSO bit. Enhanced mode select bit. When normal mode, i.e. without write double buffering. When enhanced mode with write double buffering. buffer shares same address with SPDR register.
WCOL
LDEN
SSIG
DISSO
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Figure 18-2. Shift Register Diagram
Serial
Serial Master
LATCH
Serial Slave
LATCH Serial
Parallel Master
Transmit Byte (Write Buffer)
Parallel Slave
(Read Buffer)
LATCH
LATCH
Receive Byte
Figure 18-3. Block Diagram
Oscillator
8-bit Shift Register
Read Data Buffer
Write Data Buffer
MISO P1.6 MOSI P1.5
Divider ÷4÷8÷32÷64
Clock (Mater)
Clock Clock Logic
Control Logic
Select
SPR1 SPR0
P1.4
Control
WCOL SPIF
MSTR DORD MSTR CPHA CPOL SPR1 SPR0
SPIE
Status Register
Control Register
Interrupt Request
Internal Data
DORD
MSTR
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CPHA (Clock PHAse), CPOL (Clock POLarity), (Serial Peripheral clock Rate baud rate) bits SPCR control shape rate SCK. bits provide four possible clock rates when master mode. slave mode, will operate rate incoming long does exceed maximum rate. There also four possible combinations phase polarity with respect serial data. CPHA CPOL determine which format used transmission. data transfer formats shown Figures 18-4 18-5. prevent glitches from disrupting interface, CPHA, CPOL, should modified while interface enabled, master device should enabled before slave device(s). Figure 18-4. Transfer Format with CPHA
Note:
*Not defined normally character just received.
Figure 18-5. Transfer Format with CPHA
CYCLE (FOR REFERENCE) (CPOL (CPOL MOSI (FROM MASTER) MISO (FROM SLAVE) SLAVE)
Note:
*Not defined normally previously transmitted character.
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AT89LP213/214 [Preliminary]
Analog Comparator
single analog comparator provided AT89LP213/214. analog comparator following features: Comparator Output Flag Interrupt Selectable Interrupt Condition High- Low-level Rising- Falling-edge Output Toggle Hardware Debouncing Modes Comparator operation such that output logic when positive input AIN0 (P1.0]) greater than negative input AIN1 (P1.1). Otherwise output zero. Setting ACSR enables comparator. When comparator first enabled, comparator output interrupt flag guaranteed stable corresponding comparator interrupt should enabled during that time, comparator interrupt flag must cleared before interrupt enabled order prevent immediate interrupt service. Before enabling comparator analog inputs should tristated putting P1.0 P1.1 into input-only mode. "Port Analog Functions" page comparator configured cause interrupt under variety output value conditions setting bits ACSR. comparator interrupt flag ACSR whenever comparator output matches condition specified flag polled software used generate interrupt must cleared software.
19.1
Comparator Interrupt with Debouncing
comparator output sampled every clock cycle. conditions analog inputs such that comparator output will toggle excessively. This especially true applying slow moving analog inputs. Three debouncing modes provided filter this noise. debouncing mode, comparator uses Timer modulate sampling time. When relevant transition occurs, comparator waits until Timer overflows have occurred before resampling output. sample agrees with expected value, set. Otherwise, event ignored. filter tuned adjusting time-out period Timer Because Timer free running, debouncer must wait overflows guarantee that sampling delay least time-out period. Therefore, after initial edge event, interrupt occur between time-out periods later. Figure 19-1 page default comparator disabled during Idle mode. allow comparator function during Idle, CIDL ACSR must set. When CIDL set, comparator used wake-up from Idle comparator interrupt enabled. comparator always disabled during Power-down mode. Figure 19-1. Negative Edge with Debouncing Example
Comparator Timer Overflow
Start
Compare Start Compare
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Table 19-1.
ACSR Analog Comparator Control Status Register Reset Value XXX0 0000B
ACSR Addressable
Symbol CIDL Function
CIDL
Comparator Idle Enable. CIDL comparator will continue operate during Idle mode. CIDL comparator powered down during Idle mode. comparator always shut down during Power-down mode. Comparator Interrupt Flag. when comparator output meets conditions specified [2:0] bits set. flag must cleared software. interrupt enabled/disabled setting/clearing Comparator Enable. this enable comparator. Clearing this will force comparator output prevent further events from setting When analog input pins, P1.0 P1.1, have their digital inputs disabled. Comparator Interrupt Mode Interrupt Mode Negative (Low) level Positive edge Toggle with debouncing(1) Positive edge with debouncing(1) Negative edge Toggle Negative edge with debouncing(1) Positive (High) level
[2:0]
Note:
Debouncing modes require Timer generate sampling delay.
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AT89LP213/214 [Preliminary]
Programmable Watchdog Timer
programmable Watchdog Timer (WDT) protects system from incorrect execution triggering system reset when times after software failed feed timer prior timer overflow. Default counts clock cycles. prescaler bits, PS0, WDTCON used period Watchdog Timer from 2048K clock cycles. Timer Prescaler also used lengthen time-out period (see Table page disabled Reset during Power-down mode. When times without being serviced, internal pulse generated reset CPU. Table 20-1 available period selections. Table 20-1. Watchdog Timer Time-out Period Selection
Prescaler Bits Note: Period(1) (Clock Cycles) 128K 256K 512K 1024K 2048K
time-out period dependent system clock frequency.
Time-out Period Oscillator Frequency Watchdog Timer consists 14-bit timer with 7-bit programmable prescaler. Writing sequence 1EH/E1H WDTRST register enables timer. When enabled, WDTEN WDTCON will "1". prevent from generating reset when overflows, watchdog feed sequence must written WDTRST before timeout period. feed watchdog, write instructions must sequentially executed successfully. Between write instructions, reads allowed, writes allowed. instructions should move WDTRST register then WDTRST register. incorrect feed enable sequence will cause immediate watchdog reset. program sequence feed enable watchdog timer follows: WDTRST, #01Eh WDTRST, #0E1h
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20.1
Software Reset
Software Reset AT89LP213/214 accomplished writing software reset sequence 5AH/A5H WDTRST SFR. does need enabled generate software reset. normal software reset will SWRST flag WDTCON. However, time incorrect sequence written WDTRST (i.e. anything other than 1EH/E1H 5AH/A5H), software reset will immediately generated both SWRST WDTOVF flags will set. this manner intentional software reset distinguished from software error-generated reset. program sequence generate software reset follows: WDTRST, #05Ah WDTRST, #0A5h
Table 20-2.
WDTCON Watchdog Control Register
Reset Value 0000 X000B
WDTCON Address Addressable
Symbol WDIDLE SWRST WDTOVF WDTEN Function
WDIDLE
SWRST
WDTOVF
WDTEN
Prescaler bits watchdog timer (WDT). When three bits cleared watchdog timer nominal period clock cycles. When three bits nominal period 2048K clock cycles. Disable/enable Watchdog Timer IDLE mode. When WDIDLE continues count IDLE mode. When WDIDLE freezes while device IDLE mode. Software Reset Flag. when software reset generated writing sequence 5AH/A5H WDTRST. Also when incorrect sequence written WDTRST. Must cleared software. Watchdog Overflow Flag. when rest generated timer overflow. Also when incorrect sequence written WDTRST. Must cleared software. Watchdog Enable Flag. This READ-ONLY reflects status (whether running not). disabled after reset must re-enabled writing 1EH/E1H WDTRST
Table 20-3.
WDTRST Watchdog Reset Register
(Write-Only)
WDTCON Address Addressable
enabled writing sequence 1EH/E1H WDTRST SFR. current status checked reading WDTEN WDTCON. prevent from resetting device, same sequence 1EH/E1H must written WDTRST before time-out interval expires. software reset generated writing sequence 5AH/A5H WDTRST.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Instruction Summary
AT89LP213/214 fully binary compatible with MCS-51 instruction set. difference between AT89LP213/214 standard 8051 number cycles required execute instruction. Instructions AT89LP213/214 take clock cycles complete. execution times most instructions computed using Table 21-1. Table 21-1. Instruction Execution Times Exceptions
Cycle Count Formula bytes bytes Clock Cycles Arithmetic direct #data ADDC ADDC direct ADDC ADDC #data SUBB SUBB direct SUBB SUBB #data direct direct Bytes 8051 AT89LP Code 28-2F 26-27 38-3F 36-37 98-9F 96-97 08-0F 06-07 18-1F 16-17
Generic Instruction Types Most arithmetic, logical, transfer instructions Branches Calls Single Byte Indirect (i.e. @Ri, etc.) RET, RETI MOVC MOVX DPTR
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Table 21-1.
Instruction Execution Times Exceptions (Continued)
Clock Cycles
Arithmetic DPTR
Bytes
8051
AT89LP
Code
Clock Cycles Logical direct #data direct, direct, #data direct #data direct, direct, #data direct #data direct, direct, #data SWAP Bytes 8051 AT89LP Code 58-5F 56-57 48-4F 46-47 68-6F 66-67
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AT89LP213/214 [Preliminary]
Table 21-1. Instruction Execution Times Exceptions (Continued)
Clock Cycles Data Transfer direct #data direct #data direct, direct, direct, direct direct, direct, #data @Ri, @Ri, direct @Ri, #data DPTR, #data16 MOVC @A+DPTR MOVC @A+PC MOVX MOVX @DPTR MOVX @Ri, MOVX @DPTR, PUSH direct direct direct XCHD SETB SETB Bytes 8051 AT89LP Code E8-EF E6-E7 F8-FF A8-AF 78-7F 88-8F 86-87 F6-F7 A6-A7 76-77 E2-E3 F2-F3 C8-CF C6-C7 D6-D7
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Table 21-1.
Instruction Execution Times Exceptions (Continued)
Clock Cycles
Operations /bit bit,
Bytes
8051
AT89LP
Code
Clock Cycles Branching bit, bit, bit, SJMP ACALL addr11 LCALL addr16 RETI AJMP addr11 LJMP addr16 @A+DPTR @A+PC
Bytes
8051
AT89LP
Code 11,31,51,71,9 1,B1,D1,F1 01,21,41,61,8 1,A1,C1,E1 B8-BF B6-B7 D8-DF
CJNE direct, CJNE #data, CJNE #data, CJNE @Ri, #data, DJNZ DJNZ direct, BREAK Note:
This escaped instruction extension instruction set.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
On-chip Debug System
AT89LP213/214 On-chip Debug (OCD) System uses two-wire serial interface control program flow; read, modify, write system state; program nonvolatile memory. System following features: Complete program flow control Read-modify-write access internal SFRs data memories Four hardware program address breakpoints Unlimited program software breakpoints using BREAK instruction Break stack overflow/underflow Break Watchdog overflow Non-intrusive operation Programming nonvolatile memory
22.1
Physical Interface
On-chip Debug System uses two-wire synchronous serial interface establish communication between target device controlling emulator system. interface controlled User Fuses. enabled clearing Enable Fuse. When enabled, port configured input Debug Clock (DCL). Either XTAL1 XTAL2 configured bi-directional data line Debug Data (DDA) depending clock source selected. External Clock selected, XTAL2 configured DDA. Internal Oscillator selected, XTAL1 configured DDA. device connections shown Figure 22-1. When enabled, type interface used depends Interface Select User Fuse. This fuse selects between normal two-wire interface (TWI) fast two-wire interface (FTWI). duty user program this fuse correct setting their debug system same time they enable (see "User Configuration Fuses" page 71). Figure 22-1. AT89LP213/214 On-chip Debug Connections
P1.3/RST P1.3/RST
XTAL1
XTAL1
XTAL2
Internal
External Clock
When designing system where On-chip Debug will used, following observations must considered correct operation: P1.3/RST cannot connected directly external capacitors connect must removed. external reset sources must removed. quartz crystal capacitors XTAL1 XTAL2 must removed external clock signal must driven XTAL1 user does wish internal oscillator. Some emulator systems provide user-configurable clock this purpose.
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22.2
Software Breakpoints
AT89LP213/214 microcontroller includes BREAK instruction implementing program memory breakpoints software. software breakpoint inserted manually placing BREAK instruction program code. Some emulator systems allow automatic insertion/deletion software breakpoints. Flash memory must re-programmed each time software breakpoint changed. Frequent insertions/deletions software breakpoints will reduce data retention nonvolatile memory. Devices used debugging purposes should shipped customers. BREAK instruction treated two-cycle when disabled.
22.3
Limitations On-chip Debug
AT89LP213/214 low-cost, low-pincount fully-featured microcontroller that multiplexes several functions limited pins. Some device functionality must sacrificed provide resources On-chip Debugging. On-chip Debug System following limitations: Debug Clock (DCL) physically located that same Port P1.3 External Reset (RST). Therefore, neither P1.3 external reset source emulated when enabled. Debug Data (DDA) physically located either XTAL1/P3.2 XTAL2/P3.3 pin. crystal oscillator therefore supported during debug. user must select either Internal Oscillator External Clock source provide system clock. Devices fused crystal oscillator will default external clock mode when enabled. When using Internal Oscillator during debug, located XTAL1/P3.2 pin. INT0 function cannot emulated this mode. When using External Clock during debug, located XTAL2/P3.3 system clock drives XTAL1/P3.2. INT0, INT1 CLKOUT functions cannot emulated this mode. AT89LP213/214 does support In-Application Programming therefore device must reset before changing program code during debugging. This includes insertion/deletion software breakpoints. When using watchdog generate break, state watchdog will reset. reset command should sent device prior resuming normal execution ensure correct watchdog behavior.
AT89LP213/214 [Preliminary]
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AT89LP213/214 [Preliminary]
Programming Flash Memory
Atmel AT89LP213/214 microcontroller features on-chip In-System Programmable Flash program memory. In-System Programming (ISP) allows programming reprogramming microcontroller positioned inside system. Using simple 4-wire interface, In-System programmer communicates serially with AT89LP213/214 microcontroller, reprogramming nonvolatile memories chip. In-System programming eliminates need physical removal chips from system. This will save time money, both during development lab, when updating software parameters field. interface AT89LP213/214 includes following features: Four Wire Programming Interface Active-low Reset Entry into Programming Slave Select allows multiple devices same interface User Signature Array Flexible Page Programming Erase Capability Page Write with Auto-Erase Commands Programming Status Register more detailed information In-System Programming, refer Application Note entitled "AT89LP In-System Programming Specification".
23.1
Physical Interface
In-System Programming utilizes Serial Peripheral Interface (SPI) pins AT89LP213/214 microcontroller. full duplex synchronous serial interface consisting four wires: Serial Clock (SCK), Master-In/Slave-out (MISO), Master-out/Slave-in (MOSI), active-low Slave Select (SS). When programming AT89LP213/214 device, programmer always operates master, target system always operates slave. enter remain In-System Programming mode device's reset line (RST) must held active (low). With addition GND, AT89LP213/214 microcontroller programmed with minimum seven connections shown Figure 23-1. Figure 23-1. In-System Programming Device Connections
AT89LP213/214 Serial Clock Serial Serial P1.7/SCK P1.6/MISO P1.5/MOSI P1.4/SS P1.3/RST
3538A-MICRO-7/06
In-System Programming Interface only means externally programming AT89LP213/214 microcontroller. Interface used program device both insystem stand-alone serial programmer. Interface does require clock other than limited system clock frequency. During In-System programming system clock source target device operate normally. When designing system where In-System Programming will used, following observations must considered correct operation: interface uses clock mode (CPOL 0,CPHA exclusively with maximum frequency MHz. AT89LP213/214 will enter programming mode only when reset line (RST) active (low). simplify this operation, recommended that target reset controlled In-System programmer. avoid problems, In-System programmer should able keep entire target system reset duration programming cycle. target system should never attempt drive four lines while reset active. input disabled gain extra pin. these cases will always function reset during power enter programming must driven prior Power-On Reset (POR). After completed device will remain mode until brought high. Once initial session ended, power target device must cycled enter another session. should left floating during reset enabled. Enable Fuse must allow programming during reset period. Fuse disabled, only entered POR.
23.2
Memory Organization
AT89LP213/214 offers bytes In-System Programmable (ISP) nonvolatile Flash code memory. addition, device contains 64-byte User Signature Array 32-byte readonly Atmel Signature Array. memory organization shown Table 23-1 Figure 23-2. memory divided into pages bytes each. single read write command only access single page memory. Each memory type resides address space accessed commands specific that memory. However, memory types share same page size. User configuration fuses mapped memory, with each byte representing fuse. From programming standpoint, fuses treated same normal code bytes except they affected Chip Erase. Fuses enabled time writing appropriate locations fuse row. However, disable fuse, i.e. FFh, entire fuse must erased then reprogrammed. programmer should read state fuses into temporary location, modify those fuses which need disabled, then issue Fuse Write with Auto-Erase command using temporary data. Lock bits treated similar manner fuses except they only erased (unlocked) Chip Erase. Table 23-1.
Device AT89LP213 AT89LP214
Code Memory Sizes
Code Size bytes bytes Page Size bytes bytes Pages Address Range 0000H 07FFH 0000H 07FFH
AT89LP213/214 [Preliminary]
3538A-MICRO-7/06
AT89LP213/214 [Preliminary]
Figure 23-2. AT89LP213/214 Memory Organization
User Fuse User Signature Array Atmel Signature Array
Page Page Page Page Page Page 07FF
Code Memory
Page Page
0000
23.3
Command Format
Programming commands consist opcode byte, address bytes, zero more data bytes. addition, command packets must start with two-byte preamble 55H. preamble increases noise immunity programming interface making more difficult issue unintentional commands. Figure 23-3 page shows simplified flow chart command sequence. sample command packet shown Figure 23-4 page defines packet frame. must brought before first byte command sent brought back high after final byte command been sent. command complete until returns high. Command bytes issued serially MOSI. Data output bytes received serially MISO. Packets variable length supported returning high when final required byte been transmitted. some cases command bytes have don't care value. Don't care bytes middle packet must transmitted. Don't care bytes packet ignored. Page oriented instructions always include full 16-bit address. higher order bits select page lower order bits select byte within that page. AT89LP213/214 allocates bits byte address bits page address. page accessed always fixed page address transmitted. byte address specifies starting address first data byte. After each data byte been transmitted, byte address incremented point next data byte. This allows page command linearly sweep bytes within page. byte address incremented past last byte page, byte address will roll over first byte same page. While loading bytes into page buffer, overwriting previously loaded bytes will result data corruption. summary available commands, Table 23-2 page
3538A-MICRO-7/06
Figure 23-3. Command Sequence Flow Chart
Input Preamble (AAh)
Input Preamble (55h)
Input Opcode
Input Address High Byte
Input Address Byte
Input/Output Data
Address
Figure 23-4. Command Packet
MOSI
Preamble Preamble Opcode Address High Address Data Data
MISO
AT89LP213/214 [Preliminary]
3538A-MICRO-7/06
AT89LP213/214 [Preliminary]
Table 23-2.
Command Program Enable(1) Chip Erase Read Status Load Page Buffer(2) Write Code Page(2) Write Code Page with Auto-Erase(2) Read Code Page(2) Write User Fuses(2)(3)(4) Write User Fuses with Auto-Erase(2)(3)(4) Read User Fuses(2)(3)(4) Write Lock Bits(2)(3)(5) Read Lock Bits(2)(3)(5) Write User Signature Page(2) Write User Signature Page with Auto-Erase(2) Read User Signature Page(2) Read Atmel Signature Page(2)(6) Notes:
Programming Command Summary
Opcode 1010 1100 1000 1010 0110 0000 0101 0001 0101 0000 0111 0000 0011 0000 1110 0001 1111 0001 0110 0001 1110 0100 0110 0100 0101 0010 0111 0010 0011 0010 0011 1000 Addr High 0101 0011 xxxx xxxx xxxx xxxx xxxx xaaa xxxx xaaa xxxx xaaa 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Addr xxxx xxxx xxxb bbbb aaab bbbb aaab bbbb aaab bbbb 000b bbbb 000b bbbb 000b bbbb 000b bbbb 000b bbbb xaab bbbb xaab bbbb xaab bbbb xxxb bbbb Data Status DataIn DataIn DataIn DataIn DataIn DataIn DataOut DataOut DataIn DataIn DataIn DataIn DataOut DataOut DataIn DataIn DataOut DataOut DataIn DataIn DataIn DataIn DataOut DataOut DataOut DataOut Data
Program Enable must first command issued after entering into programming mode. number Data bytes from written/read. internal address incremented between each byte. Each byte address selects fuse lock bit. Data bytes must FFh. Table 23-5 page Fuse definitions. Table 23-4 page Lock definitions. Atmel Signature Bytes:
AT89LP213: Address AT89LP214: Address
Symbol Key:
Page Address Byte Address Don't Care
3538A-MICRO-7/06
23.4
Status Register
current state memory accessed reading status register. status register shown Table 23-3.
Table 23-3.
Status Register
Symbol LOAD SUCCESS Function
LOAD
SUCCESS
WRTINH
BUSY
Load flag. Cleared load page buffer command high next memory write. This flag signals that page buffer previously loaded with data load page buffer command. Success flag. Cleared start programming cycle will only high programming cycle completes without interruption from brownout detector. Write Inhibit flag. Cleared brownout detector (BOD) whenever programming inhibited falling below minimum required programming voltage. episode occurs during programming, SUCCESS flag will remain after cycle complete. WRTINH also forces BUSY low. Busy flag. Cleared whenever memory busy programming write currently inhibited.
WRTINH BUSY
23.5
DATA Polling
AT89LP213/214 implements DATA polling indicate programming cycle. While device busy, attempted read last byte written will return data byte with complemented. Once programming cycle completed, true value will accessible. During Erase data assumed DATA polling will return 7FH. When writing multiple bytes page, DATA value will last data byte loaded before programming begins, written byte with highest physical address within page.
23.6
Flash Security
AT89LP213/214 provides Lock Bits Flash Code Memory security. Lock bits left unprogrammed (FFh) programmed (00h) obtain protection levels listed Table 234. Lock bits only erased (set FFh) Chip Erase. Lock mode disables programming memory spaces, including User Signature Array User Configuration Fuses. User fuses must programmed before enabling Lock mode Lock mode implemented mode also blocks reads from code memory; however, reads User Signature Array, Atmel Signature Array, User Configuration Fuses still allowed.
Table 23-4.
Lock Protection Modes
Program Lock Bits address) Mode Protection Mode program lock features Further programming Flash disabled Further programming Flash disabled verify (read) also disabled; disabled
AT89LP213/214 [Preliminary]
3538A-MICRO-7/06
AT89LP213/214 [Preliminary]
23.7 User Configuration Fuses
AT89LP213/214 includes user fuses configuration device. Each fuse accessed separate address User Fuse listed Table 23-5. Fuses cleared programming their locations. Programming fuse location will cause that fuse maintain previous state. fuse (set FFh) fuse must erased then reprogrammed using Fuse Write with Auto-erase command. default state fuses FFh. Table 23-5.
Address
User Configuration Fuse Definitions
Fuse Name Description Selects source system clock: Selected Source Crystal Oscillator (XTAL) Reserved External Clock XTAL1 (XCLK) Internal Oscillator (IRC)
Clock Source CS[0:1](2)
Selects time-out delay POR/BOD/PWD wake-up period: SUT1 Start-up Time SUT[0:1] Notes: Reset Enable(3) Brown-out Detector Enable On-chip Debug Enable Enable(3) Oscillator Frequency Adjustment [0:7] User Signature Programming Tristate Ports Interface Select default state fuses FFh. Changes these fuses will only take effect after device POR. Changes these fuses will only take effect after session terminates bringing high. (XTAL); (XCLK/IRC) (XTAL); (XCLK/IRC) (XTAL); (XCLK/IRC) SUT0 Selected Time-out (XTAL); (XCLK/IRC)
FFh: functions re
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