LDMOS Power-Amplifier Bias Controller Two-Channel Solution Progra

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LDMOS Power-Amplifier Bias Controller Two-Channel Solution Progra

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2/06
LDMOS Power-Amplifier Bias Controller
Two-Channel Solution Programmable Bias Control Potentiometer's Position Automatically Updated Compensate Ambient Temperature Drain Voltage Current Five-Channel, 13-Bit Continuously Monitors Ambient Temperature, VCC, ID1, Hi/Lo Alarms Each Channel Trigger Fault Output Nonvolatile Memory Device Settings, Lookup Tables, 32-Bytes User Memory I2C*-Compatible Serial Interface with Eight Devices Same Serial Single Power Supply Small 16-Pin TSSOP Package -40°C +95°C Operational Temperature Range
DS1870
DS1870 dual-channel bias controller targeted toward class LDMOS power-amplifier applications. uses lookup tables (LUTs) control 256-position potentiometers based amplifier's temperature drain voltage current other external monitored signal). With internal temperature sensor multichannel converter (ADC), DS1870 provides cost-effective solution that improves amplifier's efficiency using nonlinear compensation schemes that possible with conventional biasing solutions.
Applications
Cellular Base Stations Medical Equipment Industrial Controls Optical Transceivers
Ordering Information
PART DS1870E-010 TEMP RANGE -40°C +95°C -40°C +95°C PIN-PACKAGE TSSOP (173 mils) TSSOP (173 mils)
*Purchase components Maxim Integrated Products, Inc., sublicensed Associated Companies, conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
DS1870E-010+
+Denotes lead-free package.
Typical Operating Circuit appears data sheet.
Configuration
VIEW HCOM
DS1870
FAULT
TSSOP (173 mils) Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
LDMOS Power-Amplifier Bias Controller DS1870
ABSOLUTE MAXIMUM RATINGS
Voltage Range VCC, HCOM, SDA, Pins Relative Ground .-0.5V +6.0V Voltage Range FAULT, ID1, Relative Ground. .-0.5V 0.5V, exceed +6.0V Voltage Range Relative Ground .-0.5V HCOM 0.5V, exceed +6.0V Operating Temperature Range .-40°C +95°C EEPROM Programming Temperature Range .0°C +70°C Storage Temperature Range .-55°C +125°C Soldering Temperature .See IPC/JEDEC J-STD-020A Specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS
-40°C +95°C)
PARAMETER Supply Voltage Input Logic (SDA, SCL, Input Logic (SDA, SCL, HCOM Voltage Voltage Wiper Current SYMBOL (Note CONDITIONS -0.3 -0.3 +0.3 HCOM UNITS
ELECTRICAL CHARACTERISTICS
(VCC +4.5 5.5V, -40°C +95°C.)
PARAMETER Supply Current Input Leakage Low-Level Output Voltage (SDA, FAULT) Capacitance Digital Power-On Reset Analog Power-On Reset SYMBOL VOL1 VOL2 CI/O VPOD VPOA sink current sink current CONDITIONS (Note -200 +200 UNITS
LDMOS Power-Amplifier Bias Controller
ANALOG VOLTAGE-MONITORING CHARACTERISTICS
(VCC +4.5 5.5V, -40°C +95°C.)
PARAMETER Monitor FactoryCalibrated Monitor FactoryCalibrated Monitor FactoryCalibrated Resolution (VCC, ID1, ID2) Accuracy (VCC, ID1, ID2) Update Rate VCC, ID1, tframe SYMBOL Code FFF8h Code FFF8h Code FFF8h CONDITIONS 2.488 6.521 0.4975 2.500 6.553 0.5000 0.0122 0.25 2.513 6.587 0.5025 UNITS
DS1870
DIGITAL THERMOMETER CHARACTERISTICS
(VCC +4.5 5.5V, -40°C +95°C.)
PARAMETER Thermometer Error Update Rate SYMBOL TERR tframe -40°C 95°C CONDITIONS UNITS
ANALOG POTENTIOMETER CHARACTERISTICS
(VCC +4.5 5.5V, -40°C +95°C.)
PARAMETER Wiper Resistance Potentiometer End-to-End Resistance Resolution Absolute Linearity Relative Linearity Ratiometric Temperature Coefficient End-to-End Temperature Coefficient -3dB Cutoff Frequency Series Resistors from VHCOM/VLX (Note +25°C 15.1 0.5975 (Note (Note -0.5 19.5 25.2 0.6025 SYMBOL +25°C RPOT +25°C 10.0 CONDITIONS +0.5 1000 16.8 UNITS ppm/°C ppm/°C
LDMOS Power-Amplifier Bias Controller DS1870
LOOKUP TABLE CHARACTERISTICS
(VCC +4.5 5.5V, -40°C +95°C.)
PARAMETER POT1 POT2 Temp Size POT1 POT2 Temp Index Range Temp Step Temp Hysteresis POT1 POT2 Drain Size POT1 POT2 Drain Index Range POT1 POT2 Drain Step POT1 POT2 Drain Hysteresis POT1 POT2 Drain Index Range POT1 POT2 Drain Step POT1 POT2 Drain Hysteresis (Note (Note 0000 0200 0100 8000 0200 0100 7E00 (Note FE00 SYMBOL CONDITIONS +102 UNITS Bytes each Bytes each
LDMOS Power-Amplifier Bias Controller
ELECTRICAL CHARACTERISTICS
(VCC +4.5V 5.5V, -40°C +95°C, timing referenced VIL(MAX) VIH(MIN).) (Figure
PARAMETER Clock Frequency Free Time Between Stop Start Conditions Hold Time (Repeated) Start Condition Period High Period Data Hold Time Data Setup Time Start Setup Time Rise Time Fall Time Stop Setup Time Capacitive Loading EEPROM Write Time SYMBOL fSCL tBUF tHD:STA tLOW tHIGH tHD:DAT tSU:DAT tSU:STA tSU:STO (Note (Note (Note (Note CONDITIONS (Note 0.1CB 0.1CB UNITS
DS1870
NONVOLATILE MEMORY CHARACTERISTICS
(VCC +4.5V 5.5V, +70°C.)
PARAMETER Writes SYMBOL +70°C (Note CONDITIONS 50,000 UNITS
Note Note Note Note Note Note Note Note Note
voltages referenced ground. Supply current measured with logic inputs their inactive state (SDA VCC) driven well-defined logic levels. outputs disconnected. Absolute linearity difference measured value from expected value position. Expected value straight line from measured minimum position measured maximum position. Relative linearity deviation setting change expected change. Expected change slope straight line from measured minimum position measured maximum position. This parameter guaranteed design. Figure interface timing shown fast-mode (400kHz) operation. This device also backward compatible with standard-mode timing. CB-total capacitance line picofarads. EEPROM write begins after stop condition occurs.
LDMOS Power-Amplifier Bias Controller DS1870
Typical Operating Characteristics
(VCC +5.0V, +25°C, unless otherwise noted.)
SUPPLY CURRENT SUPPLY VOLTAGE
DS1870 toc01
SUPPLY CURRENT TEMPERATURE
SUPPLY CURRENT 4.5V 5.0V 5.5V
DS1870 toc02
HCOM CURRENT HCOM VOLTAGE
0.45 0.40 HCOM CURRENT (mA) 0.35 0.30 0.25 0.20 0.15 0.10 0.05
DS1870 toc03
SUPPLY CURRENT
0.50
SUPPLY VOLTAGE
TEMPERATURE (°C)
HCOM VOLTAGE
POTENTIOMETER OUTPUT VOLTAGE POSITON
DS1870 toc04
POTENTIOMETER DIFFERENTIAL NONLINEARITY WIPER POSITION
DS1870 toc05
POTENTIOMETER DIFFERENTIAL NONLINEARITY WIPER POSITION
0.20 0.15 0.10 0.05 -0.05 -0.10 -0.15 -0.20 -0.25
DS1870 toc06
WIPER VOLTAGE HCOM CONNECTED
0.25 DIFFERENTIAL NONLINEARITY (LSB) 0.20 0.15 0.10 0.05 -0.05 -0.10 -0.15 -0.20 -0.25
0.25 DIFFERENTIAL NONLINEARITY (LSB)
WIPER POSITION (DEC)
WIPER POSITION (DEC)
WIPER POSITION (DEC)
POTENTIOMETER INTEGRAL NONLINEARITY WIPER POSITION
DS1870 toc07
POTENTIOMETER INTEGRAL NONLINEARITY WIPER POSITION
DS1870 toc08
POTENTIOMETER WIPER RESISTANCE WIPER VOLTAGE
WIPER RESISTANCE HCOM 5.0V
DS1870 toc09
INTEGRAL NONLINEARITY (LSB) -0.1 -0.2 -0.3 -0.4 -0.5
INTEGRAL NONLINEARITY (LSB) -0.1 -0.2 -0.3 -0.4 -0.5
1000
WIPER POSITION (DEC)
WIPER POSITION (DEC)
WIPER VOLTAGE
LDMOS Power-Amplifier Bias Controller
Typical Operating Characteristics (continued)
(VCC +5.0V, +25°C, unless otherwise noted.)
POTENTIOMETER WIPER RESISTANCE WIPER VOLTAGE
DS1870 toc09
DS1870
POTENTIOMETER WIPER RESISTANCE TEMPERATURE
DS1870 toc10
POTENTIOMETER END-TO-END RESISTANCE TEMPERATURE
CHANGE FROM RESISTANCE 25°C (PPM/C) -100 -150 -200 RPOT1 RPOT2
DS1870 toc11
1000 WIPER RESISTANCE WIPER VOLTAGE HCOM 5.0V
1000 RESISTANCE CHANGE FROM 25°C (PPM/C) HCOM WIPER VOLTAGE
TEMPERATURE (°C)
TEMPERATURE (°C)
POTENTIOMETER TERMINAL VOLTAGE TEMPERATURE
DS1870 toc12
CONVERSION ERROR SUPPLY VOLTAGE
DS1870 toc13
CONVERSION ERROR INPUT VOLTAGE
ERROR -0.1 -0.2
DS1870 toc14
OUTPUT DRIFT (PPM/C) HCOM 5.0V
ERROR -0.1 -0.2 -0.3 -0.4 -0.5 DEFAULT CALIBRATION
-0.3 -0.4 -0.5
DEFAULT CALIBRATION
TEMPERATURE (°C)
SUPPLY VOLTAGE
INPUT VOLTAGE
CONVERSION ERROR INPUT VOLTAGE
DS1870 toc15
CONVERSION ERROR INPUT VOLTAGE
ERROR -0.1 -0.2 DEFAULT CALIBRATION
DS1870 toc16
ERROR -0.1 -0.2 -0.3 -0.4 -0.5 DEFAULT CALIBRATION
-0.3 -0.4 -0.5
INPUT VOLTAGE
INPUT VOLTAGE
LDMOS Power-Amplifier Bias Controller DS1870
Description
NAME FAULT HCOM Potentiometer Terminal Potentiometer Wiper Terminal Potentiometer Wiper Terminal Potentiometer Terminal Drain Current Monitor Input Drain Current Monitor Input Drain Voltage Monitor Input Ground Fault Output. This open-collector output active high when enabled alarms outside programmable limit value. Address Inputs. These inputs determine slave address device. slave address binary 1010A2A1A0. Serial Clock Input. clock input. Serial Data Input/Output. Bidirectional data pin. Potentiometer High Terminal. Common potentiometers Power Input FUNCTION
LDMOS Power-Amplifier Bias Controller
Functional Diagram
DS1870
INTERFACE CONTROL
ON-CHIP TEMP SENSOR BYTES USER MEMORY GAIN CALIBRATION REGISTERS OFFSET CALIBRATION REGISTERS 13-BIT
DATA INDEX LOAD POT1 DRAIN TABLE BYTES) TEMP INDEX LOAD POT1 TEMP TABLE BYTES) POT2 TEMP TABLE BYTES) ADDRESS GENERATION
INDEX POT2 DRAIN TABLE BYTES)
MEASURED VALUES TEMP, VCC, ID0,
LIMIT FLAG REGISTERS
FAULT LIMITS TEMP, VCC, ID1, LIMIT COMPARATOR FAULT MASK
INDEX HCOM
DS1870
POT2 RPOT POT1 RPOT
LDMOS Power-Amplifier Bias Controller DS1870
Table Voltage-Monitor Factory Default Calibration
SIGNAL SIGNAL 6.553V 2.5V 0.5V 0.5V (hex) FFF8 FFF8 FFF8 FFF8 SIGNAL (hex) 0000 0000 0000 0000
Table Voltage-Monitor Conversion Examples
SIGNAL WEIGHT (µV) 100.00 100.00 38.152 38.152 7.6303 7.6303 REGISTER VALUE (hex) 8080 C0F8 C000 8080 8000 1328 INPUT VOLTAGE 3.29 4.94 1.875 1.255 0.2500 0.0374
Detailed Description
DS1870 dual-channel LDMOS bias controller. intended replace traditional bias control solutions that limited constant temperature-coefficient correction. This offers lookup table correction that programmable function temperature well drain supply voltage current. flexibility nonlinear bias correction improves efficiency significantly. This direct consequence ability lower bias current, particularly class operation, since bias correction longer requires constant temperature coefficient. addition, correcting bias function drain supply voltage, drain current class assists distortion reduction gain management. outputs W2), each controlled dedicated two-dimensional lookup table shown functional diagram, drive LDMOS gates. degrees freedom temperature either drain supply voltage drain current. lookup tables programmed during power-amplifier assembly test. After calibration, automatically recalls proper control setting each output, based temperature drain characteristics. 13-bit samples digitizes chip temperature, VCC, drain supply voltage, drain currents. These digitized signals stored memory ready accessed look table controls. digitized values also compared alarm thresholds generating high alarm flags. FAULT output configured assert high based alarm's assertion, alarms masked prevent unwanted fault assertions. readings well alarm flags fault status accessible through I2C-compatible interface.
three least significant bits result registers masked zero. round-robin time specified tframe analog voltage-monitoring characteristics. default factory-calibrated values voltage monitors shown Table calculate voltage measured from register value, first calculate weight 16-bit register that equal full-scale voltage span divided 65,528. Next, convert hexadecimal register value decimal multiply times weight.
Example: Using factory default trim, what voltage measured register value C347h? equal (6.553V 65,528 100.00µV. C347h equal 49,991 decimal, which yields supply voltage equal 49,991 100.00µV 4.999V. Table shows more conversion examples based factory trimmed settings. using internal gain offset calibration registers, signal values shown Table modified meet customer needs. more information calibration, Voltage-Monitor Calibration section. Note: method shown above determining input voltage level only works when offset register zero.
Voltage/Current Monitor Operation
DS1870 monitors four voltages (VCC, ID1, ID2) plus temperature round-robin fashion using 13-bit ADC. converted voltage values stored memory addresses 62h-69h 16-bit unsigned numbers with result left justified register.
LDMOS Power-Amplifier Bias Controller DS1870
Table Internal Temperature-Monitor Factory Default Calibration
SIGNAL Temp SIGNAL +127.97°C (hex) 7FF8 SIGNAL -128.00°C (hex) 8000
Table Temperature Conversion Values
(bin) 01000000 01000000 01011111 11110110 11011000 (bin) 00000000 00001111 00000000 00000000 00000000 TEMPERATURE (°C) +64.059
Temperature-Monitor Operation
internal temperature monitor values stored 16-bit complement numbers memory addresses 61h. round-robin update time (tframe) temperature register same voltage monitors. factory default calibration values temperature monitor shown Table convert complement register value temperature represents, first convert 2-byte hexadecimal value decimal value unsigned value, then divide result 256. Finally, subtract result division greater than equal +128. Table shows example converted values. offset temperature sensor adjusted using internal calibration registers account differences between ambient temperature location DS1870 temperature device biasing. When offsets applied temperature measurement, value converted will fixed value from DS1870's ambient temperature. more information, Temperature Monitor Offset Calibration section.
Table Addresses Corresponding Temperature Values
ADDRESS (hex) CORRESPONDING TEMPERATURE (°C) -40°C -38°C -36°C +100°C +102°C
table POT2 Drain (memory table control potentiometer event that table values summed result greater than less than potentiometer's position respectively.
Potentiometer Operation
Both DS1870's potentiometers positions with their high terminals connected high common pin, HCOM. terminals potentiometers internally shunted resistors such that output voltage when HCOM connected source. internal shunt resistors potentiometer's end-to-end resistance feature matching temperature coefficients that prevent output voltage from drifting over temperature. External resistors placed from HCOM and/or from modify typical output voltage.
Normal Operation
During normal operation, each potentiometer's position automatically adjusted temperature drain values after each round conversions. potentiometer setting applied after both base offset values recalled from memory. currently indexed values POT1 Temp (memory table POT1 Drain (memory table control potentiometer currently indexed values POT2 Temp (memory
LDMOS Power-Amplifier Bias Controller DS1870
MEMORY LOCATION INCREASING TEMPERATURE MEMORY LOCATION INCREASING DRAIN VOLTAGE MEMORY LOCATION DECREASING TEMPERATURE DECREASING DRAIN VOLTAGE INCREASING DRAIN CURRENT DECREASING DRAIN CURRENT
TEMPERATURE (°C)
AA00 AC00 AEOO B000 B200 B400 DRAIN VOLTAGE CONVERSION (HEX)
2A00 2C00 2E00 3000 3200 3400 DRAIN CURRENT CONVERSION (HEX)
Figure Hysteresis
temperature tables (LUT bytes each. This allows biasing adjusted every between -40°C +102°C. Temperatures less than -40°C greater than +102°C -40°C +102°C values, respectively. values temperature tables 8-bit unsigned values decimal) that allow potentiometer position function temperature. temperature LUTs have hysteresis (Figure prevent potentiometer's position from chattering event temperature remains near switching point. Table shows DS1870 determines temperature tables index function temperature. drain tables (LUT LUT5) bytes each, they indexed either drain voltage drain current corresponding potentiometer. control determines voltage sensed adjusts POT1 Drain LUT, control determines voltage sensed controls POT2 Drain LUT. control bits located register memory table drain tables programmed with 8-bit signed value (-128 +127 decimal) that allow relative offset from temperature values determined amplifier's drain characteristics.
drain LUTs indexed either upper half range lower half corresponding range. Table shows index determined based values. Hysteresis equal 0100h also implemented drain monitor (Figure ensure that voltages close switching point cause potentiometer position chatter between values. drain index values specified hexadecimal because hexadecimal values applicable regardless gain offset calibration DS1870.
Manual Mode
During normal operation, potentiometer position automatically modified once conversion cycle based results. DS1870 either stop update function together using B/O_en bit, temperature drain indexes manually controlled using Index_en bit. These bits located register located memory table byte AFh. More information about these bits Register Description section.
Voltage-Monitor Calibration
DS1870 scale each analog voltage's gain offset produce desired digital result. Each inputs (VCC, ID1, ID2) unique register gain offset memory table allowing them individually calibrated. Additionally, DS1870 offers ability provide temperature offset allow temperature measurement compensated account difference temperature between DS1870 device biasing. scale gain offset converter specific input, must first know relationship between analog input expected digital result. input that would produce digital result zeros null value (normally this input GND). input that would produce digital result ones (FFF8h)
Table Addresses Values
ADDRESS (hex) VALUE (hex) 8000 8200 8400 FC00 FE00 VALUE (hex) 0000 0200 0400 7C00 7E00
LDMOS Power-Amplifier Bias Controller
full-scale (FS) value. expected value also found multiplying all-ones digital answer weight. Example: Since digital reading 65,528 (FFF8 hex) LSBs, LSB's weight 50µV, then value 65,528 50µV 3.2764V. binary search used calibrate gain converter. This requires forcing known voltages input pin. preferred that forced voltages null input other Since least significant digital reading register known, expected digital results calculated both null input full scale value. explanation binary search used scale gain best served with following example pseudocode:
Assume that null input 0.5V Assume that requirement 50µV 65528 50e-6; /*3.2764V CNT1 50e-6; 1000 CNT2 50e-6; 58981.5 null input 0.5V 2.949V input's offset register zero gain_result Working register gain calculation CLAMP FFF8h; This value*/ down begin gain_result gain_result Write gain_result input's gain register; Force input (2.949V); Meas2= result from DS1870; Meas2 CLAMP Then gain_result gain_result Else Force null input (0.5V) Meas1 result from DS1870 [(Meas2-Meas1)>(CNT2-CNT1)] Then gain_result gain_result end; Write gain_result input's gain register;
requiring non-zero null values (e.g., 0.5V) must next calibrate input's offset. desired null value leave offset register programmed 0000h skip this step. calibrate offset register, program gain register with gain_result value determined above. Next, force null input voltage (0.5V example) read digital result from part (Meas1). offset value calculated using following formula: Meas1 Offset
DS1870
Temperature-Monitor Offset Calibration
DS1870's temperature sensor comes precalibrated requires further adjustment customer proper operation. However, possible customers characterize their system fixed offset DS1870's temperature reading reflective another location's temperature. This required biasing because temperature offset accounted adjusting data's location LUTs, this feature available customers application benefits. change temperature sensor's offset: write temperature offset register 0000h, measure source reference temperature (Tref), read temperature from DS1870 (TDS1870). Then, following formula used calculate value temperature offset register.
TempOffset -275 Tref TDS1870 XORbitwise BB40h
Once value calculated, write temperature offset register.
Power-Up Low-Voltage Operation
During power-up, device inactive until exceeds digital power-on-reset voltage (VPOD). this voltage, digital circuitry, which includes I2Ccompatible interface, becomes functional. However, EEPROM-backed registers/settings cannot internally read (recalled) until exceeds analog power-on reset (VPOA), which time remainder device becomes fully functional. Once exceeds VPOA, Rdyb byte timed from indicates when conversions begin. ever dips below VPOA, Rdyb reads again. Once device exceeds EEPROM recalled, values remain active (recalled) until falls below VPOD.
gain register resolution conversion matches expected LSB. Customers
LDMOS Power-Amplifier Bias Controller DS1870
device powers alarm flag defaults until first conversion occurs sets clears flag accordingly. FAULT output active when VPOA. power-up when they first received customers. password should programmed value other than FFFFh ensure calibration data write protected. register always reads 0000h regardless programmed value.
Memory Description
DS1870 memory divided into sections that include lower memory (addresses 7Fh) five memory tables (Figure memory tables addressed setting table-select byte (7Fh) desired table number accessing upper memory locations (80h FFh). lower memory addressed time regardless state table-select byte. lower memory memory table used configure DS1870 read status monitors. lower memory also contains bytes user memory. Memory tables contain base potentiometer positions that used biasing based reading internal temperature sensor. Memory tables contain relative offsets that added base number function either drain voltage individual drain current monitors. Memory complete listing registers Register Description section details about each register.
EEPROM Write Disable
Memory locations Table locations SRAM-shadowed EEPROM. default (SEE these locations ordinary EEPROM. setting these locations begin function like SRAM cells, which allow infinite number write cycles without concern wearing EEPROM. This also eliminates requirement EEPROM write time. Because changes made with affect EEPROM, these changes retained through power cycles. power-up value last value written with This function used limit number EEPROM writes during calibration change monitor thresholds periodically during normal operation without wearing EEPROM. resides memory table byte AFh.
Memory
upper part memory organized into 8-byte 4-word (2-byte) rows. beginning address shown left-most column map, equal byte word memory address. next byte (Byte located next highest memory address, next word (Word memory addresses greater than row's beginning address. lower part memory expands bytes words show names bits within byte/word, their weights (2X) registers that contain numerical information. Numerical registers that contain most significant showing sign extension complement numbers. Descriptions each byte/bit follow Register Description section.
Password Memory Protection
DS1870 contains 2-byte password that allows memory write protected until proper password entered into password entry (PWE) word (address 78h). This allows factory calibration data bias settings, alarm thresholds, other EEPROM information write protected. password writing Password register, which first bytes memory table factory default value password FFFFh, which also factory default value power-up. This means that parts unlocked
MAIN MEMORY TABLE TABLE POT1 TEMP TABLE POT2 TEMP TABLE POT1 DRAIN TABLE POT2 DRAIN
USER MEMORY; CONFIGURATION HI/LO ALARM THRESHOLDS; RESULTS; CONFIGURATION TABLE-SELECT BYTE (7Fh)
Figure Memory Organization
LDMOS Power-Amplifier Bias Controller
LOWER MEMORY (HEX) BYTE (HEX) 00-1F Value0 Value1 Status Table Select BYTE NAME User Temp Alrm Alrm Alrm Alrm Alrm Temp Alrm Alrm Alrm Alrm Alrm Temp Value Value Value Value Value Alarm Alarm Status Status
DS1870
NAME User Row0 User Row1 User Row2 User Row3 Threshold0 Threshold1 Threshold2 Threshold3
WORD BYTE User User User User BYTE User User User User
WORD BYTE User User User User BYTE User User User User
WORD BYTE User User User User BYTE User User User User
WORD BYTE User User User User BYTE User User User User
Temp Alarm Alarm Temp Alarm Alarm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Alarm Reserved Alarm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Alarm Reserved Alarm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Alarm Reserved Alarm Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Temp Value Value Alarm Alarm
Value Reserved Reserved Reserved Reserved Reserved
Value Reserved Status Reserved BIT7
Value Reserved Reserved Reserved
Status Reserved
Reserved
EXPANDED BYTES
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8
BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Temp Temp Reserved Temp
Reserved
Reserved
Reserved
Fault
Reserved Reserved Mint Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved Rdyb Reserved
LDMOS Power-Amplifier Bias Controller DS1870
TABLE CONFIGURATION (HEX) NAME Config Scale0 Scale1 Offset0 Offset1 Index WORD BYTE BYTE Password Reserved Scale Reserved Offset Index Index Scale Reserved Offset Reserved Index POT1 base WORD BYTE BYTE WORD BYTE BYTE Scale Reserved Offset Reserved POT1 POT2 base Reserved
WORD BYTE Fault BYTE Reserved
Scale Reserved offset Temp Offset POT2
EXPANDED BYTES BYTE (HEX) BYTE NAME Password Fault Scale Scale Scale Offset Offset Temp Offset Index Index Index POT1 base POT1 POT2 base POT2 BIT3 BIT2 Reserved
BIT1 BIT0
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 Reserved Temp
BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 Reserved
Reserved
Reserved
Reserved
Reserved Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B/O_en
index_en
LDMOS Power-Amplifier Bias Controller DS1870
TABLE (POT1 TEMP LUT) (HEX) BYTE (HEX) 80-C7 BYTE NAME POT1 NAME WORD BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WORD BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WORD BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WORD BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXPANDED BYTES
LDMOS Power-Amplifier Bias Controller DS1870
(HEX) BYTE (HEX) 80-C7 BYTE NAME POT2 NAME WORD BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved TABLE POT2 TEMP LUT) WORD WORD BYTE BYTE BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved WORD BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EXPANDED BYTES
LDMOS Power-Amplifier Bias Controller DS1870
(HEX) BYTE (HEX) 80-BF NAME BYTE NAME POT1 WORD BYTE BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 TABLE POT1 DRAIN LUT) WORD WORD BYTE BYTE BYTE BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 WORD BYTE BYTE POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1 POT1
EXPANDED BYTES
(HEX) BYTE (HEX) 80-BF
NAME BYTE NAME POT2
WORD BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2
TABLE (POT2 DRAIN LUT) WORD WORD BYTE BYTE BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2
WORD BYTE BYTE POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2 POT2
EXPANDED BYTES
LDMOS Power-Amplifier Bias Controller DS1870
Register Description
register descriptions organized register's address starting with lower memory, then proceeding through each lookup table order. format register description shown below. TABLE NAME Name
Name Byte <Access><Volatility><Power-On/ Factor Default Values> Description byte's function description description Access value following each byte's name defines read/write access register. Possible values read-only (R), write-only (W), read-write (R/W). Volatility parameter defines memory volatile nonvolatile (NV). Some registers correspond values measured detected DS1870. These parameters read-only listed since their values indeterminate. Power-On values default states volatile register, Factory Default values values EEPROM memory programmed factory before they shipped from Dallas Semiconductor. LOWER MEMORY User User <R/W><NV><00h> EEPROM user memory. Threshold0 Temp Alarm <R/W><NV><0000h> Temperature measurements above this complement threshold corresponding alarm bit. Measurements below this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements input above this unsigned threshold corresponding alarm bit. Measurements below this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements input above this unsigned threshold corresponding alarm bit. Measurements below this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements input above this unsigned threshold corresponding alarm bit. Measurements below this threshold clear alarm bit. Threshold1 Alarm <R/W><NV><0000h> Voltage measurements input above this unsigned threshold corresponding alarm bit. Measurements below this threshold clear alarm bit. Threshold2 Temp Alarm <R/W><NV><0000h> Temperature measurements below this complement threshold corresponding alarm bit. Measurements above this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements below above this unsigned threshold corresponding alarm bit. Measurements above this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements input below this unsigned threshold corresponding alarm bit. Measurements above this threshold clear alarm bit. Alarm <R/W><NV><0000h> Voltage measurements input below this unsigned threshold corresponding alarm bit. Measurements above this threshold clear alarm bit. Threshold3 Alarm <R/W><NV><0000h> Voltage measurements input below this unsigned threshold corresponding alarm bit. Measurements above this threshold clear alarm bit.
LDMOS Power-Amplifier Bias Controller
Value0
DS1870
Temp Value <R><NA><0000h> signed complement direct-to-temperature measurement. Value <R><NA><0000h> Unsigned voltage measurement. Value <R><NA><0000h> Unsigned voltage measurement. Value <R><NA><0000h> Unsigned voltage measurement. Value1 Value <R><NA><0000h> Unsigned voltage measurement. Status Alarm <R><NA><00h> High-Alarm Status bits. Temp High-alarm status temperature measurement. High-alarm status measurement. High-alarm status measurement. High-alarm status measurement. High-alarm status measurement. Alarm <R><NA><40h> Low-Alarm Status bits. Temp Low-alarm status temperature measurement. Low-alarm status measurement. This when supply below trip-point value. clears itself when measurement completed value above threshold. Low-alarm status measurement. Low-alarm status measurement. Low-alarm status measurement. Status <R><NA><see below> Status FAULT pin. Fault Logical value FAULT pin. Fault logic HIGH during power-on. Mint Maskable Interrupt. FAULT open-drain output. case FAULT pulled externally missing external pullup resistor, this reflects logical value DS1870 trying output FAULT pin. Alarm' Alarm' active corresponding `Fault Ena' enabled, `RDBY' then this active high. Otherwise, this zero. Rdyb Ready Bar. When supply above power-on-analog (VPOA) trip point, this active low. Thus, this reads logic supply below VPOA communicate over bus. Status <R/W><V><00h> Status completed conversions. power-on, these bits cleared each conversion completed. These bits cleared that completion conversions verified. Temp Temperature conversion ready. conversion ready. conversion ready. conversion ready. conversion ready.
LDMOS Power-Amplifier Bias Controller DS1870
<W><V><FFFFh> Password Entry. Until correct password written this location, only memory that written addresses 7Fh. This includes Table_Select locations. memory readable regardless value. <R/W><V><00h> Table Select. DS1870 contains four tables Writing value this register grants access corresponding table.
TABLE (CONFIGURATION) Config Password <R/W><NV><FFFFh> value compared against value written this location. EEPROM memory write-protected when does match thisregister. <R/W><NV><03h> Selects which inputs used control lookup tables.
Fault Temp
Scale0
selects input control drain indexing POT2 (Table zero selects input. selects input control drain indexing POT1 (Table zero selects input. <R/W><NV><00h> Configures maskable interrupt FAULT pin. Temperature measurements, outside threshold limits, enabled create active interrupt FAULT pin. measurements, outside threshold limits, enabled create active interrupt FAULT pin. measurements, outside threshold limits, enabled create active interrupt FAULT pin. measurements, outside threshold limits, enabled create active interrupt FAULT pin. measurements, outside threshold limits, enabled create active interrupt FAULT pin.
Scale Scale Scale
Scale1
<R/W><NV><XXXX> Controls scaling gain measurements. gain factory trimmed 6.5535V <R/W><NV><XXXX> Controls scaling gain measurements. gain factory trimmed 2.500V <R/W><NV><XXXX> Controls scaling gain measurements. gain factory trimmed 0.5V <R/W><NV><XXXX> Controls scaling gain measurements. gain factory trimmed 0.5V <R/W><NV><0000h> Allows offset control measurement <R/W><NV><0000h> Allows offset control measurement. <R/W><NV><0000h> Allows offset control measurement. <R/W><NV><0000h> Allows offset control measurement. <R/W><NV><0000h> Allows offset control temperature measurement.
Scale
Offset0 Offset
Offset Offset Offset1 Offset Temp Offset Index
LDMOS Power-Amplifier Bias Controller
Index Index Index POT1 base
<R><NA><00h> Holds calculated index based temperature measurement. This index used address LUTs <R><NA><00h> Holds calculated index based measurement (dependant `LUT Sel' byte). This index used address <R><NA><00h> Holds calculated index based measurement (dependant `LUT Sel' byte). This index used address <R><NA><00h> base value used POT1 recalled from Table memory address found Index.' This register updated temperature conversion. POT1 updated with this value until conversion ensure that both base offset known POT1 POT2 they updated simultaneously. <R><NA><00h> offset value used POT1 recalled from Table memory address found Index.' Depending value written `LUT Sel' byte, this register updated conversion. POT1 updated with this value until conversion ensure that both base offset known POT1 POT2 they updated simultaneously. <R><NA><00h> base value used POT2 recalled from Table memory address found Index.' This register updated temperature conversion. POT2 updated with this value until conversion ensure that both base offset known POT1 POT2 they updated simultaneously.
DS1870
POT1
POT2 base
POT2
<R><NA><00h> Offset value used POT2 recalled from Table memory address found Index.' Depending value written `LUT Sel' byte, this register updated conversion. POT2 updated with this value until conversion ensure that both base offset known POT1 POT2 they updated simultaneously. <R/W><NA><03h> Allows user control either Index base offset values used calculate potentiometer positions. Shadow bar. power-on this low, which enables writes shadowed locations. written one, this allows trimming and/or configuring part without changing NV-shadowed memory having wait cycle time complete. Writing this zero does cause write from SRAM copy into Shadow locations addresses Table 180h A7h. B/O_en power-on this high, which enables auto control LUT. this written zero, then base offset writeable user recalls disabled. This allows user interactively test their modules writing base and/or offsets POTs. POTs update with value write cycle. Thus, four registers (`POT1 Base,' `POT1 OFF,' `POT2 Base,' `POT2 OFF') should written same write cycle. stop condition write cycle. Index_en power-on this high, which enables auto control LUT. this cleared zero, then three index values index,' Index,' Index') writeable user updates calculated indexes disabled. This allows user interactively test their modules controlling indexing lookup tables. three index values should written same write cycle. recalled values from LUTs appear base offset register after each corresponding conversion (just like would happen auto mode). ensure recalled base offset values from updated, base offset calculation will update potentiometers until completion next temperature conversion. Both pots update same time (just like would happen auto mode).
LDMOS Power-Amplifier Bias Controller DS1870
TABLE (TEMP Bytes 80h-C7h POT1 <R/W><NV><00h>The unsigned base value POT1. TABLE (TEMP Bytes 80h-C7h
POT2 <R/W><NV><00h>The unsigned base value POT2. TABLE (DRAIN Bytes 80h-B8h POT1 <R/W><NV><00h>The signed complement offset value POT1. TABLE (DRAIN
Bytes 80h-B8h POT2 <R/W><NV><00h>The signed complement offset value POT2.
Definitions
following terminology commonly used describe data transfers. Master device: master device controls slave devices bus. master device generates clock pulses, start stop conditions. Slave devices: Slave devices send receive data master's request. idle busy: Time between stop start conditions when both inactive their logic high states. When idle, often initiates low-power mode slave devices. Start condition: start condition generated master initiate data transfer with slave. Transitioning from high while remains high generates start condition. timing diagram applicable timing.
Stop condition: stop condition generated master data transfer with slave. Transitioning from high while remains high generates stop condition. timing diagram applicable timing. Repeated start condition: master repeated start condition data transfer indicate that will immediately initiate data transfer following current one. Repeated starts commonly used during read operations identify specific memory address begin data transfer. repeated start condition issued identically normal start condition. timing diagram applicable timing. write: Transitions must occur during state SCL. data must remain valid unchanged during entire high pulse plus
tBUF tLOW
tHD:STA
tHD:STA STOP START tHD:DAT NOTE: TIMING REFERENCED VIL(MAX) VIH(MIN). tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
Figure Timing Diagram
LDMOS Power-Amplifier Bias Controller
7-BIT SLAVE ADDRESS
MOST SIGNIFICANT
VALUES
DETERMINES READ WRITE
Figure Slave Address Byte
setup hold time requirements (Figure Data shifted into device during rising edge SCL. read: write operation, master must release line proper amount setup time (Figure before next rising edge during read. device shifts each data falling edge previous pulse data valid rising edge current pulse. Remember that master generates clock pulses, including when reading bits from slave. Acknowledgement (ACK NACK): acknowledgement (ACK) acknowledge (NACK) always transmitted during byte transfer. device receiving data (the master during read slave during write operation) performs transmitting zero during bit. device performs NACK transmitting during bit. Timing (Figure NACK identical other writes. acknowledgment that device properly receiving data. NACK used terminate read sequence indication that device receiving data. Byte write: byte write consists bits information transferred from master slave (most significant first) plus 1-bit acknowledgement from slave master. bits transmitted master done according write definition acknowledgement read using read definition. Byte read: byte read 8-bit information transfer from slave master plus 1-bit NACK from master slave. bits information that transferred (most significant first) from slave master read master using read definition above, master transmits using write definition receive additional data bytes. master must NACK last byte read terminated communication slave will return control master. Slave address byte: Each slave responds slave addressing byte sent immediately
following start condition. slave address byte (Figure contains slave address most significant bits least significant bit. DS1870's slave address 1010A2A1A0 (binary), where values address pins. address pins allow device respond eight possible slave addresses. writing correct slave address with master indicates will write data slave. master will read data from slave. incorrect slave address written, DS1870 assumes master communicating with another device ignores communications until next start condition sent. Memory address: During write operation, master must transmit memory address identify memory location where slave store data. memory address always second byte transmitted during write operation following slave address byte.
DS1870
Communication
Writing single byte slave: master must generate start condition, write slave address byte (R/W write memory address, write byte data, generate stop condition. Remember master must read slave's acknowledgement during byte write operations. Writing multiple bytes slave: write multiple bytes slave, master generates start condition, writes slave address byte (R/W writes memory address, writes data bytes, generates stop condition. DS1870 writes bytes page row) with single write transaction. This internally controlled address counter that allows data written consecutive addresses without transmitting memory address before each data byte sent. address counter limits write 8-byte page (one memory map). Attempts write additional pages memory without sending stop condition between pages results address counter wrapping around beginning present row. Example: 3-byte write starts address writes three data bytes (11h, 22h, 33h) three "consecutive" addresses. result that addresses would contain 22h, respectively, third data byte, 33h, would written address 00h. prevent address wrapping from occurring, master must send stop condition page, then wait bus-free EEPROM-write time elapse. Then master generate start con25
LDMOS Power-Amplifier Bias Controller
dition, write slave address byte (R/W first memory address next memory before continuing write data. Acknowledge polling: time EEPROM page written, DS1870 requires EEPROM write time (tW) after stop condition write contents page EEPROM. During EEPROM write time, DS1870 will acknowledge slave address because busy. possible take advantage that phenomenon repeatedly addressing DS1870, which allows next page written soon DS1870 ready receive data. alternative acknowledge polling wait maximum period elapse before attempting write again DS1870. EEPROM write cycles: When EEPROM writes occur, DS1870 writes whole EEPROM memory page, even only single byte page modified. Writes that modify bytes page allowed corrupt remaining bytes memory same page. Because whole page written, bytes page that were modified during transaction still subject write cycle. This result whole page being worn over time writing single byte repeatedly. Writing page
COMMUNICATIONS START WHITE BOXES INDICATE MASTER CONTROLLING SHADED BOXES INDICATE SLAVE CONTROLLING BITS ADDRESS DATA NOTES: BYTES SENT MOST SIGNIFICANT FIRST. FIRST BYTE SENT AFTER START CONDITION ALWAYS SLAVE ADDRESS, FOLLOWED READ/WRITE BIT.
byte time wears EEPROM eight times faster than writing entire page once. DS1870's EEPROM write cycles specified Nonvolatile Memory Characteristics table. specification shown worst-case temperature. handle approximately that many writes room temperature. Writing SRAM-shadowed EEPROM memory with does count EEPROM write cycle when evaluating EEPROM's estimated lifetime. Reading single byte from slave: Unlike write operation that uses memory address byte define where data written, read operation occurs present value memory address counter. read single byte from slave, master generates start condition, writes slave address byte with reads data byte with NACK indicate transfer, generates stop condition. Manipulating address counter reads: dummy write cycle used force address counter particular value. this, master generates start condition, writes slave address byte (R/W writes memory address where desires read, generates repeated start condition, writes slave address byte (R/W reads data with NACK applicable, generates stop condition.
DS1870
STOP REPEATED START
WRITE SINGLE BYTE MEMORY ADDRESS DATA
WRITE 8-BYTE PAGE WITH SINGLE TRANSACTION MEMORY ADDRESS DATA DATA
READ SINGLE BYTE WITH DUMMY WRITE CYCLE MOVE ADDRESS COUNTER MEMORY ADDRESS DATA
READ MULTIPLE BYTES WITH DUMMY WRITE CYCLE MOVE ADDRESS COUNTER MEMORY ADDRESS DATA
DATA
DATA
DATA
Figure Communications Examples
LDMOS Power-Amplifier Bias Controller
Typical Operating Circuit
DS1870
4.7k PLACES
FAULT RPOT2 RPOT1 N.C. N.C.
DS1870
FACTORY-CALIBRATED 13-BIT (CUSTOMER ADJUSTABLE FULLSCALE OFFSET VALUES)
49.9k
4.22k
N.C.
N.C.
MAX6165B REFERENCE
HCOM
RFIN
POWER
RFOUT
NOTES: THIS CONFIGURATION, VOLTAGE RANGE 3V-5V. THIS RANGE EXTENDED USING EXTERNAL RESISTORS. MAX6156B USED WITH MULTIPLE DS1870s.
Figure read example using repeated start condition specify starting memory location. Reading multiple bytes from slave: read operation used read multiple bytes with single transfer. When reading bytes from slave, master simply ACKs data byte desires read another byte before terminating transaction. After master reads last byte NACKs indicate transfer generates stop condition. This done with without modifying address counter's location before read cycle. DS1870's address counter does wrap page boundaries during read
operations, counter will roll from upper most memory address last memory location read during read transaction.
Application Information
Power-Supply Decoupling
achieve best results, recommended that power supply decoupled with 0.01µF 0.1µF capacitor. high-quality, ceramic, surface-mount capacitors, mount capacitors close possible pins minimize lead inductance.
LDMOS Power-Amplifier Bias Controller DS1870
Pullup Resistors
open-collector output DS1870 that requires pullup resistor realize high logic levels. master using either open-collector output with pullup resistor push-pull output driver used SCL. Pullup resistor values should chosen ensure that rise fall times listed electrical characteristics within specification.
Advanced Application
circuit showing implementaion current sensing using DS1870 shown under Advanced Application with Current Sense.
Advanced Application with Current Sense
4.7k PLACES
FAULT
49.9k (1%)
DS1870
4.22k (1%)
MAX4080
PASS FILTER
RPOT2
RPOT1
N.C.
N.C.
MAX6165B REFERENCE
HCOM
MAX4080
PASS FILTER
RFIN
POWER
RFOUT
NOTES: THIS CONFIGURATION, VOLTAGE RANGE 3V-5V. THIS RANGE EXTENDED USING EXTERNAL RESISTORS. MAX6156B USED WITH MULTIPLE DS1870s.
Chip Information
TRANSISTOR COUNT: 52,353 SUBSTRATE CONNECTED GROUND
Package Information
latest package outline information,
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2006 Maxim Integrated Products registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.

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