LTC2607/LTC2617/LTC2627 dual 16-, 12-bit, 2.7V 5.5V rail-to-rail volta

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LTC2607/LTC2617/LTC2627 dual 16-, 12-bit, 2.7V 5.5V rail-to-rail volta

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LTC2607/LTC2617/LTC2627 16-/14-/12-Bit Dual Rail-to-Rail DACs with Interface DESCRIPTIO
LTC2607/LTC2617/LTC2627 dual 16-, 12-bit, 2.7V 5.5V rail-to-rail voltage output DACs 12-lead package. They have built-in high performance output buffers guaranteed monotonic. These parts establish board-density benchmarks 14-bit DACs advance performance standards output drive load regulation single-supply, voltage-output DACs. parts 2-wire, compatible serial interface. LTC2607/LTC2617/LTC2627 operate both standard mode (clock rate 100kHz) fast mode (clock rate 400kHz). asynchronous update (LDAC) also included. LTC2607/LTC2617/LTC2627 incorporate power-on reset circuit. During power-up, voltage outputs rise less than 10mV above zero scale; after power-up, they stay zero scale until valid write update take place. power-on reset circuit resets LTC2607-1/LTC2617-1/ LTC2627-1 midscale. voltage outputs stay midscale until valid write update takes place.
registered trademarks Linear Technology Corporation. other trademarks property their respective owners. Protected U.S. Patents including 5396245 6891433. Patent Pending
Smallest Pin-Compatible Dual DACs: LTC2607: Bits LTC2617: Bits LTC2627: Bits Guaranteed Monotonic Over Temperature Selectable Addresses 400kHz I2CInterface Wide 2.7V 5.5V Supply Range Power Operation: 260µA Power Down 1µA, High Rail-to-Rail Output Drive (±15mA, Min) Ultralow Crosstalk (30µV) Double-Buffered Data Latches Asynchronous Update LTC2607/LTC2617/LTC2627: Power-On Reset Zero Scale LTC2607-1/LTC2617-1/LTC2627-1: Power-On Reset Midscale Tiny (3mm 4mm) 12-Lead Package
APPLICATIO
Mobile Communications Process Control Industrial Automation Instrumentation Automatic Test Equipment
BLOCK DIAGRA
REFLO
VOUTA
12-/14-/16-BIT
12-/14-/16-BIT
VOUTB
REGISTER
REGISTER
(LSB)
INPUT REGISTER
INPUT REGISTER
32-BIT SHIFT REGISTER
2-WIRE INTERFACE
LDAC
2607
Differential Nonlinearity (LTC2607)
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
2607
VREF 4.096V
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LTC2607/LTC2617/LTC2627 ABSOLUTE RATI (Note
Operating Temperature Range: LTC2607C/LTC2617C/LTC2627C 70°C LTC2607I/LTC2617I/LTC2627I 40°C 85°C 0.3V 0.3V Maximum Junction Temperature 125°C Storage Temperature Range 65°C 125°C Lead Temperature (Soldering, sec). 300°C
PACKAGE/ORDER ATIO
VIEW LDAC VOUTA REFLO VOUTB
DE12 PACKAGE 12-LEAD (4mm 3mm) PLASTIC TJMAX 125°C, 43°C/W EXPOSED (PIN MUST SOLDERED
ORDER PART NUMBER LTC2607CDE LTC2607IDE LTC2607CDE-1 LTC2607IDE-1 DE12 PART MARKING* 2607 26071
Order Options Tape Reel: Lead Free: #PBF, Lead Free Tape Reel: #TRPBF, Lead Free Part Marking: http://www.linear.com/leadfree/ Consult Marketing parts specified with wider operating temperature ranges. *The temperature grade identified label shipping container.
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), REFLO VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Performance Resolution Monotonicity Differential Nonlinearity Integral Nonlinearity Load Regulation CONDITIONS
ELECTRICAL CHARACTERISTICS
Zero-Scale Error Offset Error Temperature Coefficient Gain Error Gain Temperature Coefficient
(Note (Note (Note VREF Midscale IOUT 15mA Sourcing IOUT 15mA Sinking VREF 2.7V, Midscale IOUT 7.5mA Sourcing IOUT 7.5mA Sinking Code (Note
ORDER PART NUMBER LTC2617CDE LTC2617IDE LTC2617CDE-1 LTC2617IDE-1 DE12 PART MARKING* 2617 26171
ORDER PART NUMBER LTC2627CDE LTC2627IDE LTC2627CDE-1 LTC2627IDE-1 DE12 PART MARKING* 2626 26271
LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1 ±1.5 ±0.5 0.35 0.42
UNITS Bits Bits LSB/mA LSB/mA LSB/mA LSB/mA µV/°C %FSR ppm/°C
0.02 0.125 0.03 0.125 0.04 0.05 0.25 0.25
±0.15 ±0.7
±0.15 ±0.7
±0.15 ±0.7
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LTC2607/LTC2617/LTC2627
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), REFLO VOUT unloaded, unless otherwise noted.
SYMBOL ROUT PARAMETER Power Supply Rejection Output Impedance CONDITIONS ±10% VREF Midscale; -15mA IOUT 15mA VREF 2.7V, Midscale; -7.5mA IOUT 7.5mA Full Scale Output Change (Note Load Current Change Powering Down (per channel) 5.5V, VREF 5.5V Code: Zero Scale; Forcing Output Code: Full Scale; Forcing Output 2.7V, VREF 2.7V Code: Zero Scale; Forcing Output Code: Full Scale; Forcing Output 0.032 0.035 UNITS µV/mA
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ELECTRICAL CHARACTERISTICS
0.15 0.15
Crosstalk (Note
Short-Circuit Output Current
0.3VCC
Reference Input Input Voltage Range Resistance Capacitance IREF Reference Current, Power Down Mode Power Supply Positive Supply Voltage Supply Current
Normal Mode Powered Down Specified Performance (Note (Note Powered Down (Note Powered Down (Note
0.001
0.66 0.52 0.10
Digital (Note Level Input Voltage (SDA SCL) High Level Input Voltage (SDA SCL) VIL(LDAC) Level Input Voltage (LDAC) VIH(LDAC) VIL(CAn) VIH(CAn) RINH RINL RINF CCAX High Level Input Voltage (LDAC) Level Input Voltage High Level Input Voltage Resistance from Resistance from Resistance from Float Level Output Voltage Output Fall Time Pulse Width Spikes Suppressed Input Filter Input Leakage Capacitance Capacitive Load Each Line External Capacitive Load Address Pins
0.7VCC 0.15VCC 0.85VCC
4.5V 5.5V 2.7V 5.5V 2.7V 5.5V 2.7V 3.6V Test Circuit Test Circuit Test Circuit Test Circuit Test Circuit Sink Current VIH(MIN) VIL(MAX), 10pF 400pF (Note 0.1VCC 0.9VCC Note
0.1CB
LTC2607/LTC2617/LTC2627
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 4.096V (VCC 5V), 2.048V (VCC 2.7V), REFLO VOUT unloaded, unless otherwise noted.
SYMBOL PARAMETER Performance Settling Time (Note ±0.024% (±1LSB Bits) ±0.006% (±1LSB Bits) ±0.0015% (±1LSB Bits) ±0.024% (±1LSB Bits) ±0.006% (±1LSB Bits) ±0.0015% (±1LSB Bits) 1000 1000 V/µs nV/Hz nV/Hz µVP-P CONDITIONS LTC2627/LTC2627-1 LTC2617/LTC2617-1 LTC2607/LTC2607-1 UNITS
ELECTRICAL CHARACTERISTICS
Settling Time 1LSB Step (Note Voltage Output Slew Rate Capacitive Load Driving Glitch Impulse Multiplying Bandwidth Output Voltage Noise Density Output Voltage Noise
1000 Midscale Transition 1kHz 10kHz 0.1Hz 10Hz
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (See Figure (Notes
SYMBOL PARAMETER 2.7V 5.5V fSCL Clock Frequency tHD(STA) Hold Time (Repeated) Start Condition tLOW Period Clock tHIGH High Period Clock tSU(STA) Set-Up Time Repeated Start Condition tHD(DAT) Data Hold Time tSU(DAT) Data Set-Up Time Rise Time Both Signals Fall Time Both Signals tSU(STO) Set-Up Time Stop Condition tBUF Free Time Between Stop Start Condition Falling Edge Clock Input Byte LDAC High Transition LDAC Pulse Width CONDITIONS
CHARACTERISTICS
Note Absolute maximum ratings those values beyond which life device impaired. Note Linearity monotonicity defined from code code where resolution given 0.016(2N/VREF), rounded nearest whole code. VREF 4.096V linearity defined from code code 65,535. Note SDA, LDAC VCC, CA0, Floating. Note crosstalk measured with VREF 4.096V, with measured midscale, unless otherwise noted. Note VCC.
0.1CB 0.1CB
UNITS
(Note (Note
Note Inferred from measurement code (Note full scale. Note VREF 4.096V. stepped scale scale scale scale. Load parallel with 200pF GND. Note VREF 4.096V. stepped ±1LSB between half scale half scale Load parallel with 200pF GND. Note capacitance line Note values refer VIH(MIN) VIL(MAX) levels. Note These specifications apply LTC2607/LTC2607-1, LTC2617/LTC2617-1, LTC2627/LTC2627-1. Note Guaranteed design production tested.
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LTC2607/LTC2617/LTC2627 TYPICAL PERFOR CHARACTERISTICS
LTC2607
Integral Nonlinearity (INL)
(LSB) (LSB)
VREF 4.096V
16384 32768 CODE 49152 65535
2607
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
2607
(LSB)
Temperature
(POS) -0.6 -0.8 -1.0 TEMPERATURE (°C) VREF 4.096V
(LSB)
-0.2 -0.4 (NEG)
(LSB)
(LSB)
Settling ±1LSB
VOUT 100µV/DIV
CLOCK DATA BYTE 9.7µs
2V/DIV
VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
2607
Differential Nonlinearity (DNL)
VREF 4.096V
Temperature
VREF 4.096V
(POS)
(NEG)
TEMPERATURE (°C)
2607
VREF
5.5V (POS)
VREF
5.5V
(POS) (NEG) -0.5 -1.0 -1.5
(NEG)
VREF
2607
VREF
2607
Settling Full-Scale Step
VOUT 100µV/DIV 2V/DIV
12.3µs
CLOCK DATA BYTE
2µs/DIV
2607
5µs/DIV
2607
SETTLING ±1LSB VREF 4.096V CODE 65535 STEP AVERAGE 2048 EVENTS
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LTC2607/LTC2617/LTC2627 TYPICAL PERFOR CHARACTERISTICS
LTC2617
Integral Nonlinearity (INL)
(LSB) (LSB)
VREF 4.096V
4096 8192 CODE 12288 16383
2607
LTC2627
Integral Nonlinearity (INL)
VREF 4.096V
-0.5 -1.0 -1.5 -2.0 1024 2048 CODE 3072 4095
2607
(LSB)
(LSB)
Differential Nonlinearity (DNL)
VREF 4.096V
Settling ±1LSB
-0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 CODE 12288 16383
2607
VOUT 100µV/DIV
CLOCK DATA BYTE
2V/DIV
8.9µs
2607
2µs/DIV VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
Differential Nonlinearity (DNL)
VREF 4.096V
Settling ±1LSB
6.8µs VOUT 1mV/DIV CLOCK DATA BYTE 2µs/DIV VREF 4.096V 1/4-SCALE 3/4-SCALE STEP 200pF AVERAGE 2048 EVENTS
2607
-0.2 -0.4 -0.6 -0.8 -1.0 1024 2048 CODE 3072 4095
2607
2V/DIV
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LTC2607/LTC2617/LTC2627 TYPICAL PERFOR CHARACTERISTICS
LTC2607/LTC2617/LTC2627
Current Limiting
0.10 0.08 0.06 0.04 CODE MIDSCALE VREF VREF
OFFSET ERROR (mV)
IOUT (mA)
VOUT
0.02 -0.02 -0.04 -0.06 -0.08 -0.10 IOUT (mA) VREF VREF
VOUT (mV)
Zero-Scale Error Temperature
ZERO-SCALE ERROR (mV) GAIN ERROR (%FSR)
OFFSET ERROR (mV)
TEMPERATURE (°C)
Gain Error
GAIN ERROR (%FSR) (nA) -0.1
-0.2 -0.3 -0.4
Load Regulation
CODE MIDSCALE
Offset Error Temperature
-0.2 -0.4 -0.6 -0.8 -1.0 VREF VREF
TEMPERATURE (°C)
2607
2607
2607
Gain Error Temperature
-0.1 -0.2 -0.3 -0.4 TEMPERATURE (°C)
Offset Error
2607
2607
2607
Shutdown
2607
2607
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LTC2607/LTC2617/LTC2627 TYPICAL PERFOR CHARACTERISTICS
LTC2607/LTC2617/LTC2627
Large-Signal Response Midscale Glitch Impulse
TRANSITION FROM MS-1
VOUT 0.5V/DIV
VREF 1/4-SCALE 3/4-SCALE 2.5µs/DIV
2607
Headroom Rails Output Current
VOUT
Supply Current Logic Voltage
(µA)
LOGIC VOLTAGE
(µA)
Power-On Reset Zeroscale
VOUT 10mV/DIV CLOCK DATA BYTE TRANSITION FROM MS-1
1V/DIV
2V/DIV
PEAK VOUT 10mV/DIV
2.5µs/DIV
2606
250µs/DIV
2607
Power-On Reset Midscale
VREF
SOURCING
SOURCING
1V/DIV
SINKING SINKING
VOUT
IOUT (mA)
500µs/DIV
2607
2607
Supply Current Logic Voltage
1300 1200 1100
1000
SWEEP LDAC
SWEEP
HYSTERSIS 370mV
LOGIC VOLTAGE
2607 G029
2607
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LTC2607/LTC2617/LTC2627 TYPICAL PERFOR CHARACTERISTICS
LTC2607/LTC2617/LTC2627
Multiplying Bandwidth
VREF (DC) VREF (AC) 0.2VP-P CODE FULL SCALE 100k FREQUENCY (Hz)
2607
Short-Circuit Output Current VOUT (Sinking)
5.5V VREF 5.6V CODE VOUT SWEPT
10mA/DIV
10mA/DIV
1V/DIV
Output Voltage Noise, 0.1Hz 10Hz
VOUT 10µV/DIV
SECONDS
2607
Short-Circuit Output Current VOUT (Sourcing)
5.5V VREF 5.6V CODE FULL SCALE VOUT SWEPT
2607
1V/DIV
2607
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LTC2607/LTC2617/LTC2627
FUNCTIONS
(Pin Chip Address this VCC, leave floating select slave address part (Table (Pin Chip Address this VCC, leave floating select slave address part (Table LDAC (Pin Asynchronous Update. falling edge this input after four bytes have been written into part immediately updates register with contents input register. this input without complete 32-bit (four bytes including slave address) data write transfer part wakes sleeping DACs without updating output. Software power-down disabled when LDAC low. LDAC disabled when tied high. (Pin Serial Clock Input Pin. Data shifted into rising edges clock. This high impedance requires pull-up resistor current source VCC. (Pin Serial Data Bidirectional Pin. Data shifted into acknowledged pin. This high impedance while data shifted opendrain N-channel output during acknowledgment. Requires pull-up resistor current source VCC. (Pin Chip Address this VCC, leave floating select slave address part (Table VOUTB (Pin Analog Voltage Output. output range VREFLO VREF. (Pin Supply Voltage Input. 2.7V 5.5V. (Pin Reference Voltage Input. input range VREFLO VREF VCC. (Pin 10): Analog Ground. REFLO (Pin 11): Reference Low. voltage this sets zero scale (ZS) voltage DACs. VREFLO used voltages 100mV VOUTA (Pin 12): Analog Voltage Output. output range VREFLO VREF. Exposed (Pin 13): Ground. Must soldered ground.
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LTC2607/LTC2617/LTC2627
BLOCK DIAGRA
REFLO
VOUTA
12-/14-/16-BIT
12-/14-/16-BIT
VOUTB
REGISTER
REGISTER
INPUT REGISTER
INPUT REGISTER
32-BIT SHIFT REGISTER
2-WIRE INTERFACE
LDAC
2607
TEST CIRCUITS
Test Circuit Test Circuit
VIH(CAn)/VIL(CAn)
RINH/RINL/RINF
2607
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tLOW
tSU(DAT) tHD(STA) tBUF
DIAGRA
VOLTAGE LEVELS REFER VIH(MIN) VIL(MAX) LEVELS
LTC2607/LTC2617/LTC2627
Figure
SLAVE ADDRESS DATA BYTE DATA BYTE
DATA BYTE
START
2607 F02A
LDAC
Figure
CLOCK DATA BYTE LDAC
2607 F02b
Figure
2607
tHD(STA) tHD(DAT) tHIGH tSU(STA)
tSU(STO)
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LTC2607/LTC2617/LTC2627
OPERATIO
Power-On Reset
LTC2607/LTC2617/LTC2627 clear outputs zero scale when power first applied, making system initialization consistent repeatable. LTC2607-1/ LTC2617-1/LTC2627-1 voltage outputs midscale when power first applied. some applications, downstream circuits active during power-up, sensitive nonzero outputs from during this time. LTC2607/ LTC2617/LTC2627 contain circuitry reduce poweron glitch; furthermore, glitch amplitude made arbitrarily small reducing ramp rate power supply. example, power supply ramped 1ms, analog outputs rise less than 10mV above ground (typ) during power-on. Power-On Reset Glitch Typical Performance Characteristics section. Power Supply Sequencing voltage (Pin should kept within range 0.3V VREF 0.3V (see Absolute Maximum Ratings). Particular care should taken observe these limits during power supply turn-on turn-off sequences, when voltage (Pin transition. Transfer Function digital-to-analog transfer function VOUT(IDEAL) VREF VREFLO VREFLO where decimal equivalent binary input code, resolution VREF voltage (Pin Serial Digital Interface LTC2607/LTC2617/LTC2627 communicate with host using standard 2-wire interface. Timing Diagrams (Figures show timing relationship signals bus. lines, SCL, must high when use. External pull-up resistors current sources required these lines.
value these pull-up resistors dependent power supply obtained from specifications. operating fast mode, active pull-up will necessary capacitance greater than 200pF. LTC2607/LTC2617/LTC2627 receive-only (slave) devices. master write LTC2607/LTC2617/ LTC2627. LTC2607/LTC2617/LTC2627 respond read from master. START STOP Conditions When use, both must high. master signals beginning communication slave device transmitting START condition. START condition generated transitioning from high while high. When master finished communicating with slave, issues STOP condition. STOP condition generated transitioning from high while high. then free communication with another device. Acknowledge Acknowledge signal used handshaking between master slave. Acknowledge (active LOW) generated slave lets master know that latest byte information received. Acknowledge related clock pulse generated master. master releases line (HIGH) during Acknowledge clock pulse. slave-receiver must pull down line during Acknowledge clock pulse that remains stable during HIGH period this clock pulse. LTC2607/LTC2617/LTC2627 respond write master this manner. LTC2607/LTC2617/ LTC2627 acknowledge read (retains HIGH during period Acknowledge clock pulse). Chip Address state CA0, decides slave address part. pins CA0, each three states: VCC, float. This results
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LTC2607/LTC2617/LTC2627
OPERATIO
FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT
Table Slave Address
FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT FLOAT
GLOBAL ADDRESS
selectable addresses part. slave address assignments shown Table addition address selected address pins, parts also respond global address. This address allows common write LTC2607, LTC2617 LTC2627 parts accomplished with 3-byte write transaction bus. global address 7-bit on-chip hardwired address selectable CA0, CA2.
addresses corresponding states CA0, global address shown Table maximum capacitive load allowed address pins (CA0, CA2) 10pF, these pins driven during address detection determine they floating. Write Word Protocol master initiates communication with LTC2607/ LTC2617/LTC2627 with START condition 7-bit slave address followed Write LTC2607/ LTC2617/LTC2627 acknowledges pulling clock 7-bit slave address matches address parts (set CA0, CA2) global address. master then transmits three bytes data. LTC2607/LTC2617/LTC2627 acknowledges each byte data pulling line clock each data byte transmission. After receiving three complete bytes data, LTC2607/LTC2617/LTC2627 executes command specified 24-bit input word. more than three data bytes transmitted after valid 7-bit slave address, LTC2607/LTC2617/LTC2627 acknowledge extra bytes data (SDA high during clock). format three data bytes shown Figure first byte input word consists 4-bit command word C3-C0, 4-bit address A3-A0. next bytes consist 16-bit data word. 16-bit data word consists 16-, 12-bit input code, LSB, followed don't care bits (LTC2607, LTC2617 LTC2627 respectively). typical LTC2607 write transaction shown Figure command (C3-C0) address (A3-A0) assignments shown Table first four commands table consist write update operations. write operation loads 16-bit data word from 32-bit shift register into input register selected DAC, update operation copies data word from input register register. Once copied into register, data word becomes active 16-, 12-bit input code, converted analog voltage output. update operation also powers selected been power-down mode. data path registers shown Block Diagram.
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LTC2607/LTC2617/LTC2627
OPERATIO
Table
COMMAND* Write Input Register Update (Power Register Write Update (Power Power Down Operation
ADDRESS* DACs
*Command address codes shown reserved should used.
Power-Down Mode power-constrained applications, power-down mode used reduce supply current whenever both outputs needed. When powerdown, buffer amplifiers, bias circuits reference input disabled draw essentially zero current. outputs into high impedance state, output pins passively pulled VREFLO through resistors. Input-register DAC-register contents disturbed during power-down. Either both channels into power-down mode using command 0100b combination with appropriate address. 16-bit data word
Write Word Protocol LTC2607/LTC2617/LTC1627
SLAVE ADDRESS DATA BYTE DATA BYTE
INPUT WORD
DATA BYTE
Input Word (LTC2607)
DATA BYTE
DATA BYTE
DATA BYTE
Input Word (LTC2617)
DATA BYTE
DATA BYTE
DATA BYTE
Input Word (LTC2627)
2607
DATA BYTE
DATA BYTE
DATA BYTE
Figure
ignored. supply reference currents reduced approximately each powered down; effective resistance (Pin rises accordingly, becoming high-impedance input (typically when both DACs powered down. Normal operation resumed executing command which includes update, shown Table performing asychronous update (LDAC) described next section. selected powered voltage output updated. When powered-down state powered updated, normal settling delayed. DACs powereddown state prior update command, power delay 5µs. other hand, both DACs powered down, main bias generation circuit been automatically shut down addition amplifiers reference input power delay time 12µs (for 30µs (for Asynchronous Update Using LDAC addition update commands shown Table LDAC asynchronously updates registers with contents input registers. Asynchronous update disabled when input word being clocked into part.
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LTC2607/LTC2617/LTC2627
OPERATIO
complete input word been written part, LDAC causes registers updated with contents input registers. input word being written part, going pulse LDAC before completion three bytes data powers DACs does cause outputs updated. LDAC remains after complete input word been written part, then LDAC recognized, command specified 24-bit word just transferred executed outputs updated. DACs powered when LDAC taken low, independent activity bus. LDAC falling edge clock byte data, inhibits software power-down command that specified input word. LDAC disabled when tied high. Voltage Output Both rail-to-rail amplifiers have guaranteed load regulation when sourcing sinking 15mA (7.5mA 3V). Load regulation measure amplifiers' ability maintain rated voltage accuracy over wide range load conditions. measured change output voltage milliampere forced load current change expressed LSB/mA. output impedance equivalent load regulation, derived from simply calculating change units from LSB/mA Ohms. amplifiers' output impedance 0.035 when driving load well away from rails. When drawing load current from either rail, output voltage headroom with respect that rail limited typical channel resistance output devices; e.g., when sinking 1mA, minimum output voltage 30mV. graph Headroom Rails Output Current Typical Performance Characteristics section. amplifiers stable driving capacitive loads 1000pF.
Board Layout excellent load regulation performance achieved part separating signal power grounds REFLO pins, respectively. Board should have separate areas analog digital sections circuit. This keeps digital signals away from sensitive analog signals facilitates separate digital analog ground planes that have minimal interaction with each other. Digital analog ground planes should joined only point, establishing system star ground. Ideally, analog ground plane should located component side board, should allowed under part shield from noise. Analog ground should continuous uninterrupted plane, except necessary lead pads vias, with signal traces another layer. functions return path power supply currents device should connected analog ground. Resistance from analog power supply return should possible. Resistance here will directly channel resistance output device when sinking load current. When zero scale output voltage zero required, REFLO should connected system star ground. shared trace resistance between REFLO pins undesirable since adds effective output impedance (typically 0.035) part. Rail-to-Rail Output Considerations rail-to-rail voltage output device, output limited voltages within supply range. Since analog output device cannot below ground, limit lowest codes shown Figure Similarly, limiting occur near full scale when tied VCC. VREF full-scale error (FSE) positive, output highest codes limits shown Figure full-scale limiting will occur VREF less than FSE. Offset linearity defined tested over region transfer function where output limiting occur.
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SLAVE ADDRESS COMMAND DATA
DATA STOP
START
FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE 2607
VOUT
DON'T CARE
Figure Typical LTC2607 Input Waveform-Programming Output Full Scale
OPERATIO
LTC2607/LTC2617/LTC2627
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VREF
POSITIVE
LTC2607/LTC2617/LTC2627
VREF
OUTPUT VOLTAGE
OUTPUT VOLTAGE INPUT CODE
2607
OUTPUT VOLTAGE INPUT CODE
NEGATIVE OFFSET
INPUT CODE
Figure Effects Rail-to-Rail Operation Transfer Curve. Overall Transfer Function Effect Negative Offset Codes Near Zero Scale Effect Positive Full-Scale Error Codes Near Full Scale
OPERATIO
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LTC2607/LTC2617/LTC2627
PACKAGE DESCRIPTIO
DE/UE Package 12-Lead Plastic (4mm 3mm)
(Reference 05-08-1695)
0.65 ±0.05
3.50 ±0.05 1.70 ±0.05 2.20 ±0.05 SIDES)
PACKAGE OUTLINE
0.25 0.05 3.30 ±0.05 SIDES) 0.50
RECOMMENDED SOLDER PITCH DIMENSIONS
4.00 ±0.10 SIDES)
0.20
3.00 ±0.10 SIDES)
0.115
0.38 0.10
MARK (NOTE
1.70 0.10 SIDES)
NOTCH
(UE12) 0603
0.200
0.75 ±0.05
0.25 0.05 3.30 ±0.10 SIDES)
0.50
0.00 0.05
BOTTOM VIEW-EXPOSED NOTE: DRAWING PROPOSED VARIATION VERSION (WGED) JEDEC PACKAGE OUTLINE M0-229 DRAWING SCALE DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.15mm SIDE EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC2607/LTC2617/LTC2627
TYPICAL APPLICATIO
Demo Circuit Schematic. Onboard 20-Bit Measures Performance Parameters
VREF VOUTB LTC2607 7.5k LTC2422 7.5k ZSSET
2607 TA01
LDAC
VOUTA REFLO OUTPUT
RELATED PARTS
PART NUMBER LTC1458/LTC1458L LTC1654 LTC1655/LTC1655L LTC1657/LTC1657L LTC1660/LTC1665 LTC1664 LTC1821 LTC2600/LTC2610/ LTC2620 LTC2601/LTC2611/ LTC2621 LTC2602/LTC2612/ LTC2622 LTC2604/LTC2614/ LTC2624 LTC2605/LTC2615/ LTC2625 LTC2606/LTC2616/ LTC2626 LTC2609/LTC2619/ LTC2629 DESCRIPTION Quad 12-Bit Rail-to-Rail Output DACs with Added Functionality Dual 14-Bit Rail-to-Rail VOUT Single 16-Bit VOUT DACs with Serial Interface SO-8 Parallel 5V/3V 16-Bit VOUT DACs Octal 10/8-Bit VOUT DACs 16-Pin Narrow SSOP Quad 10-Bit VOUT 16-Pin Narrow SSOP Parallel 16-Bit Voltage Output Octal 16-/14-/12-Bit VOUT DACs 16-Lead SSOP Single 16-/14-/12-Bit VOUT DACs 10-Lead Dual 16-/14-/12-Bit VOUT DACs 8-Lead MSOP Quad 16-/14-/12-Bit VOUT DACs 16-Lead SSOP Octal 16-/14-/12-Bit VOUT DACs with Interface 16-/14-/12-Bit VOUT DACs with Interface Quad 16-/14-/12-Bit VOUT DACs with Interface COMMENTS LTC1458: 4.5V 5.5V, VOUT 4.096V LTC1458L: 2.7V 5.5V, VOUT 2.5V Programmable Speed/Power, 3.5µs/750µA, 8µs/450µA 5V(3V), Power, Deglitched Power, Deglitched, Rail-to-Rail VOUT 2.7V 5.5V, Micropower, Rail-to-Rail Output 2.7V 5.5V, Micropower, Rail-to-Rail Output Precision 16-Bit Settling Step 250µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 300µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 300µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 250µA DAC, 2.5V 5.5V Supply Range, Rail-to-Rail Output, Serial Interface 250µA DAC, 2.7V 5.5V Supply Range, Rail-to-Rail Output, Interface 270µA DAC, 2.7V 5.5V Supply Range, Rail-to-Rail Output, Interface 250µA Range DAC, 2.7V 5.5V Supply Range, Rail-to-Rail Output with Separate VREF Pins Each
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, 95035-7417
(408) 432-1900
FAX: (408) 434-0507 www.linear.com
0.1µF FSSET OUTPUT
26071727f LT/LWI/TP 0705 PRINTED LINEAR TECHNOLOGY CORPORATION 2005

LTC2607/LTC2617/LTC2627 dual 16-, 12-bit, 2.7V 5.5V rail-to-rail volta

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