Document Title Mbit CMOS Volt-only Count Flash Memory Revision History

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A49LF040A
Document Title Mbit CMOS Volt-only Count Flash Memory Revision History
Mbit CMOS 3.3Volt-only Count Flash Memory
History
Initial issue Correct part number from A49LF040A A49LF040AT page
Issue Date
March 2006 March 2006
Remark
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
FEATURES
Single Power Supply Operation voltage range: Read Write Operations Standard Intel Count Interface Read compatible Intel® Count (LPC) interface Memory Configuration 512K Mbit) Block Architecture 4Mbit: eight uniform 64KByte blocks Supports full chip erase Address/Address Multiplexed (A/A Mux) mode Automatic Erase Program Operation Embedded Byte Program Block/Chip Erase algorithms Typical µs/byte programming time Typical block erase time Operational Modes Count Interface (LPC) Mode in-system operation Address/Address Multiplexed (A/A Mux) Interface Mode programming equipment Count (LPC) Mode synchronous operation with 5-signal communication interface in-system read write operations Standard Command Data Polling (I/O7) Toggle (I/O6) features Block Locking Register blocks pins multi-chip selection pins General Purpose Input Register hardware write protection Boot Block hardware write protection whole memory array except Boot Block Address/Address Multiplexed (A/A Mux) Mode 11-pin multiplexed address 8-pin data interface Supports fast programming EPROM programmers Standard Command Data Polling (I/O7) Toggle (I/O6) features Lower Power Consumption Typical 12mA active read current Typical 24mA program/erase current High Product Endurance Guarantee 100,000 program/erase cycles each block Minimum years data retention Compatible Pin-out Packaging 32-pin TSOP (TYPE 32-pin PLCC Optional Pb-free (Lead-free) package Pb-free (Lead-free) products RoHS compliant
Mbit CMOS 3.3Volt-only Count Flash Memory
General Description
A49LF040A flash memory device designed read-compatible with Intel Count (LPC) Interface Specification 1.1. This device designed single voltage, range from Volt Volt power supply perform in-system off-system read write operations. provides protection storage update code data addition adding system design flexibility through five general-purpose inputs. interface modes supported A49LF040A: Count (LPC) Interface mode In-System programming Address/Address Multiplexed (A/A Mux) mode fast factory programming PC-BIOS applications. memory divided into eight uniform 64Kbyte blocks that erased independently without affecting data other blocks. Blocks also protected individually prevent accidental Program Erase commands from modifying memory. boot block write protected hardware method controlled register-based protection turned on/off Block Locking Registers (LPC mode only). rest blocks except boot block device also write protected Block Locking Registers (LPC mode only). Program Erase operations executed issuing Program/Erase commands into command interface which activating internal control logic automatically process Program/Erase procedures. device programmed byte-by-byte basis after performing Erase operation. addition Block Erase operation, Chip Erase feature provided mode that allows whole memory erased single Erase operation. A49LF040A provides status detection such Data Polling (I/O7) Toggle (I/O6) Functions both FWH/LPC modes. process completion Program Erase operations detected reading status bits. A49LF040A offered 32-lead TSOP 32-lead PLCC packages with optional environmental friendly leadfree package. Figures assignments Table descriptions.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040
Configurations Figure Assignments 32-Lead PLCC
LCLK GPI2 GPI3 GPI4
GPI1 GPI0 LAD0
I/O0
MODE I/O7
MODE INIT LFRAME
32-lead PLCC View
I/O1
I/O2
I/O3
I/O4
I/O5
LAD1
LAD2
LAD3
Figure Assignments 32-Lead TSOP
MODE GPI4 LCLK GPI3 GPI2 GPI1 GPI0 MODE I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 INIT LFRAME LAD3 LAD2 LAD1 LAD0
I/O6
32-lead TSOP (8MM 14MM) View
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Block Diagram
INIT LAD[3:0] LCLK LFRAME ID[3:0] GPI[4:0] A[10:0] I/O7 I/O0 Mode Mode Interface High Voltage Generator Data Latch FWH/LPC Mode Interface Control Logic Input/Output Buffers
Address Latch
Y-Decoder
Y-Gating
X-decoder
Cell Matrix
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Table Description
Interface
Symbol A10-A0 I/O7-I/O0
Name Address Data Output Enable Write Enable Interface Mode Select
Type
Descriptions Inputs addresses during Read Write operations mode. column addresses latched pin. output data during Read cycle receive input data during Write cycle mode. outputs tri-state when high. control data output buffers. control Write operations. determine which interface operational. When held high, mode enabled when held low, mode enabled. This must setup power-up before return from reset change during device operation. This internally pulled down with resistor between 20-100 This second reset in-system use. INIT pins internally combined initialize device reset when driven low. These four pins part mechanism that allows multiple devices attached same bus. identify component, correct strapping these pins must set. boot device must have ID[3:0]=0000 recommended that subsequent devices should sequential up-count strapping. These pins internally pulled down with resistor between 20100 These individual inputs used additional board flexibility. state these pins read immediately boot, through internal registers. These inputs should their desired state before start clock cycle during which read attempted, should remain place until Read cycle. Unused pins must floated.
MODE
INIT
Initialize
ID[3:0]
Identification Inputs
GPI[4:0]
General Purpose Inputs
LAD[3:0] LCLK LFRAME
Block Lock Interface I/Os Clock Frame Reset Write Protect Row/Column Select Ready/Busy Reserved Power Supply Ground Connection
prevent write operations Boot Block when driven low, regardless state block lock registers. When high disables hardware write protection Boot Block. This cannot left unconnected. Communications mode. provide clock input device. This same that clock adheres specifications. indicate start data transfer operation. LFRAME also used abort cycle progress. reset operation device When low, prevents write operations highest addressable block. When high disables hardware write protection these blocks. This cannot left unconnected. This determines whether address pins pointing addresses column addresses mode. This used determine device busy write operations. Valid only mode.
Reserved. These pins must left unconnected. provide power supply (3.0-3.6Volt). Circuit ground. pins must grounded. Unconnected pins.
Notes: IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Temperature Under Bias -55°C 125°C Storage Temperature -65°C 125°C D.C. Voltage Pins with Respect Ground -0.5V 0.5V Package Power Dissipation Capability (Ta=25°C) -0.5V 0.5V Output Short Circuit Current 50mA
Absolute Maximum Ratings*
*Comments
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage this device. These stress ratings only. Functional operation this device these other conditions above those indicated operational sections these specifications implied intended. Exposure absolute maximum rating conditions extended periods affect device reliability.
Notes:
Minimum voltage input pins -0.5V. During voltage transitions, input pins undershoot -2.0V periods 20ns. Maximum voltage input pins 0.5V. During voltage transitions, input pins overshoot 2.0V periods 20ns. more than output shorted time. Duration short circuit should greater than second.
Operating Ranges Commercial Devices Ambient Temperature (TA) +85°C Supply Voltages devices +3.0V +3.6V Operating ranges define those limits between which functionally device guaranteed.
MODE SELECTION
A49LF040A flash memory devices operate distinct interface modes: Count Interface (LPC) mode Address/Address Multiplexed (A/A Mux) mode. Mode used interface mode selection. Mode logic High, device mode; while Mode Low, device mode. Mode must configured prior device operation. Mode internally pulled down connected. mode, device configured interface with host using Intel's Count proprietary protocol. Communication between Host A49LF040A occurs 4-bit communication signals, LAD[3:0] LFRAME mode, device programmed 11-bit address A10-A0 8-bit data I/O7-I/O0. address inputs multiplexed column selected control signal pin. column addresses mapped higher internal addresses, addresses mapped lower internal addresses. Device Memory Maps Figure address assignment.
Read Operation
Read operations read from memory cells specific registers device. valid Read operation starts when LFRAME LCLK rises START value "0000b" LAD[3:0] then next nibble "010X" LAD[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Read operations. Refer Table Read Cycle Definition.
Write Operation
Write operations write Interface registers. valid Write operation starts when LFRAME LCLK rises START value "0000b" LAD[3:0] then next nibble "011X" LAD[3:0]. Addresses data transferred from device decided series "fields". Field sequences contents strictly defined Write operations. Refer Table write Cycle Definition.
MODE OPERATION
interface consists four data signals (LAD[3:0]), control signal LFRAME clock (LCLK). data signals, control signal clock comply with specifications. Operations such Memory Read Memory Write Intel propriety protocol. JEDEC Standard (Software Data Protection) Byte-Program Block-Erase command sequences incorporated into memory cycles. Chip-Erase command only available mode. addresses data transferred through LAD[3:0] synchronized with input clock LCLK during memory cycle. pulse LFRAME inserted least clock period indicate start memory cycle. address data LAD[3:0] latched rising edge LCLK. device enters standby mode when LFRAME high internal operation progress. device ready mode when LFRAME activity bus.
Abort Operation
LFRAME driven more clock cycles during cycle, cycle will terminated device will wait ABORT command. host drive LAD[3:0] with "1111b" (ABORT command) return device Ready mode. abort occurs during Write operation such checking operation status with Data Polling (I/O7) Toggle (I/O6) pins, read status cycle will aborted internal write operation will affected. this case, only reset operation initiated INIT terminate Write operation.
Response Invalid Fields
During operations, will explicitly indicate that received invalid field sequences. response specific invalid fields sequences follows:
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040
Table Read Cycle
Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction Comments
START CYCTYPE
0000
LFRAME must active (low) part respond. Only last start field (before LFRAME transitioning high) should recognized. Indicates type cycle. Bits must "01b" memory cycle. indicates type transfer Read. reserved. Address Phase Memory Cycle. protocol supports 32-bit address phase. YYYY nibble entire address. Addresses transferred most-significant nibble first. Table address bits definition Table valid memory address range. this clock cycle, host driven then floats bus. This first part "turnaround cycle."
010X
3-10
ADDRESS
YYYY
TAR0 1111 Then Float Float TAR1 1111(float) Then SYNC DATA DATA 0000 ZZZZ ZZZZ TAR0 1111 Then Float Float TAR1 1111(float) Then
A49LF040A takes control during this cycle.
A49LF040A outputs value "0000b" indicating that data will available during next clock cycle. This field least-significant nibble data byte. This field most-significant nibble data byte. this clock cycle, A49LF040A drives `1's then floats bus. This first part "turnaround cycle".
Host resumes control during this cycle.
Field contents valid rising edge present clock cycle.
Single-Byte Read Waveforms
LCLK
LFRAME#
LAD[3:0]
START CYCTYPE
ADDRESS
TAR0
TAR1
SYNC
DATA
TAR0
TAR1
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Table Write Cycle
Clock Cycle Field Name Field Contents LAD[3:0]1 LAD[3:0] Direction Comments
START CYCTYPE
0000
LFRAME must active (low) part respond. Only last start field (before LFRAME transitioning high) should recognized. Indicates type cycle. Bits must "01b" memory cycle. indicates type transfer Write. reserved. Address Phase Memory Cycle. protocol supports 32-bit address phase. YYYY nibble entire address. Addresses transferred most-significant nibble first. Table address bits definition Table valid memory address range. This field least-significant nibble data byte. This field most-significant nibble data byte. this clock cycle, host driven `1's then floats bus. This first part "turnaround cycle." A49LF040A takes control during this cycle. A49LF040A outputs values "0000b", indicating that received data flash command. this clock cycle, A49LF040A driven `1's then floats bus. This first part "turnaround cycle." Host resumes control during this cycle.
011X
3-10
ADDRESS
YYYY
DATA DATA TAR0 TAR1 SYNC
ZZZZ ZZZZ 1111 1111(float) 0000
then Float Float then then Float Float then
TAR0 TAR1
1111 1111(float)
Field contents valid rising edge present clock cycle.
Write Waveforms
LCLK
LFRAME#
LAD[3:0]
START CYCTYPE
ADDRESS
DATA
TAR0
TAR1
SYNC
TAR0
TAR1
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Address range: A49LF040A will only response address range specified Table Address special function directing reads writes flash memory (A22=1) register space (A22=0). mismatch: A49LF040A will compare bits address field with hardware strapping. there mismatch, device will ignore cycle. Refer Table Multiple Device Selection Configuration detail. Write Operation Status Detection
Device Memory Hardware Write Protection
Boot Lock Write Protect pins provided hardware write protection device memory A49LF040A. used write protect boot block Kbytes) highest flash memory address range A49LF040A. write protects remaining blocks flash memory. active signal prevents Program Erase operations boot block. When held high, write protection boot block then determined Boot Block Locking register. serves same function remaining blocks device memory. pins write protection functions operate independently another. Both pins must their required protection states prior starting Program Erase operation. logic level change occurring during Program Erase operation could cause unpredictable results. pins cannot left unconnected. internally ORed with Boot Block Locking register. When low, Boot Block hardware write protected regardless state WriteLock Boot Block Locking register. Clearing Write-Lock register when will have functional effect, even though register indicate that block longer locked. internally ORed with Block Locking register. When low, blocks hardware write protected regardless state WriteLock corresponding Block Locking registers. Clearing Write-Lock register when will have functional effect, even though register indicate that block longer locked.
A49LF040A device provides software means detect completion Write (Program Erase) cycle, order optimize system Write cycle time. software detection includes status bits: Data Polling (I/O7) Toggle (I/O6). End-of-Write detection mode incorporated into Read cycle. actual completion nonvolatile write asynchronous with system; therefore, either Data Polling Toggle read simultaneous with completion Write cycle. this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid.
Data Polling (I/O7)
When A49LF040A device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Proper status will given using Data Polling address invalid range.
Toggle (I/O6)
During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop.
Reset
INIT initiates device reset. INIT pins have same function internally. required drive INIT pins during system reset ensure proper initialization. During Read operation, driving INIT pins deselects device places output drivers, LAD[3:0], high-impedance state. reset signal must held minimal duration time TRSTP. reset latency will occur reset procedure performed during Program Erase operation. Table Reset Timing Parameters more information. device reset during active Program Erase will abort operation memory contents become invalid data being altered corrupted from incomplete Erase Program operation. this case, device take TRSTE abort Program Erase operation. PRELIMINARY (March, 2006, Version 0.1)
Multiple Device Selection
four pins, ID[3:0], allow multiple devices attached same using different strapping system. When A49LF040A used boot device, ID[3:0] must strapped 0000, subsequent devices should sequential up-count strapping (i.e. 0001, 0010, 0011, etc.). bits address field inverse hardware strapping. address bits [A23, A21:A19] A49LF004 used select device with proper IDs. Table IDs. A49LF040A will compare strapping values, there mismatch, device will ignore remainder cycle into standby mode. Since there support mode, program multiple devices stand-alone PROM programmer recommended.
AMIC Technology, Corp.
A49LF040
REGISTERS
There types registers available A49LF040A, General Purpose Inputs Register, JEDEC Registers. These registers appear their respective address location GByte system memory map. Unused register locations will read 00H. attempt read write register during internal Write operation will ignored. Refer Table register memory map.
Write-Lock. Write-Lock determines whether contents Block modified (using Program Erase Command). When Write-Lock `1', block write protected; operations that attempt change data block will fail Status Register will report error. When Write-Lock reset `0', block write protected through Locking Register modified unless write protected through some other means. Block Lock, Low, VIL, then Block (Block write protected cannot modified. Similarly, Write Protect, Low, VIL, then Main Blocks (Blocks write protected cannot modified. After power-up reset Write-Lock always (write protected). Read-Lock. Read-Lock determines whether contents Block read (from Read mode). When Read-Lock `1', block read protected; operation that attempts read contents block will read instead. When Read-Lock reset `0', read operations Block return data programmed into block expected. After power-up reset ReadLock always reset (not read protected). Lock-Down. Lock-Down provides mechanism protecting software data from simple hacking malicious attack. When Lock-Down `1', further modification Write-Lock, Read-Lock Lock-Down Bits cannot performed. reset power-up required before changes these bits made. When LockDown reset `0', Write-Lock, Read-Lock LockDown Bits changed.
General Purpose Inputs Register
GPI_REG (General Purpose Inputs Register) passes state GPI[4:0] pins power-up A49LF040A. recommended that GPI[4:0] pins desired state before LFRAME brought beginning next cycle, remain that state until cycle. There default value since this pass-through register. Table GPI_REG bits function, Table memory address locations respective device strapping.
Table General Purpose Inputs Register
Name Function Number 32-PLCC 32-TSOP
GPI[4] GPI[3] GPI[2] GPI[1] GPI[0]
Reserved GPI_REG GPI_REG GPI_REG GPI_REG GPI_REG
JEDEC Registers Block Locking Registers
A49LF040A provides software controlled lock protection through Block Locking registers. Block Locking Registers read/write registers accessible through standard addressable memory locations specified Table Table definition Block Lock Register.
JEDEC registers identify device A49LF040A manufacturer AMIC mode. Table memory address locations respective JEDEC location.
Table Address Definition
A31:A23 A21:A19 A18:A0
1111 1111b
ID[3]
Memory access Register access
ID[2:0]
Device memory address
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Table Address Decoding Range
Strapping Device Access A21:A19 Memory Size
Device Device
Memory Access Register Access Memory Access Register Access
FFFF FFFFH: FFC0 0000H FFBF FFFFH: FF80 0000H FF7F FFFFH: FF40 0000H FF3F FFFFH: FF00 0000H
MByte MByte MByte MByte
Table Multiple Device Selection Configurations
Device# Hardware Strapping ID[3:0] Address Bits Decoding
(Boot device)
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Table Register Memory (Boot Device)
Memory Address Mnemonic Register Name Default Type
FFBF0002h FFBE0002h FFBD0002h FFBC0002h FFBB0002h FFBA0002h FFB90002h FFB80002h FFBC0100h FFBC0000h FFBC0001h FFBC0003h
T_BLOCK_LK T_MINUS01_LK T_MINUS02_LK T_MINUS03_LK T_MINUS04_LK T_MINUS05_LK T_MINUS06_LK T_MINUS07_LK GPI_REG MANUF_REG DEV_REG CONT_REG
Block Lock Register (Block Block [-1] Lock Register (Block Block [-2] Lock Register (Block Block [-3] Lock Register (Block Block [-4] Lock Register (Block Block [-5] Lock Register (Block Block [-6] Lock Register (Block Block [-7] Lock Register (Block General Purpose Input Register Manufacturer Register Device Register Continuation Register
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Table Lock Register Definition
Data Reserved Read-Lock Lock-Down Write-Lock Function
00000 00000 00000 00000 00000 00000 00000 00000
Full Access. Write locked. Default state power-up. Locked open (full access locked down). Write-locked down. Read locked. Read Write locked. Read-locked down Read- Write-locked down
Data
Function Reserved Read-Lock
Prevents read operations block where Normal operation reads block where clear. This default state.
Lock-Down
Prevents further clear operations Write-Lock Read-Lock bits. Lock-Down only clear. block will remain lock-down until reset (with INIT being Low), until device power-on reset. Normal operation Write-Lock Read-Lock altering block where clear. This default state.
Write-Lock
Prevents program erase operations block where set. This default state. Normal operation programming erase block where clear.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
ADDRESS/ADDRESS MULTIPLEXED (A/A MUX) MODE Device Operation
Commands used initiate memory operation functions device. data portion software command sequence latched rising edge During software command sequence address latched falling edge column address latched rising edge Refer Table Table operation modes command sequence.
Byte-Program Operation
A49LF040A device programmed byte-by-byte basis. Before programming, must ensure that block, which byte which being programmed exists, fully erased. Byte-Program operation initiated executing four-byte command load sequence Software Data Protection with address data last byte sequence. During Byte-Program operation, address (A10-A0) latched falling edge column Address (A18-A11) latched rising edge data latched rising edge Figure Program operation timing diagram, Figure timing waveforms, Figure flowchart. During Program operation, only valid reads Data Polling Toggle Bit. During internal Program operation, host free perform additional tasks. commands written during internal Program operation will ignored.
Read
Read operation A49LF040A device controlled output control used gate data from output pins. Refer Read cycle timing diagram, Figure further details.
Reset
initiates device reset. Table Mode Operation Selection
Mode
Address
Read Write Standby Output Disable Reset Product Identification
VIL, VIL, VIH,
DOUT High High High Manufacturer Device Continuation
Block-Erase Operation
Block-Erase Operation allows system erase device KByte uniform block size A49LF040A. Block-Erase operation initiated executing six-byte command load sequence Software Data Protection with Block-Erase command (30H 50H) block address. internal Block-Erase operation begins after sixth pulse. End-of-Erase determined using either Data Polling Toggle methods. Figure timing waveforms. commands written during Block- Erase operation will ignored.
Protection command sequence with Chip-Erase command (10H) with address 5555H last byte sequence. internal Erase operation begins with rising edge sixth During internal Erase operation, only valid read Toggle Data Polling. Table command sequence, Figure timing diagram, Figure flowchart. commands written during Chip-Erase operation will ignored.
Write Operation Status Detection
A49LF040A device provides software means detect completion Write cycle, order optimize system Write cycle time. software detection includes status bits: Data Polling (I/O7) Toggle (I/O6). End-of-Write detection mode enabled after rising edge which initiates internal Write operation. actual completion nonvolatile write asynchronous with system; therefore, either Data Polling Toggle read simultaneous with completion Write cycle.
Chip-Erase
A49LF040A device provides Chip-Erase operation only mode, which allows user erase entire memory array `1's state. This useful when entire device must quickly erased. Chip-Erase operation initiated executing six-byte Software Data
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
this occurs, system possibly erroneous result, i.e., valid data appear conflict with either I/O7 I/O6. order prevent spurious rejection, erroneous result occurs, software routine should include loop read accessed location additional times. both reads valid, then device completed Write cycle, otherwise rejection valid. addition I/O6 I/O7 detect write status, also available detect Program Erase operation. actively pulled (VIL) during internal write cycles released high (VIH) completion cycle.
Hardware Data Protection
Noise/Glitch Protection: pulse less than will initiate Write cycle. Power Up/Down Detection: Write operation inhibited when less than 1.5V. Write Inhibit Mode: Forcing low, high will inhibit Write operation. This prevents inadvertent writes during power-up power-down.
Software Data Protection (SDP)
Data Polling (I/O7)
When A49LF040A device internal Program operation, attempt read I/O7 will produce complement true data. Once Program operation completed, I/O7 will produce true data. Note that even though I/O7 have valid data immediately following completion internal Write operation, remaining data outputs still invalid: valid data entire data will appear subsequent successive Read cycles after interval During internal Erase operation, attempt read I/O7 will produce `0'. Once internal Erase operation completed, I/O7 will produce `1'. Data Polling valid after rising edge fourth pulse Program operation. Block- Chip-Erase, Data Polling valid after rising edge sixth pulse. Figure Data Polling timing diagram. Proper status will given using Data Polling address invalid range.
Toggle (I/O6)
A49LF040A provides JEDEC approved Software Data Protection scheme data alteration operation, i.e., Program Erase. Program operation requires inclusion series three-byte sequences. three-byte load sequence used initiate Program operation, providing optimal protection from inadvertent Write operations, e.g., during system power-up power-down. Erase operation requires inclusion six-byte load sequence. A49LF040A device shipped with Software Data Protection permanently enabled. Table specific software command codes. During command sequence, invalid commands will abort device Read mode, within TRC.
Electrical Specifications
specifications Interface signals (LAD[3:0], LCLK, LFRAME defined Section 4.2.2 Local Specification, Rev. 2.1. Refer Table voltage current specifications. Refer specifications Table Table Clock, Read/Write, Reset operations.
Product Identification
product identification mode identifies Manufacturer Continuation Device A49LF040A. Table detail information.
During internal Program Erase operation, consecutive attempts read I/O6 will produce alternating `0's `1's, i.e., toggling between When internal Program Erase operation completed, toggling will stop. device then ready next operation. Toggle valid after rising edge fourth pulse Program operation. Block- Chip-Erase, Toggle valid after rising edge sixth pulse. Figure Toggle timing diagram.
Data Protection
A49LF040A device provides both hardware software features protect nonvolatile data from inadvertent writes.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Figure System Memory Device Memory A49LF040A
Visio.Drawing.6
A49LF040A Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes) Block (64K Bytes)
Device Memory 07FFFF 070000 06FFFF 060000 05FFFF 050000 04FFFF 040000 03FFFF 030000 02FFFF 020000 01FFFF 010000 00FFFF 000000
Table Software Data Protection Command Definition
Command Block Erase Chip Erase
Cycles
Cycle Addr
Cycle Data
Cycle Addr
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H
Cycle Addr
YYYY 5555H YYYY 5555H
Cycle Addr
YYYY 2AAAH YYYY 2AAAH
Cycle Addr
BA(4) YYYY 5555H
Data
Addr
YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH YYYY 2AAAH
Data
Data
Data
Data
30H/50H(5)
YYYY 5555H YYYY 5555H YYYY 5555H YYYY 5555H XXXX XXXXH YYYY 5555H
Byte Program Product Entry Product Exit Product Exit
YYYY 2AAAH
YYYY 5555H
Notes: Mode uses consecutive Write cycles complete command sequence; Mode uses consecutive cycles complete command sequence. YYYY A[31:16]. mode, during command sequence, YYYY must within memory address range specified Table mode, YYYY VIH, other value. Chip erase available Mode only. Block Erase Address. Either acceptable Block Erase. Program Byte Address; Byte data programmed. Both Product Exit commands equivalent.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Operating Range Range Ambient Temperature Conditions Test
Input Rise/Fall Time Output Load 30pF
Commercial
+85°C
3.0-3.6V
Table Operating Characteristics (All Interfaces)
Limits Symbol Parameter Units Test Conditions
Active Current: Read Active Current: Write IRY(2) VIHI(3) VILI(3)
-0.5 0.5VDD -0.5 0.9VDD VDD+0.5 VDD+0.5 0.3VDD 0.1VDD
Address Input=VIL/VIH, F=1/TRCMin, VDD=VDDMax(A/A Mode) =VIH, =VIH LFRAME =0.9VDD, f=33MHz, VDD=VDDMax, other inputs 0.9VDD 0.1VDD LFRAME =VIL, f=33MHz, VDD=VDDMax, other inputs 0.9VDD 0.1VDD VIN=0V VDD, VDD=VDDMax VIN=0V VDD, VDD=VDDMax VOUT=0V VDD, VDD=VDDMax VDD=VDDMax VDD=VDDMin VDD=VDDMax VDD=VDDMin IOL=1500µA, VDD=VDDMin IOH=-500µA, VDD=VDDMin
Standby Current (LPC Mode) Ready Mode Current (LPC Mode) Input Current Mode ID[3:0] Pins Input Leakage Current Output Leakage Current
INIT Input High Voltage INIT Input Voltage
Input High Voltage Input Voltage Output Voltage Output High Voltage
Notes: active while Erase Program progress. device Ready Mode when activity bus. violate processor chipset specification regarding INIT voltage.
Table Recommended System Power-Up Timings
Symbol Parameter Units
TPU-READ(1) TPU-WRITE
Power-up Read Operation Power-up Write Operation
Notes: This parameter measured only initial qualification after design process change that could affect this parameter.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.
A49LF040A
Table Impedance (VDD=3.3V, Ta=25°C, f=1MHz, other pins open)
Parameter Description Test Condition
CI/O
Capacitance Input Capacitance Inductance
VI/O
12pF 12pF 20nH
LPIN
Notes: This parameter measured only initial qualification after design process change that could affect this parameter. Refer specifications.
Table Clock Timing Parameters
Symbol Parameter Units
TCYC THIGH TLOW
LCLK Cycle Time LCLK High Time LCLK Time LCLK Slew Rate (peak-to-peak)
V/ns
Figure LCLK Waveform
TCYC THIGH Peak-to-Peak (Min) TLOW
Table Mode Read/Write Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TVAL TOFF
Parameter
Input Time LCLK Rising LCLK Rising Data Hold Time LCLK Rising Data Valid LCLK Rising Active (Float Active Delay) LCLK Rising Inactive (Active Float Delay)
Units
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A49LF040A
Table Mode Interface Measurement Condition Parameters
Symbol
VTEST VMAX Input Signal Edge Rate
Value
1V/ns
Units
Figure Input Timing Parameters
LCLK VTEST LAD[3:0] (Valid Input Data) Valid Inputs VMAX
Figure Output Timing Parameters
LCLK VTEST TVAL LAD[3:0] (Valid Output Data)
LAD[3:0] (Float Output Data) TOFF
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A49LF040A
Table Mode Interface Input/Output Characteristics
Symbol Parameter Test Conditions
VOUT 0.3VDD (AC) Switching Current High (Test Point) (AC) Switching Current (Test Point) slewr slewf Clamp Current High Clamp Current Output Rise Slew Rate Output Fall Slew Rate 0.3VDD VOUT 0.9VDD 0.7VDD VOUT VOUT 0.7VDD VOUT 0.6VDD 0.6VDD VOUT 0.1VDD 0.18VDD VOUT VOUT=0.18VDD VDD+4 VDD+1 0.2VDD-0.6VDD load 0.6VDD-0.2VDD load -25+(VIN+1)/0.015 25+(VIN-VDD-1)/0.015 16VDD 26.7VOUT Equation 38VDD
-17.1(VDD-VOUT)
Units
Equation
V/ns V/ns
Notes: specification. specification output load used.
Table Mode Interface Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TKRST TRSTP TRSTF TRST
Parameter
Stable Reset Clock Stable Reset Pulse Width Output Float High LFRAME Reset During Erase Program INIT Slew Rate
Units
TRSTE
mV/ns
Notes: There will latency TRSTE reset procedure performed during Program Erase operation.
Figure Reset Timing Diagram
LCLK TKRST RST/INIT TRSTF LAD[3:0] TRSTE TRST
Program Erase Operation Aborted
TPRST
TRSTP
LFRAME
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Figure Mode Input/Output Reference Waveforms
VIHT INPUT VILT test inputs driven VIHT (0.9VDD) logic HIGH VILT (0.1VDD) logic LOW. Measurement reference points inputs outputs (0.5VDD) (0.5VDD). Input rise fall times (10% 90%) Note: VINPUT Test VOUTPUT Test IHT: VINPUT HIGH Test ILT: VINPUT Test Reference Points OUTPUT
Figure Mode Test Load Condition
TESTER
CL=30pF
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A49LF040A
MODE CHARACTERISTICS Table Read Cycle Timing Parameters VDD=3.0-3.6V
Symbol
TRST TOLZ TOHZ
Parameter
Read Cycle Time High Address Setup Address Set-up Time Address Hold Time Address Access Time Output Enable Access Time Active Output High High-Z Output Output Hold from Address Change
Units
Table Program/Erase Cycle Timing Parameters, VDD=3.0-3.6V
Symbol
TRST TCWH TOES TOEH TOEP TOET TWPH TIDA TSCE
Parameter
High Address Setup Address Setup Time Address Hold Time Write Enable High Time High Setup Time High Hold Time Data Polling Delay Toggle Delay
Pulse Width Pulse Width High
Units
Data Setup Time Data Hold Time Product Access Exit Time Byte Programming Time Block Erase Time Chip Erase Time
Table Reset Timing Parameters, VDD=3.0-3.6V
Symbol
TPRST TRSTP TRSTF TRST
Parameter
Stable Reset Pulse Width Output Float High LFRAME
Units
TRSTE Reset During Erase Program Notes: There will reset latency TRSTE reset procedure performed during Program Erase operation.
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A49LF040A
Figure Mode Read Cycle Timing Diagram
TRSTP
TRST
Address
Column Address Address Column Address
Address
High-Z TOLZ
Data Valid
TOHZ High-Z
I/O7-I/O0
Figure Mode Write Cycle Timing Diagram
TRSTP
TRST
Address Column Address
Address
TCWH TOES
TOEH TWPH
I/O7-I/O0 High-Z
Data Valid
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A49LF040A
Figure Mode Data Polling Timing Diagram
Address Column Address Address Column Address Address Column Address Address Column Address
Address
TOEP High-Z
I/O7
Data
Data#
Data#
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
Figure Mode Toggle Timing Diagram
Address
Address Column Address Address Column Address Address Column Address Address Column Address
TOET High-Z
I/O6
Data
Data
Final Input Command
Status
Status
Data
Command Input
Write Operation Progress
Write Operation Complete
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A49LF040A
Figure Mode Byte Program Timing Diagram
Four-Byte Byte Program Command Sequence 5555 Address 2AAA 5555
TWPH
High-Z
I/O7-I/O0
Byte Program Command Input Byte Program Address Byte Program Data
Byte Program Operation Progress
Figure Mode Block Erase Timing Diagram
Six-Byte Block Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA
TWPH
High-Z
30/50
I/O7-I/O0
Block Erase Command Input Block Address
Block Erase Operation Progress
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A49LF040A
Figure Mode Chip Erase Timing Diagram
Six-Byte Chip Erase Command Sequence 5555 Address 2AAA 5555 5555 2AAA 5555
TWPH
TSCE
High-Z
I/O7-I/O0
Chip Erase Command Input
Chip Erase Operation Progress
Figure Mode Product Entry Read Timing Diagram
Three-Byte Product Entry Command Sequence 5555 Address 2AAA 5555 0000 0001 0003
TWPH
TIDA
High-Z
I/O7-I/O0
Figure Mode Product Exit Reset Timing Diagram
Three-Byte Product Exit Reset Command Sequence 5555 Address 2AAA 5555
TWPH
High-Z
I/O7-I/O0
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Figure Automatic Byte Program Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: Data:
I/O7 Data I/O6 Stop Toggle?
Byte Program Completed
Byte Program Address Byte Program Data
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A49LF040A
Figure Automatic Block Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: Data:
Block Erase Completed
Block Address
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Figure Automatic Chip Erase Algorithm
Start
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
I/O7 Data I/O6 Stop Toggle?
Write Command Address: 5555H Data:
Chip Erase Completed
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A49LF040A
Figure Product Command Flowchart
Start
Start
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: 2AAAH Data:
Write Command Address: 2AAAH Data:
Write Command Address: 5555H Data:
Write Command Address: 5555H Data:
Write Command Address: XXXXH Data:
Enter Product Mode
Exit Product Mode
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A49LF040A
Ordering Information
A49LF040AT
Package Type
Pb-Free
Clock Frequency
33MHz
Package Type
PLCC TSOP (8mmX14mm)
Device Number
Mbit Flash Memory
Part
Clock Frequency (MHz)
Boot Block Location
Temperature Range
+85°C
Package Type
A49LF040ATL-33
32-pin PLCC
A49LF040ATL-33F
+85°C +85°C +85°C
32-pin Pb-Free PLCC 32-pin TSOP (8mm 32-pin Pb-Free TSOP (8mm
A49LF040ATX-33
A49LF040ATX-33F
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A49LF040A
Package Information
PLCC Outline Dimension
unit: inches/mm
Dimensions inches
Dimensions 0.47 2.67 0.66 0.41 0.20 13.89 11.35 1.12 12.45 9.91 14.86 12.32 1.91 2.80 0.71 0.46 0.254 13.97 11.43 1.27 12.95 10.41 14.99 12.45 2.29 3.40 2.93 0.81 0.54 0.35 14.05 11.51 1.42 13.46 10.92 15.11 12.57 2.41 0.075
Symbol
0.0185 0.105 0.026 0.016 0.008 0.547 0.447 0.044 0.490 0.390 0.585 0.485 0.075
0.110 0.028 0.018 0.010 0.550 0.450 0.050 0.510 0.410 0.590 0.490 0.090
0.134 0.115 0.032 0.021 0.014 0.553 0.453 0.056 0.530 0.430 0.595 0.495 0.095 0.003
Notes: Dimensions include resin fins. Dimensions Board surface mount pitch design reference only.
PRELIMINARY (March, 2006, Version 0.1)
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A49LF040A
Package Information
TSOP TYPE 14mm) Outline Dimensions
unit: inches/mm
Pin1
0.254 Gage Plane Detail
Detail
Dimensions inches Symbol 0.002 0.037 0.0067 0.004 0.311 0.543 0.484 0.020 0.000 0.039 0.0087 0.315 0.0197 0.551 0.488 0.024 0.047 0.006 0.041 0.0106 0.0083 0.319 0.559 0.492 0.028 0.003
Dimensions 0.05 0.95 0.17 0.10 7.90 13.80 12.30 0.50 0.00 1.00 0.22 8.00 0.50 14.00 12.40 0.60 1.20 0.15 1.05 0.27 0.21 8.10 14.20 12.50 0.70 0.076
Notes: Dimension does include mold flash. Dimension does include interlead flash. Dimension does include dambar protrusion.
PRELIMINARY (March, 2006, Version 0.1)
AMIC Technology, Corp.

Document Title Mbit CMOS Volt-only Count Flash Memory Revision History

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