X1228 (512 2-WireRTC 2006 FN8100.4 Real Time Clock/Cale
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2028 Data Sheet
X1228
(512 2-WireRTC
2006 FN8100.4
Real Time Clock/Calendar/CPU Supervisor with EEPROM
FEATURES
Real Time Clock/Calendar Tracks Time Hours, Minutes, Seconds Week, Day, Month, Year Polled Alarms (Non-volatile) Settable Second, Minute, Hour, Week, Day, Month Repeat Mode (periodic interrupts) Oscillator Compensation Chip Internal Feedback Resistor Compensation Capacitors Position Digitally Controlled Trim Capacitor Digital Frequency Adjustment Settings ±30ppm Supervisor Functions Power-On Reset, Voltage Sense Watchdog Timer Selectable: 0.25s, 0.75s, 1.75s, off) Battery Switch Super Input Bits EEPROM 64-Byte Page Write Mode Modes Block LockProtection Single Byte Write Capability High Reliability Data Retention: Years Endurance: 100,000 Cycles Byte
2-WireInterface Interoperable with I2C* 400kHz Data Transfer Rate Frequency Output Selectable: Off, 1Hz, 4096Hz, 32.768kHz) Power CMOS 1.25µA Operating Current (Typical) Small Package Options SOIC TSSOP Repetitive Alarms Temperature Compensation Pb-Free Plus Anneal Available (RoHS Compliant)
APPLICATIONS Utility Meters HVAC Equipment Audio/Video Components Box/Television Modems Network Routers, Hubs, Switches, Bridges Cellular Infrastructure Equipment Fixed Broadband Wireless Equipment Pagers/PDA Equipment Test Meters/Fixtures Office Automation (Copiers, Fax) Home Appliances Computer Products Other Industrial/Medical/Automotive
BLOCK DIAGRAM
Compensation
32.768kHz
Oscillator
Frequency Divider
Timer Calendar Logic
Time Keeping Registers (SRAM)
Battery Switch Circuitry
VBACK
PHZ/IRQ
Select Control/ Registers (EEPROM) Status Registers (SRAM) Mask
Serial Interface Decoder
Control Decode Logic
Alarm
Compare Alarm Regs (EEPROM) EEPROM ARRAY
RESET
Watchdog Timer Voltage Reset
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. Rights Reserved other trademarks mentioned property their respective owners.
X1228 Ordering Information
PART NUMBER X1228S14-4.5A X1228S14Z-4.5A (Note) X1228S14I-4.5A X1228S14IZ-4.5A (Note) X1228V14-4.5A X1228V14Z-4.5A (Note) X1228V14I-4.5A X1228V14IZ-4.5A (Note) X1228S14 X1228S14Z (Note) X1228S14I X1228S14IZ (Note) X1228V14 X1228V14Z (Note) X1228V14I X1228V14IZ (Note) X1228S14-2.7A X1228S14Z-2.7A (Note) X1228S14I-2.7A X1228S14IZ-2.7A (Note) X1228V14-2.7A X1228V14Z-2.7A (Note) X1228V14I-2.7A X1228V14IZ-2.7A (Note) X1228S14-2.7* X1228S14Z-2.7* (Note) X1228S14I-2.7 X1228S14IZ-2.7 (Note) X1228V14-2.7 X1228V14Z-2.7 (Note) X1228V14I-2.7 X1228V14IZ-2.7 (Note) PART MARKING X1228S X1228S X1228S X1228S X1228V X1228V X1228V X1228V X1228S X1228S X1228S X1228S X1228V X1228V X1228V X1228V X1228S X1228S X1228S X1228S X1228V X1228V X1228V X1228V X1228S X1228S X1228S X1228S X1228V X1228V X1228V X1228V 2.65V 100mV 2.85V 100mV 4.38V 112mV RANGE VTRIP 4.63V 112mV TEMP RANGE (°C) PACKAGE SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP TSSOP (Pb-free) TSSOP TSSOP (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP TSSOP (Pb-free) TSSOP TSSOP (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb_free) TSSOP TSSOP (Pb-free) TSSOP TSSOP (Pb-free) SOIC SOIC (Pb-free) SOIC SOIC (Pb-free) TSSOP TSSOP (Pb-free) TSSOP TSSOP (Pb-free) PKG. DWG. MDP0027 MDP0027 MDP0027 MDP0027 M14.173 M14.173 M14.173 M14.173 MDP0027 MDP0027 MDP0027 MDP0027 M14.173 M14.173 M14.173 M14.173 MDP0027 MDP0027 MDP0027 MDP0027 M14.173 M14.173 M14.173 M14.173 MDP0027 MDP0027 MDP0027 MDP0027 M14.173 M14.173 M14.173 M14.173
*Add "T1" suffix tape reel. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
FN8100.4 2006
X1228
DESCRIPTIONS
TSSOP/SOIC RESET VBACK PHZ/IRQ
internal connection
ASSIGNMENTS Number SOIC/TSSOP
Symbol
Brief Description
input inverting amplifier. external 32.768kHz quartz crystal used with X1228 supply timebase real time clock. recommended crystal Citizen CFS206-32.768KDZF. Internal compensation circuitry included form complete oscillator circuit. Care should taken placement crystal layout circuit. Plenty ground plane around device short traces highly recommended. Application section more recommendations. output inverting amplifier. external 32.768kHz quartz crystal used with X1228 supply timebase real time clock. recommended crystal Citizen CFS206-32.768KDZF. Internal compensation circuitry included form complete oscillator circuit. Care should taken placement crystal layout circuit. Plenty ground plane around device short traces highly recommended. Application section more recommendations. RESET Output RESET. This reset signal output. This signal notifies host processor that watchdog time period expired that voltage dropped below fixed VTRIP threshold. open drain active output. Recommended value pullup resistor unused, ground. VSS. Serial Data (SDA). bidirectional used transfer data into device. open drain output wire ORed with other open drain open collector outputs. input buffer always active (not gated). open drain output requires pull-up resistor. output circuitry controls fall time output signal with slope controlled pull-down. circuit designed 400kHz 2-wire interface speeds. Serial Clock (SCL). input used clock data into device. input buffer this always active (not gated). Programmable Frequency/Interrupt Output PHZ/IRQ. This either output from internal oscillator interrupt signal output. CMOS output. When used frequency output, this signal frequency 32.768kHz, 4096Hz, inactive. When used interrupt output, this signal notifies host processor that alarm occurred action required. active output. control bits this function found address 0011h Clock Control Memory map. "Programmable Frequency Output Bits-FO1, FO0" page VBACK. This input provides backup supply voltage device. VBACK supplies power device event supply fails. This connected battery, Supercap tied ground used. VCC.
RESET
PHZ/IRQ
VBACK
FN8100.4 2006
X1228
ABSOLUTE MAXIMUM RATINGS Temperature Under Bias -65°C +135°C Storage Temperature -65°C +150°C Voltage VCC, VBACK PHZ/IRQ (respect ground) .-0.5V 7.0V Voltage SCL, SDA, (respect ground) -0.5V 7.0V 0.5V above VBACK (whichever higher) Output Current Lead Temperature (Soldering, sec) 300°C Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
OPERATING CHARACTERISTICS (Temperature -40°C +85°C, unless otherwise stated.) Symbol
VBACK
Parameter
Main Power Supply Backup Power Supply Switch Backup Supply Switch Main Supply
Conditions
VBACK -0.2 VBACK
VBACK -0.1 VBACK +0.2
Unit
Notes
OPERATING CHARACTERISTICS Symbol
ICC1 ICC2 ICC3
Parameter
Read Active Supply Current Program Supply Current (nonvolatile) Main Timekeeping Current Timekeeping Current (Low Voltage Sense Watchdog Timer disabled Input Leakage Current Output Leakage Current Input Voltage Input HIGH Voltage Schmitt Trigger Input Hysteresis Output Voltage RESET Output Voltage PHZ/IRQ Output HIGH Voltage PHZ/IRQ
Conditions
2.7V 5.0V 2.7V 5.0V 2.7V 5.0V VBACK 1.8V VBACK 3.3V
Unit
Notes
"See Performance Data"
1.25 -0.5 VBACK VBACK VBACK
IBACK VHYS VOL1 VOL2 VOH2
related level 2.7V 5.5V 2.7V 5.5V 2.7V 5.5V
VBACK
FN8100.4 2006
X1228
Notes: device enters Active state after start, remains active: clock cycles Device Select Bits Slave Address Byte incorrect until 200nS after stop ending read write operation. device enters Program state 200nS after stop ending write operation continues tWC. device goes into Timekeeping state 200nS after stop, except those that initiate nonvolatile write cycle; after stop that initiates nonvolatile write cycle; clock cycles after start that followed correct Device Select Bits Slave Address Byte. reference only tested. 0.1, 0.9, fSCL 400kHz VBACK VSDA VSCL=VCC, Others VSDA =VSCL=VBACK, Others VBACK (10) VSDA VCC, VSCL VCC, VRESET (11) 3.0mA 5.5V, 1.5mA 2.7V (12) -1.0mA 5.5V, -0.4mA 2.7V (13) Threshold voltages based higher Vback. (14) Using recommended crystal oscillator network applied (25°C). (15) Typical values 25°C
Capacitance 25°C, MHz, Symbol
COUT
Parameter
Output Capacitance (SDA, PHZ/IRQ, RESET) Input Capacitance (SCL)
Max.
Units
Test Conditions
VOUT
CIN(1)
Notes: This parameter 100% tested. input capacitance between pins varied between 19.75pF using analog trimming registers
CHARACTERISTICS Test Conditions
Input Pulse Levels Input Rise Fall Times Input Output Timing Levels Output Load 10ns Standard Output Load
Figure Standard Output Load testing device with 5.0V Equivalent Output Load Circuit
5.0V VOL= 0.4V PHZ/IRQ 100pF 100pF 5.0V
1533
1316
FN8100.4 2006
X1228
Specifications -40°C +85°C, +2.7V +5.5V, unless otherwise specified.) Symbol
fSCL tBUF tLOW tHIGH tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO Clock Frequency Pulse width Suppression Time inputs Data Valid Time must free before transmission start Clock Time Clock HIGH Time Start Condition Setup Time Start Condition Hold Time Data Setup Time Data Hold Time Stop Condition Setup Time Data Output Hold Time Rise Time Fall Time Capacitive load each line 50(1) +.1Cb(2) +.1Cb(2)
Parameter
Min.
Max.
Units
Notes: This parameter 100% tested. total capacitance line
TIMING DIAGRAMS Timing
tSU:STA tHD:STA tSU:DAT tHD:DAT tSU:STO tHIGH tLOW
tBUF
FN8100.4 2006
X1228
Write Cycle Timing
Last Byte
Stop Condition Start Condition
Power-up Timing Symbol
tPU(1)
Parameter
Time from Power-up Read Time from Power-up Write
Min.
Typ.(2)
Max.
Units
tPUW
Notes: Delays measured from time stable until specified operation initiated. These parameters 100% tested. slew rate should between 0.2mV/µsec 50mV/µsec. Typical values 25°C 5.0V
Nonvolatile Write Cycle Timing Symbol
tWC(1)
Note:
Parameter
Write Cycle Time
Min.
Typ.(1)
Max.
Units
time from valid stop condition write sequence self-timed internal nonvolatile write cycle. minimum cycle time allowed nonvolatile write user, unless Acknowledge Polling used.
WATCHDOG TIMER/LOW VOLTAGE RESET OPERATING CHARACTERISTICS Watchdog/Low Voltage Reset Parameters (SeeFigures Symbols
VPTRIP
Parameters
Programmed Reset Trip Voltage X1228-4.5A X1228 X1228-2.7A X1228-2.7 Detect RESET Power-up Reset Time-out Delay Fall Time Rise Time Watchdog Timer Period (Crystal 32.768kHz): Watchdog Reset Time-out Delay (Crystal=32.768kHz) 2-Wire interface Reset Valid
Min.
4.50 4.25 2.75 2.55
Typ.
4.63 4.38 2.85 2.65
Max.
4.75 4.50 2.95 2.75
Unit
tRPD tPURST tWDO tRST tRSP VRVALID
1.75
FN8100.4 2006
X1228
VTRIP Programming Timing Diagram
(VTRIP) VTRIP tTSU tTHD
RESET
tVPS tVPH tVPO
03h/01h
VTRIP Programming Parameters Parameter
tVPS tVPH tTSU tTHD tVPO VTRAN
Description
VTRIP Program Enable Voltage Setup time VTRIP Program Enable Voltage Hold time VTRIP Setup time VTRIP Hold (stable) time VTRIP Program Enable Voltage time (Between successive adjustments) VTRIP Program Recovery Period (Between successive adjustments) Programming Voltage VTRIP Programmed Voltage Range VTRIP Program variation after programming (Programmed 25°C)
Min.
Max.
Units
VTRIP programming parameters 100% Tested.
FN8100.4 2006
X1228
DESCRIPTION X1228 device Real Time Clock with clock/calendar, polled alarms with integrated 512x8 EEPROM, oscillator compensation, Supervisor (POR/LVS WDT) battery backup switch. oscillator uses external, low-cost 32.768kHz crystal. compensation trim components integrated chip. This eliminates several external discrete components trim capacitor, saving board area component cost. Real-Time Clock keeps track time with separate registers Hours, Minutes, Seconds. Calendar separate registers Date, Month, Year Day-of-week. calendar correct through 2099, with automatic leap year correction. powerful Dual Alarms Clock/Calendar value match. instance, every minute, every Tuesday, 5:23 March alarms polled Status Register provide hardware interrupt (IRQ Pin). There repeat mode alarms allowing periodic interrupt. PHZ/IRQ software selected provide frequency output 4096 32,768 X1228 device integrates Supervisor functions Battery Switch. There Power-On Reset (RESET output) with typically delay from power-on. will also assert RESET when goes below specified threshold. Vtrip threshold user repro-grammable. There WatchDog Timer (WDT) with selectable time-out periods (0.25s, 0.75s, 1.75s) disabled setting. watchdog activates RESET when expires. device offers backup power input pin. This VBACK allows device backed battery SuperCap. entire X1228 device fully operational from volts clock/calendar portion X1228 device remains fully operational down volts (Standby Mode). X1228 device provides bits EEPROM with modes BlockLockcontrol. BlockLock allows safe, secure memory critical user configuration data, while allowing large user storage area. DESCRIPTIONS
X1228 TSSOP/SOIC RESET VBACK PHZ/IRQ
internal connection
Serial Clock (SCL) input used clock data into device. input buffer this always active (not gated). Serial Data (SDA) bidirectional used transfer data into device. open drain output wire ORed with other open drain open collector outputs. input buffer always active (not gated). open drain output requires pull-up resistor. output circuitry controls fall time output signal with slope controlled pull-down. circuit designed 400kHz 2-wire interface speeds. VBACK This input provides backup supply voltage device. VBACK supplies power device event supply fails. This connected battery, Supercap tied ground used. RESET Output RESET This reset signal output. This signal notifies host processor that watchdog time period expired that voltage dropped below fixed VTRIP threshold. open drain active output. Recommended value pullup resistor unused, ground. Programmable Frequency/Interrupt Output PHZ/IRQ This either output from internal oscillator interrupt signal output. CMOS output. When used frequency output, this signal frequency 32.768kHz, 4096Hz, inactive. When used interrupt output, this signal notifies host processor that alarm occurred action required. active output. control bits this function found address 0011h Clock Control Memory map. "Programmable Frequency Output Bits-FO1, FO0" page
FN8100.4 2006
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pins input output, respectively, inverting amplifier. external 32.768kHz quartz crystal used with X1228 supply timebase real time clock. recommended crystal Citizen CFS206-32.768KDZF. Internal compensation circuitry included form complete oscillator circuit. Care should taken placement crystal layout circuit. Plenty ground plane around device short traces highly recommended. Application section more recommendations. Figure Recommended Crystal connection Reading Real Time Clock read initiating Read command specifying address corresponding register Real Time Clock. Registers then read Sequential Read Mode. Since clock runs continuously read takes finite amount time, there possibility that clock could change during course read operation. this device, time latched read command (falling edge clock prior data output) into separate latch avoid time changes during read operation. clock continues run. Alarms occurring during read unaffected read operation. Writing Real Time Clock
POWER CONTROL OPERATION power control circuit accepts VBACK input. power control circuit power clock from VBACK when VBACK 0.2V. will switch back power device from when exceeds VBACK. Figure Power Control
VBACK
Voltage
time date writing registers. avoid changing current time uncompleted write operation, current time value loaded into separate buffer falling edge clock before data input bytes, clock continues run. serial input data replaces values buffer. This value loaded back into Register stop valid write sequence. invalid write operation aborts time update procedure contents buffer discarded. After valid write operation will reflect newly loaded data beginning with next "one second" clock cycle after stop written. continues update time while register write progress continues during nonvolatile write sequences. single byte written without affecting other bytes. Accuracy Real Time Clock accuracy Real Time Clock depends frequency quartz crystal that used time base RTC. Since resonant frequency crystal temperature dependent, performance will also dependent upon temperature. frequency deviation crystal fuction turnover temperature crystal from crystal's nominal frequency. example, >20ppm frequency deviation translates into accuracy minute month. These parameters available from crystal manufacturer. Intersil's family provides on-chip crystal compensation networks adjust loadcapacitance tune oscillator frequency from +116 when using 12.5 load crystal. more detail information Application section.
REAL TIME CLOCK OPERATION Real Time Clock (RTC) uses external 32.768kHz quartz crystal maintain accurate internal representation second, minute, hour, day, date, month, year. leap-year correction. clock also corrects months having fewer than days that controls hour AM/PM format. When X1228 powers after loss both VBACK, clock will operate until least byte written clock register.
FN8100.4 2006
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CLOCK/CONTROL REGISTERS (CCR) Control/Clock Registers located area separate from EEPROM array only accessible following slave byte "1101111x" reads writes addresses [0000h:003Fh]. clock/control memory memory addresses from 0000h 003Fh. defined addresses described Table Writing reading from undefined addresses recommended. access contents modified performing byte page write operation directly address CCR. Prior writing (except status register), however, RWEL bits must using step process (See section "Writing Clock/Control Registers.") divided into sections. These are: Alarm bytes; non-volatile) Alarm bytes; non-volatile) Control bytes; non-volatile) Real Time Clock bytes; volatile) Status byte; volatile) necessary RWEL prior writing status register. Section supports single byte read write only. Continued reads writes from this section terminates operation. state read performing random read address time. This returns contents that register location. Additional registers read performing sequential read. read instruction latches Clock registers into buffer, update clock does change time being read. sequential read will result output data from memory array. read, master supplies stop condition operation free bus. After read CCR, address remains previous address user execute current address read continue reading next Register. ALARM REGISTERS There alarm registers whose contents mimic contents register, enable bits exclude hour time selection bit. enable bits specify which registers comparison between Alarm Real Time Registers. example: Setting Enable Month (EMOn*) combination with other enable bits specific alarm time, user establish alarm that triggers same time once year. Alarm Alarm
Each register read written through buffers. non-volatile portion counter portion RTC) updated only RWEL only after valid write operation stop bit. sequential read page write operation provides access contents only section operation. Access another section requires operation. Continued reads writes, once reaching section, will wrap around start section. read write begin address CCR. Table Clock/Control Memory
Addr. Type Name
(optional)
Range
003F 0037 0036 0035 0034 0033 0032 0031 0030 0013 0012 0011 0010
Status (SRAM)
Control (EEPROM)
AL1E
Y2K21 ATR5 AL0E
Y2K20 ATR4
Y2K13 ATR3
RWEL DTR2 ATR2
DTR1 ATR1
RTCF Y2K10 DTR0 ATR0
19/20 0-99 1-12 1-31 0-23 0-59 0-59
FN8100.4 2006
Default
X1228
Table Clock/Control Memory (Continued)
Addr. Type Name (optional) Range Default
000F 000E 000D 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000
Alarm1 (EEPROM)
Alarm0 (EEPROM)
Y2K1 DWA1 YRA1 MOA1 DTA1 HRA1 MNA1 SCA1 Y2K0 DWA0 YRA0 MOA0 DTA0 HRA0 MNA0 SCA0
EDW1 EMO1 EDT1 EHR1 EMN1 ESC1 EDW0 EMO0 EDT0 EHR0 EMN0 ESC0
A1Y2K21 A1Y2K20 A1Y2K13 Unused Default Year value EEPROM) Future expansion A1G20 A1G13 A1G12 A1G11 A1D21 A1D20 A1D13 A1D12 A1D11 A1H21 A1H20 A1H13 A1H12 A1H11 A1M22 A1M21 A1M20 A1M13 A1M12 A1M11 A1S22 A1S21 A1S20 A1S13 A1S12 A1S11 A0Y2K21 A0Y2K20 A0Y2K13 Unused Default Year value EEPROM) Future expansion A0G20 A0G13 A0G12 A0G11 A0D21 A0D20 A0D13 A0D12 A0D11 A0H21 A0H20 A0H13 A0H12 A0H11 A0M22 A0M21 A0M20 A0M13 A0M12 A0M11 A0S22 A0S21 A0S20 A0S13 A0S12 A0S11
A1Y2K10 A1G10 A1D10 A1H10 A1M10 A1S10 A0Y2K10 A0G10 A0D10 A0H10 A0M10 A0S10
19/20 1-12 1-31 0-23 0-59 0-59 19/20 1-12 1-31 0-23 0-59 0-59
When there match, alarm flag set. occurrence alarm determined polling bits enabling output, using hardware flag. alarm enable bits located particular register. When enable bits `0', there alarms. user X1228 alarm every Wednesday 8:00 setting EDWn*, EHRn* EMNn* enable bits setting DWAn*, HRAn* MNAn* Alarm registers 8:00 Wednesday. daily alarm 9:30PM results when EHRn* EMNn* enable bits HRAn* MNAn* registers 9:30 Alarm Alarm REAL TIME CLOCK REGISTERS
Clock/Calendar Registers (SC, These registers depict representations time. such, (Seconds) (Minutes) range from (Hour) with indicator (H21 bit) (with MIL=1), (Date) (Month) (Year)
Date Week Register (DW) This register provides Week status uses three bits represent seven days week. counter advances cycle 0-1-2-3-4-5-6-0-1-2-. assignment numerical value specific week arbitrary decided system software designer. default value defined `0'. Hour Time register uses 24-hour format. uses 12hour format functions AM/PM indicator with representing clock defaults standard time with Leap Years Leap years February defined those years that divisible Years divisible leap years, unless they also divisible 400. This means that year 2000 leap year, year 2100 not. X1228 does correct leap year year 2100.
FN8100.4 2006
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STATUS REGISTER (SR) Status Register located memory area address 003Fh. This volatile register only used control RWEL write enable latches, read power status alarm bits. This register separate from both array Clock/Control Registers (CCR). Table Status Register (SR)
Addr 003Fh Default RWEL RTCF
RTCF: Real Time Clock Fail Bit-Volatile This after total power failure. This read only that hardware (X1228 internally) when device powers after having lost power device (both VBACK 0V). regardless whether VBACK applied first. loss only supplies does RTCF "1". power-up after total power failure, registers their default states clock will increment until least byte written clock register. first valid write section after complete power failure resets RTCF (writing byte sufficient). Unused Bits: This device does bits must have zero these positions. Data Byte output during read will contain zeros these locations. CONTROL REGISTERS Control Bits Registers, described under this section, nonvolatile. Block Protect Bits-BP2, BP1, Block Protect Bits, BP2, BP0, determine which blocks array write protected. write protected block memory ignored. block protect bits will prevent write operations eight segments array. partitions described Table Table Block Protect Bits Protected Addresses X1228 None 180h 1FFh 100h 1FFh 000h 1FFh 000h 03Fh 000h 07Fh 000h 0FFh 000h 1FFh Array Lock None (Default) Upper Upper Full Array First Page First First First
BAT: Battery Supply-Volatile This indicates that device operating from VBACK, VCC. read-only set/reset hardware (X1228 internally). Once device begins operating from VCC, device sets this "0". AL1, AL0: Alarm bits-Volatile These bits announce either alarm alarm match real time clock. there match, respective `1'. falling edge last data Read operation resets flags. Note: Only bits that when read starts will reset. alarm that alarm occurring during read operation will remain after read operation complete. RWEL: Register Write Enable Latch-Volatile This volatile latch that powers (disabled) state. RWEL must prior writes Clock/Control Registers. Writes RWEL cause nonvolatile write cycle, device ready next operation immediately after stop condition. write requires both RWEL bits specific sequence. WEL: Write Enable Latch-Volatile controls access memory array during write operation. This volatile latch that powers (disabled) state. While LOW, writes array address will ignored acknowledge will issued after Data Byte). writing zeroes other bits Status Register. Once set, remains until either reset writing zeroes other bits Status Register) until part powers again. Writes cause nonvolatile write cycle, device ready next operation immediately after stop condition.
Watchdog Timer Control Bits-WD1, bits control period Watchdog Timer. Table options.
FN8100.4 2006
X1228
Table Watchdog Timer Time-Out Options Watchdog Time-Out Period
1.75 seconds milliseconds milliseconds Disabled (default)
Programmable Frequency Output Bits-FO1, These output control bits. They select three divisions internal oscillator, that applied output pin. Table shows selection bits this output. When using output function, Alarm output function disabled. Table Programmable Frequency Output Bits
INTERRUPT CONTROL FREQUENCY OUTPUT REGISTER (INT) Interrupt Control Status Bits (IM, AL1E, AL0E) There Interrupt Control bits, Alarm Interrupt Enable (AL1E) Alarm Interrupt Enable (AL0E) specifically enable disable alarm interrupt signal output (IRQ). interrupts enabled when either AL1E AL0E bits `1', respectively. volatile bits (AL1 AL0), associated with alarms respectively, indicate alarm happened. These bits alarm condition regardless whether interrupt enabled. bits status register reset falling edge eighth clock read register containing bits. Pulse Interrupt Mode pulsed interrrupt mode allows repetitive recurring alarm functionality. Hence repetitive recurring alarm every second, minute, hour, date, same week. pulsed interrupt mode considered repetitive interrupt mode, with repetition rate time setting alarm. Pulse Interrupt Mode enabled when set.
Output Frequency (average samples)
Alarm output 32.768kHz 4096Hz
ON-CHIP OSCILLATOR COMPENSATION Digital Trimming Register (DTR) DTR2, DTR1 DTR0 (Non-Volatile) digital trimming Bits DTR2, DTR1 DTR0 adjust number counts second average error achieve better accuracy. DTR2 sign bit. DTR2 means frequency compensation DTR2 means frequency compensation DTR1 DTR0 scale bits. DTR1 gives adjustment DTR0 gives adjustment. range from -30ppm +30ppm represented using three bits above. Table Digital Trimming Registers Register DTR2
Interrupt Alarm Frequency
Single Time Event Alarm Repetitive Recurring Time Event Alarm
DTR1
DTR0
Estimated frequency
(Default)
Alarm output will output single pulse short duration (approximately 10-40ms) once alarm condition met. interrupt mode bit) set, then this pulse will periodic.
FN8100.4 2006
X1228
Analog Trimming Register (ATR) (Non-volatile) analog trimming Bits from ATR5 ATR0 provided adjust on-chip loading capacitance range. on-chip load capacitance ranges from 3.25pF 18.75pF. Each different weight capacitance adjustment. addition, using Citizen CFS-206 crystal with different combinations provides estimated range from +116ppm -37ppm nominal frequency compensation. combination digital analog trimming give +146ppm adjustment. on-chip capacitance calculated follows: CATR [(ATR value, decimal) 0.25pF] 11.0pF Note that values two's complement, with ATR(000000) 11.0pF, entire range runs from 3.25pF 18.75pF 0.25pF steps. values calculated above typical, total load capacitance seen crystal will include approximately package board capacitance addition value. Application section Intersil's Application Note AN154 more information. WRITING CLOCK/CONTROL REGISTERS Changing nonvolatile bits clock/control register requires following steps: Write Status Register Write Enable Latch (WEL). This volatile operation, there delay after write. (Operation preceeded start ended with stop). Write Status Register both Register Write Enable Latch (RWEL) bit. This also volatile cycle. zeros data byte required. (Operation preceeded start ended with stop). Write bytes Clock/Control Registers with desired clock, alarm, control data. This sequence starts with start bit, requires slave byte "11011110" address within terminated stop bit. write changes EEPROM values these initiate nonvolatile write cycle will take 10ms complete. Writes undefined areas have effect. RWEL reset completion nonvolatile write cycle, sequence must repeated again initiate another change contents. sequence completed reason sending incorrect number bits sending start instead stop, example) RWEL reset device remains active mode. Writing zeros status register resets both RWEL bits. read operation occurring between previous operations will interrupt register write operation. POWER-ON RESET Application power X1228 activates Poweron Reset Circuit that pulls RESET active. This signal provides several benefits. prevents system microprocessor from starting operate with insufficient voltage. prevents processor from operating prior stabilization oscillator. allows time FPGA download configuration prior initialization circuit. prevents communication EEPROM, greatly reducing likelihood data corruption power-up. When exceeds device VTRIP threshold value typically 250ms circuit releases RESET, allowing system begin operation. Recommended slew rate between 0.2V/ms 50V/ms. WATCHDOG TIMER OPERATION watchdog timer selectable. writing value WD0, watchdog timer different time periods off. When Watchdog timer off, watchdog circuit configured power operation. Watchdog Timer Restart Watchdog Timer started falling edge when line high followed stop bit. start signal restarts watchdog timer counter, resetting period counter back maximum. another start fails detected prior watchdog timer expiration, then RESET becomes active. event that start signal occurs during reset time period, start will have effect. When using single START refresh watchdog timer, STOP should followed reset device back stand-by mode.
FN8100.4 2006
X1228
VOLTAGE RESET OPERATION When power failure occurs, voltage part drops below fixed vTRIP voltage, reset pulse issued host microcontroller. circuitry monitors line with voltage comparator which senses preset threshold voltage. Power-up power-down waveforms shown Figure Voltage Reset circuit designed RESET signal valid down 1.0V. Figure Watchdog Restart/Time
tRSP tRSP<tWDO tRSP>tWDO tRST tRSP>tWDO tRST
When voltage reset signal active, operation progress nonvolatile write cycle unaffected, allowing nonvolatile write continue long possible (down power-on reset voltage). voltage reset signal, when active, terminates progress communications device prevents commands, reduce likelihood data corruption.
RESET
Start
Stop Start Note: inputs ignored during active reset period (tRST).
Figure Power-on Reset Voltage Reset
VTRIP tPURST tRPD RESET VRVALID tPURST
THRESHOLD RESET PROCEDURE [OPTIONAL] X1228 shipped with standard threshold (VTRIP) voltage. This value will change over normal operating storage conditions. However, applications where standard VTRIP exactly right, higher precision needed VTRIP value, X1228 threshold adjusted. procedure described below, uses application nonvolatile write control signal.
Setting VTRIP Voltage necessary reset trip point before setting value. VTRIP voltage, apply desired VTRIP threshold voltage RESET programming voltage Then write data address 01h. stop following valid write operation initiates VTRIP programming sequence. Bring RESET complete operation. Note: this operation take milliseconds complete also writes address EEPROM array.
FN8100.4 2006
X1228
Figure VTRIP Level Sequence (VCC desired VTRIP value)
RESET
Note: BP0, BP1, must disabled.
Resetting VTRIP Voltage This procedure used VTRIP "native" voltage level. example, current VTRIP 4.4V VTRIP must 4.0V, then VTRIP must reset. When VTRIP reset, VTRIP something less than 1.7V. This procedure must used voltage lower value. reset VTRIP voltage, apply more than 5.5V RESET programming voltage Then write address 03h. stop valid write operation initiates VTRIP programming sequence. Bring RESET complete operation. Note: this operation takes Figure Reset VTRIP Level Sequence
milliseconds complete also writes address EEPROM array. best accuracy setting VTRIP, advised that following sequence used. 1.Program VTRIP above. 2.Measure resulting VTRIP measuring value where RESET occurs. Calculate Delta (Desired Measured) VTRIP value. 3.Perform VTRIP program using following formula voltage RESET pin: VRESET (Desired Value Delta) 0.025V
RESET Note: BP0, BP1, must disabled.
FN8100.4 2006
X1228
SERIAL COMMUNICATION Interface Conventions device supports bidirectional oriented protocol. protocol defines device that sends data onto transmitter, receiving device receiver. device controlling transfer called master device being controlled called slave. master always initiates data transfers, provides clock both transmit receive operations. Therefore, devices this family operate slaves applications. Clock Data Data states line change only during LOW. state changes during HIGH reserved indicating start stop conditions. Figure Start Condition commands preceded start condition, which HIGH transition when HIGH. device continuously monitors lines start condition will respond command until this condition been met. Figure Stop Condition communications must terminated stop condition, which HIGH transition when HIGH. stop condition also used place device into Standby power mode after read sequence. stop condition only issued after transmitting device released bus. Figure Figure Valid Data Changes
Acknowledge Acknowledge software convention used indicate successful data transfer. transmitting device, either master slave, will release after transmitting eight bits. During ninth clock cycle, receiver will pull line acknowledge that received eight bits data. Refer Figure device will respond with acknowledge after recognition start condition correct Device Identifier Select bits contained Slave Address Byte. write operation selected, device will respond with acknowledge after receipt each subsequent eight word. device will acknowledge incoming data address bytes, except for: Slave Address Byte when Device Identifier and/or Select bits incorrect Data Bytes write when Write Protect Register Data Byte Status Register Write Operation (only data byte allowed) read mode, device will transmit eight bits data, release line, then monitor line acknowledge. acknowledge detected stop condition generated master, device will continue transmit data. device will terminate further data transmissions acknowledge detected. master must then issue stop condition return device Standby mode place device into known state.
Data Stable Data Change Data Stable
FN8100.4 2006
X1228
Figure Valid Start Stop Conditions
Start Stop
Figure Acknowledge Response From Receiver
from Master Data Output from Transmitter Data Output from Receiver Start Acknowledge
DEVICE ADDRESSING Following start condition, master must output Slave Address Byte. first four bits Slave Address Byte specify access either EEPROM array CCR. Slave bits `1010' access EEPROM array. Slave bits `1101' access CCR. When shipped from factory, EEPROM array UNDEFINED, should programmed customer known state. through slave byte specify device select bits. These `111'. last Slave Address Byte defines operation performed. When this one, then read operation selected. zero selects write operation. Refer Figure After loading entire Slave Address Byte from bus, X1228 compares device identifier device select bits with `1010111' `1101111'. Upon correct compare, device outputs acknowledge line.
Following Slave Byte byte word address. word address either supplied master device obtained from internal counter. powerup internal address counter address current address read EEPROM array starts address When required, part random read, master must supply Word Address Bytes shown Figure random read operation, slave byte "dummy write" portion must match slave byte "read" section. That random read from array slave byte must 1010111x both instances. Similarly, random read Clock/Control Registers, slave byte must 1101111x both places.
FN8100.4 2006
X1228
Figure Slave Address, Word Address, Data Bytes Byte pages)
Device Identifier
Array
Slave Address Byte Byte
Word Address Byte
Word Address Byte Data Byte Byte
Write Operations Byte Write write operation, device requires Slave Address Byte Word Address Bytes. This gives master access words array CCR. (Note: Prior writing CCR, master must write 02h, then status register preceding operations enable write operation. "Writing Clock/Control Registers." Upon receipt each address byte, X1228 responds with acknowledge. After receiving both address bytes Figure Byte Write Sequence
Signals from Master
X1228 awaits eight bits data. After receiving data bits, X1228 again responds with acknowledge. master then terminates transfer generating stop condition. X1228 then begins internal write cycle data nonvolatile memory. During internal write cycle, device inputs disabled, device will respond requests from master. output high impedance. Figure
Slave Address
Word Address 0000000
Word Address
Data
Signals From Slave
Figure Writing bytes 64-byte memory page starting address
Bytes
Bytes
Address
Address Pointer Ends Here Addr
Address
Address
FN8100.4 2006
X1228
write protected block memory ignored, will still receive acknowledge. write command, X1228 will initiate internal write cycle, will continue commands. Page Write X1228 page write operation. initiated same manner byte write operation; instead terminating write cycle after first data byte transferred, master transmit more bytes memory array more bytes clock/control registers. (Note: Prior writing CCR, master must write 02h, then status register preceding operations enable write operation. "Writing Clock/Control Registers." After receipt each byte, X1228 responds with acknowledge, address internally incremented one. When counter reaches page, "rolls over" goes back first address same page. This means that master write bytes memory array page bytes section starting location that page. Figure Page Write Sequence
EEPROM array Slave Address Word Address Word Address Data Data
example, master begins writing location memory loads bytes, then first bytes written addresses through last bytes written columns through Afterwards, address counter would point location page that just written. master supplies more than maximum bytes page, then previously loaded data over written data, byte time. Refer Figure master terminates Data Byte loading issuing stop condition, which causes X1228 begin nonvolatile write cycle. with byte write operation, inputs disabled until completion internal write cycle. Refer Figure address, acknowledge, data transfer sequence. Stops Write Modes Stop conditions that terminate write operations must sent master after sending least full data byte it's associated signal. stop issued middle data byte, before full data byte sent, then X1228 resets itself without performing write. contents array affected.
Signals from Master
Signals from Slave
FN8100.4 2006
X1228
Acknowledge Polling Disabling inputs during nonvolatile write cycles used take advantage typical write cycle time. Once stop condition issued indicate master's byte load operation, X1228 initiates internal nonvolatile write cycle. Acknowledge polling begin immediately. this, master issues start condition followed Memory Array Slave Address Byte write read operation (AEh AFh). X1228 still busy with nonvolatile write cycle then will returned. When X1228 completed write operation, returned host proceed with read write operation. Refer flow chart Figure Note: Salve byte (DEh DFh) Acknowledge Polling. Read Operations There three basic read operations: Current Address Read, Random Read, Sequential Read. Current Address Read Internally X1228 contains address counter that maintains address last word read incremented one. Therefore, last read address next read operation would access data from address n+1. power-up, sixteen address initialized this way, current address read immediately after power-on reset download entire contents memory starting first location.Upon receipt Slave Address Byte with one, X1228 issues acknowledge, then transmits eight data bits. master terminates read operation responding with acknowledge during ninth clock issuing stop condition. Refer Figure address, acknowledge, data transfer sequence. Figure Current Address Read Sequence
Signals from Master Signals from Slave Continue normal Read Write command sequence
Figure Acknowledge Polling Sequence
Byte load completed issuing STOP. Enter Polling
Issue START
Issue Memory Array Slave Address Byte (Read) (Write)
Issue STOP
returned? nonvolatile write Cycle complete. Continue command sequence?
Issue STOP
PROCEED
should noted that ninth clock cycle read operation "don't care." terminate read operation, master must either issue stop condition during ninth cycle hold HIGH during ninth clock cycle then issue stop condition.
Slave Address
Data
FN8100.4 2006
X1228
Random Read Random read operations allows master access location X1228. Prior issuing Slave Address Byte with zero, master must first perform "dummy" write operation. master issues start condition slave address byte, receives acknowledge, then issues word address bytes. After acknowledging receipt each word address byte, master immediately issues another start condition slave address byte with one. This followed acknowledge from device then eight data word. master terminates read operation responding with acknowledge then issuing stop condition. Refer Figure address, acknowledge, data transfer sequence. similar operation called "Set Current Address," device sets address stop issued instead second start shown Figure X1228 then goes into standby mode after stop activity will ignored until start detected. This operation loads address into address counter. next Current Address Read operation will Figure Random Address Read Sequence
Signals from Master Slave Address
read from newly loaded address. This operation could useful master knows next address needs read, ready data. Sequential Read Sequential reads initiated either current address read random address read. first data byte transmitted with other modes; however, master responds with acknowledge, indicating requires additional data. device continues output data each acknowledge received. master terminates read operation responding with acknowledge then issuing stop condition. data output sequential, with data from address followed data from address address counter read operations increments through page column addresses, allowing entire memory contents serially read during operation. address space counter "rolls over" start address space X1228 continues output data each acknowledge received. Refer Figure acknowledge data transfer sequence.
Word Address
Word Address
Slave Address Data
Signals from Slave
0000000
Figure Sequential Read Sequence
Signals from Master Signals from Slave Slave Address
Data Data Data (n-1) Data
integer greater than
FN8100.4 2006
X1228
APPLICATION SECTION CRYSTAL OSCILLATOR TEMPERATURE COMPENSATION Intersil integrated oscillator compensation circuity on-chip, eliminate need external components adjust crystal drift over temperature enable very high accuracy time keeping (<5ppm drift). Intersil family uses oscillator circuit with on-chip crystal compensation network, including adjustable load-capacitance. only external component required crystal. compensation network optimized operation with certain crystal parameters which common many surface mount tuning-fork crystals available today. Table summarizes these parameters. Table contains some crystal manufacturers part numbers that meet requirements Intersil products. turnover temperature Table describes temperature where apex drift temperature curve occurs. This curve parabolic with drift increasing (T-T0)2. Epson MC-405 device, example, turnover temperature typically peak drift >110ppm occurs Table Crystal Parameters Required Intersil RTC's Parameter
Frequency Freq. Tolerance Turnover Temperature Operating Temperature Range Parallel Load Capacitance Equivalent Series Resistance 12.5
temperature extremes possible address this variable drift adjusting load capacitance crystal, which will result predictable change crystal frequency. Intersil family allows this adjustment over temperature since devices include on-chip load capacitor trimming. This control handled Analog Trimming Register, ATR, which bits control. load capacitance range covered circuit approximately 3.25pF 18.75pF, 0.25pf increments. Note that actual capacitance would also include about package related capacitance. Incircuit tests with commercially available crystals demonstrate that this range capacitance allows frequency control from +116ppm -37ppm, using 12.5pF load crystal. addition analog compensation afforded adjustable load capacitance, digital compensation feature available Intersil family. There three bits known Digital Trimming Register DTR, they operate adding skipping pulses clock signal. range provided ±30ppm increments 10ppm. default setting 0ppm. control used coarse adjustments frequency drift over temperature crystal initial accuracy correction.
32.768
±100
Units
Notes
Down 20ppm desired Typically value used most crystals
best oscillator performance
Table Crystal Manufacturers Manufacturer
Citizen Epson Raltron SaRonix Ecliptek
Part Number
CM201, CM202, CM200S MC-405, MC-406 RSM-200S-A 32S12A ECPSM29T-32.768K ECX-306/ECX-306I FSM-327
Temp Range
+85°C +85°C +85°C +85°C +60°C +60°C +85°C
+25°C Freq Toler.
±20ppm ±20ppm ±20ppm ±20ppm ±20ppm ±20ppm ±20ppm
FN8100.4 2006
X1228
final application control in-circuit calibration high accuracy applications, along with temperature sensor chip. Once circuit powered with battery backup, output 32.768kHz frequency drift measured. control then adjusted setting which minimizes drift. Once adjusted particular temperature, possible adjust other discrete temperatures minimal overall drift, store resulting settings EEPROM. Extremely overall temperature drift possible with this method. Intersil evaluation board contains circuitry necessary implement this control. more detailed operation Intersil's application note AN154 Intersil's website www.intersil.com. Layout Considerations crystal input very high impedance will pick high frequency signals from other circuits board. Since tied other side crystal, also sensitive node. These signals couple into oscillator circuit produce double clocking mis-clocking, seriously affecting accuracy RTC. Care needs taken layout circuit avoid noise pickup. Below Figure suggested layout X1228 device. Figure Suggested Layout Intersil SO-14 Assembly Most electronic circuits have deal with assembly issues, with devices assembly includes insertion soldering live battery into unpowered circuit. socket soldered board, battery inserted final assembly, then there issues with operation RTC. battery soldered board directly, then device Vback will some transient upset from either soldering tools intermittent battery connections which stop circuit from oscillating. Once battery soldered board, only assure circuit will start momentarily (very short period time!) short Vback ground circuit will begin oscillate. Oscillator Measurements When proper crystal selected layout guidelines above observed, oscillator should start most circuits less than second. Some circuits take slightly longer, startup should definitely occur less than seconds. When testing circuits, most common impulse apply scope probe circuit (oscillator output) observe waveform. THIS! Although some cases useable waveform, parasitics (usually 10pF ground) applied with scope probe, there will useful information that waveform other than fact that circuit oscillating. output sensitive capacitive impedance voltage levels frequency will affected parasitic elements scope probe. Applying scope probe possibly cause faulty oscillator start hiding other issues (although Intersil RTC's, internal circuitry assures startup when using proper crystal layout). best analyze circuit power read real time clock time advances, chip output, look output that oscilloscope (after enabling with control register). Alternatively, X1226/1286/1288 devices have IRQ- output which checked setting alarm each minute. Using pulse interrupt mode setting, once-per-minute interrupt functions indication proper oscillation.
0.1µF
XTAL1 32.768kGz
X1228
connections crystal kept short possible. thick ground trace around crystal advised minimize noise intrusion, ground near pins should avoided will load capacitance those pins. Keep mind these guidelines other layers vicinity device. small decoupling capacitor chip mandatory, with solid connection ground.
FN8100.4 2006
X1228
Backup Battery Operation Many types batteries used with Intersil products. 3.0V 3.6V Lithium batteries appropriate, sizes available that power Intersil device years. Another option supercapacitor applications where disappear intermittently short periods time. Depending value supercapacitor used, backup time last from days weeks (with >1F). simple silicon Schottky barrier diode used series with charge supercapacitor, which connected Vback pin. diode charge battery (especially lithium batteries!). Figure Supercapactor charging circuit
2.7-5.5V
Vback Supercapacitor
Since battery switchover occurs Vcc=Vback0.1V (see Figure 16), battery voltage must always lower than voltage during normal operation battery will drained. second consideration trip point setting system RESET- function, known Vtrip. Vtrip factory levels systems with either 3.3V operation, with following standard options: VTRIP 4.63V VTRIP 4.38V VTRIP 2.85V VTRIP 2.65V summary conditions backup battery operation given Table
Table Battery Backup Operation
Example Application, Vback 3.0V
Condition
Normal Operation with battery Backup Mode
5.00 5.00 0-1.8
Vback
3.00 1.8-3.0
Vtrip
4.38 4.38 4.38
Iback
<<1µA <2µA
Reset
Notes
Timekeeping only
Example Application, 3.3V,Vback 3.0V
Condition
Normal Operation with battery Backup Mode UNWANTED Vback powering
3.30 3.30 0-1.8 2.65 3.30
Vback
3.00 1.8-3.0*
Vtrip
2.65 2.65 2.65 2.65
Iback
<<1µA <2µA*
Reset
Timekeeping only Internal Vcc=Vback
*since Vback>2.65V higher than Vtrip, battery powering entire device
FN8100.4 2006
X1228
Referring Figure Vtrip applies "Internal Vcc" node which powers entire device. This means that powered down battery voltage Vback higher than Vtrip voltage, then entire chip will running from battery. Vback falls lower than Vtrip, then chip shuts down outputs disabled except oscillator timekeeping circuitry. fact that chip powered from Vback necessarily issue since standby current devices <2µA this mode (called "main timekeeping current" data sheet). Only when serial interface active there increase supply current, with powered down, serial interface will most likely inactive. prevent operation battery backup mode above Vtrip level diode drop (silicon diode preferred) battery insure below Vtrip. This will also provide reverse leakage protection which needed safety agency approval. mode that should always avoided operation device with Vback greater than both Vtrip (Condition Table This will cause battery drain quickly serial communication non-volatile writes will require higher supplier current. PERFORMANCE DATA IBACK Performance
IBACK Temperature Multi-Lot Process Variation Data 3.3V 1.8V
IBACK (µA)
Temperature
FN8100.4 2006
X1228 Small Outline Package Family (SO)
(N/2)+1
I.D. MARK DETAIL
(N/2)
0.010 GAUGE PLANE 0.004 0.010 DETAIL
SEATING PLANE
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL NOTES: Plastic metal protrusions 0.006" maximum side included. Plastic interlead protrusions 0.010" maximum side included. Dimensions "E1" measured Datum Plane "H". Dimensioning tolerancing ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 TOLERANCE ±0.003 ±0.002 ±0.003 ±0.001 ±0.004 ±0.008 ±0.004 Basic ±0.009 Basic Reference Reference NOTES Rev. 2/01
FN8100.4 2006
X1228 Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX AREA 0.05(0.002) -CSEATING PLANE 0.25 0.010 0.25(0.010) GAUGE PLANE
M14.173
LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL 0.002 0.031 0.0075 0.0035 0.195 0.169 0.246 0.0177 0.047 0.006 0.041 0.0118 0.0079 0.199 0.177 0.256 0.0295 MILLIMETERS 0.05 0.80 0.19 0.09 4.95 4.30 6.25 0.45 1.20 0.15 1.05 0.30 0.20 5.05 4.50 6.50 0.75 NOTES Rev. 4/06
0.10(0.004)
0.10(0.004)
0.026
0.65
NOTES: These package dimensions within allowable dimensions JEDEC MO-153-AC, Issue Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension "E1" does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.15mm (0.006 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total excess dimension maximum material condition. Minimum space between protrusion adjacent lead 0.07mm (0.0027 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. (Angles degrees)
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN8100.4 2006
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