Data Sheet December 2004 FN4817.3 Microprocessor CORE Voltage Reg

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Data Sheet December 2004 FN4817.3 Microprocessor CORE Voltage Reg

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HIP6311
Data Sheet December 2004 FN4817.3
Microprocessor CORE Voltage Regulator Multi-Phase Buck Controller
HIP6311 multi-phase control together with companion gate drivers, HIP6601, HIP6602 HIP6603 internal MOSFETs provides precision voltage regulation system advanced microprocessors. Multiphase power conversion marked departure from earlier single phase converter configurations previously employed satisfy ever increasing current demands modern microprocessors. Multi-phase convertors, distributing power load current results smaller lower cost transistors with fewer input output capacitors. These reductions accrue from higher effective conversion frequency with higher frequency ripple current phase interleaving process this topology. example, three phase convertor operating 350kHz will have ripple frequency 1.05MHz. Moreover, greater convertor bandwidth this design results faster response load transients. Outstanding features this controller include programmable codes from microprocessor that range from 1.100V 1.850V with system accuracy ±0.8%. Pull currents these pins eliminates need external pull resistors. addition "droop" compensation, used reduce overshoot undershoot CORE voltage, easily programmed with single resistor. Another feature this controller PGOOD monitor circuit which held until CORE voltage increases, during Soft-Start sequence, within programmed voltage. Over-voltage, above programmed CORE voltage, results converter shutting down turning lower MOSFETs clamp protect microprocessor. Under voltage also detected results PGOOD CORE voltage falls below programmed level. Over-current protection reduces regulator current less than programmed trip value. These features provide monitoring protection microprocessor power system.
Features
Multi-Phase Power Conversion Precision Channel Current Sharing Loss Less Current Sampling Uses rDS(ON) Precision CORE Voltage Regulation ±0.8% System Accuracy Over Temperature Microprocessor Voltage Identification Input 5-Bit Input 1.100V 1.850V 25mV Steps Programmable "Droop" Voltage Fast Transient Recovery Time Over Current Protection Automatic Selection Phase Operation High Ripple Frequency, (Channel Frequency) Times Number Channels .100kHz 6MHz Pb-Free Available (RoHS Compliant)
Ordering Information
PART NUMBER HIP6311CB HIP6311CBZ (Note) HIP6311CBZA (Note) HIP6301EVAL1 TEMP. (°C) PACKAGE SOIC PKG. DWG. M20.3
SOIC (Pb-free) M20.3 SOIC (Pb-free) M20.3
Evaluation Platform
*Add "-T" suffix part number tape reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
Pinout
HIP6311 (SOIC) VIEW
VID4 VID3 VID2 VID1 VID0 COMP FS/DIS VSEN PGOOD PWM4 ISEN4 ISEN1 PWM1 PWM2 ISEN2 ISEN3 PWM3
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2004. Rights Reserved other trademarks mentioned property their respective owners.
HIP6311 Block Diagram
PGOOD
POWER-ON RESET (POR) VSEN THREE STATE LATCH
CLOCK SAWTOOTH GENERATOR
FS/EN
X1.15
PWM1
SOFTSTART FAULT LOGIC
PWM2
COMP
PWM3
VID0 VID1 VID2 VID3 VID4
PWM4
CURRENT CORRECTION
PHASE NUMBER
CHANNEL DETECTOR
I_TOT I_TRIP
ISEN1
ISEN2 ISEN3 ISEN4
FN4817.3 December 2004
HIP6311 Simplified Power System Diagram
VSEN
SYNCHRONOUS RECTIFIED BUCK CHANNEL
SYNCHRONOUS RECTIFIED BUCK CHANNEL MICROPROCESSOR
HIP6311
SYNCHRONOUS RECTIFIED BUCK CHANNEL
SYNCHRONOUS RECTIFIED BUCK CHANNEL
Functional Description
VID4 VID3 VID2 VID1 VID0 COMP FS/DIS VSEN PGOOD PWM4 ISEN4 ISEN1 PWM1 PWM2 ISEN2 ISEN3 PWM3
converter. Pulling this ground disables converter three states outputs. Figure
(Pin
Bias reference ground. signals referenced this pin.
VSEN (Pin
Power good monitor input. Connect microprocessorCORE voltage.
PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin PWM4 (Pin
outputs each driven channel use. Connect these pins input HIP6601/2/3 driver. systems which channels, connect PWM4 high. channel systems connect PWM3 PWM4 high.
VID4 (Pin VID3 (Pin VID2 (Pin VID1 (Pin VID0 (Pin
Voltage Identification inputs from microprocessor. These pins respond 3.3V logic signals. HIP6311 decodes bits establish output voltage. Table
ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin ISEN4 (Pin
Current sense inputs from individual converter channel's phase nodes. Unused sense lines MUST left open.
COMP (Pin
Output internal error amplifier. Connect this external feedback compensation network.
PGOOD (Pin
Power good. This provides logic-high signal when microprocessor CORE voltage (VSEN pin) within specified limits Soft-Start timed out.
(Pin
Inverting input internal error amplifier.
FS/DIS (Pin
Channel frequency, FSW, select disable. resistor from this ground sets switching frequency
(Pin
Bias supply. Connect this supply.
FN4817.3 December 2004
HIP6311 Typical Application Phase Converter Using HIP6601 Gate Drivers
+12V
BOOT PVCC UGATE PHASE
VSEN COMP
DRIVER HIP6601
LGATE +VCORE
PWM4 PGOOD VID4 VID3 VID2 VID1 VID0 ISEN4 FS/DIS ISEN3 ISEN2 ISEN1 PWM3 PWM2 BOOT PWM1 PVCC UGATE +12V
MAIN CONTROL HIP6311
PHASE
DRIVER HIP6601
LGATE
FN4817.3 December 2004
HIP6311 Typical Application Phase Converter Using HIP6602 Gate Drivers
+12V
BOOT1
+12V
UGATE1 PHASE1
LGATE1
DUAL DRIVER HIP6602
VSEN COMP
PVCC
+12V
BOOT2
UGATE2 ISEN1 PWM1 PWM2 LGATE2 PHASE2
PGOOD VID4 VID3 VID2 VID1 VID0
PWM1 PWM2 ISEN2
MAIN CONTROL HIP6311
ISEN3 FS/DIS PWM3 PWM4 ISEN4 +12V
+VCORE
BOOT3
VIN+12V
UGATE3 PHASE3
LGATE3
DUAL DRIVER HIP6602
PVCC
+12V
BOOT4
UGATE4 PWM3 PWM4 LGATE4 PHASE4
FN4817.3 December 2004
HIP6311
Absolute Maximum Ratings
Supply Voltage, .+7V Input, Output, Voltage -0.3V 0.3V Classification 1.5KV
Thermal Information
Thermal Resistance (Typical, Note (°C/W) SOIC Package Maximum Junction Temperature 150°C Maximum Storage Temperature Range -65°C 150°C Maximum Lead Temperature (Soldering 10s) 300°C (SOIC Lead Tips Only)
Recommended Operating Conditions
Supply Voltage Ambient Temperature. 70°C
CAUTION: Stress above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational section this specification implied.
NOTE: measured with component mounted high effective thermal conductivity test board free air. Tech Brief details.
Electrical Specifications
PARAMETER INPUT SUPPLY POWER Input Supply Current (Power-On Reset) Threshold
Operating Conditions: 70°C, Unless Otherwise Specified TEST CONDITIONS UNITS
100k, Active Disabled Maximum Limit Rising Falling
4.25 3.75
4.38 3.88
4.00
REFERENCE System Accuracy (VID0 VID4) Input Voltage (VID0 VID4) Input High Voltage Pull-Up CHANNEL GENERATOR Frequency, Adjustment Range Disable Voltage ERROR AMPLIFIER Gain Gain-Bandwidth Product Slew Rate Maximum Output Voltage Minimum Output Voltage ISEN Full Scale Input Current Over-Current Trip Level POWER GOOD MONITOR Under-Voltage Threshold Under-Voltage Threshold PGOOD Output Voltage PROTECTION Over-Voltage Threshold Percent Over-Voltage Hysteresis VSEN Rising VSEN Falling after Over-Voltage 1.12 1.15 VDAC VSEN Rising VSEN Falling IPGOOD 0.92 0.90 0.18 VDAC VDAC 82.5 ground 100pF, ground 100pF, Load ±400µA Load 400µA Load -400µA 0.16 V/µs 100k, Figure Maximum voltage FS/DIS disable controller. IFS/DIS 1mA. 0.05 Percent system deviation from programmed Codes Programming Input Threshold Voltage Programming Input High Threshold Voltage VIDx VIDx -0.8
FN4817.3 December 2004
HIP6311
HIP6311
ERROR AMPLIFIER COMPARATOR CORRECTION
CIRCUIT PWM1 HIP6601
PHASE
PROGRAMMABLE REFERENCE
CURRENT SENSING
ISEN1
RISEN1
AVERAGE
CURRENT AVERAGING ISEN2 RISEN2 PHASE COMPARATOR CIRCUIT PWM2 HIP6601
VCORE COUT RLOAD
CURRENT SENSING
CORRECTION
FIGURE SIMPLIFIED BLOCK DIAGRAM HIP6311 VOLTAGE CURRENT CONTROL LOOPS POWER CHANNEL REGULATOR
Operation
Figure shows simplified diagram voltage regulation current control loops. Both voltage current feedback used precisely regulate voltage tightly control output currents, IL2, power channels. voltage loop comprises Error Amplifier, Comparators, gate drivers output MOSFETS. Error Amplifier essentially connected voltage follower that input, Programmable Reference output that CORE voltage.
voltage results increased Comparator output duty cycle. This increased duty cycle signal passed through CIRCUIT with phase reversal HIP6601, again with phase reversal gate drive upper MOSFETs, Increased duty cycle time MOSFET transistors results increased output voltage compensate output voltage sensed.
Current Loop
current control loop works similar fashion voltage control loop, with current control information applied individually each channel's Comparator. information used this control voltage that developed across rDS(ON) each lower MOSFET, when they conducting. single resistor converts scales voltage across MOSFETs current that applied Current Sensing circuit within HIP6311. Output from these sensing circuits applied current averaging circuit. Each channel receives difference current signal from summing circuit that compares average sensed current individual channel current. When power channel's current greater
FN4817.3 December 2004
Voltage Loop
Feedback from CORE voltage applied resistor inverting input Error Amplifier. This signal drive Error Amplifier output either high low, depending upon CORE voltage. CORE voltage makes amplifier output move towards higher output voltage level. Amplifier output voltage applied positive inputs Comparators Correction summing networks. Outof-phase sawtooth signals applied Comparators inverting inputs. Increasing Error Amplifier
HIP6311
than average current, signal applied summing Correction circuit Comparator, reduces output pulse width Comparator compensate detected "above average" current that channel. example, channel frequency 250kHz there three phases, ripple frequency 750kHz. monitors precisely regulates CORE voltage microprocessor. After initial start-up, controller also provides protection load power supply. following section discusses these features.
Droop Compensation
addition control each power channel's output current, average channel current also used provide CORE voltage "droop" compensation. Average full channel current defined 50µA. selecting input resistor, RIN, amount voltage droop required full load current programmed. average current driven into results voltage increase across resistor that direction make Error Amplifier "see" higher voltage inverting input, resulting Error Amplifier adjusting output voltage lower. voltage developed across equal "droop" voltage. "Current Sensing Balancing" section more details.
Initialization
HIP6311 usually operates from power supply. Many functions initiated rising supply voltage HIP6311. Oscillator, Sawtooth Generator, SoftStart other functions initialized during this interval. These circuits controlled POR, Power-On Reset. During this interval, outputs driven three state condition that makes these outputs essentially open. This state results gate drive output MOSFETs. Once voltage reaches 4.375V (+125mV), voltage level insure proper internal function, outputs enabled Soft-Start sequence initiated. reason, voltage drops below 3.875V (+125mV). circuit shuts converter down again three states outputs.
Applications Convertor Start-Up
Each power channel's current regulated. This enables channels accurately share load current enhanced reliability. HIP6601, HIP6602 HIP6603 MOSFET driver interfaces with HIP6311. more information, HIP6601, HIP6602 HIP6603 data sheets. HIP6311 capable controlling power channels. Connecting unused outputs automatically sets number channels. phase relationship between channels 360o/number active channels. example, three channel operation, outputs separated 120o Figure shows output signals four channel system.
Soft-Start
After function completed with reaching 4.375V, Soft-Start sequence initiated. Soft-Start, slow rise CORE voltage from zero, avoids over-current condition slowly charging discharged output capacitors. This voltage rise initiated internal that slowly raises reference voltage error amplifier input. voltage rise controlled oscillator frequency within HIP6311, therefore, output voltage effectively regulated rises final programmed CORE voltage value. first switching cycles, output remains inhibited outputs remain three stated. From 33rd cycle another, approximately cycles output remains low, clamping lower output MOSFETs ground, Figure time variability Error Amplifier, Sawtooth Generator Comparators moving into their active regions. After this short interval, outputs enabled increment pulse width from zero duty cycle operational pulse width, thus allowing output voltage slowly reach CORE voltage. CORE voltage will reach programmed value before 2048 cycles, PGOOD output will initiated until 2048th switching cycle. Soft-Start time delay time, 2048/FSW. oscillator frequency, FSW, 200kHz, first cycles 160µs, outputs held three state level explained above. After this period short interval described above, outputs initiated voltage rises 10.08ms, total delay time 10.24ms.
FIGURE FOUR PHASE OUTPUT 500kHz
Power supply ripple frequency determined channel frequency, FSW, multiplied number active channels.
FN4817.3 December 2004
HIP6311
Figure shows start-up sequence initiated fast rising supply, VCC, applied HIP6311. Note short rise three state level output during first cycles.
SUPPLY
PGOOD OUTPUT VCORE DELAY TIME PGOOD SUPPLY VCORE
CORE LOAD CURRENT FREQUENCY 200kHz SUPPLY ACTIVATED "PS-ON PIN"
FIGURE SUPPLY POWERED SUPPLY
FIGURE START-UP PHASE SYSTEM OPERATING 500kHz
Figure shows waveforms when regulator operating 200kHz. Note that Soft-Start duration function Channel Frequency explained previously. Also note pulses COMP terminal. These pulses current correction signal feeding into comparator input (see Block Diagram page
Note that Figure shows gate driver voltage available before supply HIP6311 reached threshold level. conditions were reversed supply rise first, start-up sequence would different. this case HIP6303 will sense over-current condition charging output capacitors. supply will then restart through normal Soft-Start cycle.
Fault Protection
HIP6311 protects microprocessor entire power system from damaging stress levels. Within HIP6311 both Over-Voltage Over-Current circuits incorporated protect load regulator.
COMP
Over-Voltage
VSEN connected microprocessor CORE voltage. CORE over-voltage condition detected when VSEN goes more than above programmed level. over-voltage condition latched, disabling normal operation, causing PGOOD low. latch only reset lowering returning high initiate Soft-Start sequence. During latched over-voltage, outputs will driven either three state, depending upon VSEN input. outputs driven when VSEN detects that CORE voltage above programmed level. This condition drives outputs low, resulting lower synchronous rectifier MOSFETS conduct shunt CORE voltage ground protect load. after this event, CORE voltage falls below overvoltage limit (plus some hysteresis), outputs will three state. HIP6601 family drivers pass three state information along, shuts both upper lower MOSFETs. This prevents "dumping" output capacitors
DELAY TIME PGOOD
VCORE
FIGURE START-UP PHASE SYSTEM OPERATING 200kHz
Figure shows regulator operating from supply. this figure, note slight rise PGOOD supply rises.The PGOOD output stage made NMOS PMOS transistors. rising VCC, PMOS device becomes active slightly before NMOS transistor pulls "down", generating slight rise PGOOD voltage.
FN4817.3 December 2004
HIP6311
back through lower MOSFETs, avoiding possibly destructive ringing capacitors output inductors. conditions that caused over-voltage still persist, outputs will cycled between three state VCORE clamped ground, hysteretic shunt regulator.
CORE Voltage Programming
voltage identification pins (VID0, VID1, VID3, VID4) CORE output voltage. Each pulled internal 20µA current source accepts standard lowvoltage CMOS signals. Table shows nominal voltage function codes. power supply system ±0.8% accurate over operating temperature voltage range.
TABLE VOLTAGE IDENTIFICATION CODES VID4 VID3 VID2 VID1 VID0 VDAC 1.100 1.125 1.150 1.175 1.200 1.225 1.250 1.275 1.300 1.325 1.350 1.375 1.400 1.425 1.450 1.475 1.500 1.525 1.550 1.575 1.600 1.625 1.650 1.675 1.700 1.725 1.750 1.775 1.800 1.825 1.850
Under-Voltage
VSEN also detects when CORE voltage falls more than below programmed level. This causes PGOOD low, other effect operation latched. There also hysteresis this detection point.
Over-Current
event over-current condition, over-current protection circuit reduces average current delivered less than current limit. When over-current condition detected, controller forces outputs into three state mode. This condition results gate driver removing drive output stages.The HIP6311 goes into wait delay timing cycle that equal Soft-Start ramp time. PGOOD also goes "low" during this time VSEN going below threshold voltage.To lower average output dissipation, Soft-Start initial wait time increased from 2048 cycles, then Soft-Start ramp initiated. frequency 200kHz, instance, over-current detection would cause dead time 10.24ms, then ramp 10.08ms. delay, outputs restarted Soft-Start ramp initiated. short present that time, cycle repeated. This hiccup mode. Figure shows supply shorted under operation hiccup operating mode described above. Note that high short circuit current, over-current detected before completion start-up sequence delay quite long normal Soft-Start cycle.
SHORT APPLIED HERE PGOOD
SHORT CURRENT 50A/Div
HICCUP MODE. SUPPLY POWERED SUPPLY CORE LOAD CURRENT 31A, LOAD SUPPLY FREQUENCY 200kHz, SUPPLY ACTIVATED "PS-ON PIN"
FIGURE SHORT APPLIED SUPPLY AFTER POWER-UP
FN4817.3 December 2004
HIP6311
COMP HIP6311 SAWTOOTH COMPARATOR CIRCUIT HIP6601 VCORE COUT RLOAD
ERROR AMPLIFIER
GENERATOR CORRECTION
REFERENCE
DIFFERENCE CURRENT SENSING ISEN RISEN
PHASE
OTHER CHANNELS CURRENT SENSING FROM OTHER CHANNELS AVERAGING OVER CURRENT TRIP
ONLY OUTPUT STAGE SHOWN
COMPARATOR REFERENCE
INDUCTOR CURRENT(S) FROM OTHER CHANNELS
FIGURE SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT VOLTAGE SAMPLING
Current Sensing Balancing
Overview
HIP6311 samples on-state voltage drop across each synchronous rectifier FET, indication inductor current that phase, Figure Neglecting effects discussed later), voltage drop across simply rDS(ON)(Q2) inductor current (IL). Note that inductor current, either 1/2, 1/3, total current (ILT), depending many phases use. voltage Q2's drain, PHASE node, applied RISEN resistor develop IISEN current HIP6311 ISEN pin. This held virtual ground, current through RISEN rDS(ON)(Q2) RISEN. IISEN current provides information perform following functions: Detection over-current condition Reduce regulator output voltage with increasing load current (droop) Balance currents multiple channels
Over-Current, Selecting RISEN
current detected through RISEN resistor averaged with current(s) detected other channels. averaged current compared with trimmed, internally generated current, used detect over-current condition. nominal current through RISEN resistor should 50µA full output load current, nominal trip point over-current detection 165% that value, 82.5µA. Therefore, RISEN rDS(ON) (Q2) 50µA. full load phase, rDS(ON) (Q2) RISEN over-current trip point would 165% 25A, phase. RISEN value adjusted change over-current trip point, suggested stay within ±25% nominal.
Droop, Selection
average currents detected through RISEN resistors also steered pin. There return path connected except RIN, average
FN4817.3 December 2004
HIP6311
current creates voltage drop across RIN. This drop increases apparent VCORE voltage with increasing load current, causing system decrease VCORE maintain balance pin. This desired "droop" voltage used maintain VCORE within limits under transient conditions. With high dv/dt load transient, typical high performance microprocessors, largest deviations output voltage occur leading trailing edges load transient. order fully utilize output-voltage tolerance range, output voltage positioned upper half range when output unloaded lower half range when controller under full load. This droop compensation allows larger transient voltage deviations thus reduces size cost output filter components. should selected give desired "droop" voltage normal full load current 50µA applied through RISEN resistor different full load current adjusted under "Over-Current, Selecting RISEN" above). Vdroop/50µA Vdroop 80mV, 1.6k feedback components, scaled relation RIN. iPK-PK (VIN VCORE VCORE2) VIN) Where: VCORE value output voltage value input supply voltage value inductor switching frequency
Example: VCORE 1.6V, 12V, 1.3µH, 250kHz, Then iPK-PK 4.3A
AMPERES
Current Balancing
detected currents also used balance phase currents. Each phase's current compared average phase currents, difference used create offset that phase's comparator. offset direction reduce imbalance. balancing circuit make difference rDS(ON) between synchronous rectifiers. higher rDS(ON), current through that phase will reduced. Figures show inductor current phase system without with current balancing.
AMPERES
FIGURE CHANNEL MULTIPHASE SYSTEM WITH CURRENT BALANCING DISABLED
Inductor Current
inductor current each phase multi-phase Buck converter components. There current equal load current divided number phases (ILT sawtooth current, (iPK-PK) switching. sawtooth component dependent size inductors, switching frequency each phase, values input output voltage. Ignoring secondary effects, such series resistance, peak peak value sawtooth current described
FIGURE CHANNEL MULTIPHASE SYSTEM WITH CURRENT BALANCING ENABLED
inductor, load current, flows alternately from through from ground through HIP6311 samples on-state voltage drop across each transistor indicate inductor current that phase. voltage drop sampled switching period, 1/FSW, after turned turned Because sawtooth current component, sampled current different from
FN4817.3 December 2004
HIP6311
average current phase. Neglecting secondary effects, sampled current (ISAMPLE) related load current (ILT) ISAMPLE (VINVCORE 3VCORE2) VIN) Where: total load current number channels Example: Using previously given conditions, 100A, Then ISAMPLE 25.49A discussed previously, voltage drop across each transistor point time when current sampled rDSON (Q2) ISAMPLE. voltage Q2's drain, PHASE node, applied through RISEN resistor HIP6311 ISEN pin. This held virtual ground, current into ISEN ISENSE ISAMPLE rDS(ON) (Q2) RISEN. RIsen ISAMPLE rDS(ON) (Q2) 50µA
1,000
1,000 2,000 5,000 10,000 CHANNEL OSCILLATOR FREQUENCY, (kHz)
FIGURE RESISTANCE FREQUENCY
Example: From previous conditions, where ISAMPLE rDS(ON) (Q2) Then: RISEN ICURRENT TRIP Short circuit 100A, 25.49A, 2.04K 165% 165A.
Layout Considerations
MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. These voltage spikes degrade efficiency, radiate noise into circuit lead device over-voltage stress. Careful component layout printed circuit design minimizes voltage spikes converter. Consider, example, turnoff transition upper MOSFET. Prior turnoff, upper MOSFET carrying channel current. During turnoff, current stops flowing upper MOSFET picked lower MOSFET. inductance switched current path generates large voltage spike during switching interval. Careful component selection, tight layout critical components, short, wide circuit traces minimize magnitude voltage spikes. Contact Intersil evaluation board drawings component placement printed circuit board. There sets critical components DC-DC converter using HIP6311 controller HIP6601 gate driver. power components most critical because they switch large amounts energy. Next small signal components that connect sensitive nodes supply critical bypassing current signal coupling. power components should placed first. Locate input capacitors close power switches. Minimize length connections between input capacitors, CIN, power switches. Locate output inductors output capacitors between MOSFETs load. Locate gate driver close MOSFETs.
Channel Frequency Oscillator
channel oscillator frequency placing resistor, ground from FS/DIS pin. Figure curve showing relationship between frequency, FSW, resistor avoid pickup FS/DIS pin, important place this resistor next pin. this also used disable converter, also important locate pulldown device next this pin.
FN4817.3 December 2004
HIP6311
critical small components include bypass capacitors PVCC gate driver ICs. Locate bypass capacitor, CBP, HIP6311 controller close device. especially important locate resistors associated with input amplifiers close their respective pins, since they represent input feedback amplifiers. Resistor that sets oscillator frequency should also located next associated pin. especially important place RSEN resistor(s) respective terminals HIP6311. multi-layer printed circuit board recommended. Figure shows connections critical components output channel converter. Note that capacitors COUT could each represent numerous physical capacitors. Dedicate solid layer, usually middle layer board, ground plane make critical component ground connections with vias this layer. Dedicate another solid layer power plane break this plane into smaller islands common voltage levels. Keep metal runs from PHASE terminal inductor short. power plane should support input power output power nodes. copper filled polygons bottom circuit layers phase nodes. remaining printed circuit layers small signal wiring. wiring traces from driver MOSFET gate source should sized carry least ampere current. multiple high quality capacitors different size dielectric paralleled meet design constraints. Modern microprocessors produce severe transient load rates. High frequency capacitors supply initially transient current slow load rate-of-change seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. only specialized low-ESR capacitors intended switching-regulator applications bulk capacitors. bulk capacitor's determines output ripple voltage initial voltage drop following high slew-rate transient's edge. most cases, multiple capacitors small case size perform better than single large case capacitor. Bulk capacitor choices include aluminum electrolytic, OSCon, Tantalum even ceramic dielectrics. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Consult capacitor manufacturer measure capacitor's impedance with frequency select suitable component.
Component Selection Guidelines
Output Capacitor Selection
output capacitor selected meet both dynamic load requirements voltage ripple requirements. load transient microprocessor CORE characterized high slew rate (di/dt) current demands. general,
+5VIN +12V
INDIVIDUAL METAL RUNS EACH CHANNEL HELP ISOLATE OUTPUT STAGES
PVCC LOCATE NEXT PIN(S) CBOOT PHASE COUT LOCATE NEAR TRANSISTOR VCORE
COMP FS/DIS HIP6601
LOCATE NEXT
HIP6311
LOCATE NEXT RSEN VSEN ISEN
ISLAND POWER PLANE LAYER ISLAND CIRCUIT PLANE LAYER CONNECTION GROUND PLANE
FIGURE PRINTED CIRCUIT BOARD POWER PLANES ISLANDS
FN4817.3 December 2004
HIP6311
Output Inductor Selection
parameters limiting converter's response load transient time required change inductor current. Small inductors multi-phase converter reduces response time without significant increases total ripple current. output inductor each power channel controls ripple current. control stable channel ripple current (peak-to-peak) twice average current. single channel's ripple current approximately:
SINGLE CHANNEL
CURRENT MULTIPLIER
CHANNEL CHANNEL CHANNEL
current from multiple channels tend cancel each other reduce total ripple current. Figure gives total ripple current function duty cycle, normalized parameter zero duty cycle. determine total ripple current from number channels duty cycle, multiply y-axis value
RIPPLE CURRENT (APEAK-PEAK) SINGLE CHANNEL
DUTY CYCLE (VO/VIN)
FIGURE CURRENT MULTIPLIER DUTY CYCLE
FSW)
First determine operating duty ratio ratio output voltage divided input voltage. Find Current Multiplier from curve with appropriate power channels. Multiply current multiplier full load output current. resulting value current rating required input capacitor. input bypass capacitors control voltage overshoot across MOSFETs. ceramic capacitance high frequency decoupling bulk capacitors supply current. Small ceramic capacitors should placed very close drain upper MOSFET suppress voltage induced parasitic circuit impedances. bulk capacitance, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MV-GX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surge-current power-up. series available from AVX, 593D series from Sprague both surge current tested.
CHANNEL CHANNEL CHANNEL
DUTY CYCLE (VO/VIN)
FIGURE RIPPLE CURRENT DUTY CYCLE
Small values output inductance cause excessive power dissipation. HIP6303 designed stable operation ripple currents twice load current. However, this condition, current 115% above value shown following MOSFET Selection Considerations section. With else fixed, decreasing inductance could increase power dissipated MOSFETs 30%.
MOSFET Selection Considerations
high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. These losses distributed between upper lower MOSFETs according duty factor (see following equations). conduction losses main component power dissipation lower MOSFETs, Figure Only upper MOSFETs, have significant switching losses, since lower device turns into near zero voltage. equations assume linear voltage-current transitions model power loss reverse-recovery lower MOSFETs body diode. gate-charge losses
FN4817.3 December 2004
Input Capacitor Selection
important parameters bulk input capacitors voltage rating current rating. reliable operation, select bulk input capacitors with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline. current required multi-phase converter approximated with Figure
HIP6311
dissipated Driver don't heat MOSFETs. However, large gate-charge increases switching time, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal-resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow.
UPPER LOWER
diode, anode ground, placed across These diodes function clamp that catches negative inductor swing during dead time between turn lower MOSFETs turn upper MOSFETs. diodes must Schottky type prevent lossy parasitic MOSFET body diode from conducting. usually acceptable omit diodes body diodes lower MOSFETs clamp negative inductor swing, efficiency could drop percent result. diode's rated reverse breakdown voltage must greater than maximum input voltage.
FN4817.3 December 2004
HIP6311 Small Outline Plastic Packages (SOIC)
INDEX AREA 0.25(0.010)
M20.3 (JEDEC MS-013-AC ISSUE LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL 0.0926 0.0040 0.014 0.0091 0.4961 0.2914 0.1043 0.0118 0.019 0.0125 0.5118 0.2992 MILLIMETERS 2.35 0.10 0.35 0.23 12.60 7.40 2.65 0.30 0.49 0.32 13.00 7.60 NOTES Rev. 1/02
SEATING PLANE
0.050 0.394 0.010 0.016 0.419 0.029 0.050
1.27 10.00 0.25 0.40 10.65 0.75 1.27
0.10(0.004)
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch) Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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FN4817.3 December 2004

Data Sheet December 2004 FN4817.3 Microprocessor CORE Voltage Reg

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