Data Sheet December 2004 FN4324.2 Buck Synchronous-Rectifier Puls

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Data Sheet December 2004 FN4324.2 Buck Synchronous-Rectifier Puls

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HIP6012
Data Sheet December 2004 FN4324.2
Buck Synchronous-Rectifier Pulse-Width Modulator (PWM) Controller
HIP6012 provides complete control protection DC-DC converter optimized high-performance microprocessor applications. designed drive N-Channel MOSFETs synchronous-rectified buck topology. HIP6012 integrates control, output adjustment, monitoring protection functions into single package. output voltage converter precisely regulated 1.27V, with maximum tolerance ±1.5% over temperature line voltage variations. HIP6012 provides simple, single feedback loop, voltagemode control with fast transient response. includes 200kHz free-running triangle-wave oscillator that adjustable from below 50kHz over 1MHz. error amplifier features 15MHz gain-bandwidth product 6V/µs slew rate which enables high converter bandwidth fast transient performance. resulting duty ratio ranges from 100%. HIP6012 protects against overcurrent conditions inhibiting operation. HIP6012 monitors current using rDS(ON) upper MOSFET which eliminates need current sensing resistor.
Features
Drives N-Channel MOSFETs Operates From +12V Input Simple Single-Loop Control Design Voltage-Mode Control Fast Transient Response High-Bandwidth Error Amplifier Full 100% Duty Ratio Excellent Output Voltage Regulation 1.27V Internal Reference ±1.5% Over Line Voltage Temperature Overcurrent Fault Monitor Does Require Extra Current Sensing Element Uses MOSFETs rDS(ON) Small Converter Size Constant Frequency Operation 200kHz Free-Running Oscillator Programmable from 50kHz Over 1MHz Pin, SOIC TSSOP Packages Pb-Free Available (RoHS Compliant)
Applications
Power Supply Pentium®, Pentium Pro, PowerPCand AlphaMicroprocessors High-Power 3.xV DC-DC Regulators Low-Voltage Distributed Power Supplies
Pinout
HIP6012 (SOIC, TSSOP) VIEW
OCSET COMP PVCC LGATE PGND BOOT UGATE PHASE
Ordering Information
PART NUMBER HIP6012CB HIP6012CBZ (See Note) HIP6012CV HIP6012CVZ (See Note) TEMP. RANGE (oC) PACKAGE SOIC SOIC (Pb-free) TSSOP TSSOP (Pb-free) PKG. M14.15 M14.15 M14.173 M14.173
"-T" suffix tape reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials 100% matte plate termination finish, which RoHS compliant compatible with both SnPb Pb-free soldering operations. Intersil Pb-free products classified Pb-free peak reflow temperatures that meet exceed Pb-free requirements IPC/JEDEC STD-020.
PowerPCis trademark IBM. Alphais trademark Digital Equipment Corporation. Pentium® registered trademark Intel Corporation.
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Intersil Design trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2001, Rights Reserved
HIP6012 Typical Application
OCSET MONITOR PROTECTION BOOT +12V
UGATE PHASE PVCC +12V
HIP6012
LGATE PGND
COMP
Block Diagram
POWER-ON RESET (POR) 10µA OCSET
OVERCURRENT
SOFTSTART
BOOT UGATE PHASE
200µA
1.27 VREF REFERENCE
COMPARATOR
INHIBIT
COMP
ERROR
GATE CONTROL LOGIC
PVCC LGATE PGND
OSCILLATOR
FN4324.2 December 2004
HIP6012
Absolute Maximum Ratings
Supply Voltage, +15.0V Boot Voltage, VBOOT VPHASE +15.0V Input, Output Voltage -0.3V +0.3V Classification Class
Thermal Information
Thermal Resistance (Typical, Note (oC/W) SOIC Package TSSOP Package Maximum Junction Temperature 150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (Lead tips only)
Operating Conditions
Supply Voltage, +12V ±10% Ambient Temperature Range 70oC Junction Temperature Range 125oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted high effective thermal conductivity test board free air. Tech Brief TB379 details.
Electrical Specifications
PARAMETER SUPPLY CURRENT Nominal Supply Shutdown Supply POWER-ON RESET Rising Threshold Falling Threshold Enable Input threshold Voltage Rising VOCSET Threshold OSCILLATOR Free Running Frequency Total Variation Ramp Amplitude REFERENCE Reference Voltage ERROR AMPLIFIER Gain Gain-Bandwidth Product Slew Rate GATE DRIVERS Upper Gate Source Upper Gate Sink Lower Gate Source Lower Gate Sink PROTECTION OCSET Current Source Soft Start Current
Recommended Operating Conditions, Unless Otherwise Noted SYMBOL TEST CONDITIONS UNITS
VCC; UGATE LGATE Open
VOCSET 4.5VDC VOCSET 4.5VDC VOCSET 4.5VDC
1.27
10.4
OPEN, 200k VOSC OPEN
VP-P
1.251
1.270
1.289
COMP 10pF
V/µs
IUGATE RUGATE ILGATE RLGATE
VBOOT VPHASE 12V, VUGATE ILGATE 0.3A 12V, VLGATE ILGATE 0.3A
IOCSET
VOCSET 4.5VDC
FN4324.2 December 2004
HIP6012 Typical Performance Curves
CGATE 3300pF IVCC (mA) CGATE 10pF CGATE 1000pF
1000 RESISTANCE
PULLUP +12V
PULLDOWN
SWITCHING FREQUENCY (kHz)
1000
1000
SWITCHING FREQUENCY (kHz)
FIGURE RESISTANCE FREQUENCY
FIGURE BIAS SUPPLY CURRENT FREQUENCY
Functional Descriptions
overcurrent trip cycles soft-start function.
OCSET COMP PVCC LGATE PGND BOOT UGATE PHASE
(Pin
Connect capacitor from this ground. This capacitor, along with internal 10µA current source, sets softstart interval converter.
COMP (Pin (Pin
COMP available external pins error amplifier. inverting input error amplifier COMP error amplifier output. These pins used compensate voltage-control feedback loop converter.
(Pin
This provides oscillator switching frequency adjustment. placing resistor (RT) from this GND, nominal 200kHz switching frequency increased according following equation:
200kHz
(Pin
This open-collector enable pin. Pull this below disable converter. shutdown, soft start discharged UGATE LGATE pins held low.
GND)
(Pin
Signal ground voltage levels measured with respect this pin.
Conversely, connecting pull-up resistor (RT) from this reduces switching frequency according following equation.:
200kHz
PHASE (Pin
Connect PHASE upper MOSFET source. This used monitor voltage drop across MOSFET overcurrent protection. This also provides return path upper gate drive.
12V)
OCSET (Pin
Connect resistor (ROCSET) from this drain upper MOSFET. ROCSET, internal 200µA current source (IOCS), upper MOSFET on-resistance (rDS(ON)) converter overcurrent (OC) trip point according following equation:
OCSET PEAK
UGATE (Pin
Connect UGATE upper MOSFET gate. This provides gate drive upper MOSFET.
BOOT (Pin
This provides bias voltage upper MOSFET driver. bootstrap circuit used create BOOT voltage suitable drive standard N-Channel MOSFET.
FN4324.2 December 2004
HIP6012
PGND (Pin
This power ground connection. lower MOSFET source this pin.
LGATE (Pin
Connect LGATE lower MOSFET gate. This provides gate drive lower MOSFET.
SOFT-START (1V/DIV.)
PVCC (Pin
Provide bias supply lower gate drive this pin.
(Pin
Provide bias supply chip this pin.
OUTPUT VOLTAGE (1V/DIV.)
Functional Description
Initialization
HIP6012 automatically initializes upon receipt power. Special sequencing input supplies necessary. Power-On Reset (POR) function continually monitors input supply voltages enable (EN) pin. monitors bias voltage input voltage (VIN) OCSET pin. level OCSET equal Less fixed voltage drop (see overcurrent protection). With held VCC, function initiates soft start operation after both input supply voltages exceed their thresholds. operation with single +12V power source, equivalent +12V power source must exceed rising threshold before initiates operation. Power-On Reset (POR) function inhibits operation with chip disabled low). With both input supplies above their thresholds, transitioning high initiates soft start interval.
TIME (5ms/DIV.)
FIGURE SOFT-START INTERVAL
SOFT-START OUTPUT INDUCTOR
TIME (20ms/DIV.)
Soft Start
function initiates soft start sequence. internal 10µA current source charges external capacitor (CSS) Soft start clamps error amplifier output (COMP pin) reference input terminal error amp) voltage. Figure shows soft start interval with 0.1µF. Initially clamp error amplifier (COMP pin) controls converter's output voltage. Figure voltage reaches valley oscillator's triangle wave. oscillator's triangular waveform compared ramping error amplifier voltage. This generates PHASE pulses increasing width that charge output capacitor(s). This interval increasing pulse width continues With sufficient output voltage, clamp reference input controls output voltage. This interval between Figure voltage exceeds reference voltage output voltage regulation. This method provides rapid controlled output voltage rise.
FIGURE OVERCURRENT OPERATION
Overcurrent Protection
overcurrent function protects converter from shorted output using upper MOSFETs on-resistance, rDS(ON) monitor current. This method enhances converter's efficiency reduces cost eliminating current sensing resistor. overcurrent function cycles soft-start function hiccup mode provide fault protection. resistor (ROCSET) programs overcurrent trip level. internal 200µA (typical) current sink develops voltage across ROCSET that reference VIN. When voltage across upper MOSFET (also referenced VIN) exceeds voltage across ROCSET, overcurrent function initiates soft-start sequence. soft-start function discharges with 10µA current sink inhibits operation. soft-start function recharges CSS, operation resumes with error amplifier clamped voltage. Should overload occur while recharging CSS, soft start function inhibits operation while fully charging
FN4324.2 December 2004
HIP6012
complete cycle. Figure shows this operation with overload condition. Note that inductor current increases over during charging interval causes overcurrent trip. converter dissipates very little power with this method. measured input power conditions Figure 2.5W. overcurrent function will trip peak inductor current (IPEAK) determined
OCSET OCSET PEAK
close because internal current source only 10µA. Provide local decoupling between pins. Locate capacitor, CBOOT close practical BOOT PHASE pins.
HIP6012
UGATE PHASE
VOUT
where IOCSET internal OCSET current source (200µA typical). trip point varies mainly MOSFETs rDS(ON) variations. avoid overcurrent tripping normal operating load range, find ROCSET resistor from equation above with: maximum rDS(ON) highest junction temperature. minimum IOCSET from specification table. Determine PEAK PEAK where output inductor ripple current. equation ripple current section under component guidelines titled `Output Inductor Selection'. small ceramic capacitor should placed parallel with ROCSET smooth voltage across ROCSET presence switching noise input voltage.
LGATE PGND
RETURN
FIGURE PRINTED CIRCUIT BOARD POWER GROUND PLANES ISLANDS
BOOT CBOOT
+VIN VOUT LOAD
HIP6012
PHASE +12V
Application Guidelines
Layout Considerations
high frequency switching converter, layout very important. Switching current from power device another generate voltage transients across impedances interconnecting bond wires circuit traces. These interconnecting impedances should minimized using wide, short printed circuit traces. critical components should located close together possible using ground plane construction single point grounding. Figure shows critical power components converter. minimize voltage overshoot interconnecting wires indicated heavy lines should part ground power plane printed circuit board. components shown Figure should located close together possible. Please note that capacitors each represent numerous physical capacitors. Locate HIP6012 within inches MOSFETs, circuit traces MOSFETs' gate source connections from HIP6012 must sized handle peak current. Figure shows circuit traces that require additional layout consideration. single point ground plane construction circuits shown. Minimize leakage current paths locate capacitor,
CVCC
FIGURE PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
Feedback Compensation
Figure highlights voltage-mode control loop synchronous-rectified buck converter. output voltage (VOUT) regulated Reference voltage level. error amplifier (Error Amp) output (VE/A) compared with oscillator (OSC) triangular wave provide pulse-width modulated (PWM) wave with amplitude PHASE node. wave smoothed output filter CO). modulator transfer function small-signal transfer function VOUT/VE/A. This function dominated Gain output filter CO), with double pole break frequency zero FESR. Gain modulator simply input voltage (VIN) Divided peak-to-peak oscillator voltage VOSC.
FN4324.2 December 2004
LOAD
HIP6012
COMPARATOR VOSC DRIVER DRIVER PHASE (PARASITIC) VE/A ERROR VOUT
Place Pole Half Switching Frequency Check Gain against Error Amplifier's Open-Loop Gain Estimate Phase Margin Repeat Necessary Figure shows asymptotic plot DC-DC converter's gain frequency. actual Modulator Gain high gain peak high factor output filter shown Figure Using above guidelines should give Compensation Gain similar curve plotted. open loop error amplifier gain bounds compensation gain. Check compensation gain with capabilities error amplifier. Closed Loop Gain constructed log-log graph Figure adding Modulator Gain Compensation Gain dB). This equivalent multiplying modulator transfer function compensation transfer function plotting gain.
GAIN (dB) MODULATOR GAIN FESR 100K 20LOG (R2/R1) OPEN LOOP ERROR GAIN
REFERENCE
DETAILED COMPENSATION COMPONENTS
VOUT
COMP
HIP6012
20LOG (VIN/VOSC) COMPENSATION GAIN CLOSED LOOP GAIN
FIGURE VOLTAGE MODE BUCK CONVERTER COMPENSATION DESIGN
Modulator Break Frequency Equations
FREQUENCY (Hz)
FIGURE ASYMPTOTIC BODE PLOT CONVERTER GAIN
compensation network consists error amplifier (internal HIP6012) impedance networks ZFB. goal compensation network provide closed loop transfer function with highest crossing frequency (f0dB) adequate phase margin. Phase margin difference between closed loop phase f0dB 180o. equations below relate compensation network's poles, zeros gain components (R1, Figure these guidelines locating poles zeros compensation network:
compensation gain uses external impedance networks provide stable, high bandwidth (BW) overall loop. stable control loop gain crossing with -20dB/decade slope phase margin greater than 45o. Include worst case component variations when determining phase margin.
Component Selection Guidelines
Output Capacitor Selection
output capacitor required filter output supply load transient current. filtering requirements function switching frequency ripple current. load transient requirements function slew rate (di/dt) magnitude transient load current. These requirements generally with capacitors careful layout. Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply transient slow current load rate seen bulk capacitors. bulk filter capacitor values generally determined (effective series resistance) voltage rating requirements rather than actual capacitance requirements.
FN4324.2 December 2004
Compensation Break Frequency Equations
Pick Gain (R2/R1) desired converter bandwidth Place Zero Below Filter's Double Pole (~75% FLC) Place Zero Filter's Double Pole Place Pole Zero
HIP6012
High frequency decoupling capacitors should placed close power pins load physically possible. careful inductance circuit board wiring that could cancel usefulness these inductance components. Consult with manufacturer load specific decoupling requirements. example, Intel recommends that high frequency decoupling Pentium-Pro composed least forty (40) 1.0µF ceramic capacitors 1206 surface-mount package. only specialized low-ESR capacitors intended switching-regulator applications bulk capacitors. bulk capacitor's will determine output ripple voltage initial voltage drop after high slew-rate transient. aluminum electrolytic capacitor's value related case size with lower available larger case sizes. However, equivalent series inductance (ESL) these capacitors increases with case size reduce usefulness capacitor high slew-rate transient loading. Unfortunately, specified parameter. Work with your capacitor supplier measure capacitor's impedance with frequency select suitable component. most cases, multiple electrolytic capacitors small case size perform better than single large case capacitor. where: ITRAN transient load current step, tRISE response time application load, tFALL response time removal load. With input source, worst case response time either application removal load dependent upon output voltage setting. sure check both these equations minimum maximum output levels worst case response time.
Input Capacitor Selection
input bypass capacitors control voltage overshoot across MOSFETs. small ceramic capacitors high frequency decoupling bulk capacitors supply current needed each time turns Place small ceramic capacitors physically close MOSFETs between drain source important parameters bulk input capacitor voltage rating current rating. reliable operation, select bulk capacitor with voltage current ratings above maximum input voltage largest current required circuit. capacitor voltage rating should least 1.25 times greater than maximum input voltage voltage rating times conservative guideline. current rating requirement input capacitor buck regulator approximately load current. through hole design, several electrolytic capacitors (Panasonic series Nichicon series Sanyo MV-GX equivalent) needed. surface mount designs, solid tantalum capacitors used, caution must exercised with regard capacitor surge current rating. These capacitors must capable handling surge-current power-up. series available from AVX, 593D series from Sprague both surge current tested.
Output Inductor Selection
output inductor selected meet output voltage ripple requirements minimize converter's response time load transient. inductor value determines converter's ripple current ripple voltage function ripple current. ripple voltage current approximated following equations:
VOUT
Increasing value inductance reduces ripple current voltage. However, large inductance values reduce converter's response time load transient. parameters limiting converter's response load transient time required change inductor current. Given sufficiently fast control loop design, HIP6012 will provide either 100% duty cycle response load transient. response time time required slew inductor current from initial current value transient current level. During this interval difference between inductor current transient current level must supplied output capacitor. Minimizing response time minimize output capacitance required. response time transient different application load removal load. following equations give approximate response time interval application removal transient load:
TRAN RISE TRAN FALL
MOSFET Selection/Considerations
HIP6012 requires N-Channel power MOSFETs. These should selected based upon rDS(ON), gate supply requirements, thermal management requirements. high-current applications, MOSFET power dissipation, package selection heatsink dominant design factors. power dissipation includes loss components; conduction loss switching loss. conduction losses largest component power dissipation both upper lower MOSFETs. These losses distributed between MOSFETs according duty factor (see equations below). Only upper MOSFET switching losses, since Schottky rectifier clamps switching node before synchronous rectifier turns
PUPPER rDS(ON) PLOWER rDS(ON)
Where: duty cycle VIN, switching interval, switching frequency.
FN4324.2 December 2004
HIP6012
These equations assume linear voltage-current transitions adequately model power loss reverserecovery lower MOSFETs body diode. gate-charge losses dissipated HIP6012 don't heat MOSFETs. However, large gate-charge increases switching interval, which increases upper MOSFET switching losses. Ensure that both MOSFETs within their maximum junction temperature high ambient temperature calculating temperature rise according package thermal-resistance specifications. separate heatsink necessary depending upon MOSFET power, package type, ambient temperature flow. Standard-gate MOSFETs normally recommended with HIP6012. However, logic-level gate MOSFETs used under special circumstances. input voltage, upper gate drive level, MOSFETs absolute gate-tosource voltage rating determine whether logic-level MOSFETs appropriate. Figure shows upper gate drive (BOOT pin) supplied bootstrap circuit from boot capacitor, CBOOT develops floating supply voltage referenced PHASE pin. This supply refreshed each cycle voltage less boot diode drop (VD) when lower MOSFET, turns logic-level MOSFET only used MOSFETs absolute gate-to-source voltage rating exceeds maximum voltage applied logic-level MOSFET used absolute gate-tosource voltage rating exceeds maximum voltage applied PVCC.
+12V DBOOT BOOT +12V
Figure shows upper gate drive supplied direct connection This option should only used converter systems where main input voltage less. peak upper gate-to-source voltage approximately less input supply. main power bias, gate-to-source voltage logic-level MOSFET good choice logic-level MOSFET used absolute gate-to-source voltage rating exceeds maximum voltage applied PVCC.
+12V LESS
HIP6012
BOOT UGATE PHASE +12V NOTE: VG-S PVCC NOTE: VG-S
PVCC
LGATE PGND
FIGURE UPPER GATE DRIVE DIRECT DRIVE OPTION
Schottky Selection
Rectifier clamp that catches negative inductor swing during dead time between turning lower MOSFET turning upper MOSFET. diode must Schottky type prevent lossy parasitic MOSFET body diode from conducting. acceptable omit diode body diode lower MOSFET clamp negative inductor swing, efficiency will drop percent result. diode's rated reverse breakdown voltage must greater than maximum input voltage.
HIP6012
UGATE PHASE
CBOOT
NOTE: VG-S
PVCC +12V LGATE PGND NOTE: VG-S PVCC
FIGURE UPPER GATE DRIVE BOOTSTRAP OPTION
FN4324.2 December 2004
HIP6012 HIP6012 DC-DC Converter Application Circuit
figure below shows DC-DC converter circuit microprocessor application, originally designed employ HIP6006 controller. Given similarities between HIP6006 HIP6012 controllers, circuit implemented using HIP6012 controller without modifications. However, given expanded reference voltage tolerance range, HIP6012-based converter require additional output capacitance. Detailed information circuit, including complete Bill-of-Materials circuit board description, found application note AN9722. Intersil's home page web: www.intersil.com
12VCC C1-3 680µF C17-18 1206
ENABLE 0.1µF SPARE
1206
MONITOR PROTECTION OCSET BOOT UGATE PHASE PVCC COMP 0.1µF VOUT C6-9 1000µF 1000pF 3.01K 4148
PHASE
HIP6012
LGATE PGND
-C14
33pF 0.01µF SPARE SPARE
COMP
Component Selection Notes:
C1-C3 each 680µF VDC, Sanyo MV-GX equivalent. C6-C9 each 1000µF 6.3W VDC, Sanyo MV-GX equivalent. -Core: Micrometals T50-52B; Winding: Turns 17AWG. -1N4148 equivalent. -3A, Schottky, Motorola MBR340 equivalent. -Intersil MOSFET; RFP25N05 FIGURE DC-DC CONVERTER APPLICATION CIRCUIT
FN4324.2 December 2004
HIP6012 Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M14.15 (JEDEC MS-012-AB ISSUE
LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 1.35 0.10 0.33 0.19 8.55 3.80 1.75 0.25 0.51 0.25 8.75 4.00 NOTES Rev. 12/93
0.0532 0.0040 0.013 0.0075 0.3367 0.1497
0.0688 0.0098 0.020 0.0098 0.3444 0.1574
0.10(0.004)
0.25(0.010)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
FN4324.2 December 2004
HIP6012 Thin Shrink Small Outline Plastic Packages (TSSOP)
INDEX AREA 0.05(0.002) -CSEATING PLANE 0.25 0.010 GAUGE PLANE 0.25(0.010)
M14.173
LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL 0.002 0.031 0.0075 0.0035 0.195 0.169 0.047 0.006 0.051 0.0118 0.0079 0.199 0.177 MILLIMETERS 0.05 0.80 0.19 0.09 4.95 4.30 1.20 0.15 1.05 0.30 0.20 5.05 4.50 NOTES Rev. 6/00
0.10(0.004)
0.10(0.004)
0.026 0.246 0.0177 0.256 0.0295
0.65 6.25 0.45 6.50 0.75
NOTES: These package dimensions within allowable dimensions JEDEC MO-153-AC, Issue Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension "E1" does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.15mm (0.006 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. Dimension does include dambar protrusion. Allowable dambar protrusion shall 0.08mm (0.003 inch) total excess dimension maximum material condition. Minimum space between protrusion adjacent lead 0.07mm (0.0027 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact. (Angles degrees)
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN4324.2 December 2004

Data Sheet December 2004 FN4324.2 Buck Synchronous-Rectifier Puls

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