Data Sheet January 2006 FN3705.4 Monolithic, Wideband, High Slew

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Data Sheet January 2006 FN3705.4 Monolithic, Wideband, High Slew

Datasheet Thumbnail

Top Searches for this datasheet

HA-5002/883
Data Sheet January 2006 FN3705.4
Monolithic, Wideband, High Slew Rate, High Output Current Buffer
HA-5002/883 monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing advantages Intersil Dielectric Isolation technologies, HA-5002/883 current buffer offers 1300V/µs slew rate typically 1000V/µs minimum with 110MHz bandwidth. ±100mA minimum output current capability enhanced output impedance. monolithic HA-5002/883 will replace hybrid LH0002 with corresponding performance increases. These characteristics range from (typ) input impedance increased output voltage swing. Monolithic design technologies have allowed more precise buffer developed with more than order magnitude smaller gain error. voltage gain 0.98 guaranteed minimum with load 0.96 minimum with load. HA-5002/883 will provide many present hybrid users with higher degree reliability same time increase overall circuit performance.
Features
This Circuit Processed Accordance MIL-STD-883 Fully Conformant Under Provisions Paragraph 1.2.1. Voltage Gain 0.98 (Min) 0.995 (Typ) 100) 0.96 (Min) 0.971 (Typ) High Input Impedance 1.5M (Min) (Typ) Output Impedance (Max) (Typ) Very High Slew Rate .1000V/µs (Min) 1300V/µs (Typ) Wide Small Signal Bandwidth 110MHz (Typ) High Output Current .100mA (Min) High Pulsed Output Current 400mA (Max) Monolithic Dielectric Isolation Construction Replaces Hybrid LH0002
Ordering Information
PART NUMBER PART MARKING TEMP RANGE (°C) PACKAGE
Applications
Line Driver Data Acquisition 110MHz Buffer High Power Current Booster High Power Current Source Sample Holds Radar Cable Driver Video Products
HA2-5002/883 HA2-5002/883 +125 HA4-5002/883 HA4-5002/883 +125 Ceramic
Pinouts
HA-5002/883 (CLCC) VIEW
HA-5002/883 (METAL CAN) VIEW
V1V2
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2004-2006. Rights Reserved other trademarks mentioned property their respective owners.
HA-5002/883
Absolute Maximum Ratings
Voltage Between Terminals. .44V Input Voltage Equal Supplies Peak Output Current (50ms Off) .±400mA Junction Temperature (TJ) +175°C Storage Temperature Range .-65°C +150°C Rating .<4000V Lead Temperature (Soldering 10s) +300°C
Thermal Information
Thermal Resistance (°C/W) (°C/W) Metal Package Ceramic Package. Package Power Dissipation Limit +75°C +175°C Metal Package .625mW Ceramic Package. .1.25W Package Power Dissipation Derating Factor Above +75°C Metal Package .6.3mW/°C Ceramic Package. .12.5mW/°C
Operating Conditions
Operating Temperature Range .-55°C +125°C Operating Supply Voltage ±12V ±15V
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: measured with component mounted effective thermal conductivity test board free air. Tech Brief TB379
details.
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested VSUPPLY ±12V ±15V, RSOURCE CLOAD 10pF, Unless Otherwise Specified. PARAMETERS Input Offset Voltage SYMBOL VIO1 CONDITIONS VSUP ±15V GROUP SUBGROUPS VIO2 VSUP ±12V Input Bias Current VSUP ±15V, VSUP ±12V, Voltage Gain +AV1 VSUP ±12V, VSUP ±12V, -10V VSUP ±12V, 100, VSUP ±12V, 100, -10V VSUP ±15V, 100, VSUP ±15V, 100, -10V VSUP ±15V, +10V VSUP ±15V, -10V TEMPERATURE (°C) +125, +125, +125, +125, +125, +125, +125, +125, 0.98 0.98 0.98 0.98 0.96 0.96 0.96 0.96 0.99 0.99 0.99 0.99 UNITS
-AV1
Voltage Gain
+AV2 -AV2
Voltage Gain
+AV3 -AV3
Voltage Gain
+AV4
-AV4
FN3705.4 January 2006
HA-5002/883
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested VSUPPLY ±12V ±15V, RSOURCE CLOAD 10pF, Unless Otherwise Specified. PARAMETERS Output Voltage Swing SYMBOL +VOUT1 CONDITIONS VSUP ±15V, 100, +15V VSUP ±15V, 100, -15V VSUP ±15V, +15V VSUP ±15V, -15V VSUP ±12V, +12V VSUP ±12V, -12V VSUP ±15V, VOUT +10V VSUP ±15V, VOUT -10V VSUP ±12V, VOUT +10V VSUP ±12V, VOUT -10V VSUP ±5V, +20V, -15V, +10V, -15V VSUP ±5V, +15V, -20V, +15V, -10V VSUP ±5V, +17V, -12V, +7V, -12V VSUP ±5V, +12V, -17V, +12V, VSUP ±15V, VOUT VSUP ±15V, VOUT VSUP ±12V, VOUT VSUP ±12V, VOUT GROUP SUBGROUPS TEMPERATURE (°C) +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, -100 -100 -100 -100 UNITS
-VOUT1
+VOUT2
-VOUT2
+VOUT3
-VOUT3
Output Current
+IOUT1
-IOUT1
+IOUT2
-IOUT2
Power Supply Rejection Ratio
+PSRR1
-PSRR1
+PSRR2
-PSRR2
Power Supply Current
+ICC1
-ICC1
+ICC2
-ICC2
FN3705.4 January 2006
HA-5002/883
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Table Intentionally Left Blank. Specifications Table TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized VSUPPLY ±15V ±12V, RLOAD CLOAD 10pF, Unless Otherwise Specified. PARAMETERS Input Resistance SYMBOL RIN1 RIN2 Slew Rate +SR1 CONDITIONS VSUP ±15V VSUP ±12V VSUP ±15V, VOUT VSUP ±15V, VOUT VSUP ±12V, VOUT VSUP ±12V, VOUT VSUP ±15V ±12V, VOUT +500mV VSUP ±15V ±12V, VOUT -500mV VSUP ±12V ±15V, VOUT +500mV VSUP ±12V ±15V, VOUT -500mV VSUP ±15V, IOUT VSUP ±12V, IOUT VSUP ±12V VSUP ±12V NOTES TEMPERATURE (°C) +125, +125, +125, +125, +125, +125, +125, +125, +125, +125, 1000 1000 1000 1000 1000 1000 1000 1000 UNITS V/µs V/µs V/µs V/µs V/µs V/µs V/µs V/µs
-SR1
+SR2
-SR2
Rise Fall Time
Overshoot
Quiescent Power Consumption
Output Resistance
ROUT1 ROUT2
NOTES: Parameters listed Table controlled design process parameters directly tested final production. These parameters characterized upon initial design release, upon design changes. These parameters guaranteed characterization based upon data from multiple production runs which reflect within variation. Measured between points. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. load outputs.) TABLE ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS Interim Electrical Parameters (Pre Burn-In) Final Electrical Test Parameters Group Test Requirements Groups Endpoints NOTE: applies Subgroup only. SUBGROUPS (SEE TABLE (Note
FN3705.4 January 2006
HA-5002/883 Characteristics
SUBSTRATE POTENTIAL (POWERED UP): V1TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5002/883
V1IN
(ALT) (ALT)
FN3705.4 January 2006
HA-5002/883 Ceramic Leadless Chip Carrier Packages (CLCC)
0.010
J20.A
MIL-STD-1835 CQCC1-N20 (C-2) CERAMIC LEADLESS CHIP CARRIER PACKAGE INCHES SYMBOL 0.060 0.050 0.022 0.006 0.342 0.100 0.088 0.028 0.022 0.358 MILLIMETERS 1.52 1.27 0.56 0.15 8.69 1.83 0.56 9.09 2.54 2.23 0.71 NOTES Rev. 5/18/94 NOTES:
0.072
0.200 0.100 0.342 0.358 0.358
5.08 2.54 9.09 9.09 5.08 2.54 0.38 1.02 0.51 1.14 1.14 1.91 0.08 1.40 1.40 2.41 0.38 9.09 1.27 8.69
0.010 PLANE PLANE
0.007
0.200 0.100 0.015 0.358 0.050 0.040 0.020 0.045 0.045 0.075 0.003 0.055 0.055 0.095 0.015
-HL3
-FE1
Metallized castellations shall connected plane terminals extend toward plane across least layers ceramic completely across ceramic layers make electrical connection with optional plane terminals. Unless otherwise specified, minimum clearance 0.015 inch (0.38mm) shall maintained between metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) Symbol maximum number terminals. Symbols "ND" "NE" number terminals along sides length "E", respectively. required plane terminals optional plane terminals used) shall electrically connected. corner shape (square, notch, radius, etc.) vary manufacturer's option, from that shown drawing. Chip carriers shall constructed minimum ceramic layers. Dimension controls overall package thickness. maximum dimension package height before being solder dipped. Dimensioning tolerancing ANSI Y14.5M-1982. Controlling dimension: INCH.
FN3705.4 January 2006
HA-5002/883 Metal Packages (Can)
REFERENCE PLANE BASE SEATING PLANE BASE METAL LEAD FINISH
T8.C MIL-STD-1835 MACY1-X8 (A1)
LEAD METAL PACKAGE INCHES SYMBOL 0.165 0.016 0.016 0.016 0.335 0.305 0.110 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS 4.19 0.41 0.41 0.41 8.51 7.75 2.79 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES Rev. 5/18/94
0.200 0.100 0.027 0.027 0.500 0.250 0.010 0.040 0.034 0.045 0.750 0.050 0.045
5.08 2.54 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
SECTION
NOTES: (All leads) applies between applies between 0.500 from reference plane. Diameter uncontrolled beyond 0.500 from reference plane. Measured from maximum diameter product. basic spacing from centerline terminal basic spacing each lead lead position places) from looking bottom package. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
Intersil U.S. products manufactured, assembled tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications viewed www.intersil.com/design/quality
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, www.intersil.com
FN3705.4 January 2006

Data Sheet January 2006 FN3705.4 Monolithic, Wideband, High Slew

Top Searches for this datasheet

Other recent searches