CMOS QuadCAS DRAM (EDO) family Features Organization: 4,194,304 w

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CMOS QuadCAS DRAM (EDO) family Features Organization: 4,194,304 w

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AS4C4M4EOQ AS4C4M4E1Q
CMOS QuadCAS DRAM (EDO) family Features
Organization: 4,194,304 words bits High speed 50/60 access time 25/30 column address access time 12/15 access time power consumption Active: Standby: max, CMOS Extended data Refresh 4096 refresh cycles, refresh interval 4C4M4EOQ 2048 refresh cycles, refresh interval AS4C4M4E1Q RAS-only hidden refresh CAS-before-RAS refresh self-refresh TTL-compatible separate pins allow separate operation JEDEC standard package mil, 28-pin mil, 28-pin TSOP power supply Latch-up current protection 2000
arrangement
I/O0 I/O1 *NC/A11 CAS0 CAS1 I/O3 I/O2 CAS3 CAS2 I/O0 I/O1 *NC/A11 CAS0 CAS1
designation
TSOP
I/O3 I/O2 CAS3 CAS2
Pin(s) I/O0 I/O3
Description Address inputs address strobe Column address strobe Write enable Input/output Output enable Power Ground Connection
AS4C4M4E0
refresh version; refresh version
Selection guide
Symbol Maximum access time Maximum column address access time Maximum access time Maximum output enable (OE) access time Minimum read write cycle time Minimum hyper page mode cycle time Maximum operating current Maximum CMOS standby current
3/22/01; v.1.0
AS4C4M4E0
4C4M4EOQ/E1Q-50
4C4M4EOQ/E1-60
Unit
tRAC tCAA tCAC tOEA ICC1 ICC5
Alliance Semiconductor
Copyright Alliance Semiconductor. rights reserved.
AS4C4M4EOQ AS4C4M4E1Q
Functional description
4C4M4EOQ, AS4C4M4E1Q high performance 16-megabit CMOS Quad Dynamic Random Access Memories (DRAM) organized 4,194,304 words bits. devices fabricated using advanced CMOS technology innovative design techniques resulting high speed, extremely power wide operating margins component system levels. Alliance 16Mb DRAM family optimized main memory workstation, router switch applications. These products feature high speed page mode operation where read write operations within single page) executed very high speed toggling column addresses within that row. column addresses alternately latched into input buffers using falling edge inputs respectively. Also, used make column address latch transparent, enabling application column addresses prior assertion. Extended data (EDO) read mode enables operation using devices. Four individual pins allow separate operation which enables device operate parity mode. contrast 'fast page mode' devices, data remains active outputs after de-asserted high, giving system logic more time latch data. control output impedance prevent contention during read-modify-write shared applications. Outputs also high impedance last occurrance going high. Refresh 4096 address combinations must performed every using: RAS-only refresh: asserted while held high. Each 4096 rows must strobed. Outputs remain high impedence. Hidden refresh: held while toggled. Refresh address generated internally. Outputs remain impedence with previous valid data. CAS-before-RAS refresh (CBR): least asserted prior RAS. Refresh address generated internally. Outputs high-impedence don't care). Normal read write cycles refresh being accessed. Self-refresh cycles Refresh 2048 address combinations must performed every using: RAS-only refresh: asserted while held high. Each 2048 rows must strobed. Outputs remain high impedence. Hidden refresh: held while toggled. Refresh address generated internally. Outputs remain impedence with previous valid data. CAS-before-RAS refresh (CBR): least asserted prior RAS. Refresh address generated internally. Outputs high-impedence don't care). Normal read write cycles refresh being accessed. Self-refresh cycles 4C4M4EOQ AS4C4M4E1Q available standard 28-pin plastic 28-pin plastic TSOP packages. 4C4M4EOQ AS4C4M4E1Q operate with single power supply 0.5V. provide compatible inputs outputs.
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Logic block diagram refresh
Refresh controller Column decoder Sense Data buffers
I/O0 I/O3
clock generator
clock generator
clock generator
Address buffers decoder 4,194,304 Array (16,777,216)
Logic block diagram refresh
Refresh controller Column decoder Sense Data buffers
I/O0 I/O3
clock generator
clock generator
clock generator
Address buffers decoder 4,194,304 Array (16,777,216) Substrate bias generator
Recommended operating conditions
Parameter Supply voltage 4C4M4EOQ AS4C4M4E1Q 4C4M4EOQ AS4C4M4E1Q Symbol Input voltage Ambient operating temperature
-0.5
Nominal
Unit
-3.0V pulse widths less than Recommended operating conditions apply throughout this document unlesss otherwise specified.
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Absolute maximum ratings
Parameter Input voltage Input voltage (DQs) Power supply voltage Storage temperature (plastic) Soldering temperature time Power dissipation Short circuit output current Symbol TSTG TSOLDER Iout -1.0 -1.0 -1.0 +7.0 +7.0 +150 Unit
electrical characteristics (AS4C4M4E0/E1)
Parameter Symbol Test conditions +5.5V, Pins under test DOUT disabled, Vout +5.5V RAS, UCAS, LCAS, Address cycling; tRC=min UCAS LCAS cycling, UCAS LCAS VIH, after XCAS low. VIL, UCAS LCAS, address cycling: tHPC UCAS LCAS 0.2V IOUT -5.0 IOUT RAS, UCAS LCAS cycling, UCAS LCAS 0.2V, 0.2V, other inputs 0.2V 0.2V Unit Notes
Input leakage current Output leakage current Operating power supply current standby power supply current ICC1 ICC2
Average power supply current, refresh ICC3 mode page mode average power supply ICC4 current CMOS standby power ICC5 supply current Output voltage
before refresh ICC6 current
Self refresh current
ICC7
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
electrical characteristics (AS4LC4M4E0/E1)
Parameter Input leakage current Symbol Test conditions (max) Pins under test DOUT disabled, Vout (max) RAS, UCAS, LCAS, Address cycling; tRC=min UCAS LCAS VIH, other inputs cycling, UCAS LCAS VIH, after XCAS low. VIL, UCAS LCAS, address cycling: tHPC UCAS LCAS 0.2V, IOUT -2.0 IOUT RAS, UCAS LCAS cycling, UCAS LCAS 0.2V, 0.2V, other inputs 0.2V 0.2V Unit
Notes
Output leakage current Operating power supply current standby power supply current Average power supply current, refresh mode page mode average power supply current CMOS standby power supply current Output voltage ICC1 ICC2 ICC3
ICC4 ICC5
before refresh ICC6 current
Self refresh current
ICC7
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
parameters common waveforms
Symbol Parameter tRAS tCAS tRCD tRAD tRSH tCSH tCRP tASR tRAH tREF tRAL tASC tCAH Random read write cycle time precharge time pulse width pulse width delay time column address delay time hold time hold time precharge time address setup time address hold time Transition time (rise fall) Refresh period precharge time Column address lead time Column address setup time Column address hold time 32/64 32/64 Unit 17/16 Notes
Read cycle
Symbol Parameter tRAC tCAC tRCS tRCH tRRH Access time from Access time from Access time from address Read command setup time Read command hold time Read command hold time Unit Notes 6,13 7,13
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Write cycle
Symbol Parameter tWCS tWCH tRWL tCWL Write command setup time Write command hold time Write command pulse width Write command lead time Write command lead time Data-in setup time Data-in hold time Unit Notes
Read-modify-write cycle
Symbol Parameter tRWC tRWD tCWD tAWD Read-write cycle time delay time delay time Column address delay time Unit Notes
Refresh cycle
Symbol Parameter tCSR tCHR tRPC tCPT setup time (CAS-before-RAS) hold time (CAS-before-RAS) precharge hold time precharge time (CBR counter test) Unit Notes
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Hyper page mode cycle
Symbol tCPWD tCPA tRASP tDOH tREZ tWEZ tOEZ tHPC tHPRWC tRHCP Parameter precharge delay time Access time from precharge pulse width Previous data hold time from Output buffer turn delay from Output buffer turn delay from Output buffer turn delay from Hyper page mode cycle time Hyper page mode cycle hold time from 100K 100K Unit Notes
Output enable
Symbol tCLZ tROH tOEA tOED tOEZ tOEH tOLZ tOFF Parameter output hold time referenced access time data delay Output buffer turnoff delay from command hold time output Output buffer turn-off time Unit 8,10 Notes
Self-refresh cycle
Symbol tRASS tRPS tCHS Parameter
pulse width (CBR self refresh) precharge time (CBR self refresh) hold time (CBR self refresh)
Unit Notes
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Notes
ICC1, ICC3, ICC4, ICC6 dependent frequency. ICC1 ICC4 depend output loading. Specified values obtained with output open. initial pause required after power-up followed cycles before proper device operation achieved. case internal refresh counter, minimum CAS-before-RAS initialization cycles instead cycles required. initialization cycles required after extended periods bias without clocks (greater than ms). Characteristics assume parameters measured with load equivalent loads (min) (max) VCC. (min) (max) reference levels measuring timing input signals. Transition times measured between VIL. Operation within tRCD (max) limit insures that tRAC (max) met. tRCD (max) specified reference point only. tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation within tRAD (max) limit insures that tRAC (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled exclusively tAA. Assumes three state test load Thevenin equivalent). Either tRCH tRRH must satisfied read cycle. tOFF (max) defines time which output achieves open circuit condition; referenced output voltage levels. tOFF referenced from rising edge CAS, whichever occurs last. tWCS, tWCH, tRWD, tCWD tAWD restrictive operating parameters. They included datasheet electrical characteristics only. (min) (min), cycle early write cycle data pins will remain open circuit, high impedance, throughout cycle. tRWD tRWD (min), tCWD tCWD (min) tAWD tAWD (min), cycle read-write cycle data will contain data read from selected cell. neither above conditions satisfied, condition data access time indeterminate. These parameters referenced leading edge early write cycles leading edge read-write cycles. Access time determined longest tCAA tCAC tCPA tASC achieve (min) tCPA (max) values. These parameters sampled 100% tested. These characteristics apply AS4C4M4EOQ devices. These characteristics apply AS4C4M4E1Q devices.
test conditions
Access times measured with output reference levels 2.4V 0.4V, 2.4V 0.8V Input rise fall times:
Dout
*including scope capacitance
+3.3V Dout
*including scope capacitance
Figure Equivalent output load (AS4C4M4E0/AS4C4M4E1)
Figure Equivalent output load (AS4C4M4E0/AS4C4M4E1)
switching waveforms
Rising input Falling input Undefined output/don't care
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Read waveform
tRAS tRCD tRSH
tCSH tCRP tASC tRCS tCAH tCAS
tRAD tASR tRAH Column address tRRH tRCH tRAL
Address
address
tROH tROH
tWEZ
tRAC tOEA tCAC tCLZ tREZ Data tOLZ tOEZ tOFF (see note
Early write waveform
tRAS
tCSH tRSH tCRP tRCD tRAD tASC tASR tRAH tCAH Column address tCWL tRWL tWCS tWCH tCAS tRAL
Address
address
Data
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Write waveform
tRAS
controlled
tCSH tCRP tRCD tRSH tCAS tRAL tRAD tRAH tASC tCAH Column address tRWL tCWL
tASR
Address
address
tOEH
tOED
Data
Read-modify-write waveform
tRWC tRAS tCAS tCRP tRCD tCSH tRSH
tRAD tASR tRAH address
tRAL tASC tCAH Column address tRWD tAWD tRCS tCWD tOEA tOEZ tOED tCWL tRWL
Address
tRAC
tCAC tCLZ Data
tOLZ
Data
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
page mode read waveform
tRASP
tCSH tCRP tRCD tCAS tRHCP tHPC tRSH
tRAD tASR tRAH address tRCS tASC address tCAH address tRCH tOEA tOEA tCPA tOEZ tCPA Data tOLZ Data tCLZ Data tCLZ tOEZ tOFF tRRH tRAL
Address
tRAC tCLZ tCAC
page mode early write waveform
tRASP tRAH tRWL tCSH tCAS tASC tWCS tRAL address address address tCWL tWCH tOEH tCAH tRSH
tCRP tRCD
tASR tRAD address
Address
tHDR Data Data Data tOED
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
page mode read-modify-write waveform
tRASP
tHPRWC tCSH tRCD tCAS tRAD tASR tRAH tASC tCAH tRWD tRCS tCWD tAWD tASC tCWL tCWD tCAH tASC tCRP
tRAL tCAH tCPWD tCWD tAWD tOEZ tCLZ tCAC Data Data Data Data tCPA tCLZ tCAC Data Data tCLZ tCAC tOED tOEA tRWL tCWL
Address
address
tOEA
tRAC
before refresh waveform
tRAS
tRPC tCSR tCHR
OPEN
only refresh waveform
tRAS tRPC
tCRP
tASR tRAH address
Address
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
Hidden refresh waveform (read)
tRAS tCHR tRCD tRSH tCRP tRAS
tCRP
tRAD tRAH tASR tASC tRCS address tRRH tOEA tCAH
Address
tRAC tCAC tCLZ tOEZ Data tOFF
Hidden refresh waveform (write)
tRAS tCHR
tCRP tRCD tRSH
tRAD tRAH tASR tASC address tWCR tWCS tWCH address tRWL tRAL tCAH
Address
tDHR Data
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
before refresh counter test waveform
tRAS tRSH
tCSR tCHR tCPT tCAS
tASC tCAH
tRAL
Address
address tCAC tCLZ tOFF tOEZ Data tRCS tRRH tRCH
Read cycle
tROH tOEA
tRWL tCWL tWCH tWCS
Write cycle
Data
tRCS tCWD tAWD
tRWL tCWL
Read-Write cycle
tOEA tOED
tCLZ tCAC tOEZ Data Data
3/22/01; v.1.0
Alliance Semiconductor
AS4C4M4EOQ AS4C4M4E1Q
CAS-before-RAS self refresh cycle
tRASS tRPS
tRPC tCSR tCHS tRPC
UCAS, LCAS
tCEZ
Capacitance
Parameter Input capacitance capacitance Symbol CIN1 CIN2 Signals RAS, UCAS, LCAS, DQ15
MHz, Room temperature Test conditions Vout Unit
4C4M4EOQ ordering information
Package access time Plastic SOJ, mil, 24/26-pin Plastic TSOP, mil, 24/26-pin 4C4M4EOQ-50JC 4C4M4EOQ-50TC 4C4M4EOQ-60JC 4C4M4EOQ-60TC
AS4C4M4E1Q ordering information
Package access time Plastic SOJ, mil, 24/26-pin Plastic TSOP, mil, 24/26-pin AS4C4M4E1Q-50JC AS4C4M4E1Q-50TC AS4C4M4E1Q-60JC AS4C4M4E1Q-60TC
4C4M4EOQ family part numbering system
DRAM prefix E0=4K refresh E1=2K refresh access time CMOS 3.3V CMOS Package: Commercial temperature mil, 24/26 range, TSOP mil, 24/26
3/22/01; v.1.0
Alliance Semiconductor

CMOS QuadCAS DRAM (EDO) family Features Organization: 4,194,304 w

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