89HPES3T3 Data Sheet Advance Information* Device Overview
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3-Lane 3-Port Express® Switch
89HPES3T3 Data Sheet
Advance Information*
Device Overview
89HPES3T3 member IDT's PRECISEfamily Express switching solutions. PES3T3 3-lane, 3-port peripheral chip that performs Express Base switching. provides connectivity switching functions between Express upstream port four downstream ports supports switching between downstream ports.
Features
High Performance Express Switch Three 2.5Gbps Express lanes Three switch ports Upstream port Downstream ports latency cut-through switch architecture Support payload sizes bytes virtual channel Eight traffic classes Express Base Specification Revision compliant Flexible Architecture with Numerous Configuration Options Automatic lane reversal ports Automatic polarity inversion lanes Ability load device configuration from serial EEPROM Legacy Support compatible INTx emulation locking
Highly Integrated Solution Requires external components Incorporates on-chip internal memory packet buffering queueing Integrates three Gbps embedded SerDes with 8B/10B encoder/decoder separate transceivers needed) Reliability, Availability, Serviceability (RAS) Features Internal end-to-end parity protection TLPs ensures data integrity even systems that implement end-to-end (ECRC) Supports ECRC Advanced Error Reporting Supports Express Native Hot-Plug, Hot-Swap capable Compatible with Hot-Plug expanders used motherboards Power Management Utilizes advanced low-power design techniques achieve typical power consumption Supports Power Management Interface specification (PCIPM 1.2) Unused SerDes disabled. Supports Advanced Configuration Power Interface Specification, Revision (ACPI) supporting active link state Testability Debug Features Built Pseudo-Random Stream (PRBS) generator Numerous SerDes test modes Ability bypass link training force link into mode Provides statistics performance counters
Block Diagram
3-Port Switch Core Express Lanes
Frame Buffer Route Table Port Arbitration Scheduler
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Transaction Layer Data Link Layer
Demux
Logical Layer
Demux
Logical Layer
Demux
Logical Layer
SerDes
SerDes
SerDes
(Port
(Port
Figure Internal Block Diagram
(Port
logo registered trademarks Integrated Device Technology, Inc.
2007 Integrated Device Technology, Inc. *Notice: information this document subject change without notice
September 2007
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89HPES3T3 Data Sheet
Five General Purpose Input/Output Pins Each individually configured input output Each individually configured interrupt input Four pins have selectable alternate functions Packaged 13mm 13mm 144-ball with ball spacing
Product Description Utilizing standard Express interconnect, PES3T3 provides most efficient fan-out solution applications requiring connectivity, latency, simple board layout with minimum number board layers. Each lane provides Gbps bandwidth both directions fully compliant with Express Base specification 1.1. PES3T3 based flexible efficient layered architecture. Express layer consists SerDes, Physical, Data Link Transaction layers compliance with Express Base specification Revision 1.1. PES3T3 operate either store forward cut-through switch designed switch memory transactions. supports eight Traffic Classes (TCs) Virtual Channel (VC) with sophisticated resource management allow efficient switching applications requiring additional narrow port connectivity also some high-end connectivity.
Processor
Processor
North Bridge
Memory Memory Memory Memory
South Bridge
PES3T3
1394
Figure Expansion Application
SMBus Interface PES3T3 contains SMBus master interface. This master interface allows default configuration register values PES3T3 overridden following reset with values programmed external serial EEPROM. master interface also used external Hot-Plug expander. pins make SMBus master interface. These pins consist SMBus clock SMBus data pin. Hot-Plug Interface PES3T3 supports Express Hot-Plug each downstream port. reduce number pins required device, PES3T3 utilizes external expander, such that used motherboards, connected SMBus master interface. Following reset configuration, whenever state Hot-Plug output needs modified, PES3T3 generates SMBus transaction expander with value outputs. Whenever Hot-Plug input changes, expander generates interrupt which received IOEXPINTN input (alternate function GPIO) PES3T3. response expander interrupt, PES3T3 generates SMBus transaction read state Hot-Plug inputs from expander.
September 2007
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89HPES3T3 Data Sheet
General Purpose Input/Output PES3T3 provides General Purpose Input/Output (GPIO) pins that used system designer ports. Each GPIO configured independently input output through software control, each GPIO shared with another on-chip function. These alternate functions enabled software serial configuration EEPROM.
Description
following tables lists functions pins provided PES3T3. Some functions listed multiplexed onto same pin. active polarity signal defined using suffix. Signals ending with defined being active, asserted, when logic zero (low) level. other signals (including clocks, buses, select lines) will interpreted being active, asserted, when logic (high) level.
Signal PE0RP[0] PE0RN[0] PE0TP[0] PE0TN[0] PE2RP[0] PE2RN[0] PE2TP[0] PE2TN[0] PE3RP[0] PE3RN[0] PE3TP[0] PE3TN[0] PEREFCLKP PEREFCLKN
Type
Name/Description Express Port Serial Data Receive. Differential Express receive pair port Express Port Serial Data Transmit. Differential Express transmit pair port
Express Port Serial Data Transmit. Differential Express transmit pair port Express Port Serial Data Receive. Differential Express receive pair port Express Port Serial Data Transmit. Differential Express transmit pair port Express Reference Clock. Differential reference clock pair input. This clock used reference clock on-chip PLLs generate clocks required system logic on-chip SerDes. frequency differential reference clock MHz. Table Express Interface Pins
Signal MSMBCLK MSMBDAT
Type
Name/Description Master SMBus Clock. This bidirectional signal used synchronize transfers master SMBus. Master SMBus Data. This bidirectional signal used data master SMBus. Table SMBus Interface Pins
September 2007
Advance Information
Express Port Serial Data Receive. Differential Express receive pair port
89HPES3T3 Data Sheet
Signal GPIO[0]
Type
Name/Description General Purpose I/O. This configured general purpose pin. Alternate function name: P2RSTN Alternate function type: Output Alternate function: Reset output downstream port General Purpose I/O. This configured general purpose pin. General Purpose I/O. This configured general purpose pin. Alternate function name: IOEXPINTN0 Alternate function type: Input Alternate function: Expander interrupt input General Purpose I/O. This configured general purpose pin. Alternate function name: GPEN Alternate function type: Output Alternate function: General Purpose Event (GPE) output General Purpose I/O. This configured general purpose pin. Alternate function name: P3RSTN Alternate function type: Output Alternate function: Reset output downstream port Table General Purpose Pins
GPIO[1] GPIO[2]
GPIO[7]
GPIO[9]
Signal APWRDISN CCLKDS
Type
Name/Description Auxiliary Power Disable Input. When this active, disables device from using auxiliary power supply. Common Clock Downstream. assertion this indicates that downstream ports using same clock source that provided downstream devices.This used initial value Slot Clock Configuration Link Status Registers downstream ports. value override modifying SCLK downstream port's PCIELSTS register. Common Clock Upstream. assertion this indicates that upstream port using same clock source upstream device. This used initial value Slot Clock Configuration Link Status Register upstream port. value overridden modifying SCLK PA_PCIELSTS register. Fundamental Reset. Assertion this signal resets logic inside PES3T3 initiates Express fundamental reset. Table System Pins (Part
CCLKUS
PERSTN
September 2007
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89HPES3T3 Data Sheet Signal RSTHALT Type Name/Description Reset Halt. When this signal asserted during Express fundamental reset, PES3T3 executes reset procedure remains reset state with Master SMBus active. This allows software read write registers internal device before normal device operation begins. device exits reset state when RSTHALT cleared PA_SWCTL register SMBus master. Switch Mode. These configuration pins determine PES3T3 switch operating mode. Normal switch mode Normal switch mode with Serial EEPROM initialization through Reserved Wake Input/Output. WAKEN signal input output. WAKEN signal input/output selection made through WAKEDIR setting WAKEUPCNTL register. Table System Pins (Part
SWMODE[2:0]
WAKEN
Signal JTAG_TCK
Type
Name/Description JTAG Clock. This input test clock used clock shifting data into boundary scan logic JTAG Controller. JTAG_TCK independent system clock with nominal duty cycle. JTAG Data Input. This serial data input boundary scan logic JTAG Controller. JTAG Data Output. This serial data shifted from boundary scan logic JTAG Controller. When data being shifted out, this signal tri-stated. JTAG Mode. value this signal controls test mode select boundary scan logic JTAG Controller. JTAG Reset. This active signal asynchronously resets boundary scan logic JTAG Controller. external pull-up board recommended meet JTAG specification cases where tester access this signal. However, systems running functional mode, following should occur: actively drive this signal with control logic statically drive this signal with external pull-down board Table Test Pins
JTAG_TDI JTAG_TDO
JTAG_TMS JTAG_TRST_N
Signal VDDCORE VDDI/O VDDPE VDDAPE VTTPE
Type
Name/Description Core VDD. Power supply core logic. VDD. LVTTL buffer power supply. Express Digital Power. Express digital power used digital power SerDes. Express Analog Power. Express analog power used bias generator. Express Termination Power. Ground. Table Power Ground Pins
September 2007
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89HPES3T3 Data Sheet
Characteristics
Note: Some input pads PES3T3 contain internal pull-ups pull-downs. Unused inputs should tied appropriate levels. This especially critical unused control signal inputs which, left floating, could adversely affect operation. Also, input left floating cause slight increase power consumption.
Function Express Interface
Name PE0RN[0] PE0RP[0] PE0TN[0] PE0TP[0] PE2RN[0] PE2RP[0] PE2TN[0] PE2TP[0] PE3RN[0] PE3RP[0] PE3TN[0] PE3TP[0] PEREFCLKN PEREFCLKP
Type
Buffer
Type Serial Link
Internal Resistor
Notes
LVPECL/ LVTTL LVTTL LVTTL
Diff. Clock Input STI1 High Drive Input pull-up pull-down pull-up pull-up pull-down pull-down open-drain
Refer toTable
SMBus General Purpose System Pins
MSMBCLK MSMBDAT GPIO[9,7,2:0] APWRDISN CCLKDS CCLKUS PERSTN RSTHALT SWMODE[2:0] WAKEN
EJTAG JTAG
JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N
LVTTL
pull-up pull-up pull-up pull-up
Schmitt Trigger Input (STI).
Table Characteristics
September 2007
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89HPES3T3 Data Sheet
Logic Diagram PES3T3
Reference Clock
PEREFCLKP PEREFCLKN PE0TP[0] PE0TN[0]
Express Switch SerDes Input Port
Express Switch SerDes Output Port
PE0RP[0] PE0RN[0] PE2TP[0] PE2TN[0]
Express Switch SerDes Input Port
Express Switch SerDes Output Port
PE2RP[0] PE2RN[0] PE3TP[0] PE3TN[0]
Express Switch SerDes Input Port
PE3RP[0] PE3RN[0]
PES3T3
Express Switch SerDes Output Port
GPIO[9,7,2:0]
General Purpose
MSMBDAT
JTAG_TDI JTAG_TDO JTAG_TMS JTAG_TRST_N VDDCORE
JTAG Pins
System Pins
CCLKDS CCLKUS RSTHALT PERSTN SWMODE[2:0]
WAKEN APWRDISN
VDDI/O VDDPE VDDAPE VTTPE
Power/Ground
Figure PES3T3 Logic Diagram
September 2007
Advance Information
Master SMBus Interface
MSMBCLK
JTAG_TCK
89HPES3T3 Data Sheet
System Clock Parameters
Values based systems running recommended supply voltages operating temperatures, shown Tables
Parameter PEREFCLK RefclkFREQ RefclkDC1 Tjitter
ClkIn
Description
Typical
Unit
Input reference clock frequency range Duty cycle input clock Rise/Fall time input clocks Differential input voltage swing3 Input clock jitter (cycle-to-cycle)
0.2*RCUI
RCUI2
Table Input Clock Requirements
must coupled. 0.01 ceramic capacitors. RCUI (Reference Clock Unit Interval) refers reference clock period. coupling required.
Timing Characteristics
Parameter PCIe Transmit TTX-RISE, TTX-FALL TTX-MAX-JITTER TTX-EYE TTX-EYE-MEDIAN-toMAX-JITTER
Description
Typical
1101
Units
Rise Fall time TxP, outputs Unit Interval Transmitter Total Jitter (peak-to-peak) Minimum Width TTX-MAX-JITTER) Maximum time between jitter median maximum deviation from median Transmitter data latency (for n=10) Transmitter data latency (for n=20) Transmitter data skew between lanes Maximum time transition valid electrical idle after sending Electrical Idle ordered Time exit Electrical Idle (L0s) state into Time from asserting Beacon TxEn beacon being transmitted lane Pulse width RxDetectEn input RxDetectEn falling edge RxDetect delay Recover data latency n=10 Recover data latency n=20 Receiver data skew between lanes
399.88 0.75
bits bits bits bits
400.12 0.252 0.15
LTLAT-10 LTLAT-20 TTX-SKEW TTX-IDLE-SET-TOIDLE
1300 10.2
TEIExit TBTEn TRxDetectEn TRxDetect PCIe Receive LRLAT-10 LRLAT-20 TRX-SKEW
Table PCIe Timing Characteristics (Part
September 2007
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89HPES3T3 Data Sheet Parameter TBDDly TRX-IDLE_ENTER TRX-IDLE_EXIT TRX-MAX-JITTER TRX-EYE TRX-EYE-MEDIAN-toMAX JITTER
Description Beacon-Activity channel detection Beacon3 Delay from detection Electrical Idle condition channel assertion TxIdleDetect output Delay from detection transition de-assertion TxIdleDetect output Receiver total jitter tolerance Minimum Receiver Width Maximum time between jitter median deviation from median
Typical
Units
0.65
0.35 0.325
Table PCIe Timing Characteristics (Part
measured between points. Will depend package characteristics. Compliance Pattern. This function beacon frequency.
Measured using Express
Signal GPIO GPIO[9,7,2:0]1
Symbol
Reference Unit Edge
Timing Diagram Reference
Tpw_13b2
None
Figure
Table GPIO Timing Characteristics
GPIO signals must meet setup hold times they synchronous minimum pulse width they asynchronous.
values
this symbol were determined calculation, testing.
EXTCLK Tdo_13a GPIO (synchronous output) Tpw_13b GPIO (asynchronous input) Tdo_13a
Figure GPIO Timing Waveform
September 2007
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89HPES3T3 Data Sheet
Signal JTAG JTAG_TCK
Symbol
Reference Edge
Unit
Timing Diagram Reference
Tper_16a Thigh_16a, Tlow_16a
none
25.0 10.0
50.0 25.0 11.3 11.3
Figure
JTAG_TMS1, JTAG_TDI JTAG_TDO JTAG_TRST_N
Tsu_16b Thld_16b Tdo_16c Tdz_16c2 Tpw_16d2
JTAG_TCK rising JTAG_TCK falling none
25.0
Table JTAG Timing Characteristics
values this symbol were determined calculation, testing.
Tlow_16a Thigh_16a JTAG_TCK Thld_16b Tsu_16b JTAG_TDI Thld_16b Tsu_16b JTAG_TMS Tdo_16c JTAG_TDO Tpw_16d JTAG_TRST_N Figure JTAG Timing Waveform Tdz_16c Tper_16a
September 2007
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JTAG specification, IEEE 1149.1, recommends that JTAG_TMS should held while signal applied JTAG_TRST_N changes from Otherwise, race occur JTAG_TRST_N deasserted (going from high) rising edge JTAG_TCK when JTAG_TMS low, because controller might either Run-Test/Idle state stay Test-Logic-Reset state.
89HPES3T3 Data Sheet
Recommended Operating Supply Voltages
Symbol VDDCORE VDDI/O VDDPE VDDAPE VTTPE Parameter Internal logic supply supply except SerDes LVPECL/CML Express Digital Power Express Analog Power Express Serial Data Transmit Termination Voltage Common ground Minimum 3.135 1.425 Table PES3T3 Operating Voltages Typical Maximum 3.465 1.575 Unit
Power-Up/Power-Down Sequence
When powering each voltage level must ramp stabilize prior applying next voltage sequence ensure internal latch-up issues avoided. There maximum time limitations ramping valid power levels. power-down sequence must reverse order power-up sequence.
Recommended Operating Temperature
Grade Commercial Temperature +70°C Ambient Table PES3T3 Operating Temperatures
September 2007
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This section describes sequence which various voltages must applied part during power-up ensure proper functionality. PES3T3, power-up sequence must follows: VDDI/O 3.3V VDDCore, VDDPE, VDDAPE 1.0V VTTPE 1.5V
89HPES3T3 Data Sheet
Power Consumption
Parameter IDDI/O Typ. Max. Unit Conditions Tambient 25oC Max. values maximum voltages listed Table Typical values typical voltages listed that table.
IDDCore IDDPE, ITTPE Power Dissipation
Normal mode Standby mode1
Normal mode Standby mode
ports state.
September 2007
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Table PES3T3 Power Consumption
89HPES3T3 Data Sheet
Electrical Characteristics
Values based systems running recommended supply voltages, shown Table Note: Table Characteristics, complete listing.
Min1 Typ1 Max1
Type Serial Link
Parameter PCIe Transmit VTX-DIFFp-p VTX-DE-RATIO VTX-DC-CM VTX-CM-ACP VTX-CM-DCactive-idle-delta
Description
Unit
Conditions
Differential peak-to-peak output voltage De-emphasized differential output voltage Common mode voltage peak common mode output voltage delta common mode voltage between idle delta common mode voltage between DElectrical idle diff peak output Voltage change during receiver detection Transmitter Differential Return loss Transmitter Common Mode Return loss Differential impedance Single ended Impedance Height (De-emphasized bits) Height (Transition bits)
-0.1
1200
delta
VTX-Idle-DiffP VTX-RCV-Detect RLTX-DIFF RLTX-CM ZTX-DEFF-DC ZOSE Transmitter Diagram Transmitter Diagram PCIe Receive VRX-DIFFp-p VRX-CM-AC RLRX-DIFF RLRX-CM ZRX-DIFF-DC ZRX-COMM-DC
Differential input voltage (peak-to-peak) Receiver common-mode voltage coupling Receiver Differential Return Loss Receiver Common Mode Return Loss Differential input impedance (DC) Single-ended input impedance
1200
200k 350k
ZRX-COMM-HIGH- Powered down input common mode impedance (DC) Z-DC VRX-IDLE-DETDIFFp-p
Electrical idle detect threshold
PCIe REFCLK Input Capacitance
Table Electrical Characteristics (Part
September 2007
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VTX-CM-DC-line-
89HPES3T3 Data Sheet Type Other I/Os Drive Output High Drive Output Schmitt Trigger Input (STI) Input Capacitance Leakage Inputs I/OLEAK Pull-ups/downs I/OLEAK WITH Pull-ups/downs
Parameter
Description
Min1
Typ1
Max1
Unit
Conditions
-0.3 -0.3
-5.5 12.0 -20.0
VDDI/O VDDI/O
0.4v 1.5V 0.4v 1.5V VDDI/O (max) VDDI/O (max) VDDI/O (max)
Table Electrical Characteristics (Part
Minimum, Typical, Maximum values meet requirements under Specification 1.1.
September 2007
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89HPES3T3 Data Sheet
Package Pinout 144-BGA Signal Pinout PES3T3
following table lists numbers signal names PES3T3 device.
VDDIO APWRDISN VTTPE VTTPE PE0TP00 VDDPE PE0RP00 VDDIO SWMODE_0 SWMODE_1 VDDCORE WAKEN CCLKUS VDDPE VDDPE PE0TN00 VDDPE PE0RN00 CCLKDS SWMODE_2 JTAG_TMS VDDCORE VDDAPE VDDAPE VDDCORE VDDCORE Function Function VDDCORE JTAG_TDO MSMBCLK VDDCORE VDDCORE PERSTN RSTHALT JTAG_TDI MSMBDAT VDDIO VDDCORE VDDCORE VDDCORE GPIO_00 JTAG_TCK VDDIO VDDCORE VDDCORE VDDCORE Function VDDCORE VDDIO VDDIO GPIO_01 JTAG_TRST_N VDDCORE VDDCORE VDDCORE VDDCORE GPIO_02 PEREFCLKP VDDIO VDDAPE VDDCORE VDDCORE GPIO_07 PEREFCLKN VDDCORE VDDCORE VDDIO GPIO_09 VDDCORE VDDIO VDDPE VDDPE VDDCORE VDDIO PE2RN00 PE2TP00 PE3TN00 VDDAPE PE3RN00 VTTPE VDDCORE PE2RP00 PE2TN00 VTTPE VDDCORE Function
Table PES3T3 144-pin Signal Pin-Out (Part
September 2007
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89HPES3T3 Data Sheet Function PE3TP00 Function PE3RP00 VDDAPE Function Function
Table PES3T3 144-pin Signal Pin-Out (Part
Alternate Signal Functions
GPIO GPIO_00 GPIO_02 GPIO_07 GPIO_09 Alternate P2RSTN IOEXPINTN0 GPEN P3RSTN
Table PES3T3 Alternate Signal Functions
Power Pins
VDDCore VDDCore Table PES3T3 Power Pins VDDI/O VDDPE VDDAPE VTTPE
September 2007
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89HPES3T3 Data Sheet
Ground Pins
Table PES3T3 Ground Pins
Signals Listed Alphabetically
Signal Name APWRDISN CCLKDS CCLKUS GPIO_00 GPIO_01 GPIO_02 GPIO_07 GPIO_09 JTAG_TCK JTAG_TDI JTAG_TDO JTAG-TMS JTAG-TRST_N MSMBCLK MSMBDAT Type Location SMBus JTAG General Purpose Input/Output Signal Category System
Table 89PES3T3 Alphabetical Signal List (Part
September 2007
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89HPES3T3 Data Sheet Signal Name Connection PE0RN00 PE0RP00 PE0TN00 PE0TP00 PE2RN00 PE2RP00 PE2TN00 PE2TP00 PE3RN00 PE3RP00 PE3TN00 PE3TP00 PEREFCLKN PEREFCLKP PERSTN RSTHALT SWMODE_0 SWMODE_1 SWMODE_2 WAKEN VDDCORE, VDDAPE, VDDI/O, VDDPE, VTTPE Type Location L11, Express Signal Category
Table listing power pins. System
Table listing ground pins. Table 89PES3T3 Alphabetical Signal List (Part
September 2007
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89HPES3T3 Data Sheet
PES3T3 Pinout View
VDDCore (Power) VDDI/O (Power)
VTTPE (Power) VDDPE (Power) VDDAPE (Power)
(Ground)
Signals Connect
September 2007
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89HPES3T3 Data Sheet
PES3T3 Package Drawing 144-Pin BC144/BCG144
September 2007
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89HPES3T3 Data Sheet
PES3T3 Package Drawing Page
September 2007
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89HPES3T3 Data Sheet
Revision History
August 2007: Initial publication advanced data sheet. September 2007: Added Power-Up/Power Down Sequence.
September 2007
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89HPES3T3 Data Sheet
Ordering Information
Product Family Operating Voltage Device Family NNAN Product Detail Device Revision Legend Alpha Character Numeric Character
Package Temp Range
Blank
Commercial Temperature (0°C +70°C Ambient) BC144 144-ball CABGA BCG144 144-ball CABGA, Green revision
3-lane, 3-port
Express Switch
1.0V 0.1V Core Voltage Serial Switching Product
Valid Combinations
89HPES3T3ZABC 89HPES3T3ZABCG 144-pin BC144 package, Commercial Temperature 144-pin Green BC144 package, Commercial Temperature
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Tech Support: email: ssdhelp@idt.com phone: 408-284-8208
September 2007
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