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Frequency Generator CPU, PCIe PCIe Recommended Application:


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ICS9FG1904B-1
Frequency Generator CPU, PCIe PCIe
Recommended Application:
DB1900GS/GSO with 15:4 output grouping
Functionality Power (PLL Mode) CLK_IN (CPU FSB) FS_A_410 CLK_IN 200<= CLK_IN
Features:
Power default outputs mode DIF_(14:0) "gear-shifted" from input Host Clock DIF_(18:15) "gear-shifted" from input Host Clock Spread spectrum compatible Supports output clock frequencies Selectable SMBus addresses SMBus address determines Bypass mode
DIF_(18:0) CLK_IN CLK_IN
FS_A_410 low-threshold input. Please VIL_FS VIH_FS
specifications Input/Supply/Common Output Parameters Table correct values.
Power Down Functionality
INPUTS CKPWRGD/ CLK_IN/ CLK_IN# Running OUTPUTS State DIF/DIF# Running Hi-Z
Specifications:
output cycle-to-cycle jitter 50ps output-to-output skew 100ps within group
SMB_A2_PLLBYP#
Configuration
CKPWRGD/PD#
OE_17_18#
OE_15_16#
CLK_IN#
DIF_18#
DIF_17#
DIF_16#
DIF_15#
DIF_14#
DIF_
CLK_IN
DIF_18
DIF_17
DIF_15
IREF GNDA VDDA HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 OE14# DIF_13# DIF_13 OE13# DIF_12# DIF_12 OE12# DIF_11# DIF_11 OE11# DIF_10# DIF_10 OE10# DIF_9# DIF_9 OE9#
ICS9FG1904-1
DIF_6 DIF_6# OE7# DIF_7
72-pin
1255B-08/03/07
Other names brands claimed property others.
DIF_14
ICS9FG1904B-1
Description
NAME IREF GNDA VDDA HIGH_BW# FS_A_410 DIF_0 DIF_0# DIF_1 DIF_1# DIF_2 DIF_2# DIF_3 DIF_3# DIF_4 DIF_4# OE_01234# SMBCLK SMBDAT OE5# DIF_5 DIF_5# OE6# DIF_6 DIF_6# OE7# DIF_7 DIF_7# OE8# DIF_8 DIF_8# SMB_A0 SMB_A1 TYPE DESCRIPTION This establishes reference current differential current-mode output pairs. This requires fixed precision resistor tied ground order establish appropriate current. ohms standard value. Ground core. 3.3V power core. 3.3V input selecting Band Width High, 3.3V tolerant threshold input frequency selection. This requires CK410 FSA. Refer input electrical characteristics Vil_FS Vih_FS threshold values. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pairs tri-state outputs, enable outputs Clock SMBUS circuitry, tolerant Data SMBUS circuitry, tolerant Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output SMBus address (LSB) SMBus address
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ICS9FG1904B-1
Description (Continued)
NAME OE9# DIF_9 DIF_9# OE10# DIF_10 DIF_10# OE11# DIF_11 DIF_11# OE12# DIF_12 DIF_12# OE13# DIF_13 DIF_13# OE14# DIF_14 DIF_14# CKPWRGD/PD# DIF_15 DIF_15# OE_15_16# DIF_ DIF_16# DIF_17 DIF_17# DIF_18 DIF_18# OE_17_18# CLK_IN CLK_IN# SMB_A2_PLLBYP# TYPE DESCRIPTION Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Ground pin. Power supply, nominal 3.3V Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output rising edge samples latched inputs release Power Down Mode, puts part into power down mode tristates outputs. 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs 0.7V differential true clock output 0.7V differential complement clock output Power supply, nominal 3.3V Ground pin. 0.7V differential true clock output 0.7V differential complement clock output 0.7V differential true clock output 0.7V differential complement clock output Active input enabling pair tri-state outputs, enable outputs Input reference clock. "Complementary" reference clock input. SMBus address When Low, part operates fanout buffer with bypassed. When High, part operates zero-delay buffer (ZDB) with operating. fanout mode (PLL bypassed), mode (PLL used)
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ICS9FG1904B-1
General Description
ThThe ICS9FG1904-1 follows Intel DB1900GS Differential Buffer Specification, except output groupings gear table. gear table blend gearing. This buffer provides output clocks Host Bus, PCIExpress, Fully Buffered DIMM applications. outputs configured with groups. Both groups, DIF_(14:0) DIF_(18:15) equal have gear ratio input clock. differential clock from CK410B+ main clock generator, such ICS932S421, drives ICS9FG1904-1. ICS9FG1904-1 provide outputs 400MHz.
Block Diagram
OE_17_18# OE_15_16#
SPREAD COMPATIBLE
DIF(18:15)
OE(14:5)#, OE_01234#
CLK_IN CLK_IN#
SPREAD COMPATIBLE GEARING
DIF(14:0)
HIGH_BW# FS_A_410 CKPWRGD/PD# SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK
CONTROL LOGIC
IREF
Power Groups Number 11,27,47,63 10,28,46,64
Description Main PLLs, Analog clocks
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ICS9FG1904B-1
9FG1904B-1 Programmable Gear Ratios
CLK_IN (CPU FSB) 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 160/ 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.667/ 320.00 266.67 333.33 320/ 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared Outputs 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 100.00 133.33 200.00 266.67 320/ 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67/ 200.00 200.00 133.33 160/ 166.67 200.00 133.33 160.00 166.67 320.00 333.33 Gear Ratio 1.333 1.667 2.000 2.667 3.333 4.000 1.250 1.500 1.250 1.500 0.750 0.800 1.200 1.600 2.000 2.400 0.667 0.833 1.333 1.667 2.000 0.500 0.625 0.750 0.400 0.500 0.600 0.333 0.400 0.417 0.800 0.833 (FS_A_410#) Byte Byte Byte Byte Byte Notes
Notes: Targetted input/output frequency pairs This Gear also used 160MHz/320 MHz. Gear Ratio power default FS_A_410 Gear Ratio power default FS_A_410 This Gear also used 400MHz/200MHz This Gear also used 320MHz/200MHz
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ICS9FG1904B-1
9FG1904B-1 Programming
Byte
Byte9,
Byte FS_A_410
CLK_IN (CPU FSB) Outputs 100.00 100.00 133.33 133.33 166.67 166.67 200.00 200.00 266.67 266.67 333.33 333.33 400.00 400.00 Reserved
Notes
Notes:FS_A_410 Powerup Default FS_A_410 Powerup Default FS_A_410 Setting exact frequency after Power required best phase noise performance.
Output Divider Ratios Binary Desired Value Decimal write Value Register 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
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ICS9FG1904B-1
Absolute
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input protection SYMBOL VDD_A VDD_In Tambient Tcase prot CONDITIONS Human Body Model 2000 UNITS 0.5V 0.5V
Notes
Electrical Characteristics Input/Supply/Common Output Parameters
70°C; Supply Voltage +/-5% PARAMETER SYMBOL Input High Voltage Input Voltage Input High Current Input Current Threshold InputHigh Voltage Threshold InputLow Voltage Operating Current Powerdown Current Input Frequency Inductance Input Capacitance Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage Low-level Output Voltage Current sinking SCLK/SDATA Clock/Data Rise Time SCLK/SDATA Clock/Data Fall Time VIH_FS VIL_FS IDD3.3OP IDD3.3PD Lpin COUT TSTAB CONDITIONS +/-5% 0.35 (Max 0.15) (Min 0.15) (Min 0.15) (Max 0.15) 1000 UNITS Notes
+/-5% Inputs with pull-up resistors +/-5%, Applies FS_A_410
+/-5%, Applies FS_A_410 outputs driven differential pairs tri-stated Logic Inputs Output capacitance From Power-Up deassertion clock Triangular Modulation output enable after de-assertion fall time rise time Maximum input voltage PULLUP
VMAX IPULLUP TRI2C TFI2C
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ICS9FG1904B-1
Electrical Characteristics 0.7V Current Mode Differential Pair
70°C; +/-5%; =2pF, RS=33.2, RP=49.9, PARAMETER Current Source Output Impedance Voltage High Voltage Voltage Voltage Crossing Voltage (abs) Crossing Voltage (var) Long Accuracy SYMBOL
CONDITIONS Statistical measurement single ended signal using oscilloscope math function. Measurement single ended signal using absolute value.
3000 -150 -300
UNITS NOTES 1,2,7 1,4,5
VHigh VLow Vovs Vuds Vcross(abs) d-Vcross
1150
Variation crossing over edges Tperiod min-max values 400MHz nominal 400MHz spread 333.33MHz nominal 333.33MHz spread 266.66MHz nominal 266.66MHz spread 200MHz nominal 200MHz spread 166.66MHz nominal 166.66MHz spread 133.33MHz nominal 133.33MHz spread 100.00MHz nominal 100.00MHz spread 400MHz nominal/spread 333.33MHz nominal/spread 266.66MHz nominal/spread 200MHz nominal/spread 166.66MHz nominal/spread 133.33MHz nominal/spread 100.00MHz nominal/spread 0.175V, 0.525V 0.525V 0.175V 2.4993 2.4993 2.9991 2.9991 3.7489 3.7489 4.9985 4.9985 5.9982 5.9982 7.4978 7.4978 9.9970 9.9970 2.4143 2.9141 3.6639 4.8735 5.8732 7.3728 9.8720
Average period
Tperiod
2.5008 2.5133 3.0009 3.016 3.7511 3.77 5.0015 5.0266 6.0018 6.0320 7.5023 7.5400 10.0030 10.0533
Absolute period
Tabsmin
Rise Time Fall Time Rise Time Variation Fall Time Variation Duty Cycle Jitter, Cycle cycle Notes:
d-tr d-tf tJCYC-CYC tJBYP
Measurement from differential wavefrom mode, from differential wavefrom Bypass mode additive jitter
1.Guaranteed design characterization, 100% tested production. Long Term Accuracy Clock Period specifications guaranteed assuming that input frequency meets CK410 accuracy requirements 3.IREF VDD/(3xRR). (1%), IREF 2.32mA. IREF 0.7V ZO=50. Measured into fixed load cap. Input output skew measured first output edge following corresponding input. Measured from differential cross-point differential cross-point Bypass Mode Input-to-Output specs refer timing between input edge specific output edge created This device does introduce errors input clock.
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ICS9FG1904B-1
Electrical Characteristics Skew Differential Jitter Parameters 70°C; Supply Voltage +/-5% Group Parameter Description Input-to-Output Skew mode (1:1 only), tSPO_PLL CLK_IN, DIF[x:0] nominal value 25°C, 3.3V Input-to-Output Skew Bypass mode (1:1 only), tPD_BYP CLK_IN, DIF[x:0] nominal value 25°C, 3.3V Input-to-Output Skew Variation mode CLK_IN, [x:0] tSPO_PLL (over specified voltage temperature operating ranges) CLK_IN, [x:0] DIF[14:0] DIF[18:15] DIF[18:0] DIF[18:0] DIF[18:0] NOTES: tPD_BYP tSKEW_G15
tSKEW_G4
-500
Units Notes |350| |500|
1,2,4,5,8 1,2,3,5 1,2,4,5,6, 1,2,3,4,5, 6,10 1,2,3 1,4,7 1,4,9
Input-to-Output Skew Variation Bypass mode (over specified voltage temperature operating ranges) Output-to-Output Skew Group (Common Bypass mode) Output-to-Output Skew Group (Common Bypass mode) Output-to-Output Skew across outputs (Common Bypass mode outputs same gear) Differential Phase Jitter (RMS Value) Differential Spread Spectrum Tracking Error (peak peak)
tSKEW_A19 tJPH tSSTERROR
Measured into fixed load cap. Input output skew measured first output edge following corresponding input. Measured from differential cross-point differential cross-point Bypass Mode Input-to-Output specs refer timing between input edge specific output edge created This parameter deterministic given device Measured with scope averaging find mean value. Long-term variation from nominal input-to-output skew over temperature voltage single device. This parameter measured outputs separate ICS9FG1900 devices driven single CK410B. ICS9FG1900's must high bandwidth. Differential phase jitter accumulation phase jitter shared outputs (eg. including affects spread spectrum). Target ranges consideration agents with 1-22Mhz 11-33Mhz. period input clock Differential spread spectrum tracking error difference spread spectrum tracking between ICS9FG1900 devices This parameter measured outputs separate ICS9FG1900 devices driven single CK410B Spread Spectrum mode. ICS9FG1900's must high bandwidth. spread spectrum characteristics are: maximum 0.5%, 30-33KHz modulation frequency, linear profile. This parameter absolute value. double-sided figure.
Electrical Characteristics Phase Jitter Parameters 70°C; Supply Voltage +/-5%, when driven 932S421B equivalent PARAMETER Symbol Conditions jphPCIe1 PCIe PCIe jphPCIe2Lo 10kHz 1.5MHz Jitter, Phase jphPCIe2Hi jphFBD1_3.2G jphFBD1_4.0G
Units (p-p) (RMS) (RMS) (RMS) (RMS)
Notes
PCIe 1.5MHz Nyquist (50MHz) FBD1 3.2/4G 11MHz 33MHz FBD1 4.8G 11MHz 33MHz
Notes: Guaranteed design characterization, 100% tested production. http://www.pcisig.com complete specs
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ICS9FG1904B-1
Programming 9FG1904B-1
9FG1904B-1 uses advanced power saving features detect when only geared outputs only outputs needed. then shuts down unused PLL. power outputs coming from Gear shut down. This power saving feature requires little care when configuring gear outputs device.
Configuring Gear Outputs 9FG1904B-1
Selecting Pre-configured Gear Ratios Byte contains both bits that enable gear ratio outputs (Bits bits that select actual gear ratio (bits (4:0)). tempting enable gearing outputs select gear ratio same time. However, this result inability obtain proper output frequency. power saving feature, necessary perform this operation steps: First, enable outputs gear ratio PLL, which actually powers gear ratio (Set Byte bits Then select desired gear ratio separate write byte (Set Byte bits (4:0) actual order operations unimportant, steps could reversed desired. Programming Gear Ratios that Pre-Configured Most applications using 9FG1904B-1 obtain desired output frequencies from selections built into gear table. There gear tables defined these devices. There original gear indicated DBxxxxGS yellow cover designation newer optimized gear indicated DBxxxxGSO yellow cover designation. 9FG1904B-1 contains gear that combination gear sets. differences between gear sets highlighted Figure versus versus 9FG1904B-1 Gear Ratios. gear table that pre-configured 9FG1904B-1, virtually other input/output combination obtained programming. Note that care must used jitter/bandwidth characteristics compromised. values provided later this document have been verified preserve performance device. Refer section Using Programming Obtain Other Gear Ratios additional details.
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ICS9FG1904B-1
Gear Ratios
CLK_IN (CPU FSB) 100.00 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 160/ 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.667/ 266.67 333.33 320/ 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared Outputs 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 400.00 133.33 200.00 266.67 320/ 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67/ 200.00 133.33 160/ 166.67 200.00 133.33 160.00 166.67 320.00 333.33 Gear Ratio 1.33 1.67 2.00 2.67 3.33 4.00 1.25 1.50 1.25 1.50 3.00 0.80 1.20 1.60 2.00 2.40 0.67 0.83 1.33 1.67 2.00 0.50 0.63 0.75 0.40 0.50 0.60 0.33 0.40 0.42 0.80 0.83
Gear Ratios
CLK_IN (CPU FSB) 100.00 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 133.33 133.33 166.67 166.67 166.67 166.67 166.67 200.00 200.00 200.00 200.00 200.00 266.67 266.67 266.67 333.33 333.33 333.33 400.00 400.00 400.00 400.00 400.00 Geared Outputs 133.33 166.67 200.00 266.67 333.33 100.00 166.67 200.00 266.67 333.33 400.00 133.33 200.00 266.67 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67 200.00 133.33 166.67 200.00 133.33 166.67 200.00 266.67 333.33
9FG1904-1 Gear Ratios
CLK_IN Gear (CPU FSB) Ratio 1.33 100.00 1.67 100.00 2.00 100.00 2.67 100.00 3.33 100.00 0.75 100.00 1.25 133.33 1.50 133.33 2.00 133.33 2.50 133.33 3.00 133.33 0.80 166.67 1.20 166.67 1.60 166.67 160/ 2.00 166.67 2.40 166.67 0.67 200.00 0.83 200.00 1.33 200.00 1.67 200.00 2.00 200.00 0.50 266.67 266.667/ 0.63 320.00 0.75 266.67 0.40 333.33 320/ 0.50 333.33 0.60 333.33 0.33 400.00 0.42 400.00 0.50 400.00 0.67 400.00 0.83 400.00 Geared Outputs 133.33 166.67 200.00 266.67 333.33 400.00 166.67 200.00 266.67 333.33 100.00 133.33 200.00 266.67 320/ 333.33 400.00 133.33 166.67 266.67 333.33 400.00 133.33 166.67/ 200.00 200.00 133.33 160/ 166.67 200.00 133.33 160.00 166.67 320.00 333.33 Gear Ratio 1.33 1.67 2.00 2.67 3.33 4.00 1.25 1.50 1.25 1.50 0.75 0.80 1.20 1.60 2.00 2.40 0.67 0.83 1.33 1.67 2.00 0.50 0.63 0.75 0.40 0.50 0.60 0.33 0.40 0.42 0.80 0.83
Figure versus versus 9FG1904B-1 Gear Ratios
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ICS9FG1904B-1
Using Programming Obtain Other Gear Ratios
programming used obtain input output frequency combinations that preconfigured 9FG1904B-1. Refer Figure Block Diagram. internal architecture 9FG1904B-1 standard pseudo-ZDB architecture with internal feedback. This means that divider, Output divider Feedback divider play role determining output frequency. output frequency given equation: Output Frequency (Input Frequency Output Div)/M
Input Clock
OUTPUT
BUFFERS
Output Clocks
Figure Block Diagram
DBxxxxGSO input/output combinations that 9FG1904B-1 gear table shown Table DBxxxxGSO Gears Present 9FG1904B-1. This table also gives values needed program gearing provide desired input/output combination.
Byte Byte (Hex) Byte Byte (Hex) Byte Byte Output (Hex)
Bytes Gear Bytes Decimal Post Divider FS_A_410# Input Frequency (Fref) Output Frequency Decimal Value Decimal Value
Line
133.33 400.00 3.000 400.00 200.00 0.500 400.00 266.67 0.667 Table DBxxxxGSO Gears Present 9FG1904B-1
Gear
Note before programming accomplished, Byte (the M/N_Enable bit) must `1'. values provided table above have been verified meet specified performance 9FG1901B-1. Performance guaranteed other values that have been pre-approved IDT. Contact your local representative other values mentioned here.
Setting Operating Point
After configuring Gearing outputs, also necessary operating point writing input frequency value Byte bits (2:0). input frequency usually HCLK frequency.
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ICS9FG1904B-1
9FG1904-1 SMBus Address Mapping when using CK410/CK410B, 9FG1200, 9DB401/801 SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS) SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
YPAS 2_PLLB
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
Adr: 954101 932S401 (CK410/410B)
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
B_A2_PLLBYP#
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
Adr: 9DB401/801 (DB400/800)
SMB_A(2:0) Adr: 9FG1904-1 (DB1900GS)
SMB_A(2:0) Adr: 9FG1200-1 (DB1200GS)
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ICS9FG1904B-1
General SMBus serial interface information ICS9FG1904B-1 Write:
Controller (host) sends start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) sends data byte count clock will acknowledge Controller (host) starts sending Byte through Byte (see Note clock will acknowledge each byte time Controller (host) sends Stop
Read:
Controller (host) will send start bit. Controller (host) sends write address clock will acknowledge Controller (host) sends begining byte location clock will acknowledge Controller (host) will send separate start bit. Controller (host) sends read address clock will acknowledge clock will send data byte count clock sends Byte clock sends Byte through byte X(H) written byte Controller (host) will need acknowledge each byte Controllor (host) will send acknowledge Controller (host) will send stop
Index Block Write Operation
Controller (Host) starT Slave Address *D0(H) WRite Beginning Byte Data Byte Count Beginning Byte Byte (Slave/Receiver)
Index Block Read Operation
Controller (Host) starT Slave Address *D0(H) WRite Beginning Byte Repeat starT Slave Address *D1(H) ReaD Data Byte Count Beginning Byte (Slave/Receiver)
Byte stoP
SMBus Address this device programmable. preceding page details SMBus address.
Byte Byte acknowledge stoP
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ICS9FG1904B-1
SMBusTable: Gear Ratio Select Register Name Control Function Byte Group gear ratio enable DIF(14:0) Group gear ratio enable DIF(18:15) Reserved Gear Ratio (Inverse FS_A_410 input!) Gear Ratio Gear Ratio Gear Ratio Gear Ratio
Type Gear Ratio Gear Ratio
Latch
ICS9FG1904-1 Programmable Gear Ratios Table
SMBusTable: Output Control Register Name Byte DIF_7 DIF_6 DIF_5 DIF_4 DIF_3 DIF_2 DIF_1 DIF_0
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable Enable Enable Enable
SMBusTable: Output Control Register Byte Name Control Function Type High note PLL_BW# adjust Bypass note BYPASS# test mode DIF_13 Output Control Hi-Z Enable DIF_12 Output Control Hi-Z Enable DIF_11 Output Control Hi-Z Enable DIF_10 Output Control Hi-Z Enable DIF_9 Output Control Hi-Z Enable DIF_8 Output Control Hi-Z Enable Note: wired HIGH_BW# input, selects High Note: wired SMB_A2_PLLBYP# input, selects Fanout Bypass mode SMBusTable: Output Enable Readback Register Byte Name Control Function Readback OE9# Input Readback OE8# Input Readback OE7# Input Readback OE6# Input Readback OE5# Input Readback OE_01234# Input Readback HIGH_BW# Readback SMB_A2_PLLBYP#
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Type
Readback Readback Readback Readback Readback Readback Readback Readback
ICS9FG1904B-1
SMBusTable: Output Enable Readback Register Byte Name Control Function Readback OE17_18# Input Readback OE15_16# Input Reserved Readback OE14# Input Readback OE13# Input Readback OE12# Input Readback OE11# Input Readback OE10# Input SMBusTable: Vendor Revision Register Name Control Function Byte RID3 RID2 REVISION RID1 RID0 VID3 VID2 VENDOR VID1 VID0 SMBusTable: DEVICE Byte
Type
Readback Readback Readback Readback Readback Readback Readback
Type
Name
Control Function Device (MSB) Device Device Device Device Device Device Device
Type
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SMBusTable: Byte Count Register Byte Name
Type Writing this register configures many bytes will read back.
Control Function
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ICS9FG1904B-1
SMBusTable: Control Readback Register Name Control Function Byte Readback FS_A_410 RESERVED RESERVED DIF_18 Output Control DIF_17 Output Control DIF_16 Output Control DIF_15 Output Control DIF_14 Output Control SMBusTable: Operating Point Register Name Control Function Byte RESERVED RESERVED RESERVED RESERVED RESERVED Frequency Select Frequency Select FS_A_410
Type
Readback
Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Enable Enable Enable Enable Enable
Type
ICS9FG1904 Programming Table
Latch
SMBus Table: Programming Watchdog Safe Register Name Control Function Byte Gear M/N_EN Programming Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SMBus Table: Gear Frequency Control Register Byte Name Control Function RESERVED RESERVED Gear Div5 Gear Div4 Gear Div3 Divider Gear Div2 Gear Div1 Gear Div0
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Type
Disable
Enable
Type
Programming Section Data Sheet
ICS9FG1904B-1
SMBus Table: Gear Frequency Control Register Byte Name Control Function Gear Div7 Gear Div6 Gear Div5 Gear Div4 Divider Gear Div3 Gear Div2 Gear Div1 Gear Div0 SMBusTable: Reserved Register Byte Name Gear Gear Gear Gear SMBusTable: Reserved Register Byte Name SMBusTable: Reserved Register Byte Name
Type Programming Section Data Sheet
Control Function RESERVED RESERVED RESERVED RESERVED Gear Output Divider Gear Output Divider Gear Output Divider Gear Output Divider
Type
Output Divider Ratios Table
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
1255B-08/03/07
ICS9FG1904B-1
SMBusTable: Reserved Register Byte Name SMBus Table: Byte SMBus Table: Byte
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
Frequency Control Register Name Control Function Type RESERVED RESERVED Div5 Div4 Divider Programming Programming Section Div3 Data Sheet bits Div2 Div1 Div0 Frequency Control Register Name Control Function Type Div7 Div6 Div5 Divider Programming Programming Section Div4 Data Sheet b(7:0) Div3 Div2 Div1 Div0
SMBusTable: Reserved Register Name Byte
Control Function RESERVED RESERVED RESERVED RESERVED Output Divider Output Divider Output Divider Output Divider
Type
Output Divider Ratios Table
1255B-08/03/07
ICS9FG1904B-1
SMBusTable: Reserved Register Byte Name
Control Function RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED
Type
SMBusTable: Test Byte Register Byte Test Test Function ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST ONLY TEST Note: write Erratic device operation will result!
Type
Test Result Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1255B-08/03/07
ICS9FG1904B-1
Seating Plane Index Area View Anvil Singulation Sawn Singulation
(Ref.
(Ref.
Even (Typ.) Even
(Ref.
(Ref.)
Thermal Base
Chamfer OPTIONAL
0.08
THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL MIN. MAX. 0.05 0.25 Reference 0.18 0.50 BASIC
DIMENSIONS SYMBOL BASIC MIN. MAX. MIN. MAX. MIN. MAX. TOLERANCE 10.00 10.00 5.75 6.15 5.75 6.15 0.30/ 0.50
Ordering Information
9FG1904BK-1LFT
Example:
XXXX
Designation tape reel packaging Lead Free, RoHS Compliant (Optional) Variation Number Package Type Revision Designator (will correlate with datasheet revision) Device Type (consists digit numbers)
1255B-08/03/07
ICS9FG1904B-1
Revision History
Rev. Issue Date Description Added Output Divider Table. Added Phase Jitter Table electrical characteristics. 05/04/07 Added programming information. Changed part number reference 9FG1904B-1. 08/03/07 Release Final. Page Various
1255B-08/03/07

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