4Bank 16bits Synchronous DRAM Revision 0.01 Initial Draft Editori

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4Bank 16bits Synchronous DRAM Revision 0.01 Initial Draft Editori

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64Mb Synchronous DRAM based 4Bank
4Bank 16bits Synchronous DRAM
Revision 0.01 Initial Draft Editorial chage 0.80Typ 0.45 +/-0.05 (page12, Ball Dimension) Before dimension History Draft Date Dec. 2004 Remark Preliminary
0.80 Typ.
0.65 Typ.
After dimension
June. 2005
Preliminary
0.450 0.05
0.65 Typ.
Added Speed Product(100MHz CL2) (see Page
This document general product description subject change without notice. Hynix does assume responsibility circuits described. patent licenses implied. Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
DESCRIPTION
Hynix HY5V66E(L)F6(P) series 67,108,864bit CMOS Synchronous DRAM, ideally suited memory applications which require wide data high bandwidth. HY5V66E(L)F6(P) organized 4banks 1,048,576 HY5V66E(L)F6(P) offering fully synchronous operation referenced positive edge clock. inputs outputs synchronized with rising edge clock input. data paths internally pipelined achieve very high bandwidth. input output voltage levels compatible with LVTTL. Programmable options include length pipeline (Read latency number consecutive read write cycles initiated single control command (Burst length 1,2,4,8 full page), burst count sequence(sequential interleave). burst read write cycles progress terminated burst terminate command interrupted replaced burst read write command cycle. (This pipelined design restricted '2N' rule)
FEATURES
Voltage: VDD, VDDQ 3.3V supply voltage device pins compatible with LVTTL interface Ball FBGA (Lead Lead Free Package) inputs outputs referenced positive edge system clock Data mask function UDQM, LDQM Internal four banks operation Burst Read Single Write operation Programmable Latency; Clocks Auto refresh self refresh 4096 Refresh cycles 64ms Programmable Burst Length Burst Type full page Sequential Burst Interleave Burst
ORDERING INFORMATION
Part HY5V66E(L)F6(P)-5 HY5V66E(L)F6(P)-6 HY5V66E(L)F6(P)-7 HY5V66E(L)F6(P)-H HY5V66E(L)F6(P)-P
Note: HY5V66EF6 Series: Normal power, Leaded. HY5V66ELF6 Series: power, Leaded. HY5V66EF6P Series: Normal power, Lead Free. HY5V66ELF6P Series: power, Lead Free.
Clock Frequency 200MHz 166MHz 143MHz 133MHz 100MHz
Organization
Interface
Package
4Banks 1Mbits
LVTTL
Ball FBGA
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
BALL CONFIGURATION
/CAS
/RAS
LDQM
VSSQ
VDDQ
VSSQ
VDDQ
Bottom View
UDQM
VDDQ
VSSQ
DQ11
VDDQ
VSSQ
DQ15
DQ10
DQ12
DQ13
DQ14
BALL DESCRIPTION
SYMBOL BA0, RAS, CAS, UDQM, LDQM DQ15 VDD/VSS VDDQ/VSSQ
Rev. June. 2005
TYPE INPUT INPUT INPUT INPUT INPUT INPUT INPUT SUPPLY SUPPLY
DESCRIPTION Clock: system clock input. other inputs registered SDRAM rising edge Clock Enable: Controls internal clock signal when deactivated, SDRAM will states among (deep) power down, suspend self refresh Chip Select: Enables disables inputs except CLK, CKE, UDQM LDQM Bank Address: Selects bank activated during activity Selects bank read/written during activity Address: RA11, Column Address: Auto-precharge flag: Command Inputs: RAS, define operation Refer function truth table details Data Mask: Controls output buffers read mode masks input data write mode Data Input Output: Multiplexed data input output Power supply internal circuits Power supply output buffers connection These pads should left unconnected
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
FUNCTIONAL BLOCK DIAGRAM
1Mbit 4banks Synchronous DRAM
Self refresh logic timer
Internal Counter
State Machine Active
1Mx16 BANK
Decoder
1Mx16 BANK 1Mx16 BANK 1Mx16 BANK
Buffer Logic Sense Gate
X-Decoder X-Decoder X-Decoder X-Decoder
Refresh
Memory Cell Array
Column Active
U/LDQM
Column Decoder
DQ15
Y-Decoder
Bank Select
Column Counter
Address Buffers
Address Register
Burst Counter
Mode Register
Latency
Data Control
Pipe Line Control
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
BASIC FUNCTIONAL DESCRIPTION
Mode Register
Code Latency Burst Length
Code
Write Mode Burst Read Burst Write Burst Read Single Write
Burst Type
Burst Type Sequential Interleave
Latency
Latency Reserved Reserved Reserved Reserved Reserved
Burst Length
Burst Length Reserved Reserved Reserved Full Page A3=1 Reserved Reserved Reserved Reserved
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
ABSOLUTE MAXIMUM RATING
Parameter Ambient Temperature Storage Temperature Voltage relative Voltage supply relative Short Circuit Output Current Power Dissipation Soldering Temperature Time Symbol TSTG VIN, VOUT VDD, VDDQ TSOLDER Rating -1.0 -1.0 Unit
OPERATING CONDITION (TA= 70oC)
Parameter Power Supply Voltage Input High Voltage Input Voltage Symbol VDD, VDDQ -0.3 VDDQ+0.3 Unit Note
Note: voltages referenced (max) acceptable 5.6V pulse width with <=3ns duration. (min) acceptable -2.0V pulse width with <=3ns duration.
OPERATING TEST CONDITION (TA= VDD=3.3±0.3V, VSS=0V)
Parameter Input High Level Voltage Input Timing Measurement Reference Level Voltage Input Rise Fall Time Output Timing Measurement Reference Level Voltage Output Load Capacitance Access Time Measurement
Note
Vtt=1.4V
Symbol Vtrip Voutref
Value
Unit
Note
Vtt=1.4V
RT=500
RT=50
Output
Output
30pF
30pF
Output Load Circuit
Output Load Circuit
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
CAPACITANCE (TA= f=1MHz, VDD=3.3V)
Parameter Input capacitance A11, BA0, BA1, CKE, RAS, CAS, LDQM, UDQM DQ15 Symbol CI/O Unit
Data input output capacitance
CHARACTERRISTICS (TA= 70oC)
Parameter Input Leakage Current Output Leakage Current Output High Voltage Output Voltage
Note: 3.3V, other balls tested under DOUT disabled, VOUT=0
Symbol
Unit
Note
-2mA +2mA
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
CHARACTERISTICS (TA= 70oC)
Parameter Symbol Test Condition Burst length=1, bank active tRC(min), IOL=0mA VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. VIL(max), 15ns VIL(max), VIH(min), VIH(min), 15ns Input signals changed time during 2clks. other pins VDD-0.2V 0.2V VIH(min), Input signals stable. tCK(min), IOL=0mA banks active tRC(min), banks active
Normal
Speed
Unit Note
Operating Current
IDD1
Precharge Standby Current IDD2P Power Down Mode IDD2PS
Precharge Standby Current Power Down Mode
IDD2N
IDD2NS Active Standby Current Power Down Mode IDD3P IDD3PS
Active Standby Current Power Down Mode
IDD3N
IDD3NS Burst Mode Operating CurIDD4 rent Auto Refresh Current Self Refresh Current IDD5 IDD6
0.2V
power
Note IDD1 IDD4 depend output loading cycle rates. Specified values measured with output open Min. tRRC (Refresh cycle time) shown CHARACTERISTICS HY5V66EF6(P) Series Normal Power HY5V66ELF6(P) Series Power
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Latency=3 Latency=2 Symbol tCK3 tCK2 tCHW tCLW tAC3 tAC2 tCKS tCKH Unit Note
1000 1000 1000 1000 1000
System Clock Cycle Time
Clock High Pulse Width Clock Pulse Width Access Time From Clock Latency=3 Latency=2
Data-out Hold Time Data-Input Setup Time Data-Input Hold Time Address Setup Time Address Hold Time Setup Time Hold Time Command Setup Time Command Hold Time
Data Output Low-Z tOLZ Time Data Output High-Z Time Latency=3 Latency=2 tOHZ3 tOHZ2
Note Assume (input rise fall time) 1ns. 1ns, then [(tR+tF)/2-1]ns should added parameter. Access time measured with input signals 1V/ns edge rate, from 0.8V 0.2V. 1ns, then (tR/2-0.5)ns should added parameter.
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
CHARACTERISTICS operating conditions unless otherwise noted)
Parameter Cycle Time Cycle Time Operation Auto Refresh Symbol tRRC tRCD tRAS tRRD tCCD tWTL tDPL tDAL tDQZ tDQM tMRD tPROZ3 tPROZ2 tDPE tSRE tREF Unit Note
100K 100K tDPL
Delay Active Time Precharge Time Bank Active Delay Delay Write Command Data-In Delay Data-in Precharge Command Data-In Active Command Data-Out Hi-Z Data-In Mask Command Precharge Data Output High-Z Latency=3 Latency=2
38.7 100K
Power Down Exit Time Self Refresh Exit Time Refresh Time
Note
command given tRRC after self refresh exit.
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
COMMAND TRUTH TABLE
Command Mode Register Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge Banks Precharge selected Bank Burst Stop Auto Refresh Burst-Read-Single-WRITE Entry Self Refresh1 Exit CKEn-1 CKEn ball High (Other balls code)
Mode
ADDR
A10/AP code
Note
Entry Precharge power down Exit
Clock Suspend
Entry Exit
Rev. June. 2005
Synchronous DRAM Memory 64Mbit (4Mx16bit) HY5V66E(L)F6(P) Series
11Preliminary
PACKAGE INFORMATION Ball FBGA 10.1mm 6.4mm
10.10 +/-0.10 0.500 0.10
Unit [mm]
1.1MAX
9.10
0.65 Typ.
6.40 0.10
Bottom View
1.80 0.10
3.90 1.30 Typ.
0.450 0.05
0.65 Typ. 0.280 0.05
Rev. June. 2005

4Bank 16bits Synchronous DRAM Revision 0.01 Initial Draft Editori

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