4.75to26.5Voperation LowVIN-to-VOUT voltage drop current sense feedbac
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A6850 Dual Channel Switch Interface
4.75to26.5Voperation LowVIN-to-VOUT voltage drop current sense feedback Survive40Vloaddump Outputcurrentlimiting two-wire sensors
Description
Allegro® A6850 designed interface between microprocessor pair 2-wire Hall effect sensors. A6850 uses protected high-side resistance DMOS MOSFETs switch supply voltage Hall effect devices. Each switch controlled independently individual ENABLE pins both switches protected with current-limiting circuitry. output switches rated operate 26.5 will source least channel before current limiting. Typical two-wire Hall sensor applications require user measure supply current determine whether Hall sensor switched (magnetic field present) switched magnetic field present). This usually accomplished using external series shunt resistor protection circuits microprocessor. many systems, sensed voltage used input microprocessor analog-to-digital (A-to-D) input. This provides system with indication status two-wire switch well provides capability diagnostic information there open shorted sensor.
Package: SOIC (suffix
Approximate Scale Continued next page.
Functional Block Diagram
ENABLE1
Control Block
ENABLE2
SENSE1
IOUTPUT1
Fault Detection
OUTPUT1
SENSE2
IOUTPUT2
Fault Detection
OUTPUT2
GROUND
6850-DS
A6850
Description (continued) A6850 eliminates need external series shunt resistor Hall sensor applications incorporating integrated current mirror which reports Hall sensor supply current 1/10 value SENSE1 SENSE2 output pin. current Sleep mode
Dual Channel Switch Interface
available (<15 driving both ENABLE pins low. Also, A6850 used interface mechanical switches. A6850 supplied 8-pin (lead) free SOIC package, with 100% matte leadframe plating.
Selection Guide
A6850KLTR-T A6850KL-T
Part Number
Packing
13-in. reel, 3000 pieces/reel Tube, pieces/tube
Absolute Maximum Ratings
Characteristic Supply Voltage Output Voltage SENSEx Voltage Range ENABLEx Voltage Range Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Rating Human Body Model Rating Charged Device Model Symbol VOUTPUTx VSENSEx VENABLEx TJ(max) Tstg AEC-Q100-00; OUTPUT1 OUTPUT AEC-Q100-00; other pins AEC-Q100-011; pins Range Notes Rating -0.3 -0.3 -0.3 1050 Units
Pin-out Diagram
Terminal List Table
Name
ENABLE1
Number
Description
Digital input pulled ground Sensed current output Digital input pulled ground Sensed current output Chip power supply voltage Switchable voltage supply sensor Ground reference Switchable voltage supply sensor
ENABLE1
Control Switch
OUTPUT1
SENSE1 ENABLE SENSE OUTPUT GROUND OUTPUT1
SENSE1
GROUND
ENABLE2
Switch
OUTPUT2
SENSE2
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
ELECTRICAL CHARACTERISTICS +150°C (unless noted otherwise) Characteristics Symbol Test Conditions Supply Input Voltage Range Operating mode, IOUTPUTx Sleep mode: Supply Input Quiescent Current IINQ ENABLE1 ENABLE VOUTPUT1 VOUTPUT Power-Up Time1 OUTPUTx Source Resistance RDS(on) IOUTPUTx OUTPUTx Leakage Current IOUTPUTQ VOUTPUTx disabled ISENSEx (IOUTPUTx ISENSE(ofs) ISENSE(ofs), IOUTPUT SENSEx Output Current Offset ISENSEQ VSENSEx disabled SENSEx Voltage3 VSENSEx VENABLEH ENABLEx Input Voltage Range VENABLEL ENABLEx Input Hysteresis VENABLEhys least output enabled ENABLEx ENABLEx Current IENABLE ENABLEx OUTPUT Current Limit IOUTPUReverse bias blocking: 4.75 OUTPUT Reverse Bias Current IOUTPUT(rvrs) VOUTPUT Overvoltage Protection Threshold VOVP Rising Overvoltage Protection Hysteresis VOVPhys Thermal Shutdown Threshold TTSD Temperature Increasing Thermal Shutdown Hysteresis TTSDhys
1Delay
Min. 4.75 -100
Typ. 35.0
Max. 45.0 33.0
Units
from Sleep mode outputs enabled. input output current specifications, negative current defined coming (sourced from) specified device pin. 3User ensure that SENSEx remains within specified range. VSENSEx exceeds maximum value, device self-protected internal clamp, parameters perform specified.
THERMAL CHARACTERISTICS require derating maximum conditions, application information Characteristic Package Thermal Resistance Symbol Test Conditions* 4-layer based JEDEC standard 1-layer with copper limited solder pads Value Units
*Additional thermal data available Allegro site.
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Functional Description
Thermal Shutdown (TSD)
A6850 protects itself from excessive heat damage disabling both outputs when junction temperature, rises above threshold (TTSD). outputs will remain until junction temperature falls below TTSD level minus hysteresis, TTSDhys. estimated calculating power dissipation (PD) A6850. calculate IINQ VOUTPUT1 IOUTPUT1 VOUTPUT2 IOUTPUT2 VSENSE1 ISENSE1 VSENSE2 ISENSE2 IINQ (VIN VOUTPUT1 IOUTPUT1 (VIN VOUTPUT2 IOUTPUT2 (VIN VSENSE1 ISENSE1 (VIN VSENSE2 ISENSE2 temperature rise A6850 calculated multiplying thermal resistance from junction ambient, formula temperature rise, 8-pin SOIC (Allegro package) (More thermal data available Allegro MicroSystems site.) total junction temperature calculated where ambient temperature. Example: Calculating power dissipation temperature rise, given: 25°C, IINQ IOUTPUT1 IOUTPUT2 VDropx VOUTPUTx 0.7V, ISENSEx IOUTPUTx RSENSE1 RSENSE2 =2k. Then: Substitutinginequation4: 25°C+7.3°C 32.3°C
Substituting equation
Output Current Limit
A6850 limits output current maximum current IOUTPUTM. output current will remain current limit until output load reduced A6850 goes into thermal shutdown. high output current limit allows bypass capacitor, CBYP Hall sensor charge quickly. This allows high slew rate Hall sensor, ensuring that sensor Power-On State will correct. Applications Information section schematic diagrams power calculations.
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Output Faults
A6850 withstands short-to-ground short-to-battery OUTPUTx pins. case short-to-ground, current held current limit (IOUTPUTM). A6850 monitors VOUTPUTx disables outputs. Because protection circuitry requires finite amount time disable outputs, bypass capacitor necessary VIN. Although OUTPUTx sinks current into A6850 this state, current bled ground does chargeup capacitors tied VIN.
limits sense (see Electrical Characteristics table).
Sleep Mode
Low-leakage sleep modes required automotive applications minimize battery drain when vehicle parked. A6850 enters sleep mode when both ENABLE pins low. sleep mode, internal regulators other internal circuitry disabled. When enabling output, part must first come sleep mode. Consequently, wake-up time amounts propagation delay before outputs turn Also, ENABLE pins switch with hysteresis until regulators stabilize. After internal regulators stabilize, internal circuitry enabled outputs turn shown figure long ENABLE held high, A6850 operates with hysteresis.
Overvoltage Protection
A6850 built-in overvoltage protection against load dump supply bus. case load dump, when connected battery supply rises above overvoltage threshold, VOVP A6850 will shut outputs.
SENSE Outputs
A6850 divides OUTPUTx current mirrors onto corresponding SENSEx pin. Putting sense resistors, RSENSE from these pins ground will create voltage that read (analog-to-digital converter). value RSENSE should chosen that voltage drop across sense resistor (VRSENSE) does exceed maximum voltage rating ADC. further protection ADC, external clamping circuit, such Zener diode, used clamp transient current spikes that occur output that would translated onto SENSE pins. sense current tenth output current, plus offset current. This offset current consistent across whole range output current. sense current calculated following formula: ISENSEx (IOUTPUTx ISENSE(ofs) sense resistor must also chosen meet voltage
ENABLE VENABLEL
RegOk VREG
OUTPUT
Figure Activation Timing Diagram. Exiting Sleep mode ENABLE signal output waveform.
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Applications Information
Two-Wire Sensor Interfacing
When voltage applied two-wire Hall effect sensors, current flows within narrow ranges. current level within these ranges indicates fault condition.
Signal Fault Table Condition OUTPUT Short-to-Ground Logic High from Hall Sensor Short-to-Battery Logic from Hall Sensor* Thermal Shutdown OUTPUT Open
*This
following table describes some possible output conditions that monitored through SENSE pins. Figure typical application using A6850 with dual Hall effect sensors.
Output Current (mA)
Sense Current (mA) 0.69
Sense Voltage, Rsense= 3.75 6.75 1.04
current range includes A114x A118x sensors.
Digital Output Digital Output Controller
VBAT
ENABLE1 ENABLE2
OUTPUT1
Wiring Harness
A6850 SENSE1 SENSE2
CBYP 0.01 A114x A118x
OUTPUT2 GROUND
RSENSE1
RSENSE2
CBYP 0.01 A114x A118x
Figure Typical Application with 2-Wire Hall Effect Sensors
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Mechanical Switch Interfacing
A6850 used interface between mechanical switches, switch-to-ground configuration, voltage microprocessor. series resistor must placed circuit limit current when mechanical switch closed, order prevent excessive power dissipation A6850. example, calculate power dissipation A6850 with assume that current limit each outputs maximum value, IOUTPU(max) 45mA.
series resistor included circuit reduces power dissipation A6850. voltage drop across resistor would VRSERIES VDrop1 =12V-0.7V 11.3 current then limited IOUTPUT1 VRSERIES RSERIES =11.3V/1k
11.3 When mechanical switch closed without series resistor, A6850 will current limit. full Power dissipation A6850 from this switch much lower: dissipation mechanical switch closed would VDrop1 IOUTPUT1 VDrop1 IOUTPUT1 =7.91mW. =540mW.
Digital Output Digital Output Controller Input1 Input2
VBAT
ENABLE1 ENABLE2
OUTPUT1
Wiring Harness RSERIES
A6850 SENSE1 SENSE2 RSERIES
OUTPUT2 GROUND
RSENSE1
RSENSE2
Figure Typical Application with Mechanical Switches
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Ganging SENSE1 SENSE2
certain applications both outputs read with single channel. OUTPUTx loads enabled alternatively activating ENABLEx. fact, both ENABLE1
ENABLE2 activated simultaneously, with SENSE1 SENSE2 currents added together. valid measurements load resistor need only selected that VSENSEx remain within specification.
Vbat Digital Output Digital Output
0.47µF Enable Enable Output
Controller
Sense Sense
A6850
Output
VENABLE1 VENABLE2 IOUTPUT1 ILOAD1 ILOAD1
IOUTPUT2 VADC R*ILOAD1/10
ILOAD2 R*ILOAD2/10
ILOAD2
R*(ILOAD1/10 ILOAD2/10)
LOAD2
LOAD1
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
A6850
Dual Channel Switch Interface
Package, 8-Pin SOIC
6.20 .244 5.80 .228 0.25 [.010] 5.00 .197 4.80 .189 0.25 .010 0.17 .007 Preliminary dimensions, reference only Dimensions millimeters U.S. Customary dimensions (in.) brackets, reference only (reference JEDEC MS-012 Dimensions exclusive mold flash, gate burrs, dambar protrusions Exact case lead configuration supplier discretion within limits shown Terminal mark area
Reference layout (reference SOIC127P600-8M);
4.00 .157 3.80 .150 1.27 .050 0.40 .016
adjust necessary meet application process requirements 0.25 .010 0.10 [.004] 0.51 .020 0.31 .012 0.25 [.010] 1.27 .050 SEATING PLANE GAUGE PLANE
SEATING PLANE 1.75 .069 1.35 .053 0.25 .010 0.10 .004
2.50 .098
4.90 .193
0.65 .026
1.27 .050
products described here manufactured under more U.S. patents U.S. patents pending. Allegro MicroSystems, Inc. reserves right make, from time time, such departures from detail specifications required permit improvements performance, reliability, manufacturability products. Before placing order, user cautioned verify that information being relied upon current. information included herein believed accurate reliable. However, Allegro MicroSystems, Inc. assumes responsibility use; infringement patents other rights third parties which result from use. Copyright©2006 AllegroMicroSystems, Inc. latest version this document, visit website: www.allegromicro.com
Allegro MicroSystems, Inc. Northeast Cutoff, 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com
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