AKD4115-A AK4115 Evaluation Board Rev.3 GENERAL DESCRIPTION

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AKD4115-A AK4115 Evaluation Board Rev.3 GENERAL DESCRIPTION

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[AKD4115-A]
AKD4115-A
AK4115 Evaluation Board Rev.3
GENERAL DESCRIPTION AKD4115 evaluation board AK4115, 192kHz digital audio transceiver. This board optical, cannon connector (XLR), connectors interface with other digital audio equipment. Ordering guide
AKD4115-A -Evaluation board AK4115 cable connecting printer port (parallel port) IBM-AT compatible control software packed with this document. Please note that control software does operate Windows
FUNCTION Digital interface -S/PDIF channel input (optical, XLR) channel output (optical, XLR) Serial audio data input (for data input. 10-pin port) output (for data output. 10-pin port) -B,C,U,V input/output port (10-pin port) -Serial control data input/output port (10-pin port)
3.3V Control
AK4115
B,C,U,V
Serial Data DIT)
Serial Data (From
Figure AKD4115-A Block Diagram *Circuit diagram layout attached this manual.
<KM076403>
2006/08
[AKD4115-A]
Evaluation Board Manual
Operating sequence power supply lines. (Red) [GND] (Black) Each supply line should distributed from power supply unit. evaluation mode jumper pins. (Refer following item.) Connect cables. (Refer following item.) Power AK4115 should reset once bringing (SW2) upon power-up.
Evaluation modes Evaluation
MCLK BICK LRCK SDTI
S/PDIF
Optical, connector
AK4115 (DIR)
PORT2 (10pin Header)
MCLK BICK LRCK SDTI
AKD4115-A
generates MCLK, BICK, LRCK SDATA from received data through optical connector(PORT1: TORX176), connector cannon connector(XLR). AKD4115 connected with AKM's evaluation board 10-pin cable. Set-up Bi-phase Input RXP0/RXN0 RX1-7 should select same time. a-1. RXP0/RXN0 Connector Optical (PORT1) (J1) (J2)
JP2(RXP0) JP3(RXN0) Table Set-up RXP0/RXN0
a-2. RX1, inputted from (J2) connector only. Only RX1, used parallel mode. jumper which selects channel should Short. Input Short Short Short Table Set-up RX1, JP10
<KM076403>
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[AKD4115-A]
a-3. Set-up AK4115 input path Parallel Mode will need SW1_1 SW1_5. Serial Mode will need IPS2-0 bits. IPS1 IPS0 (SW1_5) (SW1_1) INPUT Data IPS2 IPS1 IPS0 parallel mode, IPS2 fixed "0") Table Recovery Data Select Set-up clock input output signal level outputted/inputted from PORT2 3.3V.
MCLK SDTO LRCK BICK PORT2
Default
Figure PORT2 layout b-1. MCKO1/MCKO2 output MCKO1 MCKO2 selected JP12. output frequency MCKO1/MCKO2 selected OCKS 1-0. Output JP12 signal Default MCKO1 MCKO1 MCKO2 MCKO2 Table MCKO1/MCKO2 set-up
OCKS1 (SW3_2) OCKS1
OCKS0 (SW3_3) OCKS0
(X'tal)
MCKO1
MCKO2
(max) Default
256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table Master Clock Frequency Select
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[AKD4115-A]
b-2. Set-up BICK LRCK input output Please select (DIR_I/O) according setup audio format AK4115 (Refer Table Audio format SW3_7 (DIR_I/O) Slave mode Master mode Table DIR_I/O set-up Set-up Audio format sets parallel mode. Please DIF2-0 AES3 serial mode. Mode AES3 DIF2 DIF1 (SW1_3) DIF1 DIF0 (SW1_2) DIF0 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, 16bit, Right justified 18bit, Right justified 20bit, Right justified 24bit, Right justified 24bit, Left justified 24bit, 24bit, Left justified 24bit, LRCK DAUX SDTO 64fs 64fs 64fs 64fs 64fs 64fs 64-128f 64-128f 64fs Default BICK
Default
24bit, Left AES3 Mode justified Table Audio format
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[AKD4115-A]
Set-up operation mode selected CM0. parallel mode, selected SW3_4, SW3_1 JP18. serial mode, selected PSEL CM1-0 bits. PSEL (SW3_4) PSEL (SW3_1) (JP18) SDTO source DAUX DAUX DAUX DAUX DAUX DAUX Default
(UNLOCK)
X'tal ON(Note) ON(Note)
Clock source PLL(RX) X'tal PLL(RX) X'tal X'tal PLL(ELRCK) X'tal PLL(ELRCK)
X'tal DAUX Oscillation (Power-up), OFF: STOP (Power-Down) Note: When X'tal used clock comparison detection (XTL0, "1,1"), X'tal OFF. Table Clock Operation Mode Select
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[AKD4115-A]
Evaluation Synchronous mode
MCLK BICK LRCK DAUX
PORT2 (10pin Header) PORT5 (10pin Header)
MCLK BICK LRCK DAUX
AK4115 (DIT)
Optical, connector
S/PDIF
AKD4115-A
Asynchronous mode
EMCK EBICK ELRCK DAUX
PORT2 (10pin Header)
EMCK EBICK ELRCK DAUX
AK4115 (DIT)
Optical, connector
S/PDIF
AKD4115-A
MCLK, BICK, LRCK DAUX input 10pin header (PORT5: DIT). AKD4115-A connected with AKM's evaluation board 10-pin cable. Set-up Bi-phase output signal TXP0/TXN0 should select optical connector connector same time. a-1. data outputted from TXP1/TXN1 selected OPS12-10 bit. Connector JP19 (TXP1) JP14 (TXN1) Optical (PORT4) (J3) (J4) Table Set-up TXP1/TXN1 a-2. TX0, only loop back mode corresponds. This mode fixed parallel mode. serial mode, selected OPS02-00 bits. Connector Optical (PORT4) (J4) JP13 (TX0) JP19 (TXP1) Open Open Table Set-up JP14 (TXN1)
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[AKD4115-A]
Set-up clock input output b-1. case synchronous mode (ASYNC bit="0" Parallel mode) used signals MCKO1, MCKO2, LRCK, BICK, ELRCK DAUX. signal level outputted inputted from PORT2 PORT5 3.3V. Clock PORT MCLK PORT2 BICK PORT2 LRCK PORT2 DAUX PORT5 ELRCK PORT5(LRCK) Table Clock input output b-1-1. MCKO1/MCKO2 output MCKO1 MCKO2 selected JP12. output frequency MCKO1/MCKO2 sets OCKS 1-0. Output JP12 JP15 JP11 signal MCKO1 MCKO1 MCKO MCKO1 MCKO2 MCKO2 MCKO MCKO2 Table Selection MCKO1/MCKO2 OCKS1 (SW3_2) OCKS1 OCKS0 (SW3_3) OCKS0
Default
(X'tal)
MCKO1
MCKO2
(max) Default
256fs 256fs 256fs 256fs 256fs 128fs 512fs 512fs 256fs 128fs 128fs 64fs Table Master Clock Frequency Select
b-1-2. Set-up BICK LRCK input output Please select (DIR_I/O) according setup audio format AK4115 (Refer Table Audio format SW3_7 (DIR_I/O) Slave mode Master mode Table Set-up DIR_I/O b-1-3. ELRCK reference clock PLL, when using ELRCK clock, inputs from PORT5 (LRCK). JP16 When inputting coupling When inputting CMOS level Table Set-up ELRCK input JP17
Default
Default
<KM076403>
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[AKD4115-A]
b-2. case asynchronous mode (ASYNC bit= This mode supported serial mode.) used signals EMCK, X'tal, EBICK, ELRCK, DAUX. These signal levels outputted inputted from PORT5 3.3V. Clock PORT MCLK PORT5 BICK PORT5 LRCK PORT5 DAUX PORT5 ELRCK PORT5 Table Clock input output b-2-1. Set-up Master clock When EMCK used MSEL Output signal JP15 EMCK EMCK Table Selection EMCK When X'tal used master clock Output signal MCKO1 MCKO2 JP12 JP15 JP11 MCKO1 MCKO MCKO1 MCKO2 MCKO MCKO2 Table Selection MCKO1/MCKO2
b-2-2. Setup BICK LRCK input output Please (DIT_I/O) according setup audio format AK4115 (Refer Table 20). JP16 fixed "DC" side. Audio format SW3_8 (DIT_I/O) Slave mode Master mode Table DIT_I/O set-up Set-up audio data format c-1. case synchronous mode. Please refer Table c-2. case asynchronous mode Mode EDIF1 ELRCK EBICK 24bit, Left justified 64fs 24bit, 64fs 24bit, Left justified 64-128fs 24bit, 64-128fs Table Audio data format asynchronous mode EDIF0 DAUX
Default
Default
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[AKD4115-A]
Set-up PSEL, d-1. case synchronous mode. Please refer Table d-2. case asynchronous mode
(UNLOCK)
X'tal
Clock source (RX) X'tal (RX) X'tal X'tal
Clock Note Note Note Note Note
SDTO
Clock source X'tal EMCK (Note X'tal EMCK X'tal EMCK X'tal EMCK X'tal EMCK
Clock Note Note Note Note Note Default
ON(Note
Oscillation (Power-up), OFF: STOP (Power-Down) Note When X'tal used clock comparison sampling frequency detection (i.e. XTL1, 1"), X'tal OFF. Note MCKO1/2, BICK, LRCK Note EMCK X'tal, EBICK, ELRCK, DAUX Note When X'tal OFF, clock source supports EMCK only. Table Clock Operation Mode Select
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[AKD4115-A]
Inputs output
B(block start), C(channel status), U(user data) V(validity) inputted 10pin header (PORT3: BCUV). When BCU_IO "1", they input signals. when BCU_IO "0", they output signals. parallel mode, they fixed output signals. arrangement PORT3 become like Figure
VOUT PORT3 BCUV
Figure PORT3 layout
Serial control
AK4115 controlled printer port (parallel port) IBM-AT compatible Connect included 10pin cable PORT6 (uP-I/F) AKD4115-A. Take care direction connector. There mark pin#1. layout PORT6 Figure shows.
Mode wire Serial
SW1_5
JP18
CDTO/CM0="H" (Short) (Short) CM0="L" (Short) (Note)
Note: mode, chip address fixed "01". Table Set-up Parallel mode Serial mode
PORT6
Figure PORT6 layout evaluation board also includes control software software operation procedure included evaluation board manual.
<KM076403>
CDTO
CCLK
CDTI
2006/08
[AKD4115-A]
Toggle switch set-up Reset switch AK4115. during normal operation. Bring once after power supplied.
indication INT0 INT1
Bright when INT0 goes "H". Bright when INT1 goes "H".
switch (SW1) set-up: -off- means Switch Name Function IPS0 Set-up IPS0 pin. parallel mode) DIF0 Set-up DIF0 pin. parallel mode) DIF1 Set-up DIF1 pin. parallel mode) XSEL Set-up XSEL pin. parallel mode) "L": X'tal "H": X'tal Set-up IPS1 pin. parallel mode) IPS1/IIC Set-up pin. serial mode) "L": wire Serial, "H": P/SN TEST Set-up P/SN pin. "L": Serial mode, "H": parallel mode Set-up TEST pin. (always "OFF") Set-up ACKS pin. parallel mode) ACKS "L": Manual Setting, "H": Auto Setting Table switch (SW3) set-up: -off- means Switch Name Function Set-up pin. parallel mode) OCKS1 Set-up OCKS1 pin. parallel mode) OCKS0 Set-up OCKS0 pin. parallel mode) Set-up PSEL pin. parallel mode) PSEL "L": S/PDIF Input, "H": ELRCK Input Clock XTL0 Set-up XTL0 pin. XTL1 Set-up XTL1 pin. Set-up transmission direction 74AC245 DIR_I/O "L": When inputting from PORT2, "H": When outputting from PORT2 Set-up transmission direction 74AC245 DIT_I/O "L": When inputting from PORT5, "H": When outputting from PORT5. Table Set-up XSEL, XTL1 XTL0 SW1_4 XSEL Status X'tal X'tal Power-Up Power-Down Power-Down Power-Up Table Setting X'tal oscillator X'tal Frequency X'tal 11.2896MHz 12.288MHz 24.576MHz (Use channel status) Table Reference X'tal frequency X'tal 12.288MHz 11.2896MHz 22.5792MHz
Default
Default
SW3_6 XTL1
SW3_5 XTL0
Default
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[AKD4115-A]
Jumper Jumper Name D3V/VD
RXP0
4,5,6 7,8,9,10
RXN0 RX1-3 RX4-7 MCLK MCLK
11,12
TXN1
MCLK
16,17
ELRCK
SDA/CDTO
TXP1
Function Set-up Power supply source 74AC245. (default) Set-up RXP0 input circuit. Optical (default) Set-up RXP0 input circuit. Optical (default) Set-up RX1-3 input circuit. RX4-7 set-up depending serial/parallel mode RX4-7 Serial mode (default) DIF2-0,IPS0 Parallel mode MCKO set-up PORT5(DIT) PORT2(DIR) MCKO1 MCKO1 AK4115 (default) MCKO2 MCKO2 AK4115 Set-up output circuit. Optical (default) Set-up TXN1 output circuit. (default) MCLK input output selection PORT5(DIT). MCKO MCKO (default) EMCK EMCK Set-up ELRCK input signal. (default) Set-up SDA/CDTO pin. wire Serial CDTO/CM0="H" (default) Set-up TXP1 input circuit. Optical (default)
<KM076403>
2006/08
[AKD4115-A]
Control Software Manual Set-up evaluation board control software
AKD4115-A according previous term. Connect IBM-AT compatible with AKD4115-A 10-line type flat cable (packed with AKD4115-A). Take care direction 10pin header. (Please install driver CD-ROM when this control software used Windows 2000/XP. Please refer "Installation Manual Control Software Driver device control software". case Windows95/98/ME, this installation needed. This control software does operate Windows NT.) Insert CD-ROM labeled "AKD4115-A Evaluation Kit" into CD-ROM drive. Access CD-ROM drive double-click icon "akd4115-a.exe" control program. Then please evaluate according follows.
Operation flow
Keep following flow. control program according explanation above. Click "Port Reset" button. Click "Write default" button
Explanation each buttons
[Port Reset] [Write default] [All Write] [Function1] [Function2] [Function3] [Function4] [Function5]: [SAVE] [OPEN] [Write] interface board (AKDUSBIF-A) Initialize register AK4115. Write registers that currently displayed. Dialog write data keyboard operation. Dialog write data keyboard operation. sequence register setting executed. sequence that created [Function3] assigned buttons executed. register setting that created [SAVE] function main window assigned buttons executed. Save current register setting. Write saved values register. Dialog write data mouse operation.
Indication data
Input data indicated register map. letter indicates blue indicates "0".
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[AKD4115-A]
Explanation each dialog [Write Dialog]: Dialog write data mouse operation
There dialogs corresponding each register. Click [Write] button corresponding each register dialog. check check box, data becomes "1". not, "0". want write input data AK4115, click [OK] button. not, click [Cancel] button.
[Function1 Dialog]: Dialog write data keyboard operation
Address Box: Data Box: Input registers address figures hexadecimal. Input registers data figures hexadecimal.
want write input data AK4115, click [OK] button. not, click [Cancel] button.
[Function2 Dialog] Dialog evaluate volume
Address Box: Input registers address figures hexadecimal. Start Data Box: Input starts data figures hexadecimal. Data Box: Input data figures hexadecimal. Interval Box: Data written AK4115 this interval. Step Box: Data changes this step. Mode Select Box: check this check box, data reaches data, returns start data. [Example] Start Data Data Data flow: check this check box, data reaches data, does return start data. [Example] Start Data Data Data flow: want write input data AK4115, click [OK] button. not, click [Cancel] button.
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[AKD4115-A]
[SAVE] [OPEN]
4-1. [SAVE] current register setting values displayed main window saved file. extension file name "akr". <Operation flow> Click [SAVE] Button. file name click [SAVE] Button. extension file name "akr". 4-2. [OPEN] register setting values saved [SAVE] written AK4115. file type same [SAVE]. <Operation flow> Click [OPEN] Button. Select file (*.akr) Click [OPEN] Button.
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[AKD4115-A]
[Function3 Dialog]
sequence register setting executed. Click [F3] Button. control sequence. address, Data Interval time. "-1" address step where sequence should paused. Click [START] button. Then this sequence executed. sequence paused step Interval="-1". Click [START] button, sequence restarts from paused step. This sequence saved opened [SAVE] [OPEN] button Function3 window. extension file name "aks".
Figure Window [F3]
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[AKD4115-A]
[Function4 Dialog]
sequence file (*.aks) saved [Function3] listed files, assigned buttons then executed. When [F4] button clicked, window shown Figure opens.
Figure [F4] window
<KM076403>
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[AKD4115-A]
6-1. [OPEN] buttons left side [START] buttons Click [OPEN] button select sequence file (*.aks) saved [Function3]. sequence file name displayed shown Figure case that selected sequence file name "DAC_Stereo_ON.aks")
Figure [F4] window(2) Click [START] button, then sequence executed.
6-2. [SAVE] [OPEN] buttons right side [SAVE] name assign sequence file displayed [Function4] window saved file. extension file "*.ak4". [OPEN] name assign sequence file(*.ak4) saved [SAVE] loaded.
6-3. Note This function doesn't support pause function sequence function. files used [SAVE] [OPEN] function right side need same folder. When sequence changed [Function3], sequence file (*.aks) should loaded again order reflect change.
<KM076403>
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[AKD4115-A]
[Function5 Dialog]
register setting file(*.akr) saved [SAVE] function main window listed files, assigned buttons then executed. When [F5] button clicked, window shown Figure opens.
Figure [F5] window 7-1. [OPEN] buttons left side [WRITE] button Click [OPEN] button select register setting file (*.akr). register setting file name displayed shown Figure case that selected file name "DAC_Output.akr") Click [WRITE] button, then register setting executed.
<KM076403>
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[AKD4115-A]
Figure [F5] windows(2) 7-2. [SAVE] [OPEN] buttons right side [SAVE] name assign register setting file displayed [Function5] window saved file. file name "*.ak5". [OPEN] file extension assignment register setting file(*.ak5) saved [SAVE] loaded.
7-3. Note files used [SAVE] [OPEN] function right side need same folder. When register setting changed [SAVE] Button main window, register setting file (*.akr) should loaded again order reflect change.
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[AKD4115-A]
Revision History
Date (YY/MM/DD) 04/12/08 06/02/15 06/06/15 Manual Board Revision Revision KM076400 KM076401 KM076402 Reason First edition Modification Contents
06/08/10
KM076403
Circuit diagram changed (page 1/3). changed from 10k. explanation "Instruction use" added. Change control software Control software updated: Control software manual changed: P13-14 P14-21 Error Correct SW_6 SW_5 CDTO/CM0="H" CDTO/CM0="H" (Short) CM0="L" (Short) CM0="L" (Short) Change device Revision AK4115: Rev. Rev. Delete explanation "Instruction use" deleted. Change control software Control software updated:
IMPORTANT NOTICE These products their specifications subject change without notice. Before considering application, consult Asahi Kasei Microsystems Co., Ltd. (AKM) sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing them, require export license other official approval under regulations country export pertaining customs tariffs, currency exchange, strategic materials. products neither intended authorized critical components safety, life support, other hazard related device system, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, other fields, which failure function perform reasonably expected result loss life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise places product with third party notify that party advance above content conditions, buyer distributor agrees assume responsibility liability hold harmless from claims arising from said product absence such notification.
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AVDD
AVDD
RXP0
RXN0
ACKS
P/SN
IPS0/RX4
AVDD
0.1u 0.1u 0.1u
4.7u
AVSS
AVSS
ACKS
IPS0/RX4
VCOM
RXN0
AVDD
AVDD
AVDD
AVSS
RXP0
P/SN
DIF0/RX5
100p
0.01u
DIF0/RX5
FILT
XTL1
TEST
TEST
XTL1
DIF1/RX6
DIF1/RX6
XTL0
XTL0
PSEL
PSEL
XSEL/RX7
XSEL/RX7
IPS1/IIC
IPS1/IIC
DVDD 0.1u
DVDD
BVSS
DVSS
OCKS0/CSN/CAD0 Title Size Date: Document Number 0.1u
DVDD
DAUX
DAUX
DVDD
MCKO1
DVSS
AK4115
OCKS0/CSN/CAD0
MCKO1
OCKS1/CCLK/SCL
OCKS1/CCLK/SCL
MCKO2
MCKO2
CM1/CDTI/SDA
CM1/CDTI/SDA
0.1u
OVDD
CM0/CDTO/CAD1
CM0/CDTO/CAD1
BICK
OVSS
INT1
INT1
BICK
INT0
INT0
SDTO
SDTO
ELRCK
ELRCK
LRCK
LRCK EBICK OVDD
EMCK
EMCK
VOUT
OVSS
TVDD
XTO1
XTO2
TVSS
TXN1
TXP1
XTI1
XTI2
0.1u
12.288MHz
11.2896MHz
0.1u
VOUT
TVDD
TXP1
TXN1
OVDD
EBICK
AKD4115
Sockt
Thursday, August 2006 Sheet
PORT1
D3V/VD
TORX176
0.1u
0.1u
0.1u0.1u0.1u
0.1u 0.1u
AVDD P/SN/ANS ACKS
AVDD P/SN/ANS ACKS RXN0 RXP0
DA02-F
LP2950A
0.1u
TVDD/VDD
AVDD
0.1u
short
XLIN
0.1u
short
TA48M033F DVDD
0.1u
IPS0
AVDD
AVDD
short
OVDD
IPS0 DIF0 DIF1 DIF2/XSEL IPS1/IIC P/SN/ANS TEST ACKS
short
AVDD IPS0/RX4
short
AVDD
DIF0 IPS1/IIC P/SN/ANS TEST ACKS DIF0/RX5 DIF1 JP10 DIF2/XSEL TEST DIF1/RX6 DIF2/XSEL/RX7 DVDD DAUX
TEST
EMCK1 DAUX1
1S1588
DVDD
74HC14
74HC14
DAUX2
EMCK2 DAUX2
0.1u
JP11
MCKO1 MCKO2
MCKO1 MCKO MCKO2 OVDD
74LVC157
DIT_MCLK DIR_MCLK
D3V/VD PORT2 JP12 MCKO1 MCKO2
OVDD
100k
100k
D3V/VD
MCLK BICK LRCK SDTO
BICK SDTO LRCK
74AC245
DIR_I/O
Title Size Date: Document Number
AKD4115-A
MAIN1
Thursday, August 2006 Sheet
PORT3 T45_BK JP19 T45_BK TXP1
VOUT
VOUT TVDD
BCUV
JP13
TVDD/VDD
PORT4
TOTX176
DA02-F
TXP1
0.1u
DA02-F
XLOUT
TXN1
PORT5
DAUX1 JP16
ELRCK
100k
100k
100k
D3V/VD
MCLK BICK LRCK DAUX
74HC14
INT0
74HC14
INT1
74HC14
P/SN/ANS
SCL/CCLK SDA/CDTI SDA(ACK)/CDTO
PORT6
uP-I/F
74HC14 CM1/FS1 OCKS1/FS2 OCKS0/FS0 PSEL XTL0/CKS1 XTL1/TRANS DIR_I/O DIT_I/O JP18
D3V/VD
DIR_I/O DIT_I/O
MCKO EMCK
JP14 JP15
TXN1
MCLK
D3V/VD MCKO EMCK1
100k
OVDD OVDD
EBICK
DIT_I/O
74AC245
JP17
0.1u
ELRCK
EMCK2
EMCK ELRCK INT0 INT1 CM0/CDTO/CAD1
CM1/CDTI/SDA OCKS1/CCLK/SCL OCKS0/CSN/CAD0
74LS07 DVDD DVDD
74LVC157
CDTO/CM0=H
IPS1/IIC IPS1/IIC PSEL XTL0 XTL1
74LS07
CM0=L
SDA/CDTO
74LS07
74LS07
74LS07
74LS07
Title Size Date:
AKD4115-A
Document Number
MAIN2
Thursday, August 2006 Sheet

AKD4115-A AK4115 Evaluation Board Rev.3 GENERAL DESCRIPTION

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