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MC9RS08KA2 MC9RS08KA1
RS08 Microcontrollers
MC9RS08KA2 Rev. 12/2006
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MC9RS08KA2 Features
8-Bit RS08 Central Processor Unit (CPU) System Protection
Simplified instruction with added high-performance instructions LDA, STA, instructions support short addressing mode; address $0000 $001F accessed single-byte instruction ADD, SUB, INC, instructions support tiny addressing mode; address $0000 $000F accessed single-byte instruction with reduced instruction cycle Shadow register instructions: Pending interrupt indication Index addressing D[X] register Direct page access entire memory through paging window
Computer operating properly (COP) reset running bus-independent clock source Low-voltage detection with reset stop wakeup
Peripherals
MTIM 8-bit modulo timer ACMP Analog comparator Full rail-to-rail supply operation Option compare fixed internal bandgap reference voltage operate stop mode Keyboard interrupt ports Three ports 6-pin package Five ports 8-pin package
Development Support
Memory
On-chip Flash EEPROM MC9RS08KA2: 2048 bytes MC9RS08KA1: 1024 bytes bytes on-chip
Background debug system Breakpoint capability allow single breakpoint setting during in-circuit debug
Package Options
Power-Saving Modes
Wait stop Wakeup from power-saving modes using real-time interrupt (RTI), KBI, ACMP
Clock Source
Trimmable 20-MHz internal clock source 10-MHz internal operation 0.2% trimmable resolution, deviation over temperature voltage range
6-pin dual flat lead (DFN) package general-purpose input/output (I/O) pins general-purpose input general-purpose output 8-pin plastic dual in-line (PDIP) package Four general-purpose input/output (I/O) pins general-purpose input general-purpose output 8-pin narrow body SOIC package Four general-purpose input/output (I/O) pins general-purpose input general-purpose output
MC9RS08KA2 Series Covers: MC9RS08KA2 MC9RS08KA1
MC9RS08KA2 Rev. 12/2006
Revision History
provide most up-to-date information, revision documents World Wide will most current. Your printed copy earlier revision. verify have latest information available, refer http://freescale.com following revision history table summarizes changes contained this document.
Revision Number
Revision Date 04/2006 12/2006 Initial public release version Added MC9RS08KA1
Description Changes
This product incorporates SuperFlash® technology licensed from SST. Freescale, Freescale logo trademarks Freescale Semiconductor, Inc. Freescale Semiconductor, Inc., 2006. rights reserved. MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
List Chapters
Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Chapter Appendix Appendix
MC9RS08KA2 Series Device Overview Pins Connections Modes Operation Memory Resets, Interrupts, General System Control. Parallel Input/Output Control. Keyboard Interrupt (RS08KBIV1) Central Processor Unit (RS08CPUV1) Internal Clock Source (RS08ICSV1) Analog Comparator (RS08ACMPV1). Modulo Timer (RS08MTIMV1) Development Support Electrical Characteristics. Ordering Information Mechanical Drawings.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Table Contents
Section Number Title Chapter MC9RS08KA2 Series Device Overview
Overview Block Diagram System Clock Distribution
Page
Chapter Pins Connections
Introduction Device Assignment Recommended System Connections Detail 2.4.1 Power 2.4.2 PTA2/KBIP2/TCLK/RESET/VPP 2.4.3 PTA3/ACMPO/BKGD/MS 2.4.4 General-Purpose Peripheral Ports
Chapter Modes Operation
Introduction Features Mode Active Background Mode Wait Mode Stop Mode 3.6.1 Active Enabled Stop Mode 3.6.2 Enabled Stop Mode
Chapter Memory
Memory Unimplemented Memory Indexed/Indirect Addressing Register Addresses Assignments Flash 4.6.1 Features 4.6.2 Flash Programming Procedure 4.6.3 Flash Mass Erase Operation 4.6.4 Security
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Section Number
Title
Page
Flash Registers Control Bits 4.7.1 Flash Options Register (FOPT NVOPT) 4.7.2 Flash Control Register (FLCR) Page Select Register (PAGESEL)
Chapter Resets, Interrupts, General System Control
Introduction Features Reset Computer Operating Properly (COP) Watchdog Interrupts Low-Voltage Detect (LVD) System 5.6.1 Power-On Reset Operation 5.6.2 Reset Operation 5.6.3 Interrupt Operation Real-Time Interrupt (RTI) Reset, Interrupt, System Control Registers Control Bits 5.8.1 System Reset Status Register (SRS) 5.8.2 System Options Register (SOPT) 5.8.3 System Device Identification Register (SDIDH, SDIDL) 5.8.4 System Real-Time Interrupt Status Control Register (SRTISC) 5.8.5 System Power Management Status Control Register (SPMSC1) 5.8.6 System Interrupt Pending Register (SIP1)
Chapter Parallel Input/Output Control
Behavior Low-Power Modes Parallel Registers 6.2.1 Port Registers Control Registers 6.3.1 Port Control Registers 6.3.1.1 Internal Pulling Device Enable 6.3.1.2 Pullup/Pulldown Control 6.3.1.3 Output Slew Rate Control Enable
Chapter Keyboard Interrupt (RS08KBIV1)
Introduction 7.1.1 Features 7.1.2 Modes Operation 7.1.2.1 Operation Wait Mode 7.1.2.2 Operation Stop Mode 7.1.2.3 Operation Active Background Mode 7.1.3 Block Diagram
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Section Number
Title
Page
External Signal Description Register Definition 7.3.1 Status Control Register (KBISC) 7.3.2 Enable Register (KBIPE) 7.3.3 Edge Select Register (KBIES) Functional Description 7.4.1 Edge Only Sensitivity 7.4.2 Edge Level Sensitivity 7.4.3 Pullup/Pulldown Device 7.4.4 Initialization
Chapter Central Processor Unit (RS08CPUV1)
Introduction Programmer's Model Registers 8.2.1 Accumulator 8.2.2 Program Counter (PC) 8.2.3 Shadow Program Counter (SPC) 8.2.4 Condition Code Register (CCR) 8.2.5 Indexed Data Register (D[X]) 8.2.6 Index Register 8.2.7 Page Select Register (PAGESEL) Addressing Modes 8.3.1 Inherent Addressing Mode (INH) 8.3.2 Relative Addressing Mode (REL) 8.3.3 Immediate Addressing Mode (IMM) 8.3.4 Tiny Addressing Mode (TNY) 8.3.5 Short Addressing Mode (SRT) 8.3.6 Direct Addressing Mode (DIR) 8.3.7 Extended Addressing Mode (EXT) 8.3.8 Indexed Addressing Mode (IX, Implemented Pseudo Instructions) Special Operations 8.4.1 Reset Sequence 8.4.2 Interrupts 8.4.3 Wait Stop Mode 8.4.4 Active Background Mode Summary Instruction Table
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Section Number
Title Chapter Internal Clock Source (RS08ICSV1)
Page
Introduction Introduction 9.2.1 Features 9.2.2 Modes Operation 9.2.2.1 Engaged Internal (FEI) 9.2.2.2 Bypassed Internal (FBI) 9.2.2.3 Bypassed Internal Power (FBILP) 9.2.2.4 Stop (STOP) 9.2.3 Block Diagram External Signal Description Register Definition 9.4.1 Control Register (ICSC1) 9.4.2 Control Register (ICSC2) 9.4.3 Trim Register (ICSTRM) 9.4.4 Status Control (ICSSC) Functional Description 9.5.1 Operational Modes 9.5.1.1 Engaged Internal (FEI) 9.5.1.2 Bypassed Internal (FBI) 9.5.1.3 Bypassed Internal Power (FBILP) 9.5.1.4 Stop 9.5.2 Mode Switching 9.5.3 Frequency Divider 9.5.4 Power Usage 9.5.5 Internal Reference Clock 9.5.6 Fixed Frequency Clock
Chapter Analog Comparator (RS08ACMPV1)
10.1 Introduction 10.1.1 Features 10.1.2 Modes Operation 10.1.2.1 Operation Wait Mode 10.1.2.2 Operation Stop Mode 10.1.2.3 Operation Active Background Mode 10.1.3 Block Diagram 10.2 External Signal Description 10.3 Register Definition 10.3.1 ACMP Status Control Register (ACMPSC) 10.4 Functional Description
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Section Number
Title Chapter Modulo Timer (RS08MTIMV1)
Page
11.1 Introduction 11.1.1 Features 11.1.2 Modes Operation 11.1.2.1 Operation Wait Mode 11.1.2.2 Operation Stop Modes 11.1.2.3 Operation Active Background Mode 11.1.3 Block Diagram 11.2 External Signal Description 11.3 Register Definition 11.3.1 MTIM Status Control Register (MTIMSC) 11.3.2 MTIM Clock Configuration Register (MTIMCLK) 11.3.3 MTIM Counter Register (MTIMCNT) 11.3.4 MTIM Modulo Register (MTIMMOD) 11.4 Functional Description 11.4.1 MTIM Operation Example
Chapter Development Support
12.1 Introduction 12.2 Features 12.3 RS08 Background Debug Controller (BDC) 12.3.1 BKGD Description 12.3.2 Communication Details 12.3.3 SYNC Serial Communication Timeout .100 12.4 Registers Control Bits .101 12.4.1 Status Control Register (BDCSCR) .101 12.4.2 Breakpoint Match Register .102 12.5 RS08 Commands .103
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Section Number
Title Appendix Electrical Characteristics
Page
Introduction .107 Absolute Maximum Ratings .107 Thermal Characteristics .108 Electrostatic Discharge (ESD) Protection Characteristics .109 Characteristics .109 Supply Current Characteristics .113 Analog Comparator (ACMP) Electricals .115 Internal Clock Source Characteristics .115 Characteristics .116 A.9.1 Control Timing .116 A.10 FLASH Specifications .117
Appendix Ordering Information Mechanical Drawings
Ordering Information .121 Mechanical Drawings .121
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter MC9RS08KA2 Series Device Overview
Overview
MC9RS08KA2 Series microcontroller unit (MCU) extremely low-cost, small count device home appliances, toys, small geometry applications. This device composed standard on-chip modules including, very small highly efficient RS08 core, bytes RAM, bytes Flash, 8-bit modulo timer, keyboard interrupt, analog comparator. device available small 8-pin packages.
Block Diagram
RS08 CORE 5-BIT KEYBOARD INTERRUPT MODULE (KBI)
block diagram, Figure 1-1, shows structure MC9RS08KA2 Series MCU.
ACMP+ TCLK ACMPO
RS08 SYSTEM CONTROL RESET STOP WAKEUP MODES OPERATION POWER MANAGEMENT WAKEUP
ANALOG COMPARATOR MODULE (ACMP)
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP- PTA2/KBIP2/TCLK/RESET/VPP (1),( PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1),
ACMP-
MODULO TIMER MODULE (MTIM)
USER FLASH MC9RS08KA2 2048 BYTES MC9RS08KA1 1024 BYTES
USER BYTES
INTERNAL CLOCK SOURCE (ICS)
POWER INTERNAL REGULATOR
NOTES: Pins software configurable with pullup/pulldown device input port. Integrated pullup device enabled reset enabled (RSTPE=1). These pins available 6-pin package.
Figure 1-1. MC9RS08KA2 Series Block Diagram
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter MC9RS08KA2 Series Device Overview
Table provides functional versions on-chip modules.
Table 1-1. Block Versions
Module Analog Comparator (ACMP) Keyboard Interrupt (KBI) Modulo Timer (MTIM) Internal Clock Source (ICS) Version
System Clock Distribution
SYSTEM CONTROL LOGIC TCLK RTICLKS MTIM
1-kHz ICSIRCLK ICSFFCLK ICSOUT CLOCK
FIXED CLOCK (XCLK)
FLASH
Figure 1-2. System Clock Distribution Diagram
Figure shows simplified clock connection diagram MCU. clock frequency half output frequency used internal modules.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
Introduction
This chapter describes signals that connect package pins. includes pinout diagram, table signal properties, detailed discussion signals.
Device Assignment
Figure Figure show assignments packages available MC9RS08KA2 Series.
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP-
Figure 2-1. MC9RS08KA2 Series 6-Pin
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 PTA5/KBIP5
Figure 2-2. MC9RS08KA2 Series 8-Pin PDIP
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
PTA2/KBIP2/TCLK/RESET/VPP PTA3/ACMPO/BKGD/MS
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 PTA5/KBIP5
Figure 2-3. MC9RS08KA2 Series 8-Pin Narrow Body SOIC
Recommended System Connections
MC9RS08KA2 CBUK
Figure shows reference connection background debug Flash programming.
BKGD/MS
BACKGROUND HEADER
RESET/VPP
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMPPTA4/KBIP4 (Note
NOTES: This available 6-pin package.
PTA5/KBIP5 (Note
Figure 2-4. Reference System Connection Diagram
Detail
This section provides detailed description system connections.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
2.4.1
Power
primary power supply pins MCU. This voltage source supplies power buffer circuitry internal voltage regulator. internal voltage regulator provides regulated lower-voltage source other internal circuitry MCU. Typically, application systems have separate capacitors across power pins: bulk electrolytic capacitor, such 10-µF tantalum capacitor, provide bulk charge storage overall system, bypass capacitor, such 0.1-µF ceramic capacitor, located near power pins practical suppress high-frequency noise.
2.4.2
PTA2/KBIP2/TCLK/RESET/VPP
After power-on reset (POR) into user mode, PTA2/KBIP2/TCLK/RESET/VPP defaults general-purpose input port pin, PTA2. Setting RSTPE SOPT configures RESET input pin. After configured RESET, will remain RESET until next POR. RESET used reset from external source when driven low. When enabled RESET (RSTPE internal pullup device automatically enabled. External voltage (typically Section A.10, "FLASH Specifications") required this when performing Flash programming erasing. connection always connected internal Flash module regardless function. avoid over stressing Flash, external voltage must removed voltage higher than must avoided when Flash programming erasing taking place. NOTE This does contain clamp diode should driven above when Flash programming erasing taking place.
2.4.3
PTA3/ACMPO/BKGD/MS
background mode select function shared with output-only PTA3 optional analog comparator output. While reset, functions mode select pin. Immediately after reset rises, functions background used background debug communication. While functioning background mode select pin, this internal pullup device enabled. output-only port, BKGDPE SOPT must cleared. nothing connected this pin, will enter normal operating mode rising edge reset. debug system connected 6-pin standard background debug header, hold BKGD/MS during power-on-reset, which forces active background mode. BKGD used primarily background debug controller (BDC) communications using custom protocol that uses clock cycles target MCU's clock time. target MCU's clock equals clock rate; therefore, significant capacitance should connected BKGD/MS that could interfere with background serial communications. Although BKGD pseudo open-drain pin, background debug communication protocol provides brief, actively driven, high speedup pulses ensure fast rise times. Small capacitances from
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Pins Connections
cables absolute value internal pullup device play almost role determining rise fall times BKGD pin.
2.4.4
General-Purpose Peripheral Ports
remaining pins shared among general-purpose on-chip peripheral functions such timers analog comparator. Immediately after reset, these pins configured high-impedance general-purpose inputs with internal pullup/pulldown devices disabled. NOTE avoid extra current drain from floating input pins, reset initialization routine application program should either enable on-chip pullup/pulldown devices change direction unused pins outputs.
Table 2-1. Sharing Reference
Name PTA0 Direction Pullup/Pulldown1 PTA0 KBIP0 ACMP+ PTA1 KBIP1 ACMPPTA2 KBIP2 TCLK RESET PTA3 ACMPO BKGD PTA4 KBIP4 PTA5 KBIP5 Alternative Functions2 Power Ground General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) Analog comparator input General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) Analog comparator input General-purpose input Keyboard interrupt (stop/wait wakeup only) Modulo timer clock source Reset General-purpose output Analog comparator output Background debug data Mode select General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only) General-purpose input/output (GPIO) Keyboard interrupt (stop/wait wakeup only)
PTA1
PTA2
SWC4
PTA3
I/O3
PTA45 PTA55
software-controlled pullup/pulldown resistor; register associated with respective port. Alternative functions listed lowest priority first. example, GPIO lowest priority alternative function PTA0 pin; ACMP+ highest priority alternative function PTA0 pin. Output-only when configured PTA3 function. When PTA2 PTA3 configured RESET BKGD/MS, respectively, pullup enabled. When attached, pullup/pulldown disabled automatically. This available 6-pin package. Enabling either pullup pulldown device recommended prevent extra current leakage from floating input pin.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
Introduction
This chapter describes operating modes MC9RS08KA2 Series described this chapter. also details entry into each mode, exit from each mode, functionality while each modes.
Features
Active background mode code development Wait mode: shuts down conserve power System clocks continue Full voltage regulation maintained Stop mode: System clocks stopped; voltage regulator standby internal circuits remain powered fast recovery
Mode
This normal operating mode MC9RS08KA2 Series. This mode selected when BKGD/MS high rising edge reset. this mode, executes code from internal memory with execution beginning address $3FFD. instruction (opcode $BC) with operand located $3FFE-$3FFF must programmed correct reset operation into user application. operand defines location which user program will start. Instead using vector fetching process HC08/S08 families, user program responsible performing instruction relocate program counter correct user program start location.
Active Background Mode
active background mode functions managed through background debug controller (BDC) RS08 core. provides means analyzing operation during software development. Active background mode entered four ways: When BKGD/MS during power-on-reset (POR) immediately after issuing background debug force reset (BDC_RESET) command When BACKGROUND command received through BKGD When BGND instruction executed
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
When breakpoint encountered
After active background mode entered, held suspended state waiting serial background commands rather than executing instructions from user application program. Background commands types: Non-intrusive commands, defined commands that issued while user program running, issued through BKGD while mode. Non-intrusive commands also executed when active background mode. Non-intrusive commands include: Memory access commands Memory-access-with-status commands BACKGROUND command Active background commands, which executed only while active background mode, include commands Read write registers Trace user program instruction time Leave active background mode return user application program (GO) Active background mode used program user application code into Flash program memory before operated mode first time. When MC9RS08KA2 Series shipped from Freescale Semiconductor factory, Flash program memory usually erased there program that could executed mode until Flash memory initially programmed. active background mode also used erase reprogram Flash memory after been previously programmed. additional information about active background mode, refer Development Support chapter this data sheet.
Wait Mode
Wait mode entered executing WAIT instruction. Upon execution WAIT instruction, enters low-power state which clocked. program counter (PC) halted position where WAIT instruction executed. When interrupt request occurs: exits wait mode resumes processing. incremented fetches next instruction processed. responsibility user program probe corresponding interrupt source that woke MCU, because vector fetching process involved. While wait mode, background debug commands used. Only BACKGROUND command memory-access-with-status commands available when wait mode. memory-access-with-status commands allow memory access, they report error indicating that either stop wait mode. BACKGROUND command used wake from wait mode enter active background mode.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
Table summarizes behavior wait mode.
Table 3-1. Wait Mode Behavior
Mode Wait Standby Digital Peripherals Optionally ACMP Optionally Regulator Pins States held Optionally
Stop Mode
Stop mode entered upon execution STOP instruction when STOPE system option register set. stop mode, internal clocks modules halted. STOPE when executes STOP instruction, will enter stop mode illegal opcode reset forced. Table summarizes behavior stop mode.
Table 3-2. Stop Mode Behavior
Mode Stop
Standby
Digital Peripherals Standby
ICS1 Optionally
ACMP2 Optionally
Regulator Standby
Pins States held
RTI3 Optionally
requires IREFSTEN LVDE LVDSE must allow operation stop. bandgap reference required, LVDE LVDSE bits SPMSC1 must both before entering stop. 32-kHz trimmed clock module selected clock source RTI, LVDE LVDSE bits SPMSC1 must both before entering stop.
Upon entering stop mode, clocks halted. turned default when IREFSTEN cleared voltage regulator standby. states internal registers logic, well content, maintained. states held. Exit from stop done asserting RESET, asynchronous interrupt that been enabled, real-time interrupt. asynchronous interrupts pins, interrupt, ACMP interrupt. stop exited asserting RESET pin, will reset program execution starts location $3FFD. exited means asynchronous interrupt real-time interrupt, next instruction after location where STOP instruction executed will executed accordingly. responsibility user program probe corresponding interrupt source that woke CPU. separate self-clocked source kHz) real-time interrupt allows wakeup from stop mode with external components. When RTIS 000, real-time interrupt function 1-kHz source disabled. Power consumption lower when 1-kHz source disabled, that case, real-time interrupt cannot wake from stop. trimmed 32-kHz clock module also enabled real-time interrupt allow wakeup from stop mode with external components. 32-kHz clock reference enabled setting
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Modes Operation
IREFSTEN bit. stop, LVDE LVDSE bits SPMSC1 must both before entering stop.
3.6.1
Active Enabled Stop Mode
Entry into active background mode from mode enabled ENBDM BDCSCR set. This register described Development Support chapter this data sheet. ENBDM when executes STOP instruction, system clocks background debug logic remain active when enters stop mode background debug communication still possible. addition, voltage regulator does enter low-power standby state; maintains full internal regulation. Most background commands available stop mode. memory-access-with-status commands allow memory access, they report error indicating that either stop wait mode. BACKGROUND command used wake from stop enter active background mode ENBDM set. After active background mode entered, background commands available. Table summarizes behavior stop when entry into active background mode enabled.
Table 3-3. Enabled Stop Mode Behavior
Mode Stop Standby Digital Peripherals Standby ACMP Optionally Regulator Pins States held Optionally
3.6.2
Enabled Stop Mode
system capable generating either interrupt reset when supply voltage drops below voltage. enabled stop (LVDE LVDSE bits SPMSC1 both set) time executes STOP instruction, voltage regulator remains active. Table summarizes behavior stop when reset enabled.
Table 3-4. Enabled Stop Mode Behavior
Mode Stop Standby Digital Peripherals Standby Optionally ACMP Optionally Regulator Pins States held Optionally
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Memory
memory divided into following groups: Fast access using tiny short instructions ($0000-$000E1) Indirect data access D[X] ($000E) Index register D[X] ($000F) Frequently used peripheral registers ($0010-$001E) PAGESEL register ($001F) ($0020-$004F) Paging window ($00C0-$00FF) Other peripheral registers ($0200-$023F) Nonvolatile memory MC9RS08KA2: $3800-$3FFF MC9RS08KA1: $3C00-$3FFF
Physical $000E accessed through D[X] register when content index register $0E. MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
$0000 $000D $000E $000F $0010 $001E $001F $0020
FAST ACCESS BYTES D[X] REGISTER FREQUENTLY USED REGISTERS PAGESEL BYTES
PAGE REGISTER CONTENT
$0000 $000D $000E $000F $0010 $001E $001F $0020
FAST ACCESS BYTES D[X] REGISTER FREQUENTLY USED REGISTERS PAGESEL BYTES
PAGE REGISTER CONTENT
$004F UNIMPLEMENTED $00C0 PAGING WINDOW $00FF
$004F UNIMPLEMENTED $00C0 PAGING WINDOW $00FF
UNIMPLEMENTED
UNIMPLEMENTED
$0200 $023F HIGH PAGE REGISTERS
(reset value)
$0200 $023F HIGH PAGE REGISTERS
(reset value)
UNIMPLEMENTED $3800 FLASH 2044 BYTES $3FFB $3FFC $3FFD NVOPT $3C00 $3FFB $3FFC $3FFD
UNIMPLEMENTED
FLASH 1020 BYTES NVOPT
FLASH $3FFF MC9RS08KA2 $3FFF
FLASH
MC9RS08KA1
Figure 4-1. MC9RS08KA2 Series Memory Maps
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Unimplemented Memory
Attempting access either data instruction unimplemented memory address will cause reset.
Indexed/Indirect Addressing
Register D[X] register together perform indirect data access. Register D[X] mapped address $000E. Register located address $000F. 8-bit register contains address that used when register D[X] accessed. Register cleared zero upon reset. programming register location first page ($0000-$00FF) read/written register D[X]. Figure shows relationship between D[X] register example, HC08/S08 syntax comparable D[X] RS08 coding when register been programmed with index value. physical location $000E RAM. Accessing location through D[X] returns $000E content when register contains $0E. physical location $000F register itself. Reading location through D[X] returns register content; writing location modifies register
$0000
$000E $000F
D[X] Register Register specify location between $0000-$00FF
Address indicated Register
Content this location accessed D[X]
$00FF $0100
Figure 4-2. Indirect Addressing Registers
Register Addresses Assignments
fast access area accessed instructions using tiny, short, direct addressing mode instructions. tiny addressing mode instructions, operand encoded along with opcode single byte.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Frequently used registers make short addressing mode instructions faster load, store, clear operations. short addressing mode instructions, operand encoded along with opcode single byte.
Table 4-1. Register Summary
Address Register Name $0000- $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $0020- $004F $0050- $00BF $00C0- $00FF $0100- $01FF $0200 $0201 $0202 $0203 $0204 $0205 $0206 $0207 $0208 $0209 $020A $020B
Fast Access D[X]1 PTAD PTADD Unimplemented ACMPSC ICSC1 ICSC2 ICSTRM ICSSC MTIMSC MTIMCLK MTIMCNT MTIMMOD KBISC KBIPE KBIES PAGESEL ACME BDIV TOIE ACBGS CLKS PTAD4 PTAD3 PTADD4 ACIE TRIM TRST TSTP CLKS COUNT KBIPE5 KBIPE4 KBEDG5 KBEDG4 AD11 AD10 Unimplemented PTAD5 PTADD5 PTAD2 ACOPE CLKST PTAD1 PTAD0 PTADD1 PTADD0 ACMOD IREFSTEN FTRIM
AD13
AD12
KBACK KBIPE2 KBEDG2
KBIE KBIPE1 KBEDG1
KBIMOD KBIPE0 KBEDG0
Paging Window Unimplemented SOPT SIP1 Unimplemented Reserved Unimplemented SDIDH SDIDL SRTISC SPMSC1 Reserved Reserved COPE REV3 RTIF LVDF COPT REV2 RTIACK LVDACK STOPE REV1 RTICLKS LVDIE ILOP REV0 RTIE LVDRE LVDSE LVDE RTIS BGBE ILAD ACMP MTIM BKGDPE RSTPE
Unimplemented Reserved
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Table 4-1. Register Summary (continued)
Address Register Name $020C- $020F $0210 $0211 $0212- $0213 $0214- $021F $0220 $0221 $0222 $0223- $023F $3FF8 $3FF9 $3FFA2 $3FFB2 $3FFC Unimplemented FOPT FLCR Reserved Unimplemented PTAPE PTAPUD PTASE Unimplemented PTAPE5 PTAPUD5 PTASE5 PTAPE4 PTAPUD4 PTASE4 HVEN PTASE3 MASS PTAPE2 PTAPUD2 PTAPE1 PTAPUD1 PTASE1 SECD PTAPE0 PTAPUD0 PTASE0
Reserved Reserved Reserved Reserved NVOPT
Reserved Room Temperature Trim Reserved
FTRIM SECD
Unimplemented Reserved
Physical $000E accessed through D[X] register when content index register $0E. using untrimmed, $3FFA $3FFB used applications.
device includes sections static RAM. locations from $0000 $000D directly accessed using more efficient tiny addressing mode instructions short addressing mode instructions. Location $000E either accessed through D[X] register when register through paging window location $00CE when PAGESEL register $00. second section starts from $0020 $004F, accessed using direct addressing mode instructions. retains data when low-power wait stop mode. data unaffected reset provided that supply voltage does drop below minimum value retention.
Flash
Flash memory intended primarily program storage. In-circuit programming allows operating program loaded into Flash memory after final assembly application product. possible program entire array through single-wire background debug interface. Because device does include on-chip charge pump circuitry, external required program erase operations.
4.6.1
Features
Features Flash memory include:
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
1000 program/erase cycles typical voltage temperature Security feature Flash
4.6.2
Flash Programming Procedure
Programming Flash memory done basis. consists consecutive bytes starting from addresses $3X00, $3X40, $3X80, $3XC0. following procedure program Flash memory: Apply external VPP. bit. This configures memory program operation enables latching address data programming. Write data Flash location, high page accessing window $00C0-$00FF, within address range programmed. (Prior data writing operation, PAGESEL register must configured correctly high page accessing window corresponding Flash row). Wait time, tnvs. HVEN bit. Wait time, tpgs. Write data Flash location programmed. Wait time, tprog. Repeat steps until bytes within programmed. Clear bit. Wait time, tnvh. Clear HVEN bit. After time, trcv, memory accessed read mode again. Remove external VPP. This program sequence repeated throughout memory until data programmed. NOTE Flash memory cannot programmed erased software code executed from Flash locations. program erase Flash, commands must executed from commands. User code should enter wait stop during erase program sequence. These operations must performed order shown; other unrelated operations occur between steps.
4.6.3
Flash Mass Erase Operation
following procedure mass erase entire Flash memory: Apply external VPP. MASS Flash control register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
Write data Flash location, high page accessing window $00C0-$00FF. (Prior data writing operation, PAGESEL register must configured correctly high page accessing window Flash locations). Wait time, tnvs. HVEN bit. Wait time tme. Clear MASS bit. Wait time, tnvh1. Clear HVEN bit. After time, trcv, memory accessed read mode again. Remove external VPP. NOTE Flash memory cannot programmed erased software code executed from Flash locations. program erase Flash, commands must executed from commands. User code should enter wait stop during erase program sequence. These operations must performed order shown, other unrelated operations occur between steps.
4.6.4
Security
MC9RS08KA2 Series includes circuitry help prevent unauthorized access contents Flash memory. When security engaged, Flash considered secure resource. RAM, direct-page registers, background debug controller considered unsecured resources. Attempts access secure memory location through background debug interface, whenever BKGDPE set, blocked (reads return 0s). Security engaged disengaged based state nonvolatile register (SECD) FOPT register. During reset, contents nonvolatile location NVOPT copied from Flash into working FOPT register high-page register space. user engages security programming NVOPT location, which done same time Flash memory programmed. Notice erased state (SECD makes unsecure. When SECD NVOPT programmed (SECD next time device reset POR, internal reset, external reset, security engaged. order disengage security, mass erase must performed commands followed reset. separate background debug controller still used registers access. Flash mass erase possible writing Flash control register that follows Flash mass erase procedure listed Section 4.6.3, "Flash Mass Erase Operation," commands. Security always disengaged through background debug interface following these steps: Mass erase Flash background commands loaded program. Perform reset device will boot with security disengaged.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
NOTE When device boots normal operating mode, where high during reset, with SECD programmed (SECD Flash security engaged. BKGDPE reset communication blocked, background debug allowed.
Flash Registers Control Bits
Flash module nonvolatile register, NVOPT ($3FFC), Flash memory which copied into corresponding control register, FOPT ($0210), reset.
4.7.1
Flash Options Register (FOPT NVOPT)
During reset, contents nonvolatile location NVOPT copied from Flash into FOPT. Bits through used always read This register read time, writes have meaning effect. change value this register, erase reprogram NVOPT location Flash memory usual then issue reset.
Reset
SECD
This register loaded from nonvolatile location NVOPT during reset. Unimplemented Reserved
Figure 4-3. Flash Options Register (FOPT) Table 4-2. FOPT Field Descriptions
Field SECD Description Security State Code This field determines security state MCU. When secured, contents Flash memory cannot accessed instructions from unsecured source including background debug interface; refer Section 4.6.4, "Security". Security engaged. Security disengaged.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
4.7.2
Flash Control Register (FLCR)
Reset
HVEN MASS
PGM1
Unimplemented Reserved
Figure 4-4. Flash Control Register (FLCR) Table 4-3. FLCR Field Descriptions
Field HVEN Description High Voltage Enable This read/write enables high voltages Flash array program erase operations. HVEN only either MASS proper sequence program erase followed. High voltage disabled array. High voltage enabled array. Mass Erase Control This read/write configures memory mass erase operation. Mass erase operation selected. Mass erase operation selected. Program Control This read/write configures memory program operation. interlocked with MASS such that both bits cannot equal same time. Program operation selected. Program operation selected.
MASS PGM1
When Flash security engaged, writing effect. result, Flash programming allowed.
Page Select Register (PAGESEL)
There 64-byte window ($00C0-$00FF) direct-page reserved paging access. Programming page select register determines corresponding 64-byte block memory direct-page access. example, when PAGESEL register programmed with value $08, high page registers ($0200-$023F) accessed through paging window ($00C0-$00FF) direct addressing mode instructions.
AD13 Reset AD12 AD11 AD10
Figure 4-5. Page Select Register (PAGESEL) Table 4-4. PAGESEL Field Descriptions
Field AD[13:6] Description Page Selector- These bits define address line which determines 64-byte block boundary memory block accessed direct page window. Figure Table 4-5.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Memory
14-bit memory address Start address memory block selected AD[13:6]
Figure 4-6. Memory Block Boundary Selector
Table shows memory block accessed through paging window ($00C0-$00FF).
Table 4-5. Paging Window $00C0-$00FF
Page Memory Address $0000-$003F $0040-$007F $0080-$00BF $00C0-$00FF $0100-$013F $3F80-$3FBF $3FC0-$3FFF
NOTE Physical location $0000-$000E RAM. Physical location $000F register D[X] register mapped address $000E only. physical $000E accessing through D[X] register when register either with PAGESEL $00. When PAGESEL register $00, paging window mapped first page ($00-$3F). Paged location $00C0-$00CE mapped physical location $0000-$000E, i.e., RAM. Paged location $00CF mapped register Therefore, accessing address returns physical content $000E, accessing address $000E returns D[X] register content.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Introduction
This chapter discusses basic reset interrupt mechanisms various sources reset interrupt MC9RS08KA2 Series. Some interrupt sources from peripheral modules discussed greater detail within other chapters this data sheet. This chapter gathers basic information about reset interrupt sources place easy reference. reset wakeup sources, including computer operating properly (COP) watchdog real-time interrupt (RTI), part on-chip peripheral systems with their chapters part system control logic.
Features
Reset interrupt features include: Multiple sources reset flexible system configuration reliable operation System reset status register (SRS) indicate source most recent reset System interrupt pending register (SIP1) indicate status pending system interrupts Analog comparator interrupt with enable Keyboard interrupt with enable Low-voltage detect interrupt with enable Modulo timer interrupt with enable Real-time interrupt with enable; available stop with multiple rates based separate 1-kHz self-clocked source
Reset
Resetting provides start processing from known initial conditions. During reset, most control status registers forced initial values program counter started from location $3FFD. instruction (opcode $BC) with operand located $3FFE-$3FFF must programmed into user application correct reset operation. operand defines location which user program will start. On-chip peripheral modules disabled pins initially configured general-purpose high-impedance inputs with pullup/pulldown devices disabled. MC9RS08KA2 Series seven sources reset: External reset (PIN) enabled using RSTPE SOPT Power-on reset (POR) Low-voltage detect (LVD)
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Computer operating properly (COP) timer Illegal opcode detect (ILOP) Illegal address detect (ILAD) Background debug forced reset command BDC_RESET
Each these sources, with exception background debug forced reset, associated system reset status register (SRS).
Computer Operating Properly (COP) Watchdog
watchdog intended force system reset application software fails execute expected. prevent system reset from timer (when enabled), application software must reset counter periodically. application program gets lost fails reset counter before times out, system reset generated force system back known starting point. After reset, COPE becomes SOPT, which enables watchdog (see Section 5.8.2, "System Options Register (SOPT)," additional information). watchdog used application, disabled clearing COPE. counter reset writing value address SRS. This write does affect data read-only SRS. Instead, writing this address decoded sends reset signal counter. There associated short long time-out controlled COPT SOPT. Table summaries control functions COPT bit. watchdog operates from 1-kHz clock source defaults associated long time-out cycles).
Table 5-1. Configuration Options
COPT
Overflow Count1 cycles cycles (256
Values shown this column based tRTI tRTI Section A.9.1, "Control Timing," tolerance this value.
Even application will reset default settings COPE COPT, user should write write-once SOPT registers during reset initialization lock settings. That way, they cannot changed accidentally application program gets lost. initial write SOPT will reset counter. background debug mode, counter will increment. When enters stop mode, counter re-initialized zero upon entry stop mode. counter begins from zero soon exits stop mode.
Interrupts
MC9RS08KA2 Series does include interrupt controller with vector table lookup mechanism used HC08 HCS08 devices. However, interrupt sources from modules such LVD, KBI,
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
ACMP still available wake from wait stop mode. responsibility user application poll corresponding module determine source wakeup. Each wakeup source module associated with corresponding interrupt enable bit. disabled, interrupt source gated, that particular source cannot wake from wait stop mode. However, corresponding interrupt flag will still indicate that external wakeup event occurred. system interrupt pending register (SIP1) indicates status system pending interrupt. When read-only SIP1 enabled, shows there pending interrupt serviced from indicated module. Writing register effect. pending interrupt flag will cleared automatically when corresponding interrupt flags from indicated module cleared.
Low-Voltage Detect (LVD) System
MC9RS08KA2 Series includes system protect against voltage conditions order protect memory contents control system states during supply voltage variations. system comprised power-on reset (POR) circuit circuit with predefined trip voltage. circuit enabled with LVDE SPMSC1. disabled upon entering stop mode unless LVDSE SPMSC1. LVDSE LVDE both set, current consumption stop with enabled will greater.
5.6.1
Power-On Reset Operation
When power initially applied MCU, when supply voltage drops below VPOR level, circuit will cause reset condition. supply voltage rises, circuit will hold reset until supply risen above VLVD level. Both following POR.
5.6.2
Reset Operation
configured generate reset upon detection voltage condition setting LVDRE After reset occurred, system will hold reset until supply voltage risen above level VLVD. register following either reset POR.
5.6.3
Interrupt Operation
When voltage condition detected circuit configured using SPMSC1 interrupt operation (LVDE set, LVDIE set, LVDRE clear), LVDF SPMSC1 will interrupt request will occur.
Real-Time Interrupt (RTI)
real-time interrupt function used generate periodic interrupts. driven from either 1-kHz internal clock reference trimmed 32-kHz internal clock reference from module. 32-kHz internal clock reference divided logic produce trimmed 1-kHz clock
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
applications requiring more accurate real-time interrupts. RTICLKS SRTISC used select clock source. Both the1-kHz 32-kHz clock sources used when run, wait stop mode. 32-kHz clock source stop, LVDE LVDSE bits SPMSC1 must both before entering stop. SRTISC register includes read-only status flag, write-only acknowledge bit, 3-bit control value (RTIS) used select seven wakeup periods disable RTI. local interrupt enable, RTIE, allow masking real-time interrupt. disabled writing each RTIS interrupts will generated. Section 5.8.4, "System Real-Time Interrupt Status Control Register (SRTISC)," detailed information about this register.
Reset, Interrupt, System Control Registers Control Bits
Refer direct-page register summary Chapter "Memory," absolute address assignments registers. This section refers registers control bits only their names. Freescale-provided equate header file used translate these names into appropriate absolute addresses. Some control bits SOPT register related modes operation. Although brief descriptions these bits provided here, related functions discussed greater detail Chapter "Modes Operation".
5.8.1
System Reset Status Register (SRS)
This high page register includes read-only status flags indicate source most recent reset. When debug host forces reset BDC_RESET command, status bits will cleared. Writing value this register address clears watchdog timer without affecting contents this register. reset state these bits depends what caused reset.
POR: LVR: other reset:
ILOP
ILAD
Writing value address clears watchdog timer. Note Note Note Note
these reset sources that active time reset entry will cause corresponding bit(s) set; bits corresponding sources that active time reset entry will cleared.
Figure 5-1. System Reset Status (SRS)
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-2. Field Descriptions
Field Description Power-On Reset Reset caused power-on detection logic. Because internal supply voltage ramping time, low-voltage reset (LVR) status also indicate that reset occurred while internal supply below threshold. Reset caused POR. caused reset. External Reset Reset caused active-low level external reset pin. Reset caused external reset pin. External reset caused reset. Computer Operating Properly (COP) Watchdog Reset caused watchdog timer timing out. This reset source blocked COPE Reset caused timeout. timeout caused reset. Illegal Opcode Reset caused attempt execute unimplemented illegal opcode. STOP instruction considered illegal stop disabled STOPE SOPT register. BGND instruction considered illegal active background mode disabled ENBDM BDCSC register. Reset caused illegal opcode. illegal opcode caused reset. Illegal Address Reset caused attempt access either data instruction unimplemented memory address. Reset caused illegal address. illegal address caused reset. Voltage Detect LVDRE supply drops below trip voltage, reset will occur. This also POR. Reset caused trip POR. Either trip caused reset.
ILOP
ILAD
5.8.2
System Options Register (SOPT)
This high page register write-once register only first write after reset honored. read time. subsequent attempt write SOPT (intentionally unintentionally) ignored avoid accidental changes these sensitive settings. SOPT must written during user's reset initialization program desired controls even desired settings same reset settings.
COPE Reset: POR: COPT STOPE
BKGDPE RSTPE
(Note (Note1)
Unimplemented Reserved
Unaffected
Figure 5-2. System Options Register (SOPT)
When device reset into normal operating mode high during reset), BKGDPE reset Flash security disengaged (SECD BKGDPE reset Flash security engaged (SECD When device reset into active mode during reset), BKGDPE always reset such that communication allowed.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-3. SOPT Register Field Descriptions
Field COPE COPT STOPE Description Watchdog Enable This write-once selects whether watchdog enabled. watchdog timer disabled. watchdog timer enabled (force reset timeout). Watchdog Timeout This write-once selects timeout period COP. Short timeout period selected. Long timeout period selected. Stop Mode Enable This write-once used enable stop mode. stop mode disabled user program attempts execute STOP instruction, illegal opcode reset forced. Stop mode disabled. Stop mode enabled.
Background Debug Mode Enable This write-once when enables PTA3/ACMPO/BKGD/MS BKGDPE1,2 function BKGD/MS. When clear, functions output only alternative functions. This defaults BKGD/MS function following reset. PTA3/ACMPO/BKGD/MS functions PTA3 ACMPO. PTA3/ACMPO/BKGD/MS functions BKGD/MS. RSTPE RESET Enable When set, this write-once enables PTA2/KBIP2/TCLK/RESET/VPP function RESET. When clear, functions input-only alternative functions. This input-only port function following POR. When RSTPE set, internal pullup device enabled RESET. PTA2/KBIP2/TCLK/RESET/VPP functions PTA2/KBIP2/TCLK/VPP. PTA2/KBIP2/TCLK/RESET/VPP functions RESET/VPP.
When device reset into normal operating mode high during reset), BKGDPE reset Flash security disengaged (SECD BKGDPE reset Flash security engaged (SECD When device reset into active mode during reset), BKGDPE always reset such that communication allowed. BKGDPE only write once from value Writing from value user software allowed. BKGDPE changed back only reset with proper condition stated Note
5.8.3
System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers included host development systems identify RS08 derivative revision number. This allows development software recognize where specific memory blocks, registers, control bits located target MCU.
Reset:
REV3
REV2
REV1
REV0
ID11
ID10
(Note
(Note
(Note
(Note
Unimplemented Reserved
revision number that hard coded into these bits reflects current silicon revision level.
Figure 5-3. System Device Identification Register High (SDIDH)
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-4. SDIDH Register Field Descriptions
Field REV[3:0] ID[11:8] Description Revision Number high-order bits address SDIDH hard coded reflect current mask revision number (0-F). Part Identification Number Each derivative RS08 Family unique identification number. MC9RS08KA2 Series hard coded value $0800. also bits Figure 5-4.
Reset:
Unimplemented Reserved
Figure 5-4. System Device Identification Register (SDIDL) Table 5-5. SDIDL Register Field Descriptions
Field ID[7:0] Description Part Identification Number Each derivative RS08 Family unique identification number. MC9RS08KA2 Series hard coded value $0800. also bits Figure 5-3.
5.8.4
System Real-Time Interrupt Status Control Register (SRTISC)
This high page register contains status control bits RTI.
Reset:
RTIF
RTICLKS RTIACK RTIE
RTIS
Unimplemented Reserved
Figure 5-5. System Status Control Register (SRTISC) Table 5-6. SRTISC Register Field Descriptions
Field RTIF RTIACK RTICLKS Description Real-Time Interrupt Flag This read-only status indicates periodic wakeup timer timed out. Periodic wakeup timer timed out. Periodic wakeup timer timed out. Real-Time Interrupt Acknowledge This write-only used acknowledge real-time interrupt request (write clear RTIF). Writing meaning effect. Reads always return Real-Time Interrupt Clock Select This read/write selects clock source real-time interrupt. Real-time interrupt request clock source internal 1-kHz oscillator. Real-time interrupt request clock source internal trimmed 32-kHz oscillator (ICS module) divided logic produce trimmed 1-kHz clock source counter.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
Table 5-6. SRTISC Register Field Descriptions (continued)
Field RTIE RTIS Description Real-Time Interrupt Enable This read-write enables real-time interrupts. Real-time interrupts disabled. Real-time interrupts enabled. Real-Time Interrupt Delay Selects These read/write bits select period RTI. Table 5-7.
Table 5-7. Real-Time Interrupt Period
RTIS
Timeout1 Disable 1.024
Timeout values shown based clock source period. Consult electricals tolerances internal 1-kHz source, tRTI (Table A-8) internal 32-kHz from (Table A-7).
NOTE power down internal 1-kHz oscillator completely STOP mode, RTIS bits must selected %000 RTICLKS must
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
5.8.5
System Power Management Status Control Register (SPMSC1)
This high page register contains status control bits support voltage detect function, enable bandgap voltage reference ACMP module.
Reset:
LVDF
LVDIE LVDACK
LVDRE(1)
LVDSE
LVDE(1)
BGBE
Unimplemented Reserved
This written only time after reset. Additional writes ignored.
Figure 5-6. System Power Management Status Control Register (SPMSC1) Table 5-8. SPMSC1 Register Field Descriptions
Field LVDF LVDACK LVDIE LVDRE Description Low-Voltage Detect Flag Provided LVDE this read-only status indicates low-voltage detect event. Low-Voltage Detect Acknowledge This write-only used acknowledge voltage detection errors (write clear LVDF). Reads always return Low-Voltage Detect Interrupt Enable This enables hardware interrupt requests LVDF. Hardware interrupt disabled (use polling). Request hardware interrupt when LVDF Low-Voltage Detect Reset Enable This write-once enables low-voltage detect events generate hardware reset (provided LVDE LVDF does generate hardware resets. Force reset when LVDF Low-Voltage Detect Stop Enable Provided LVDE this read/write determines whether low-voltage detect function operates when stop mode. Low-voltage detect disabled during stop mode. Low-voltage detect enabled during stop mode. Low-Voltage Detect Enable This write-once enables low-voltage detect logic qualifies operation other bits this register. logic disabled. logic enabled. Bandgap Buffer Enable This enables internal buffer bandgap voltage reference ACMP module internal channels. Bandgap buffer disabled. Bandgap buffer enabled.
LVDSE
LVDE
BGBE
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Resets, Interrupts, General System Control
5.8.6
System Interrupt Pending Register (SIP1)
This high page register contains status pending interrupt from modules.
Reset:
ACMP
MTIM
Unimplemented Reserved
Figure 5-7. System Interrupt Pending Register (SIP1) Table 5-9. SIP1 Register Field Descriptions
Field Description Keyboard Interrupt Pending This read-only indicates there pending interrupt from module. Clearing flag KBISC register clears this bit. Reset also clears this bit. There pending interrupt; i.e., flag and/or KBIE cleared. There pending interrupt; i.e., flag KBIE set. Analog Comparator Interrupt Pending This read-only indicates there pending interrupt from ACMP module. Clearing flag ACMPSC register clears this bit. Reset also clears this bit. There pending ACMP interrupt; i.e., flag and/or ACIE cleared. There pending ACMP interrupt; i.e., flag ACIE set. Modulo Timer Interrupt Pending This read-only indicates there pending interrupt from MTIM module. Clearing flag MTIMSC register clears this bit. Reset also clears this bit. There pending MTIM interrupt; i.e., flag and/or TOIE cleared. There pending MTIM interrupt; i.e., flag TOIE set. Real-Time Interrupt Pending This read-only indicates there pending interrupt from RTI. Clearing RTIF flag SRTISC register clears this bit. Reset also clears this bit. There pending interrupt; i.e., RTIF flag and/or RTIE cleared. There pending interrupt; i.e., RTIF flag RTIE set. Low-Voltage Detect Interrupt Pending This read-only indicates there pending interrupt from voltage detect module. Clearing LVDF flag SPMSC1 register clears this bit. Reset also clears this bit. There pending interrupt; i.e., LVDF flag and/or LVDE cleared. There pending interrupt; i.e., LVDF flag, LVDIE, LVDE bits set.
ACMP
MTIM
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
This section explains software controls related parallel input/output (I/O) control. MC9RS08KA2 Series parallel port, which includes pins 6-pin package four pins 8-pin packages, output-only pin, input-only pin. Chapter "Pins Connections," more information about assignments external hardware considerations these pins. these pins shared with on-chip peripheral functions shown Table 2-1. peripheral modules have priority over I/Os that when peripheral enabled, functions associated with shared pins disabled. After reset, shared peripheral functions disabled that pins controlled I/O. I/Os configured inputs (PTADDn with pullup/pulldown devices disabled (PTAPEn except output-only PTA3, which defaults BKGD/MS function. Reading writing parallel I/Os performed through port data registers. direction, either input output, controlled through port data direction registers. parallel port function individual illustrated block diagram shown Figure 6-1.
PTADDn Output Enable
PTADn Output Data
Port Read Data Synchronizer Input Data
BUSCLK
Figure 6-1. Parallel Block Diagram
data direction control (PTADDn) determines whether output buffer associated enabled, also controls source port data register reads. input buffer associated always enabled unless enabled analog function output-only pin.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
When shared digital function enabled pin, output buffer controlled shared function. However, data direction register will continue control source reads port data register. When shared analog function enabled pin, both input output buffers disabled. value read port data where input (PTADDn input buffer disabled. general, whenever shared with both alternative digital function analog function, analog function priority such that both digital analog functions enabled, analog function controls pin. good programming practice write port data register before changing direction port become output. This ensures that will driven temporarily with data value that happened port data register. Associated with parallel ports registers located high page register space that operate independently parallel registers. These registers used control pullup/pulldown slew rate pins. Section 6.3, "Pin Control Registers" more information.
Behavior Low-Power Modes
wait stop modes, states maintained because internal logic stays powered Upon recovery, functions same before entering stop.
Parallel Registers
This section provides information about registers associated with parallel ports. parallel registers located within $001F memory boundary memory map, that short direct addressing mode instructions used. Refer tables Chapter "Memory," absolute address assignments parallel I/O. This section refers registers control bits only their names. Freescale Semiconductor-provided equate header file normally used translate these names into appropriate absolute addresses.
6.2.1
Port Registers
Port parallel function controlled data data direction registers described this section.
Reset:
PTAD5 PTAD4 PTAD3
PTAD2 PTAD1 PTAD0
Figure 6-2. Port Data Register (PTAD)
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Table 6-1. PTAD Register Field Descriptions
Field PTAD[5:0] Description Port Data Register Bits port pins that inputs, reads return logic level pin. port pins that configured outputs, reads return last value written this register. Writes latched into bits this register. port pins that configured outputs, logic level driven corresponding pin. Reset forces PTAD these driven corresponding pins because reset also configures port pins high-impedance inputs with pullup/pulldowns disabled.
Reset:
PTADD5 PTADD4
PTADD1 PTADD0
Figure 6-3. Port Data Direction Register (PTADD)
Table 6-2. PTADD Register Field Descriptions
Field Description
5:4,1:0 Data Direction Port Bits These read/write bits control direction port pins what read PTADD[5:4,1:0] PTAD reads. Input (output driver disabled) reads return value. Output driver enabled port PTAD reads return contents PTADn.
Control Registers
This section provides information about registers associated with parallel ports that used control functions. Refer tables Chapter "Memory," absolute address assignments control registers. This section refers registers control bits only their names. Freescale Semiconductor-provided equate header file normally used translate these names into appropriate absolute addresses.
6.3.1
Port Control Registers
pins associated with port controlled registers provided this section. These registers control pullup/pulldown slew rate port pins independent parallel registers.
6.3.1.1
Internal Pulling Device Enable
internal pulling device enabled each port setting corresponding pulling device enable register (PTAPEn). pulling device disabled configured output parallel control logic shared peripheral output function regardless state
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
corresponding pulling device enable register bit. pulling device also disabled controlled analog function.
Reset:
PTAPE5 PTAPE4
PTAPE2 PTAPE1 PTAPE0
Figure 6-4. Internal Pulling Device Enable Port Register (PTAPE) Table 6-3. PTAPE Register Field Descriptions
Field Description
5:4,2:0 Internal Pulling Device Enable Port Bits Each these control bits determines whether internal PTAPE[5:4,2:0] pulling device enabled associated pin. port pins that configured outputs, these bits have effect internal pullup devices disabled. Internal pulling device disabled port Internal pulling device enabled port
6.3.1.2
Pullup/Pulldown Control
Pullup/pulldown control used select pullup pulldown device enabled corresponding PTAPE bit.
Reset:
PTAPUD5 PTAPUD4
PTAPUD2 PTAPUD1 PTAPUD0
Figure 6-5. Pullup/Pulldown Device Control Port (PTAPUD) Table 6-4. PTAPUD Register Field Descriptions
Field Description
5:4,2:0 Pullup/Pulldown Device Control Port Bits Each these control bits determines whether PTAPUD[5:4,2:0] internal pullup pulldown device selected associated pin. actual pullup/pulldown device only enabled enabling associated PTAPE bit. Internal pullup device selected port Internal pulldown device selected port
6.3.1.3
Output Slew Rate Control Enable
Slew rate control enabled each port setting corresponding slew rate control register (PTASEn). When enabled, slew control limits rate which output transition order reduce emissions. Slew rate control effect pins that configured inputs.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
Reset:
PTASE5 PTASE4 PTASE3
PTASE1 PTASE0
Figure 6-6. Slew Rate Enable Port Register (PTASE) Table 6-5. PTASE Register Field Descriptions
Field Description
5:3;1:0 Output Slew Rate Enable Port Bits Each these control bits determines whether output slew PTASE[5:3;1:0] rate control enabled associated pin. port pins that configured inputs, these bits have effect. Output slew rate control disabled port Output slew rate control enabled port
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Parallel Input/Output Control
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
Introduction
keyboard interrupt (KBI) module provides independently enabled external interrupt sources.
RS08 CORE 5-BIT KEYBOARD INTERRUPT MODULE (KBI)
ACMP+ TCLK ACMPO RS08 SYSTEM CONTROL RESET STOP WAKEUP MODES OPERATION POWER MANAGEMENT WAKEUP ANALOG COMPARATOR MODULE (ACMP) ACMP-
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP- PTA2/KBIP2/TCLK/RESET/VPP (1),( PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1),
MODULO TIMER MODULE (MTIM)
USER FLASH 2,048 BYTES
USER BYTES
INTERNAL CLOCK SOURCE (ICS)
POWER INTERNAL REGULATOR
NOTES: Pins software configurable with pullup/pulldown device input port. Integrated pullup device enabled reset enabled (RSTPE=1). These pins available 6-pin package
Figure 7-1. MC9RS08KA2 Series Block Diagram with Block Pins Highlighted
7.1.1
Features
features include: Each keyboard interrupt individual enable Each keyboard interrupt programmable falling edge rising edge) only, both falling edge level both rising edge high level) interrupt sensitivity software-enabled keyboard interrupt Exit from low-power modes
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
7.1.2
Modes Operation
This section defines operation wait, stop, background debug modes.
7.1.2.1
Operation Wait Mode
continues operate wait mode enabled before executing WAIT instruction. Therefore, enabled (KBPEn used bring wait mode interrupt enabled (KBIE
7.1.2.2
Operation Stop Mode
operates asynchronously stop mode enabled before executing STOP instruction. Therefore, enabled (KBPEn used bring stop mode interrupt enabled (KBIE
7.1.2.3
Operation Active Background Mode
When microcontroller active background mode, will continue operate normally.
7.1.3
Block Diagram
KBACK KBIPE0 RESET SYNCHRONIZER BUSCLK
block diagram keyboard interrupt module shown Figure 7-2.
KBIP0
KBEDG0 KEYBOARD INTERRUPT KBIPEn KBMOD KBIE KBEDGn STOP STOP BYPASS INTERRUPT REQUEST
KBIPn
Figure 7-2. Keyboard Interrupt (KBI) Block Diagram
External Signal Description
input pins used detect either falling edges, both falling edge level interrupt requests. input pins also used detect either rising edges, both rising edge high level interrupt requests. signal properties shown Table 7-1.
Table 7-1. Signal Properties
Signal KBIPn Function Keyboard interrupt pins
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
Register Definition
includes three registers: 8-bit status control register 8-bit enable register 8-bit edge select register Refer direct-page register summary Chapter "Memory," absolute address assignments registers. This section refers registers control bits only their names. registers summarized Table 7-2.
Table 7-2. Register Summary
Name KBISC KBIPE KBIES KBEDG5 KBEDG4 KBEDG2 KBEDG1 KBEDG0 KBIPE5 KBIPE4 KBIPE2 KBIPE1 KBIPE0 KBACK
KBIE KBMOD
7.3.1
Status Control Register (KBISC)
KBISC contains status flag control bits, which used configure KBI.
Reset:
KBIE KBACK KBMOD
Unimplemented
Figure 7-3. Status Control Register (KBISC) Table 7-3. KBISC Register Field Descriptions
Field KBACK Description Keyboard Interrupt Flag indicates that keyboard interrupt detected. Writes have effect KBF. keyboard interrupt detected. Keyboard interrupt detected. Keyboard Acknowledge Writing KBACK part flag-clearing mechanism. KBACK always reads
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
Table 7-3. KBISC Register Field Descriptions (continued)
Field KBIE KBMOD Description Keyboard Interrupt Enable KBIE enables keyboard interrupt requests. Keyboard interrupt request enabled. Keyboard interrupt request enabled. Keyboard Detection Mode KBMOD (along with KBEDG bits) controls detection mode keyboard interrupt pins. Keyboard detects edges only. Keyboard detects both edges levels.
7.3.2
Enable Register (KBIPE)
KBIPE contains enable control bits.
Reset:
KBIPE5 KBIPE4
KBIPE2 KBIPE1 KBIPE0
Figure 7-4. Enable Register (KBIPE) Table 7-4. KBIPE Register Field Descriptions
Field 5,4, KBIPEn Description Keyboard Enables Each KBIPEn bits enables corresponding keyboard interrupt pin. Corresponding enabled keyboard interrupt. Corresponding enabled keyboard interrupt.
7.3.3
Edge Select Register (KBIES)
KBIES contains edge select control bits.
Reset:
KBEDG5 KBEDG4
KBEDG2 KBEDG1 KBEDG0
Figure 7-5. Edge Select Register (KBIES) Table 7-5. KBIES Register Field Descriptions
Field 5,4, KBEDGn Description Keyboard Edge Selects Each KBEDGn bits selects falling edge/low level rising edge/high level function corresponding pin. Falling edge/low level. Rising edge/high level.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
Functional Description
This on-chip peripheral module called keyboard interrupt (KBI) module because originally designed simplify connection row-column matrices keyboard switches. However, these inputs also useful extra external interrupt inputs external means waking from stop wait low-power modes. module allows pins additional interrupt sources. Writing KBIPEn bits keyboard interrupt enable register (KBIPE) independently enables disables each pin. Each configured edge sensitive edge level sensitive based KBMOD keyboard interrupt status control register (KBISC). Edge sensitive software programmed either falling rising; level either high. polarity edge edge level sensitivity selected using KBEDGn bits keyboard interrupt edge select register (KBIES). Synchronous logic used detect edges. Prior detecting edge, enabled keyboard inputs must deasserted logic level. falling edge detected when enabled keyboard input signal seen logic (the deasserted level) during cycle then logic (the asserted level) during next cycle. rising edge detected when input signal seen logic during cycle then logic during next cycle.
7.4.1
Edge Only Sensitivity
valid edge enabled will KBISC. KBIE KBISC set, interrupt request will presented CPU. Clearing accomplished writing KBACK KBISC.
7.4.2
Edge Level Sensitivity
valid edge level enabled will KBISC. KBIE KBISC set, interrupt request will presented CPU. Clearing accomplished writing KBACK KBISC, provided enabled keyboard inputs their deasserted levels. will remain enabled asserted while attempting clear writing KBACK.
7.4.3
Pullup/Pulldown Device
pins does automatically configure internal pullup/pulldown device when enabled. internal pull device used configuring associated port pull device enable register (PTAPE) pullup/pulldown control register (PTAPUD).
7.4.4
Initialization
When keyboard interrupt first enabled, possible false keyboard interrupt flag. prevent false interrupt request during keyboard initialization, user should following: Mask keyboard interrupts clearing KBIE KBISC. using internal pullup/pulldown device, configure associated port pullup/pulldown device. Enable polarity setting appropriate KBEDGn bits KBIES. Enable pins setting appropriate KBIPEn bits KBIPE.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Keyboard Interrupt (RS08KBIV1)
Write KBACK KBISC clear false interrupts. KBIE KBISC enable interrupts.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Introduction
This chapter summary information about registers, addressing modes, instruction RS08 Family CPU. more detailed discussion, refer RS08 Core Reference Manual, volume Freescale Semiconductor document order number RS08RMv1. RS08 been developed target extremely low-cost embedded applications using process-independent design methodology, allowing keep pace with rapid developments silicon processing technology. main features RS08 core are: Streamlined programmer's model Subset HCS08 instruction with minor instruction extensions Minimal instruction cost-sensitive embedded applications instructions shadow program counter manipulation, short tiny addressing modes code size optimization bytes accessible memory space Reset will fetch first instruction from $3FFD Low-power modes supported through execution STOP WAIT instructions Debug FLASH programming support using background debug controller module Illegal address opcode detection with reset
Programmer's Model Registers
Figure shows programmer's model RS08 CPU. These registers located memory microcontroller. They built directly inside logic.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
ACCUMULATOR SHADOW PROGRAM COUNTER PROGRAM COUNTER
CONDITION CODE REGISTER
CARRY ZERO
Figure 8-1. Registers
addition registers, there three memory mapped registers that tightly coupled with core address generation during data read write operations. They indexed data register (D[X]), index register (X), page select register (PAGESEL). These registers located $000E, $000F, $001F, respectively.
INDEXED DATA REGISTER D[X] (location $000E) INDEX REGISTER PAGE SELECT PAGESEL (location $001F) (location $000F)
Figure 8-2. Memory Mapped Registers
8.2.1
Accumulator
This general-purpose 8-bit register primary data register RS08 MCUs. Data read from memory into with load accumulator (LDA) instruction. data written into memory with store accumulator (STA) instruction. Various addressing mode variations allow great deal flexibility specifying memory location involved load store instruction. Exchange instructions allow values exchanged between high (SHA) also between (SLA). Arithmetic, shift, logical operations performed value ADD, SUB, RORA, INCA, DECA, AND, ORA, EOR, etc. some these instructions, such INCA LSLA, value only input operand result replaces value other cases, such AND, there operands: value second value from memory. result arithmetic logical operation replaces value Some instructions, such memory-to-memory move instructions (MOV), accumulator. DBNZ also relieves because allows loop counter implemented memory variable rather than accumulator. During reset, accumulator loaded with $00.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
8.2.2
Program Counter (PC)
program counter 14-bit register that contains address next instruction operand fetched. During normal execution, program counter automatically increments next sequential memory location each time instruction operand fetched. Jump, branch, return operations load program counter with address other than that next sequential location. This called change-of-flow. During reset, program counter loaded with $3FFD program will start execution from this specific location.
8.2.3
Shadow Program Counter (SPC)
shadow program counter 14-bit register. During subroutine call using either instruction, return address will saved into SPC. Upon completion subroutine, instruction will restore content program counter from shadow program counter. During reset, shadow program counter loaded with $3FFD.
8.2.4
Condition Code Register (CCR)
2-bit condition code register contains status flags. content RS08 directly readable. bits tested using conditional branch instructions such BEQ. These register bits directly accessible through interface. following paragraphs provide detailed information about bits they used. Figure identifies bits their positions.
CONDITION CODE REGISTER
CARRY ZERO
Figure 8-3. Condition Code Register (CCR)
status bits cleared after reset. status bits indicate results arithmetic other instructions. Conditional branch instructions will either branch program location allow program continue next instruction after branch, depending values status bit. Conditional branch instructions, such BCC, BCS, BNE, cause branch depending state single bit. Often, conditional branch immediately follows instruction that caused bit(s) updated, this sequence:
deca lower ;compare accumulator ;branch smaller this higher than same
more: lower:
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Other instructions executed between test conditional branch long only instructions used those which disturb bits that affect conditional branch. instance, test performed subroutine function conditional branch executed until subroutine returned main program. This form parameter passing (that information returned calling program condition code bits). Zero Flag indicate result operation $00. Branch equal (BEQ) branch equal (BNE) simple branches that branch based solely value bit. load, store, move, arithmetic, logical, shift, rotate instructions cause updated. Carry After addition operation, source operands were both greater than equal operands greater than equal result less than $80. This equivalent unsigned overflow. subtract compare performs subtraction memory operand from contents register after subtract operation, unsigned value memory operand greater than unsigned value register. This equivalent unsigned borrow underflow. Branch carry clear (BCC) branch carry (BCS) branches that branch based solely value bit. also used unsigned branches BHS. Add, subtract, shift, rotate instructions cause updated. branch (BRSET) branch clear (BRCLR) instructions copy tested into facilitate efficient serial-to-parallel conversion algorithms. carry (SEC) clear carry (CLC) allow carry cleared directly. This useful combination with shift rotate instructions routines that pass status information back main program, from subroutine, bit. included shift rotate operations those operations easily extended multi-byte operands. shift rotate operations considered 9-bit shifts that include 8-bit operand register carry CCR. After logical shift, holds that shifted 8-bit operand. rotate instruction used next, this shifted into operand rotate, that gets shifted other operand replaces value used subsequent rotate instructions.
8.2.5
Indexed Data Register (D[X])
This 8-bit indexed data register allows user access data direct page address space indexed This register resides memory mapped location $000E. details D[X] register, please refer Section 8.3.8, "Indexed Addressing Mode (IX, Implemented Pseudo Instructions)."
8.2.6
Index Register
This 8-bit index register allows user index address location direct page address space. This register resides memory mapped location $000F. details register, please refer Section 8.3.8, "Indexed Addressing Mode (IX, Implemented Pseudo Instructions)."
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
8.2.7
Page Select Register (PAGESEL)
This 8-bit page select register allows user access memory locations entire 16K-byte address space through page window located from $00C0 $00FF. This register resides memory mapped location $001F. details PAGESEL register, please refer RS08 Core Reference Manual.
Addressing Modes
Whenever reads information from memory writes information into memory, addressing mode used determine exact address where information read from written This section explains several addressing modes each useful different programming situations. Every opcode tells perform certain operation certain way. Many instructions, such load accumulator (LDA), allow several different ways specify memory location operated each addressing mode variation requires separate opcode. these variations same instruction mnemonic, assembler knows which opcode based syntax location operand field. some cases, special characters used indicate specific addressing mode (such [pound] symbol, which indicates immediate addressing mode). other cases, value operand tells assembler which addressing mode use. example, assembler chooses short addressing mode instead direct addressing mode operand address from $0000 $001F. Besides allowing assembler choose addressing mode based operand address, assembler directives also used force direct tiny/short addressing mode using prefix before operand, respectively. Some instructions more than addressing mode. example, move instructions addressing mode access source value from memory second addressing mode access destination memory location. these move instructions, both addressing modes listed documentation. branch instructions relative (REL) addressing mode determine destination branch, BRCLR, BRSET, CBEQ, DBNZ also must access memory operand. These instructions classified addressing mode used memory operand, relative addressing mode branch offset assumed. discussion following paragraphs includes each addressing mode works syntax clues that instruct assembler specific addressing mode.
8.3.1
Inherent Addressing Mode (INH)
This addressing mode used when inherently knows everything needs complete instruction addressing information supplied source code. Usually, operands that needs located CPU's internal registers, LSLA, CLRA, INCA, SLA, RTS, others. inherent instructions, including operation (NOP) background (BGND), have operands.
8.3.2
Relative Addressing Mode (REL)
Relative addressing mode used specify offset address branch instructions relative program counter. Typically, programmer specifies destination with program label expression
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
operand field branch instruction; assembler calculates difference between location counter (which points next address after branch instruction time) address represented label expression operand field. This difference called offset 8-bit two's complement number. assembler stores this offset object code branch instruction. During execution, evaluates condition that controls branch. branch condition true, sign-extends offset 14-bit value, adds offset current uses this address where will fetch next instruction continue execution rather than continuing execution with next instruction after branch. Because offset 8-bit two's complement value, destination must within range -128 +127 locations from address that follows last byte object code branch instruction. common method create simple infinite loop branch instruction that branches itself. This sometimes used short code segments during debug. Typically, this infinite loop, debug host (through background commands) stop program, examine registers memory, start execution from location. This construct used normal application programs except case where program detected error wants force watchdog timer timeout. (The branch infinite loop executes repeatedly until watchdog timer eventually causes reset.)
8.3.3
Immediate Addressing Mode (IMM)
this addressing mode, operand located immediately after opcode instruction stream. This addressing mode used when programmer wants explicit value that known time program written. (pound) symbol used tell assembler operand data value rather than address where desired value should accessed. size immediate operand always bits. assembler automatically will truncate extend operand needed match size needed instruction. Most assemblers generate warning 16-bit operand provided. programmer's responsibility symbol tell assembler when immediate addressing should used. assembler does consider error leave symbol because resulting statement still valid instruction (although mean something different than programmer intended).
8.3.4
Tiny Addressing Mode (TNY)
addressing mode capable addressing only first bytes address map, from $0000 $000F. This addressing mode available INC, DEC, ADD, instructions. system optimized placing most computation-intensive data this area memory. Because 4-bit address embedded opcode, only least significant four bits address must included instruction; this saves program space execution time. During execution, adds high-order 4-bit operand address uses combined 14-bit address ($000x) access intended operand.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
8.3.5
Short Addressing Mode (SRT)
addressing mode capable addressing only first bytes address map, from $0000 $001F. This addressing mode available CLR, LDA, instructions. system optimized placing most computation-intensive data this area memory. Because 5-bit address embedded opcode, only least significant five bits address must included instruction; this saves program space execution time. During execution, adds nine high-order 5-bit operand address uses combined 14-bit address ($000x $001x) access intended operand.
8.3.6
Direct Addressing Mode (DIR)
addressing mode used access operands located direct address space ($0000 through $00FF). During execution, adds high-order byte direct address operand that follows opcode. uses combined 14-bit address ($00xx) access intended operand.
8.3.7
Extended Addressing Mode (EXT)
extended addressing mode, 14-bit address operand included object code low-order bits next bytes after opcode. This addressing mode only used instructions jump destination address RS08 MCUs.
8.3.8
Indexed Addressing Mode (IX, Implemented Pseudo Instructions)
Indexed addressing mode sometimes called indirect addressing mode because index register used reference access intended operand. important feature indexed addressing mode that operand address computed during execution based current contents index register located $000F memory rather than being constant address location that determined during program assembly. This allows writing program that accesses different operand locations depending results earlier program instructions (rather than accessing location that determined when program written). index addressing mode supported RS08 Family uses register located $000F index D[X] register located $000E indexed data register. programming index register location direct page read/written indexed data register D[X]. These pseudo instructions used with instructions supporting direct, short, tiny addressing modes using D[X] operand.
Special Operations
Most what does described instruction set, special operations must considered, such starts beginning application program after power first applied. After program begins running, current instruction normally determines what will next. exceptional events cause temporarily suspend normal program execution:
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Reset events force start over beginning application program, which forces execution start $3FFD. host development system cause active background mode rather than continuing next instruction application program.
8.4.1
Reset Sequence
Processing begins trailing edge reset event. number things that cause reset events vary slightly from RS08 derivative another; however, most common sources are: power-on reset, external RESET pin, low-voltage reset, watchdog timeout, illegal opcode detect, illegal address access. more information about recognizes reset events determines difference between internal external causes, refer Resets Interrupts chapter. Reset events force immediately stop what doing begin responding reset. instruction that process will aborted immediately without completing remaining clock cycles. short sequence activities completed decide whether source reset internal external record cause reset. remainder time, reset source remains active internal clocks stopped save power. trailing edge reset event, clocks resume exits from reset condition. program counter reset $3FFD instruction fetch will started after release reset. device execute code from on-chip memory starting from $3FFD after reset, care should taken force BKDG reset because this will force device into active background mode where will wait command from background communication interface.
8.4.2
Interrupts
interrupt mechanism RS08 used interrupt normal flow instructions; used wake RS08 from wait stop modes. mode, interrupt events must polled CPU. interrupt feature compatible with Freescale's HC05, HC08, HCS08 Families.
8.4.3
Wait Stop Mode
Wait stop modes entered executing WAIT STOP instruction, respectively. these modes, clocks shut down save power activity suspended. remains this low-power state until interrupt reset event wakes Please refer Resets Interrupts chapter effects wait stop other device peripherals.
8.4.4
Active Background Mode
Active background mode refers condition which stopped executing user program instructions waiting serial commands from background debug system. Refer Development Support chapter detailed information active background mode. arithmetic left shift pseudo instruction also available because operation identical logical shift left.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Summary Instruction Table
Instruction Summary Nomenclature nomenclature listed here used instruction descriptions Table through Table 8-2. Operators
Contents register memory location shown inside parentheses loaded with (read: "gets") Exchange with Boolean Boolean Boolean exclusive-OR Concatenate Accumulator Condition code register Program counter Program counter, higher order (most significant) bits Program counter, lower order (least significant) eight bits Shadow program counter Shadow program counter, higher order (most significant) bits Shadow program counter, lower order (least significant) eight bits
registers SPCH SPCL
Memory addressing memory location absolute data, depending addressing mode relative offset, which two's complement number stored last byte machine code corresponding branch instruction Pseudo index register, memory location $000F D[X] Memory location $000E pointing memory location defined pseudo index register (location $000F) Condition code register (CCR) bits Zero indicator Carry/borrow activity notation affected forced forced cleared according results operation Undefined after operation Machine coding notation
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Source form
Low-order eight bits direct address $0000-$00FF (high byte assumed $00) byte immediate data High-order 6-bit 14-bit extended address prefixed with 2-bit Low-order byte 14-bit extended address Relative offset
Everything source forms columns, except expressions italic characters, literal information which must appear assembly source file exactly shown. initial 5-letter mnemonic always literal expression. commas, pound signs (#), parentheses, plus signs literal characters. label expression that evaluates single integer range 0-7. label expression that evaluates single hexadecimal integer range $0-$F. opr8i label expression that evaluates 8-bit immediate value. opr4a label expression that evaluates Tiny address (4-bit value). instruction treats this 4-bit value order four bits address 16-Kbyte address space ($0000-$000F). This 4-bit value embedded order four bits opcode. opr5a label expression that evaluates Short address (5-bit value). instruction treats this 5-bit value order five bits address 16-Kbyte address space ($0000-$001F). This 5-bit value embedded order bits opcode. opr8a label expression that evaluates 8-bit value. instruction treats this 8-bit value order eight bits address 16-Kbyte address space ($0000-$00FF). opr16a label expression that evaluates 14-bit value. RS08 core, upper bits always instruction treats this value address 16-Kbyte address space. label expression that refers address that within -128 +127 locations from next address after last byte object code current instruction. assembler will calculate 8-bit signed offset include object code this instruction. Address modes Inherent operands) Immediate Direct instruction) Immediate Direct Direct instruction) Direct Short Tiny Extended 8-bit relative offset
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Summary (Sheet
Source Form
#opr8i opr8a #opr8i opr8a opr4a #opr8i opr8a ASLA(1)
Description
Operation
Effect
Operand
Address Mode
Opcode
with Carry
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
without Carry
Logical
Arithmetic Shift Left Branch Carry Clear
(PC) $0002 rel,
BCLR n,opr8a
BCLR n,D[X]
Clear Memory
BCLR
BGND
Branch Carry (Same BLO) Branch Equal Background Branch Higher Same (Same BCC) Branch Lower (Same BCS) Branch Equal Branch Always Branch Never
(PC) $0002 rel, (PC) $0002 rel, Enter Background Debug Mode (PC) $0002 rel, (PC) $0002 rel, (PC) $0002 rel, (PC) $0002 (PC) $0002
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Summary (Sheet
Source Form Effect Operand
Address Mode
Opcode
Description
Operation
BRCLR n,opr8a,rel
BRCLR n,D[X],rel
Branch Memory Clear
(PC) $0003 rel, (Mn)
BRCLR n,X,rel
BRSET n,opr8a,rel
BRSET n,D[X],rel
Branch Memory
(PC) $0003 rel, (Mn)
BRSET n,X,rel
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Summary (Sheet
Source Form Effect Operand
Address Mode
Opcode
Description
Operation
BSET n,opr8a
BSET n,D[X]
Memory
BSET
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
CBEQA #opr8i,rel CBEQ opr8a,rel CBEQ ,X,rel (1),(2) CBEQ X,rel opr8a opr5a CLRA CLRX #opr8i opr8a COMA
Branch Subroutine
(PC) Push shadow (PC) (PC) $0003 rel, (PC) $0003 rel, (PC) $0003 rel,
Compare Branch Equal Clear Carry
Clear
Compare Accumulator with Memory Complement (One's Complement)
DBNZ opr8a,rel DBNZ ,X,rel DBNZA DBNZX opr8a opr4a DECA #opr8i opr8a
(PC) $0003 (result) DBNZ direct Decrement Branch (PC) $0002 (result) Zero DBNZA (PC) $0003 (result) Decrement
Exclusive Memory with Accumulator
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Summary (Sheet
Source Form
opr8a opr4a INCA INCX opr16a opr16a #opr8i opr8a opr5a
Description
Operation
Effect
Operand
Address Mode
Opcode
Increment
Effective Address (PC) Push shadow Effective Address
Jump Jump Subroutine
Cx/Dx
Load Accumulator from Memory Load Index Register from Memory
#opr8i opr8a LSLA
Logical Shift Left
LSRA
Logical Shift Right
IX/DIR DIR/IX IMM/IX
opr8a,opr8a #opr8i,opr8a D[X],opr8a opr8a,D[X] #opr8i,D[X] #opr8i opr8a ROLA
Move
(M)destination (M)source None
Operation Inclusive Accumulator Memory
Rotate Left through Carry
RORA
Rotate Right through Carry Return from Subroutine Subtract with Carry Carry Swap Shadow High with Swap Shadow with Store Accumulator Memory
#opr8i opr8a opr8a opr5a
Pull from shadow SPCH SPCL
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Summary (Sheet
Source Form
opr8a STOP #opr8i opr8a opr4a TAX(1) opr8a TSTA TSTX TXA(1) WAIT
Description
Store Index Register Memory into stop mode
Operation
Effect
Operand
Address Mode
Opcode
Subtract
Transfer Test Zero Transfer into WAIT mode
This pseudo instruction supported normal RS08 instruction set. This instruction different from that HC08 HCS08 that RS08 does auto-increment index register.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Cycles
Chapter Central Processor Unit (RS08CPUV1)
Table 8-2. Opcode
HIGH DIR/REL IMM/INH DIR/EXT
BRSET0 BSET0
BRCLR0 BCLR0
CBEQ
CBEQA
BRSET1 BSET1
BRCLR1 BCLR1
COMA
BRSET2 BSET2
LSRA
BRCLR2 BCLR2
BRSET3 BSET3
RORA
BRCLR3 BCLR3
BRSET4 BSET4
LSLA
BRCLR4 BCLR4
ROLA
BRSET5 BSET5
DECA
BRCLR5 BCLR5
DBNZ
DBNZA
BRSET6 BSET6
INCA
BRCLR6 BCLR6
BRSET7 BSET7
STOP
BRCLR7 BCLR7
Inherent Immediate Direct Extended Direct-Direct
CLRA
WAIT
BGND
Relative Short Tiny Immediate-Direct
High Byte Opcode Hexadecimal
Gray decoded illegal instruction Byte Opcode Hexadecimal
RS08 Cycles Opcode Mnemonic Number Bytes Addressing Mode
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Internal Clock Source (RS08ICSV1)
Introduction
internal clock source (ICS) module provides clock source choices MCU. module contains frequency-locked loop (FLL) clock source that controllable internal reference clock. module provide this clock internal reference clock source system clock, ICSOUT. Whichever clock source chosen, ICSOUT passed through clock divider (BDIV), which allows lower final output clock frequency derived. ICSOUT times frequency. Figure shows MC9RS08KA2 Series block diagram with highlighted.
RS08 CORE 5-BIT KEYBOARD INTERRUPT MODULE (KBI)
ACMP+ TCLK ACMPO RS08 SYSTEM CONTROL RESET STOP WAKEUP MODES OPERATION POWER MANAGEMENT WAKEUP ANALOG COMPARATOR MODULE (ACMP) ACMP-
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP- PTA2/KBIP2/TCLK/RESET/VPP (1),( PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1),
MODULO TIMER MODULE (MTIM)
USER FLASH MC9RS08KA2 2048 BYTES MC9RS08KA1 1024 BYTES
USER BYTES
INTERNAL CLOCK SOURCE (ICS)
POWER INTERNAL REGULATOR
NOTES: Pins software configurable with pullup/pulldown device input port. Integrated pullup device enabled reset enabled (RSTPE=1). These pins available 6-pin package
Figure 9-1. MC9RS08KA2 Series Block Diagram Highlighting Block Pins
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
Introduction
internal clock source (ICS) module provides clock source choices MCU. module contains frequency-locked loop (FLL) clock source that controllable internal reference clock. module provide this clock internal reference clock source system clock, ICSOUT. Whichever clock source chosen, ICSOUT passed through clock divider (BDIV) which allows lower final output clock frequency derived. ICSOUT times frequency.
9.2.1
Features
features module are: Frequency-locked loop (FLL) trimmable accuracy 0.2% resolution using internal reference deviation over voltage temperature using internal reference output times internal reference frequency Internal reference clock trim bits available Internal reference clock selected clock source Whichever clock selected source divided down select clock divider provided (allowable dividers are: engaged internal mode automatically selected reset
9.2.2
Modes Operation
There four modes operation ICS: FEI, FBI, FBILP, stop.
9.2.2.1
Engaged Internal (FEI)
engaged internal mode, which default mode, supplies clock derived from which controlled internal reference clock.
9.2.2.2
Bypassed Internal (FBI)
bypassed internal mode, enabled controlled internal reference clock, bypassed. supplies clock derived from internal reference clock.
9.2.2.3
Bypassed Internal Power (FBILP)
bypassed internal power mode, disabled bypassed, supplies clock derived from internal reference clock.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
9.2.2.4
Stop (STOP)
stop mode, disabled internal reference clocks selected enabled disabled. does provide clock source.
9.2.3
Block Diagram
IREFSTEN ICSIRCLK CLKS
Internal Reference Clock
Figure shows block diagram.
BDIV
n=0-3
ICSOUT1
kHz)
TRIM DCOOUT ICSIRCLK ICSFFCLK
Filter
ICSOUT
times frequency
Figure 9-2. Internal Clock Source (ICS) Block Diagram
External Signal Description
signal connects chip.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
Register Definition
Table 9-1. Register Summary
Name ICSC1 ICSC2 BDIV
Table summary registers.
CLKS
IREFSTEN
ICSTRM ICSSC
TRIM CLKST FTRIM
9.4.1
Control Register (ICSC1)
Reset:
CLKS Unimplemented
IREFSTEN
Figure 9-3. Control Register (ICSC1) Table 9-2. ICSC1 Field Descriptions
Field CLKS Description Clock Source Select Selects clock source that controls frequency. actual frequency depends value BDIV bits. Output selected Internal reference clock selected Internal Reference Stop Enable Controls whether internal reference clock remains enabled when enters stop mode. Internal reference clock remains enabled stop Internal reference clock disabled stop
IREFSTEN
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
9.4.2
Control Register (ICSC2)
BDIV Reset: Unimplemented
Figure 9-4. Control Register (ICSC2) Table 9-3. ICSC2 Field Descriptions
Field BDIV Description Frequency Divider Selects amount divide down clock source selected CLKS bit. This controls frequency. Encoding Divides selected clock Encoding Divides selected clock (reset default) Encoding Divides selected clock Encoding Divides selected clock Power Select Controls whether disabled bypassed modes. disabled bypass modes disabled bypass mode
9.4.3
Trim Register (ICSTRM)
TRIM POR: Reset:
Figure 9-5. Trim Register (ICSTRM) Table 9-4. ICSTRM Field Descriptions
Field TRIM Description Trim Setting TRIM bits control internal reference clock frequency controlling internal reference clock period. bits' effect binary weighted (i.e., will adjust twice much Increasing binary value TRIM will increase period, decreasing value will decrease period. additional fine trim available ICSSC FTRIM bit.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
9.4.4
Status Control (ICSSC)
POR: Reset:
CLKST
FTRIM
Unimplemented
Figure 9-6. Status Control Register (ICSSC) Table 9-5. ICSSC Field Descriptions
Field CLKST Description Clock Mode Status CLKST read-only indicate current clock mode. CLKST does update immediately after write CLKS internal synchronization between clock domains. Output selected Internal reference clock selected Fine Trim FTRIM controls smallest adjustment internal reference clock frequency. Setting FTRIM will increase period clearing FTRIM will decrease period smallest amount possible.
FTRIM
9.5.1
Functional Description
Operational Modes
states shown state diagram described this section. arrows indicate allowed movements between states.
CLKS=1 LP=0 Bypassed Internal (FBI) CLKS=1 LP=1 Bypassed Internal Power(FBILP)
CLKS=0 Engaged Internal (FEI)
Stop1,
enters Stop state when enters stop, always disabled. returns state that active before entered stop, unless reset occurs while stop. IREFSTEN when enters stop, ICSIRCLK remains running.
Figure 9-7. Clock Switching Modes
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
9.5.1.1
Engaged Internal (FEI)
engaged internal (FEI) default mode operation reset entered when CLKS written engaged internal mode, ICSOUT clock derived from clock, which controlled internal reference clock. loop will lock frequency times filter frequency.
9.5.1.2
Bypassed Internal (FBI)
bypassed internal (FBI) mode entered when CLKS written bypassed internal mode, ICSOUT clock derived from internal reference clock. clock controlled internal reference clock, loop will lock frequency times filter frequency.
9.5.1.3
Bypassed Internal Power (FBILP)
bypassed internal power (FBILP) mode entered when CLKS written bypassed internal power mode, ICSOUT clock derived from internal reference clock disabled.
9.5.1.4
Stop
stop mode entered whenever enters stop. this mode, clocks stopped except ICSIRCLK which will remaining running IREFSTEN written When interrupted from stop, will back operating mode that running when entered stop. internal reference running stop (IREFSTEN will take some time, tir_wu, internal reference wakeup. internal reference already running stop (IREFSTEN entering into will take some time, tfll_wu, return previous acquired frequency.
9.5.2
Mode Switching
When changing from FBILP either FBI, anytime trim value written, user should wait acquisition time, tacquire, before will guaranteed desired frequency.
9.5.3
Frequency Divider
BDIV bits changed anytime actual switch frequency will occur immediately.
9.5.4
Power Usage
power (LP) provided allow disabled thus conserve power when being used. However, some applications desirable enable allow lock
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Internal Clock Source (RS08ICSV1)
maximum accuracy before switching engaged mode. disabled bypass mode when
9.5.5
Internal Reference Clock
ICSIRCLK frequency re-targeted trimming period internal reference clock. This done writing value TRIM bits ICSTRM register. Writing larger value will slow down ICSIRCLK frequency, writing smaller value ICSTRM register will speed ICSIRCLK frequency. TRIM bits will affect ICSOUT frequency engaged internal (FEI), bypassed internal (FBI), bypassed internal power (FBILP) mode. TRIM FTRIM values will affected reset. stop, LVDE LVDSE bits SPMSC1 must both before entering stop. Until ICSIRCLK trimmed, ICSOUT frequencies exceed maximum chip-level frequency violate chip-level clock timing specifications (see Device Overview chapter). BDIV reset divide prevent frequency from exceeding maximum. user should trim device allowable frequency before changing BDIV divide operation.
9.5.6
Fixed Frequency Clock
provides ICSFFCLK output which used additional clock source peripheral such timer, when FEI. ICSFFCLK valid clock source peripheral when either FBILP modes. ICSFFCLK ICSRCLK divided two.
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Chapter Analog Comparator (RS08ACMPV1)
10.1 Introduction
analog comparator module (ACMP) provides circuit comparing analog input voltages comparing analog input voltage internal reference voltage. comparator circuit designed operate across full range supply voltage (rail rail operation). Figure 10-1 shows MC9RS08KA2 Series block diagram with ACMP highlighted.
RS08 CORE 5-BIT KEYBOARD INTERRUPT MODULE (KBI)
ACMP+ TCLK ACMPO RS08 SYSTEM CONTROL RESET STOP WAKEUP MODES OPERATION POWER MANAGEMENT WAKEUP ANALOG COMPARATOR MODULE (ACMP) ACMP-
PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP- PTA2/KBIP2/TCLK/RESET/VPP (1),( PTA3/ACMPO/BKGD/MS PTA4/KBIP4 (1),(3) PTA5/KBIP5 (1),
MODULO TIMER MODULE (MTIM)
USER FLASH MC9RS08KA2 2048 BYTES MC9RS08KA1 1024 BYTES
USER BYTES
INTERNAL CLOCK SOURCE (ICS)
POWER INTERNAL REGULATOR
NOTES: Pins software configurable with pullup/pulldown device input port. Integrated pullup device enabled reset enabled (RSTPE=1). These pins available 6-pin package
Figure 10-1. MC9RS08KA2 Series Block Diagram Highlighting ACMP Block Pins
MC9RS08KA2 Series Data Sheet, Rev. Freescale Semiconductor
Analog Comparator (RS08ACMPV1)
10.1.1
Features
ACMP following features: Full rail-to-rail supply operation Less than input offset Less than hysteresis Selectable interrupt rising edge, falling edge, either rising falling edges comparator output Option compare fixed internal bandgap reference voltage Option allow comparator output visible pin, ACMPO Remains
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