XRT8000 FEATURES Clock Adaptation Most Popular Telecommunication

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XRT8000 FEATURES Clock Adaptation Most Popular Telecommunication

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Clock Synchronizer/Adapter Communications
XRT8000
FEATURES Clock Adaptation Most Popular Telecommunication Frequencies Wide Input Frequency Range Programmable Output Frequencies Less than 0.05UI Wide Band Output Jitter Power Operation 3.3V) Maximum Lock Time 45mS GENERAL DESCRIPTION XRT8000 dual phase-locked loop chip that generates simultaneous, very jitter, output clocks synchronization applications wide area networking systems. outputs phase locked input signal. chip four basic modes operation; referred master (FORWARD, REVERSE) slave (FORWARD, REVERSE) modes (See Figure FORWARD mode accepts 16th harmonic either 1.544MHz 2.048MHz input reference generates 1.2kHz multiples 2.4kHz, 56kHz 64kHz. REVERSE mode input clock 56kHz 64kHz used ORDERING INFORMATION
Part XRT8000IP XRT8000ID Package Lead PDIP Lead JEDEC SOIC Operating Temperature Range -40°C +85°C -40°C +85°C
Cascadable External Components Needed Lock Detect Indication APPLICATIONS DSU's, CSU's Access Equipment ISDN Terminals Concentrators Multiplexers
generate 1.544MHz 2.048MHz output clocks. SLAVE (FORWARD, REVERSE) modes generate same output frequencies MASTER (FORWARD/ REVERSE MODES) except that input frequency (FIN) 8kHz. optional divide eight enabled each outputs. input output frequency selection done through serial microprocessor interface. XRT8000 available either SOIC package plastic DIP.
XRT8000 CLK2 1.544{T1} 2.048{E1} CLK1 56kHz 64kHz 1.2kHz 43.2kHz SYNC 8kHz 56kHz 64kHz
XRT8000 CLK2 CLK1
XRT8000
(1.544) (2.048) SYNC 8kHz
CLK2 CLK1
SYNC
MASTER FORWARD
MASTER REVERSE
SLAVE FORWARD/REVERSE
Figure System Diagram
Rev.1.11
E1999-2006 EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017 www.exar.com
XRT8000
BLOCK DIAGRAM
Analog PhaseLocked Loop
Post Divider
Div.
Driver
CLK2
Feedback Divider
DIV/8_EN
Lock Detector
LOCKDET SYNC
Input Divider
Analog PhaseLocked Loop
Post Divider
Div.
Driver
CLK1
100K
100K
Feedback Divider DIV/8_EN
SCLK
Serial Interface
Mode Frequency Select Control
Figure Block Diagram
Rev. 1.11
XRT8000
CONFIGURATION
SYNC CLK1
SCLK CLK2 LOCKDET
SYNC CLK1
SCLK CLK2 LOCKDET
Lead PDIP (0.300")
Lead SOIC (Jedec, 0.300")
DESCRIPTION
Symbol SYNC CLK1 Pin# Type Description Serial Data Output (Microprocessor Serial Interface). Data output from command registers. 8kHz Signal SubDivided From FIN. This output threestated CR5. SYNC used synchronize other XRT8000 which configured slave modes. Reference Frequency Input. Digital Ground. Digital Ground. Clock Output phase-locked loop Digital Positive Power Supply. Master/Slave Mode Select Input. this input high, then MASTER mode selected. this input low, then SLAVE mode enabled. This internally pulled 100KW resistor. Analog Ground. Analog Positive Supply. Lock Detect. This output high when both phase-locked loops lock will either phase locked loops loses lock. Digital Positive Power Supply. Clock Output phase-locked loop Digital Ground. Digital Positive Power Supply. Serial Data Input (Microprocessor Serial Interface) Data input command registers. Chip Select (Microprocessor Serial Interface) When this input data will shifted appropriate registers. Internal pull (100K). Serial Clock Input (Microprocessor Serial Interface) This clock will serve reference data streams (the positive edge SCLK used latch data).
LOCKDET CLK2 SCLK
Rev. 1.11
XRT8000
ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C 85_C Test Conditions: 25_C, 5.0V Unless Otherwise Specified
Symbol Parameter Input level Input high level Output level (CLK1,CLK2) Output high level (CLK1,CLK2) Output level (LOCKDET,SYNC) Output high level (LOCKDET,SYNC) Input current (CSB,MSB) Input high current (CSB,MSB) Input current (except CSB,MSB) Input high current (except CSB,MSB) Operating current Input pull-up resistance (CSB,MSB) -150 Unit Conditions
-6.0 -3.0 load. Clock
ELECTRICAL CHARACTERISTICS (See Figure
Symbol T112 Parameter Input frequency Minimum input signal high duration Output frequency Duty cycle CLK1, CLK2 Jitter added 8KHz-40KHz Jitter added 10Hz-40KHz Broad Band-jitter Jitter added 20Hz-100KHz Jitter added 18kHz-100KHz Capture time Clock output rise time Clock output fall time Duty cycle SYNC Spec.3 0.008 47.5 0.025 0.025 0.05 32.7 Unit Conditions
0.007 0.022 0.03 0.05 0.01
52.5 0.02 0.05 0.07 0.03
VCC/2 switch point. 30pF load. Output =1.544MHz Output =1.544MHz Output =1.544MHz Output =2.048MHz Output =2.048MHz 30pF load. Measured 20/80 30pF load. Measured 20/80 VCC/2 switch point master forward mode). 30pF load. table values
Delay time between rising edge SYNC rising edge CLK1 CLK2
T-20
T+20
Notes:
Specifications from AT&T Publication 62411 ITU-T Recommendations G-823 (for 1.544MHz 2.048MHz, respectively). guaranteed characterization, tested. Specifications subject change without notice. Rev. 1.11
XRT8000
ELECTRICAL CHARACTERISTICS (Except Serial Interface) Operating Temperature: -40_C 85_C Test Conditions: 25_C, 3.3V Unless Otherwise Specified
Symbol Input level Input high level Output level (CLK1,CLK2) Output high level (CLK1,CLK2) Output level (LOCKDET,SYNC) Output high level (LOCKDET,SYNC) Input current (CSB,MSB) Input high current (CSB,MSB) Input current (except CSB,MSB) Input high current (except CSB,MSB) Operating current Input pull-up resistance (CSB,MSB) -150 Parameter Unit load. Clock -2.5 Conditions
ELECTRICAL CHARACTERISTICS (See Figure
Symbol T112 Parameter Input frequency Minimum input signal high duration Output frequency Duty cycle CLK1, CLK2 Jitter added 8KHz-40KHz Jitter added 10Hz-40KHz Broad Band Jitter added 20Hz-100KHz Jitter added 18kHz-100KHz Capture time Clock output rise time Clock output fall time Duty cycle SYNC 0.025 0.025 0.05 Spec.3 0.008 47.5 0.01 0.030 0.035 0.045 0.010 0.05 0.07 0.03 52.5 0.02 32.7 Unit 30pF load. Measured 20/80 30pF load. Measured 20/80 VCC/2 switch point master forward mode). 30pF load. Notes:
Conditions
VCC/2 switch point. 30pF load. Output =1.544MHz Output =1.544MHz Output =1.544MHz Output =2.048MHz Output =2.048MHz
Delay time between SYNC CLK1 CLK2
T-20
T+20
table values
Specifications from AT&T Publication 62411 ITUT Rcommendations G-823 (for 1.544MHz 2.048MHz, respectively) guaranteed characterization, tested. Specifications subject change without notice. Rev. 1.11
XRT8000
ELECTRICAL CHARACTERISTICS (See Figure
Symbol Parameter SCLK Setup Time SCLK Hold Time SCLK Setup Time SCLK Hold Time SCLK Time SCLK High Time SCLK Period SCLK Hold Time Inactive Time SCLK Valid SCLK SDOx Delay SCLK Edge Edge Rise/Fall Time Output Min. Typ. Max. Unit Conditions
Electrical Characteristics (See Figure
Specifications subject change without notice
ABSOLUTE MAXIMUM RATINGS Supply Range Voltage GND0.3V +0.3V
Operating Temperature 40°C +85°C Storage Temperature 40°C +150°C Package Dissipation 500mW
CLK1 CLK2
SYNC
Figure Clocks Timing
Rev. 1.11
XRT8000
SYSTEM DESCRIPTION power clock outputs XRT8000 will tri-stated. This means that clocks will seen outputs lock detect output will low. After power XRT8000 needs initialized. Therefore serial interface provided load internal registers. These registers will define modes operation, output frequencies enabling clock outputs. Master/Forward Mode Operation When XRT8000 device operating "Master/Forward" Mode, will receive either 2.048 MHz" 1.544 MHz" clock signal input (pin3); where range from From this input signal, XRT8000 device will internally divide synthesize following signals. CLK1 and/or CLK2 output pins: kHz)/8 kHz)/8 where range from SYNC Output pin: 8kHz user selects configures XRT8000 device generate these clock frequencies writing appropriate values into Command Registers (CR1, CR2, CR3, CR5), Microprocessor Serial Interface. Reverse Mode Operation When XRT8000 device operating "Reverse" Mode, will receive either clock signal Slave (Forward, Reverse) Mode Operation activate slave modes operations input must tied low. these modes 8kHz signal must applied input order obtain output frequencies rates. output frequencies selected serial interface similar fashion described master forward reverse modes. Lock Detect Output both PLL's enabled locked state then LOCKDET will active. loses lock then LOCKDET will false. only enabled then only active will control state LOCKDET. input. From this input signal, XRT8000 device will synthesize following clock signal frequencies. CLK1 and/or CLK2 output pins: 1.544 2.048 1.544 MHz/8 2.048 MHz/8 SYNC output pin: user configure XRT8000 device generate these clock frequencies writing appropriate values into Command Registers (CR1, CR2, CR3, CR5), Microprocessor Serial Interface. Note: REVERSE mode contents one's.
Rev. 1.11
XRT8000
Command Registers Between input Command Registers, user configure XRT8000 device into operating modes that have been described this data sheet. user access these Command Registers
AD2~0 Register IOC4 SEL14 SEL24 SYNCEN Reserved Reserved Reserved IOC3 SEL13 SEL23 CLK1EN Reserved Reserved Reserved
Microprocessor Serial Interface. Table presents Address Location Format each Command Registers, within XRT8000 device.
IOC2 SEL12 SEL22 CLK2EN Reserved Reserved Reserved IOC1 SEL11 SEL21 PL2/8 Reserved Reserved Reserved PL1EN PL2EN SEL10 SEL10 PL1/8 Reserved Reserved Reserved
Table Control Registers next pages describe role/functionality each bit-field within Command Registers.
Rev. 1.11
XRT8000
Register (Power State "00000") (PL1EN): Enable control PLL1. PL1EN "1", then PLL1 enabled. Otherwise, PL1EN "0", then PLL1 disabled. D1~D4 (IOC1~IOC4): These four bit-fields function control bits PLL1 PLL2 operation modes. These bits select FORWARD, REVERSE, DATA, Kx56 Kx64 clock rates. Multiplier Kx56 Kx64 refers harmonics 56kHz 64kHz clocks, this notation extended 1,544kHz 2,048kHz frequencies following table (Table
Note: value PLL1 PLL2 independent each other.
Table Table creates values through within command register operating mode XRT8000 device.
Input Freq. [kHz] nx1544 nx1544 nx1544 nx1544 nx1544 nx1544 nx2048 nx2048 nx2048 nx2048 nx2048 nx2048 PLL1 Output [kHz] Kx56 Kx56 Kx64 Kx56 Kx64 DATA 1544 1544 Kx56 Kx56 Kx64 Kx56 Kx64 DATA 1544 2048 PLL2 Output [kHz] Kx56 Kx64 Kx64 DATA DATA DATA 1544 2048 Kx56 Kx64 Kx64 DATA DATA DATA 2048 2048
IOC4
IOC3
IOC2
IOC1
Mode Forward Forward Forward Forward Forward Forward Reverse Reverse Forward Forward Forward Forward Forward Forward Reverse Reverse
Table Operation Mode/Output Clock Frequency Select Options Through Bits within Register
Note:
values selected through bits, within Register (see Table values selected Sel14 through SelP bits within Register (see Table
Rev. 1.11
XRT8000
Register (Power State "00000") (PL2EN): Enable control PLL2. PL2EN "1", then PLL2 enabled. Otherwise, PL2EN "0", PLL2 disabled. D1~D4 (M1~M4): Control bits prescaler divider. These bits will divide ratio prescaler such that MASTER/ FORWARD REVERSE modes output this block always 8kHz. settings M4~M1 bits based input frequency mode operation (which determined state IOC4~IOC1 bits) provided Table
Mode Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Forward Reverse Reverse Input Freq.[kHz] 1x(1544 2048) 2x(1544 2048) 3x(1544 2048) 4x(1544 2048) 5x(1544 2048) 6x(1544 2048) 7x(1544 2048) 8x(1544 2048) 9x(1544 2048) 10x(1544 2048) 11x(1544 2048) 12x(1544 2048) 13x(1544 2048) 14x(1544 2048) 15x(1544 2048) 16x(1544 2048)
Note: This table applies MASTER (FORWARD, REVERSE) mode only
Table Register
Rev. 1.11
XRT8000
Register (Power State "00000") SEL14~SEL10: These bits control parameters: frequency multiplier PLL1, after selecting Kx56, Kx64 DATA mode through register 32),
delay time between rising edge sync output signal (Pin rising edge CLK1 output signals (See Table Table provides settings SEL14~10 bits generate harmonic 56kHz, 64kHz 1.2kHz output PLL1.
PLL1 Output Frequency (kHz) SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 factor Kx56 MODE 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 Kx64 MODE 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 DATA MODE 14.4 16.8 19.2 21.6 26.4 28.8 31.2 33.6 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2
Note: This table applies forward slave modes only
Table Register
Rev. 1.11
XRT8000
Register (Power State "00000") SEL24~SEL20: These bits control frequency multiplier PLL2, after selecting Kx56, Kx64 DATA mode through register 32). Table provides settings SEL24~20 bits generate harmonic 56kHz, 64kHz 1.2kHz output PLL2.
PLL2 Output Frequency (kHz) SEL24~SEL20 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 factor Kx56 MODE 1008 1064 1120 1176 1232 1288 1344 1400 1456 1512 1568 1624 1680 1736 1792 Kx64 MODE 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 DATA MODE 14.4 16.8 19.2 21.6 26.4 28.8 31.2 33.6 38.4 40.8 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2 43.2
Note: This table applies forward slave forward mode only
Table Register
Rev. 1.11
XRT8000
Table presents information delay between rising edge SYNC CLK1 CLKL output signals. important note that this delay behaves function settings within register.
values (nS) SEL14~SEL10 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Kx56 MODE Kx64 MODE
Notes: This table does apply data mode Kx56 mode with divide eight enabled. This table does apply when XRT8000 device operating REVERSE Mode.
Table Delay Time Between SYNC CLK1 CLK2
Rev. 1.11
XRT8000
Register (Power State "00000") PL1/8) Select divider PLL1, PL1/8 CLK1 output frequency divided PL1/8 CLK1 output frequency table PL2/8) Select divider PLL2, PL2/8 CLK2 output frequency divided PL2/8 CLK2 output frequency table CLK2EN) PLL2: Output enable bit, CLK2EN CLK2 output enabled. CLK2EN CLK2 output State CLK1EN) PLL1: Output enable bit, CLK1EN CLK1 output enabled. CLK1EN CLK1 output State SYNCEN) 8kHz SYNC enable bit: SYNCEN SYNC output enabled. SYNCEN SYNC output State Register Register reserved future use.
SCLK
Address
Data
Data
Figure Serial Processor Interface Data Structure
Note: always Low. care. read operation write operation always
SERIAL INTERFACE serial interface simple four wire interface that compatible with many microcontrollers available market. This interface consists following signals:
Rev. 1.11
SCLK
Chip Select (Active Low) Serial Clock Input Serial Data Input Serial Data Output
XRT8000
Using Serial Interface following instructions, using serial interface, best understood referring diagram Figure order serial interface user must first provide clock signal SCLK input pin. Afterwards, user will initiates "Read" "Write" operation asserting active Chip Select Input (CSB). important note that user assert coincident with falling edge SCLK. Once input been asserted type operation target register address must provided user. user will provide this information serial interface writing four serial bits data input. Note: Each these bits will "clocked" into input, rising edge SCLK. These four bits identified described below. (Read/Write) This will clocked into input, first rising edge SCLK (after been asserted). This indicates whether current operation read write operation. this will cause "Read" operation; whereas this will cause "Write" operation. Bits through three address value (A0, These next three rising edges SCLK signal will clock 3-bit address value this particular read write) operation. This address selects command register within XRT8000 device that user will either reading data from, writing data user must supply address bits input pin, ascending order with first. must "don't care"). Once "Read/Write" Address bits have been written, subsequent action depends upon whether current operation "Read" "Write" operation. Read Operation Once last address (A2) been clocked into input, read operation will proceed through idle period, lasting four SCLK periods. falling edge SCLK Cycle (See Figure serial output signal (SDO) becomes active. this point user begin reading data contents addressed command register Address pin. will output this five data word through ascending order, with first, rising edges SCLK pin. Write Operation Once last address (A2) been clocked into input, write operation will proceed through idle period, lasting four SCLK periods. Prior rising edge SCLK Cycle (See Figure user must begin apply eight-bit data word, that he/she wishes write serial input interface onto input pin. microprocessor serial interface will catch value rising edge SCLK. user must apply this word through D7), serially, ascending order with first. Simplified Interface Option user simplify design circuitry connecting serial interface tying both pins together, reading data from and/or writing data this "combined" signal. This simplification possible because only these signals active given time. inactive signal will tri-stated. Notes:
Prior reading data from writing data Serial Interface, user required provide clock signal SCLK. However, shortly before performing read write operations with Serial Interface, user must supply clock signal SCLK input pin. Each Read Write operation, with Serial Interface, will require SCLK periods, depicted Figure Upon completion Read Write cycle, user must negate least 250ns (see timing parameter Characteristics), before asserting again next Read Write operation.
Rev. 1.11
XRT8000
SCLK
SCLK SDOD0 SDOD1 SDOD7
SDI[D7]
Figure Serial Interface Timing
Rev. 1.11
XRT8000
CONFIGURATION DIAGRAMS following figures depict configuration possibilities XRT8000. table left (FIN) lists different possibilities reference clock input, while table right lists possibilities output clocks.
Output Frequencies (kHz) 56)/8 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792 1,024 1,088 1,152 1,216 1,280 1,344 1,408 1,472 1,536 1,600 1,664 1,728 1,792 1,856 1,920 1,984 2,048 64)/8
(1<=n<=16) Reference Freq. (kHz) 1,544 3,088 4,632 6,176 7,720 9,264 10,808 12,352 13,896 15,440 16,984 18,528 20,072 21,616 23,160 24,704 2,048 4,096 6,144 8,192 10,240 12,288 14,336 16,384 18,432 20,480 22,528 24,576 26,624 28,672 30,720 32,768
XRT8000
CLK1 (1<=k<=32) CLK2 SYNC
Figure Master Forward Mode
Rev. 1.11
XRT8000
XRT8000
(1<=n<=16) Output Frequencies (Hz) CLK1 (1<=k<=18) SYNC 2400) 2400)/8 1,200 2,400 4,800 7,200 9,600 12,000 14,400 16,800 19,200 21,600 24,000 26,400 28,800 31,200 33,600 36,000 38,400 40,800 43,200 1,200 1,500 1,800 2,100 2,400 2,700 3,000 3,300 3,600 3,900 4,200 4,500 4,800 5,100 5,400
Reference 1,544 3,088 4,632 6,176 7,720 9,264 10,808 12,352 13,896 15,440 16,984 18,528 20,072 21,616 23,160 24,704
Freq.n (kHz) 2,048 4,096 6,144 8,192 10,240 12,288 14,336 16,384 18,432 20,480 22,528 24,576 26,624 28,672 30,720 32,768 CLK2
Figure Master Forward Mode (Cont'd)
Rev. 1.11
XRT8000
XRT8000
Output CLK1 T1/8 E1/8 CLK2 SYNC 1544 2048 Freq.
Figure Master Reverse Mode
Output Frequencies (kHz) 56)/8 64)/8 1,024 1,088 1,152 1,216 1,280 1,344 1,408 1,472 1,536 1,600 1,664 1,728 1,792 1,856 1,920 1,984 2,048
XRT8000
CLK1 (1<=k<=32) CLK2
SYNC
56)/8 1,008 1,064 1,120 1,176 1,232 1,288 1,344 1,400 1,456 1,512 1,568 1,624 1,680 1,736 1,792
Figure Slave Forward Mode
Rev. 1.11
XRT8000
0.50 Output Frequencies (Hz) 2400) 1,200 2,400 4,800 7,200 9,600 12,000 14,400 16,800 19,200 21,600 24,000 26,400 28,800 31,200 33,600 36,000 38,400 40,800 43,200 2400)/8 1,200 1,500 1,800 2,100 2,400 2,700 3,000 3,300 3,600 3,900 4,200 4,500 4,800 5,100 5,400
XRT8000
CLK1 (1<=k<=18) CLK2
SYNC
Figure Slave Forward Mode (Cont'd)
Rev. 1.11
XRT8000
XRT8000
CLK1 T1/8 E1/8 CLK2 SYNC Output 1544 2048 Freq.
Figure Slave Reverse Mode (Cont'd)
Board Layout Considerations CLK1 outputs surrounded with supply pins (GND(514),Vcc(712). recommended decouple these supplies with 0.1uF very close pins. positive supply (7,12,15) ground pins (4,5,14) connected Digital Supply Ground. internal proper supply's pins (GND these supply pins have decoupled 0.1uF capacitor should connected Analog Supply possible. there Analog Supply, then connect these pins close possible supply source. layout done with separate layers supplies, island under XTT8000 such that current flows under circuit. been observed that coupling occur because heavy digital currents flowing under locations XRT8000.
Rev. 1.11
XRT8000
LEAD PLASTIC DUALINLINE (300 PDIP)
Rev. 1.00
Seating Plane
INCHES SYMBOL 0.145 0.015 0.115 0.014 0.030 0.008 0.845 0.300 0.240 0.210 0.070 0.195 0.024 0.070 0.014 0.925 0.325 0.280
MILLIMETERS 3.68 0.38 2.92 0.36 0.76 0.20 21.46 7.62 6.10 5.33 1.78 4.95 0.56 1.78 0.38 23.50 8.26 7.11
0.100 0.300 0.310 0.115 0.430 0.160
2.54 7.62 7.87 2.92 10.92 4.06
Note: control dimension inch column
Rev. 1.11
XRT8000
LEAD SMALL OUTLINE (300 JEDEC SOIC)
Rev. 1.00
Seating Plane
INCHES SYMBOL 0.093 0.004 0.013 0.009 0.447 0.291 0.394 0.016 0.104 0.012 0.020 0.013 0.463 0.299 0.419 0.050
MILLIMETERS 2.35 0.10 0.33 0.23 11.35 7.40 10.00 0.40 2.65 0.30 0.51 0.32 11.75 7.60 10.65 1.27
0.050
1.27
Note: control dimension millimeter column
Rev. 1.11
XRT8000
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained herein only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed inaccuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances. Copyright 1999-2006 EXAR Corporation Datasheet September 2006 Reproduction, part whole, without prior written consent EXAR Corporation prohibited.
Rev. 1.11

XRT8000 FEATURES Clock Adaptation Most Popular Telecommunication

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