Dual 10-Bit 40MSPS CMOS FEATURES APPLICATIONS 10-Bit Re
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XRD64L43
Dual 10-Bit 40MSPS CMOS
FEATURES
APPLICATIONS
10-Bit Resolution Monolithic Complete 10-Bit ADCs
MSPS Conversion Rate On-Chip Track-and-Hold On-Chip Voltage Reference Input Capacitance TTL/CMOS Outputs Tri-State Output Buffers Single +3.0V Power Supply Operation Power Dissipation: 200mW-typ 2.7V Power Down Mode Less Than 75dB Crosstalk (fin=1.0MHz) -40°C +85°C Operation Temperature Range
Medical Imaging Instrumentation Data Aquisition Systems Digital Comunications
BENEFITS
Reduction Components Reduction System Cost High Performance Power Dissipation Long Term Time Temperature Stability
GENERAL DESCRIPTION XRD64L43 10-bit, monolithic, MSPS ADCs. Manufactured using standard CMOS process, XRD64L43 offers power, cost excellent performance. on-chip track-and-hold amplifier(T/H) voltage reference (VREF) eliminate need external active components, requiring only external conversion clock application. XRD64L43 analog input driven with ease high input impedance. design architecture uses time- interleaved 10bit ADCs each converter achieve high conversion rate MSPS minimum. order insure maintain accurate 10-bit operation with respect time temperature, XRD64L43 incorporates auto-calibration circuit which continuously adjusts matches offset linearity each ADC. This auto-calibration circuit transparent user after initial 4.2ms calibration (168,000 initial clock cycles). power dissipation only 200mW MSPS with +2.7V power supply. digital output data straight binary format, tristate disable function provided common interface. XRD64L43 internal reference provides cost savings simplifies design/development. output voltage internal reference external resistors. internal reference disabled external reference used power savings 50mW.
ORDERING INFORMATION
Part Number XRD64L43AIV Package Type 64-Lead LQFP Temperature Range -40°C +85°C
Rev. P1.00 EXAR Corporation, 48720 Kato Road, Fremont, 94538 (510) 668-7000 (510) 668-7017
XRD64L43
VINA+VINA-
Bandgap
A/D's
VFBK VRHF VRHS
DA0, OTRA TRI_A DIFF SYNCO CKIN
CONTROL LOGIC
VRLS VRLF
A/D's
VCMO
DB0, OTRB TRI_B
VINB+VINB-
Figure XRD64L43 Simplified Block Diagram
Rev. P1.00
XRD64L43
DOGND
DOVDD
DGND
DVDD
OTRA
OTRB
VCM0 DGND AGND AVDD AGND AGND VINBVINB+ AGND VINA+ VINAAGND AVDD AVDD AGND AGND
DGND DOVDD DOGND SYNCO CKIN TRI_A
XRD64L43
DGND
DGND
AGND
AGND
DVDD
TRI_B
VRHS
VRHF
VRHF
VFBK
VRLS
VRLF
VRLF
Rev. P1.00
DIFF
XRD64L43
DESCRIPTION
Symbol VFBK VRHS VRHF VRHF VRLF VRLF VRLS AGND AGND DGND DGND DVDD TRI_B DIFF TRI_A CKIN SYNCO DOGND DOVDD DGND OTRB DOVDD DOGND DVDD
Description Bandgap Voltage Output Analog Reference Feedback Voltage Reference Sense Voltage Reference Force Voltage Reference Force Bottom Voltage Reference Force Bottom Voltage Reference Force Bottom Voltage Reference Sense Analog Ground Analog Ground Digital Ground Digital Ground Power Down, Active High Digital Supply Voltage Tri-state Channel Outputs, Active High Hi=Differential Mode, Lo=Single-Ended Mode Tri-state Channel Outputs, Active High Clock Input Data Valid Output (Rising Edge) Digital Output (LSB) Digital Output Digital Output Digital Output Ground Digital Output Supply Voltage Digital Ground Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output (MSB) Over Range Digital Output Digital Output (LSB) Digital Output Digital Output Digital Output Digital Output Digital Output Supply Voltage Digital Output Ground Digital Supply Voltage
Rev. P1.00
DESCRIPTION (CONT'D)
Symbol DGND OTRA VCMO DGND AGND AVDD AGND AGND VINBVINB+ AGND VINA+ VINAAGND AVDD AVDD AGND AGND Description Digital Ground Digital Output Digital Output Digital Output Digital Output Digital Output Over Range Digital Output Differential Common Mode Voltage Output Digital Ground Analog Ground Analog Supply Voltage Analog Ground Analog Ground Analog Input B(-) Analog Input B(+) Analog Ground Analog Input A(+) Analog Input A(-) Analog Ground Analog Supply Voltage Analog Supply Voltage Analog Ground Analog Ground
XRD64L43
Rev. P1.00
XRD64L43
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) 25°C AVDD DVDD +3.0V, +2.5V, VRLF GND, VRHF +2.5V MSPS, Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
ACCURACY Differential Non-Linearity Integral Non-Linearity Monotonicity Full Scale Error Zero Scale Error -0.75 +/-0.25 +/-0.5 Missing Codes 0.75 Guaranteed Test Note Single Ended Mode
ANALOG INPUT INVR INRES INCAP INBW Input Voltage Range Input Resistance Input Capacitance Input Bandwidth
VRHS VRLS
KOhms
VRLF Grounded
-1dB Small Signal
REFERENCE INPUT, INTERNAL BANDGAP REFERENCE REFERENCE BUFFER RLADDER RSENSE RLADTCO Ladder Resistance Sense Resistance Ladder Resistance Tempco Bandgap Output Voltage Range VBGTC Bandgap Reference Tempco VRLF VRHF VRHF External Reference VRLF+ VRLF+ VRHF PSRR Internal Reference Buffer VCMO, Common Mode Voltage VCMO Isource Notes:
+0.8
Ohms Ohms Ohms/°C
Note
1.15
1.25
1.35
ppm/°C
AVdd-0.3
mV/V Internal Reference Buffer External
AVdd
Common Mode Voltage Current Source
1.15
1.25
1.35
Full Scale reference VRHS VRLS.
Rev. P1.00
XRD64L43
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) 25°C AVDD DVDD +3.0V, +2.5V, VRLF GND, VRHF +2.5V 40MSPS, Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
DYNAMIC PERFORMANCE 40MHz Signal-to-Noise Ratio 10.0 SINAD Signal-to Noise Distortion ENOB EFFECTIVE NUMBER BITS SFDR SPURIOUS FREE DYNAMIC RANGE SFDR Crosstalk fin1 fin2 CONVERSION TIMING CHARACTERISTICS 10pF) MAXCON MINCON APJT tden tdis CLKDC Maximum Conversion Minimum Conversion Latency Aperture Jitter Time Digital Output Rise Time Digital Output Fall Time Output Data Propagation Delay Output Data Enable Delay Output Data Disable Delay Clock Duty Cycle Guaranteed Design Guaranteed Design Guaranteed Design MSPS KSPS cycles Guaranteed Design Peak-to Peak Intermodulation Distortion Including Harmonics Including Harmonics
Rev. P1.00
XRD64L43
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) 25°C AVDD DVDD +3.0V, +2.5V, VRLF GND, VRHF +2.5V MSPS, Duty Cycle, Differential Input Mode
Symbol DVINH DVINL DIINH CKIN DIFF TRI_A/TRI_B DIINL CKIN DIFF TRI_A/TRI_B DINC DOHV DOLV Parameter Digital Input High Voltage Digital Input Voltage Digital Input High Leakage Clock Input Differential/Single-Ended Input Channel Tri-State Power Down Digital Input Leakage Clock Input Differential/Single-Ended Input Channel Tri-State Power Down Digital Input capacitance Digital Output High Voltage Digital Output Voltage High-Z Leakage -100 DVdd -0.4V -1.0 -1.0 0.25 0.25 DVdd0.3V Internal pull-down resistor Internal pull-down resistor -5.0 50.0 0.05 90.0 125.0 Internal pull-up resistor -125.0 -125.0 -90.0 -90.0 -50.0 -50.0 Internal pull-down resistor Internal pull-down resistor -1.0 -1.0 0.05 -0.25 Internal pull-up resistor Min. Typ. Max. Unit Conditions
DIGITAL INPUTS
DIGITAL OUTPUTS
Rev. P1.00
XRD64L43
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) 25°C AVDD DVDD +3.0V, +2.5V, VRLF GND, VRHF +2.5V MSPS, Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions
POWER SUPPLIES AVDD DVDD Analog Power Supply Voltage Digital Power Supply Range MHz, AVDD DVDD 2.7V, 10pF, 10MHz (Includes Iref Current) AIDD DIDD DOIDD Analog Supply Current Digital Supply Current Output Driver Current AVDD DVDD AVDD
PDISS Power Dissipation MHz, AVDD DVDD 3.3V, 10pF, 10MHz (Includes Iref Current) AIDD DIDD DOIDD Analog Supply Current Digital Supply Current Output Driver Current
PDISS Power Dissipation POWER DOWN CURRENT Power Down Current
ABSOLUTE MAXIMUM RATINGS +25°C unless otherwise noted)1, Inputs Outputs Storage Temperature
Notes:
+7.0V +0.5 -0.5V +0.5 -0.5V +0.5 -0.5V +0.5 -0.5V -65°C 150°C
Lead Temperature (Soldering seconds) 300°C Maximum Junction Temperature 150°C Package Power Dissipation Ratings (TA= +70°C) TQFP 89.4°C/W 2000V
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation above this specification implied. Exposure maximum rating conditions extended periods affect device reliability. input which value outside absolute maximum ratings should protected Schottky diode clamps from input supplies. inputs have protection diodes which will protect device from short transients outside supplies less than 100mA less than 100ms. refers AVDD DVDD. refers AGND DGND
Rev. P1.00
XRD64L43
APPLICATION SECTION
Bandgap AVdd VFBK
XRD64L43
VoltageReferences ladder voltage XRD64L43 provided from internal bandgap reference. bandgap reference feedback path, Pins respectively, used voltage VRHF. Select gain necessary) that VRHF=VBG(1+Rf/Ri). internal bandgap voltage 1.24 volts. XRD64L43 impedence ladder, therefore, typical value recommended greater than 5K).See Figure simplified diagram. Decoupling caps sense inputs AGND should used reduce injectioin high-frequency noise.
VRHF VRHS
Resistive Ladder
VRLS VRLF
Figure Voltage Reference Provided External Source Direct Inputs Single-Ended Inputs XRD64L43 used either single-ended differential input mode. differential inputs, Differential Inputs Section. Single-ended inputs minimize amount external components necessary interface with XRD64L43. common inputs, VINA(-) VINB(-) should tied ground. VINA(+) VINB(+) used apply direct inputs XRD64L43. Figure simplied diagram singleended inputs. DIFF should held select single-ended inputs.
Bandgap VFBK VRHF VRHS
XRD64L43
Resistive Ladder
VRLS VRLF
Figure Voltage Reference Generated from Internal Bandgap Voltage w/gain External voltage references forced VRHF VRLF. VRHF VRLF driven externally, VFBK should connected AVdd, which tri-states bandgap reference. Direct inputs inputs driven external amplifiers used drive ladder reference voltages XRD64L43. Figure simplified diagram. sense inputs intended sensing purposes only care must taken insure that current flow present sense lines.
Input
VINA(+) VINA(-)
Input
VINB(+) VINB(-)
Figure Single-Ended Inputs XRD64L43
Rev. P1.00
Differential Inputs XRD64L43 used either differential single-ended input mode. single-ended inputs, Single-Ended Inputs Section. Differential inputs reduce system noise removing noise components common both input pins. Figure simplified diagram that used common test circuit with XRD64L43ES application board. This circuit used evaluate dynamic performance XRD64L43 using differential inputs. DIFF should held high select differential inputs.
XRD64L43
Auto-Calibration XRD64L43 incorporates auto-calibration circuit which continuously adjusts matches offset linearity each ADC. This auto-calibration circuit transparent user after initial 4.2ms calibration (168,000 initial clock cycles).
Note: avoid auto-calibration after power down, disable CKIN. CKIN slowed down significantly save power without losing calibration.
Input
Transformer
VINA(+) VCMO VINA(-)
Input
Transformer
VINB(+) VINB(-)
Figure Common Test Circuit Differential Input Mode
SYNCO, Data Valid Delay Latency SYNCO output provided XRD64L43. Valid data available rising edge SYNCO, Figure Latency XRD64L43 clock cycles.
CKIN
Valid Data
N-17 tden=20ns
N-16
N-15
SYNCO tsynco=2ns (typical)
Figure SYNCO, Data Valid Delay Latency XRD64L43
Rev. P1.00
XRD64L43
Rev. P1.00
Figure XRD64L43ES Application Circuit XRD64L43
Rev. P1.00
XRD64L43
Figure XRD64L43ES Application Circuit XRD64L43
XRD64L43
Rev. P1.00
Figure XRD64L43ES Application Circuit XRD64L43
XRD64L43
XRD64L43 DIFFERENTIAL NONLINEARITY ERROR 40MHz
Error -0.2 -0.4 -0.6 -0.8 1001
XRD64L43 INTEGRAL NONLINEARITY
ERROR
-0.2 -0.4 -0.6 -0.8 1000
OUTPUT CODE
OUTPUT CODE
Figure Differential Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V
Figure Integral Non-Linearity, Differential Input Mode, Fc=40MHz, Fin=1.5kHz, VRHF=2.5V, VDD=3V
XRD64L43
Fin1 2.51Mhz, Fin2 3.4375Mhz
8192-Point FFT, Fclock =40.0MHz, Differential input mode
Crosstalk (dB)
0.00 -10.00 -20.00 -30.00 -40.00 -50.00 -60.00 -70.00 -80.00 -90.00 -100.00 -110.00 -120.00 Fbin 1.060 2.124 3.188 4.253 5.317 6.382 7.446 8.511 9.575 10.640 11.704 12.769 13.833 14.897 15.962 17.026 18.091 19.155
XRD64L43 Crosstalk Fs=40MSPS Singel-Ended Differential Modes Channel 1=1MHz, Channel 2=(1.5MH z10.5MH -100
Relative Power
Single-Ended Input Differential Input 10.5
Frequency
Input Frequency (MHz)
Figure Intermodulation Distortion, Fin1=2.51MHz, Fin2=3.4375MHz, 8192-point FFT, Fc=40MHz, Differential Input Mode
Figure Crosstalk Input Frequency, VDD=3V, Differential Single Ended Inputs
Rev. P1.00
XRD64L43
SFDR
SingleT 8192 Point -73.18
lativ
12.2 14.6 17.1
-100
-100
-120
-120
-140
-140
-160
-160 12.2 14.6 17.1
Figure Spectrum @Fclock 40.0MHz, 1.0MHz, DIFFERENTIAL INPUT MODE
Figure Spectrum @Fclock 40.0MHz, 4.0MHz, DIFFERENTIAL INPUT MODE
ingleTone 8192
Frequency
lock
-100
-120
-140
-160 12.2 14.6 19.5
Figure Spectrum @Fclock 40.0MHz, 10.0MHz, DIFFERENTIAL INPUT MODE
Figure Input Frequency, Differential Single Ended Inputs, VDD=3V
Rev. P1.00
XRD64L43
SINAD Input Frequency
70.00 Differential Input
60.00
25°C, 1MHz< n<10M DIDD
50.00 Relative Power Single-ended 40.00
30.00
20.00 ClockRate: 40MHz AVDD,DVDD @3.0v 10.00
0.00 (MHz)
Figure SINAD Input Frequency, Differential Single Ended Inputs, VDD=3V
1.26 1.255 (Voltage) 1.25 1.245 1.24 =3.0V 1.235
Curre
Figure Supply Current Sample Clock Frequency
Figure VCMO Temperature
Figure VINA+, VINB+ Temperature Fc=40MSPS
Rev. P1.00
XRD64L43
LEAD LOW-PROFILE QUAD FLAT PACK LQFP, Form)
Rev. 3.00
Note: control dimension millimeters. INCHES 0.055 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.004 0.008 0.465 0.480 0.390 0.398 0.020 0.018 0.030 MILLIMETERS 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.09 0.20 11.80 12.20 9.90 10.10 0.50 0.45 0.75
SYMBOL
Rev. P1.00
Notes
XRD64L43
Rev. P1.00
XRD64L43
NOTICE EXAR Corporation reserves right make changes products contained this publication order improve design, performance reliability. EXAR Corporation assumes responsibility circuits described herein, conveys license under patent other right, makes representation that circuits free patent infringement. Charts schedules contained here only illustration purposes vary depending upon user's specific application. While information this publication been carefully checked; responsibility, however, assumed accuracies. EXAR Corporation does recommend products life support applications where failure malfunction product reasonably expected cause failure life support system significantly affect safety effectiveness. Products authorized such applications unless EXAR Corporation receives, writing, assurances satisfaction that: risk injury damage been minimized; user assumes such risks; potential liability EXAR Corporation adequately protected under circumstances.
Copyright 2000 EXAR Corporation
Datasheet July 2003 Reproduction, part whole, without prior written consent EXAR Corporation prohibited. Rev. P1.00
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