Standards Silicon Product Brief SPI-4 Phase Core FIFOs V1.0 Alter

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Standards Silicon Product Brief SPI-4 Phase Core FIFOs V1.0 Alter

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Standards Silicon
Product Brief SPI-4 Phase Core FIFOs V1.0 Altera PLDs June 2001 Benefits
Faster FPGA ASIC development improved time-to-market with FlexBUS4 functions Lower development cost through design reuse Available source code licensing easy design integration migration gate arrays ASICs Ample design flexibility using control signals generics/parameters Verified functionality standards compliance
Features
OIF-compliant SPI-4 Phase (compatible with AMCC FlexBUS-4) with FIFOs ATM, Packet Over SONET (POS), Direct Data Mapping1 modes Single- multi-link operation, scalable from links. Programmable per-port bandwidth allocation Programmable FIFO size with programmable almost empty/almost full thresholds. Programmable burst size Automatic link selection Source block based Source FIFO threshold flow control information. 64-bit data width. Parity generation/checking data control words over
Description
Optical Interworking Forum's (OIF) SPI4 Phase interface allows interconnection Physical Layer devices Link Layer devices 10Gb/s ATM, POS, Ethernet applications. Modelware's SPI-4 Phase core performs interface functions both sides interface shown Figure 1and Figure
Spi4
Altera's Atlantic Interface user's side. Full synchronous design, exceeds: Fully automatic test bench including driver/monitor. Easy Mux/Demux bridge functions
FIFO(s) Layer Processor PluriBus Interface
Line Data Spi4Tx Link Layer
SPI-4 Line Data Spi4Rx FIFO(s)
Standards Compliance
SPI-4 Phase AMCC FlexBUS-4
Control
Status
Figure SPI-4 Phase Layer Application
Direct Data Mapping data mode supported AMCC's Ganges device.
SPI-4 Phase Core V1.0
Product Brief
June 2001
Spi4
Line Data
Spi4Rx
Sink FIFO(s)
Design Package
Link Layer Processor
Layer
SPI-4
Line Data
Spi4Tx
Atlantic Interface
SPI-4 Phase Core source code package contains: Source code Netlist Test bench (source code option) Scripts data files simulation (behavioral, gate-level, backannotated), synthesis, FPGA layout Detailed documentation: Reference Guide: Core features, architecture, interfaces, operation User's Guide: Core simulation, synthesis, FPGA layout step-by step procedures.
Source FIFO(s)
Control
Status
Figure SPI-4 Phase Link Layer Application
system side, SPI-4 Phase core interfaces single multiple links ports Altera's Atlantic interface. Spi4Tx block monitors Source FIFOs fill level flow control information received from opposite side SPI-4 interface. Source FIFO data flow control information corresponding channel indicates that ready accept data, Spi4Tx block initiates data transfer from Source FIFO towards SPI-4 interface. Spi4Rx block transmits Sink FIFO status information opposite side according Sink FIFO almost-full flags. Spi4Rx block stores data received particular link that link's FIFO. Sink FIFO flags indicate user presence data FIFO(s).
Supported Tools
Modelsim simulation Exemplar Leonardo Spectrum synthesis Altera Quartus
Ordering Information
Modelware, Inc. Tel: (732)936-1808 Fax: (732)936-1838 E-mail: sales@modelware.com Internet: www.modelware.com
Gate Count
SPI-4 Phase Core configured channels targeted APEX uses: Logic Elements (LEs): 2700 Embedded System Blocks (ESBs): above numbers include core small amount circuitry implement loopback Atlantic Interface.
Trademarks
Modelware registered trademark Modelware, Inc. Altera, Quartus, Atlantic trademarks Altera Corporation. FlexBUS trademark AMCC.
odel
Standards Silicon
Product Brief SPI-4 Phase Core FIFOs V1.0 Altera PLDs June 2001
Exemplar Leonardo Spectrum trademarks Exemplar Logic, Inc.

Standards Silicon Product Brief SPI-4 Phase Core FIFOs V1.0 Alter

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