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aMC8500

TWO PHASE VARIABLE SPEED FAN MOTOR CONTROLLER

Preliminary Specification
aMC8500
TWO PHASE VARIABLE SPEED FAN MOTOR CONTROLLER
Product Description
The aMC8500 is a full featured monolithic brushless DC motor controller containing all the required functions to implement fan speed control. This device features a selectable slope pulse width modulator (PWM) for efficient speed control with analog and digital control signal compatibility, programmable minimum speed setting, Hall amplifier with propriety noise immunity circuitry for proper drive sequencing, fixed non-overlapping commutation delay for reduced supply current spiking, dual on-chip 0.5 power MOSFETs with thermal protection for direct motor drive, programmable cycle-by-cycle current limiting, internal fault timer with auto start retry, motor kick start timer to insure start up, combined frequency generator / rotor lock output, uncommitted op amp with reference for thermal sensor voltage scaling, and a selectable automatic low current power down mode for power sensitive applications.
PRODUCT SPECIFICATION
Pin Configuration
Phase 2 Output Current Limit Set Hall +
Phase 1 Output
Preliminary Specification - Subject to change without notice
Freq Gen. Rotor Lock Slope Select Power Ground VDD Signal Ground Speed Control Input Op Amp Output
Hall Reference Output Minimum Speed Set Non-Inverting Input Inverting Input
aMC8500
Features
· · · · · · · · · · · · · · · · · · · · · · · · Analog and digital speed control signal compatibility Programmable minimum speed setting Selectable PWM speed control slope Latching PWM for enhanced noise immunity Integrated fault timer with auto start retry Motor kick start timer Combined frequency generator / rotor lock output Differential unbuffered and digital Hall compatibility Hall amplifier with propriety noise immunity circuitry Pinned out reference Uncommitted op amp for thermal sensor voltage scaling Fixed non-overlapping commutation delay Dual on-chip 0.5 MOSFET motor drives Programmable cycle-by-cycle current limit protection Thermal shutdown protection Under voltage lockout protection Selectable automatic low current power down mode Personal computer fans Workstation and mainframe fans LAN server blowers Industrial control system fans Telcom system fans Instrumentation test and measurement fans Card rack fans
Application Diagram
VDD Ref. Non-Inv. Inv. Output
Reference Op Amp Fault Timer Commutation Logic Motor Drive
Applications
Minimum Speed Speed Control
PWM Logic
Current Limit
Current Limit Set
Slope Select
Signal Gnd
Power Gnd
Ordering Information
Part Number
aMC8500DE16 aMC8500QS16
Ayww - Assembly site year workweek
Package
SOIC 16 Lead Exposed Pad QSOP 16 Lead
Operating Junction Temperature Range
-40°C to 125°C
Marking
aMC8500 Ayww
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Preliminary Specification
aMC8500
Absolute Maximum Ratings (Note 1)
Preliminary Specification - Subject to change without notice
Op Amp Output (Pin 9, Note 4) Voltage Range Source or Sink Current Slope Select Input Voltage Range (Pin 14) Current Limit Set Input Voltage Range (Pin 2) Frequency Generator / Rotor Lock Output (Pin 15) Voltage Range Sink Current Drive Outputs (Pin 1, 16, Note 4) Voltage Range Sink Current Source Current Thermal Characteristics SOP-16 Exposed Pad Package Thermal Resistance, Junction to Air Thermal Resistance, Junction to Pad QSOP-16 Package Thermal Resistance, Junction to Air Operating Junction Temperature Range Storage Temperature Range IR Reflow Peak Temperature Lead Soldering Temperature (10 sec) Electrostatic Discharge (Note 2) Human Body Model Machine Model
Preliminary Specification - Subject to change without notice
92 15 136 -40°C to 125 -60°C to 150 260 300 2000 250 °C °C °C °C V
Notes: 1. Absolute maximum ratings are limits beyond which operation may cause permanent damage to the device. These are stress ratings only. Functional operation at or above these limits is not implied. 2. Human Body Model: 100 pF capacitor discharged through a 1.5 k resistor into each pin. Machine Model: 200 pF capacitor discharged directly into each pin. 3. These specifications are guaranteed only for the test conditions listed. 4. Maximum package power dissipation limits must be observed.
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Preliminary Specification
aMC8500
Electrical Characteristics
Preliminary Specification - Subject to change without notice
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Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
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Preliminary Specification
aMC8500
Figure 1- Motor Drives Percent On-Time versus Speed Control Input Voltage
Figure 2- Motor Drives Percent On-Time versus Speed Control Input Voltage
Kick Start 1.0 sec. Motor remains at min speed setting. Auto power down disabled. IO(Ref) 2.0 mA
Minimum speed set shown for 1.5 V, 1.7 V, and 1.9 V.
Preliminary Specification - Subject to change without notice
Motor turns on / off at min speed setting. Auto power down enabled after 1 sec. IO(Ref) 1.0 mA
Motor turns on / off at min speed setting. Auto power down enabled after 1.0 sec. IO(Ref) 1.0 mA
Minimum speed set shown for 2.1 V, 2.3 V, and 2.5 V.
Preliminary Specification - Subject to change without notice
2.0 3.0 4.0 Vin(SC), Speed Control Input Voltage (V)
1.0 2.0 3.0 4.0 Vin(SC), Speed Control Input Voltage (V)
Figure 3- Op Amp Small Signal Transient Response
Figure 4- Op Amp Large Signal Transient Response
VO, Output Voltage (V)
1.0 s / Division
4.0 s / Division
VOL(FG / RL), Low State Output Voltage (V)
0 VO(OA), Output Voltage (V) -1.0 -2.0 2.0
Figure 5- Op Amp Source and Sink Output Voltage versus Current
Figure 6- Frequency Generator / Rotor Lock Low State Output Voltage versus Sink Current
Low state output Load to VDD
4.0 8.0 12 IO, Output Load Current (mA)
3.0 4.5 Isink, Sink Current (mA)
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Preliminary Specification
aMC8500
Vref, Reference Output Voltage Change (mV)
Vref, Reference Output Voltage (V)
Figure 7- Reference Output Voltage Change versus Output Source Current
Figure 8- Reference Output Voltage versus Power Supply Voltage
Preliminary Specification - Subject to change without notice
4.0 8.0 12 16 IO, Reference Output Source Current (mA)
4.0 8.0 12 VDD, Power Supply Voltage (V)
VOL(Drv), Low State Voltage (V)
Ron, Drive Output On Resistance ()
Figure 9- Phase 1 / Phase 2 Drive Output Low State Voltage versus Sink Current 1.0 0.9 0.8 0.7 0.6 0.5 0.4 4.0
Figure 10- Phase 1 / Phase 2 Drive Output On Resistance versus Power Supply Voltage
0.4 0.6 0.8 Isink, Sink Current (A)
8.0 10 12 14 VDD, Power Supply Voltage (V)
Figure 11- Phase 1 / Phase 2 Current Limit Threshold versus Programming Voltage 1.2 Ilim, Current Limit Threshold (A) 1.0 0.8 0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 Vpgm, Programming Voltage, Pin 2 (V) 1.0 Ilim, Current Limit Threshold (A)
1.2 1.0 0.8 0.6 0.4 0.2 0 10 k
Figure 12- Programming Resistance versus Current Limit Threshold
100 k 1.0 M Rpgm, Programming Resistance ()
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Preliminary Specification
aMC8500
Figure 13- Representative Block Diagram
Hall + Input 3
Hall Input 4
Phase 1 Output
Phase 2 Output
Reference Output
Reference 5 Op Amp 7 8 9
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Preliminary Specification - Subject to change without notice
Non-Inverting Input Inverting Input Output Minimum Speed Set Input
Frequency Generator / Rotor Lock Output 15
Preliminary Specification - Subject to change without notice
Thermal Shutdown Current Limit Latch R
6 Oscillator
Min Speed Comparator PWM Comparator PWM Logic
Power Ground
Speed Control Input
Q S Current Limit Comparator 10 A 2 Current Limit Set
Digital Detector
Signal Ground
Slope Select
INTRODUCTION The aMC8500 is a full featured two phase half wave variable speed brushless motor controller containing all the required functions for implementing a fan control system. Motor control features consists of a selectable slope pulse width modulator (PWM) with double pulse suppression for efficient speed control that is compatible with an analog voltage or a varying duty cycle digital pulse train, a programmable minimum speed set input, and an uncommitted op amp with a pinned out reference for speed control signal scaling, Hall sensor amplifier with propriety noise immunity circuitry for proper drive sequencing, non-overlapping commutation drive for reduced supply current spiking, on-chip 0.5 power MOSFETs for direct coil drive. Protective and diagnostic features include an internal fault timer with auto start retry, motor kick start timer to insure proper start up, programmable cycle-by-cycle current limiting, power supply under voltage lockout, and over temperature thermal shutdown, and a combined frequency generator / rotor lock output for status reporting. Also included is a selectable automatic low current power down mode aimed at power sensitive applications. The aMC8500 is designed for use in thermal open or closed loop systems. It can be controlled by simple NTC or PTC thermistors, Simistor silicon temperature sensors, or by complex digital or microcontroller based temperature monitors. FUNCTIONAL DESCRIPTION A representative block diagram is shown in Figure 13 and a detailed discussion on each of the functional blocks and features are given in the following sections. A complete list of the pin functions with a brief description is shown in Figure 33.
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Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
Controlling Input
Slope Select Pin 14
Comments
Speed Control Minimum Speed Set Speed Control Speed Control Speed Control Minimum Speed Set Speed Control Speed Control
Gnd (Disabled) Tied to Pin 14 (Disabled)
35 35 to 100 100 Duty Cycle
Tied to Pin 14 (Disabled)
Note that if the end application does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse train, the Minimum Speed Set comparator must be disabled as shown in Figure 28. For applications that do not require speed control, the device can be configured to provide commutation only, yielding maximum motor speed without requiring any additional components. This is accomplished by directly grounding Pins 6 and 10, while leaving Pin 14 open.
Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
Commutation The aMC8500 features a non-overlapping commutation delay circuit that prevents simultaneous drive conduction for reduced power supply current spikes and radio frequency interference (RFI). The non-overlap delay time (tdly) is internally set to 40 µs. The commutation waveforms and truth table are shown below in Figures 15 and 16. Figure 15- Two Phase, Two Step, Half Wave Commutation Waveforms
0 Hall Inputs H+ HVClamp 180 360 Rotor Electrical Position (Degrees) 540 720 0 180 360 540 720
Phase 1 Drain Voltage VMotor 0 Phase 1 Drain Current
0 tdly(Com) tdly(Com)
VClamp Phase 2 Drain Voltage VMotor 0 Phase 2 Drain Current FGRL Output Voltage
Figure 16- Commutation Truth Table
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Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
Differential Hall Inputs Rotor Locked Fault Timer Fault Detected 0.25 s On Running Frequency Generator / Rotor Lock Output Constant Speed
Possible Low Or High State Rotor Free ton(Flt) 0.25 s toff(Flt) 2.0 s On Retry Off Cool Down Kick Start 1.0 s Accelerating Constant Speed On Running
Motor Drives
Off Cool Down
Defaults To High State After Fault Detected
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Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
Figure 18- Typical DC Motor Startup and Run Characteristics
Kick Start Extended Speed Range
Typical Useful Speed Range
The Kick Start time, ton(KS), is internally set to 1.0 second and is automatically activated whenever the motor is at rest and commanded to run, or when it is under a command to run and one of the following events takes place: 1) Device comes out of power down mode 2) Rotor was locked and the obstruction has cleared 3) Device recovered from a thermal shutdown 4) Device comes out of an under voltage lockout condition
Current Limit Abnormally high drive current conditions can occur if the motor is mechanically overloaded and may result in device and the drive coil overheating. During motor overload, any reduction in rotational speed reduces the generated back electromotive force, EMF, resulting in an corresponding increase in drive current. The most severe condition occurs when the rotor is locked and there is no back EMF generated. Under this condition, the drive current is limited only by the resistance total of the MOSFET switch and the driven coil. In order to protect the device and motor from abnormally high currents, a programmable Current Limit Comparator is incorporated. The comparator indirectly senses the drive current and when a maximum level is exceeded, the motor drive on-time is immediately terminated on a cycle-by-cycle basis of either the internal oscillator or the digital control signal applied to the Speed Control Input. The current limit threshold defaults to a peak current of 1.1 A with Pin 2 open. This level can be reduced by either applying a bias voltage to Pin 2 or by connecting a single resistor from this pin to ground. Figures 11 and 12 show the current limit behavior while Figure 32 illustrates two biasing methods. The Current Limit Set input is high impedance and in most applications will require a 10 nF bypass capacitor to prevent false triggering due to noise pick up.
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Preliminary Specification
aMC8500
Preliminary Specification - Subject to change without notice
Figure 19- Thermal Shutdown Operation
Thermal Shut Down Deactivated Motor Drives Enabled
Thermal Shut Down Activated Motor Drives Disabled
TJ(max)
100 120 140 TJ, Junction Temperature (°C)
SYSTEM APPLICATIONS The following section shows numerous device circuit configurations and several complete fan control solutions with a brief description. For clarity, many of the circuits show only the internal functional blocks that are of interest with the associated pin numbers.
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Preliminary Specification
Figure 20- Motor Supply Powered Unbuffered Hall
Asahi Kasei HW-101A
aMC8500
Figure 21- Reference Powered Unbuffered Hall
R1 H H VDD Reference 12 3 4
Toshiba TSH124
4 5 Hall Amplifier Non-Overlap Commutation
Under Voltage Lockout
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation
Preliminary Specification - Subject to change without notice
When powering an unbuffered Hall sensor from motor voltage VM, resistor R1 is required. This resistor sets the Hall operating current and places the output within the input common mode voltage range of the Hall Amplifier.
Unbuffered Hall sensors that require less than 10 mA can be powered directly from the Reference output thus eliminating the need for bias resistor R1. This bias method will disable the automatic power down feature if the sensors require more than 2.0 mA.
Figure 22- Op Amp Powered Unbuffered Hall
Figure 23- Motor Supply Biased Buffered Hall
H VDD 5 Reference 12 3 4
Toshiba TSH124
Ana Chip ATS177
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation
The Op Amp output can be used as alternative method for powering unbuffered Hall sensors that require less than 10 mA. This method eliminates the need for bias resistor R1 while also preserving the automatic power down feature. With this bias method the reference output is essentially unloaded.
Pull-up resistor R1 is required when using buffered Hall sensors that have an open collector output. Resistors R2 and R3 bias the unused amplifier input to a level that is within its input common mode range.
Figure 24- Reference Biased Buffered Hall
Figure 25- Reference Buffer
R1 H VDD Reference 12 3 4
Ana Chip ATS177
KEC KTA1270 0.1
100 VDD 12
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation
5 Load
Reference
Under Voltage Lockout
Resistor R1 is required for buffered Hall sensors with an open collector output. Resistors R2 and R3 can be eliminated by biasing the unused amplifier input from the reference.
With the addition of an economical PNP transistor, the Reference output current can be boosted above 100 mA. This simple buffer circuit will not have the benefit of maintaining short circuit protection.
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Preliminary Specification
Figure 26- Higher Voltage Reference
aMC8500
Op Amp
The Op Amp can be used to gain up the Reference voltage in applications that require an additional regulated voltage source. This circuit can supply up to 10 mA for powering additional circuitry or to provide a higher reference voltage. To insure that the Op Amp output maintains regulation, the maximum programmed output voltage must be less than VDD - 1.7 V.
Preliminary Specification - Subject to change without notice
Figure 27- Connections If Op Amp Is Not Required
Reference Op Amp
Unity gain amplifier configuration with the output forced low.
Comparator configuration with the output forced high.
Comparator configuration with the output forced low.
Figure 28- Connections To Disable Minimum Speed Set Or Digital Signal Speed Control Operation Slope Select Grounded
Reference Op Amp
Slope Select Open
Reference Op Amp
Oscillator
Min Speed Comp PWM Comp PWM Logic Digital Detector
Oscillator
Min Speed Comp PWM Comp PWM Logic Digital Detector
If the end application does not require a programmed minimum speed or is to be controlled by a variable duty cycle digital pulse train, the
Minimum Speed Set comparator must be disabled by connecting Pin 6 directly to Pin 14.
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Preliminary Specification
aMC8500
Figure 29- Driving Higher Current Motors
Preliminary Specification - Subject to change without notice
12 Under Voltage Lockout
Hall Amplifier Non-Overlap Commutation
Motor Drives
The Current Limit Comparator protects the Motor Drives by limiting the output sink current to 1100 mA. In applications that require driving higher current motors, the drive current can be significantly increased with the addition of two external P-channel MOSFET. Current limit protection is not maintained since the load is no longer in series with the internal MOSFETs.
Figure 30- Driving Higher Voltage Motors
12 Under Voltage Lockout
Hall Amplifier Non-Overlap Commutation
Motor Drives
The Motor Drives are limited to a maximum of 36 V. These outputs can be cascoded with two external N-channel MOSFETs for driving higher voltage motors. The cascode configuration maintains current limit protection since the load is in series with the internal MOSFETs.
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Preliminary Specification
aMC8500
Figure 31- Driving Single Phase Full Wave Motors
Preliminary Specification - Subject to change without notice
12 Under Voltage Lockout
Hall Amplifier Non-Overlap Commutation
Motor Drives
Single phase full wave motors can be driven with the addition of two external P-channel MOSFETs. With the gates cross coupled as shown above, the internal and external MOSFETs can perform as a full bridge driver. Commutation shoot through current is minimized by the internal non-overlapping delay circuit. The resistor capacitor time constant must be just long enough to prevent pulse width modulation of the two external PFETs. Current limit protection is maintained since the load is in series with the internal MOSFETs. The motor drive outputs are limited to a maximum of 36 V.
Figure 32- Current Limit Threshold Programming, Noise Pick Up and Motor Soft Acceleration
Current Limit Latch R Q S Current Limit Comparator 10 A
13 Current Limit Set 2 110 k
Noise Pick Up Elimination
Current Limit Threshold Reduction
To Vref
Soft Motor Acceleration
To VM Optional
10 nF Bypass Capacitor Single Resistor Current Source Biased Dual Resistor Reference Biased
Caccl
The Current Limit Set input is susceptible to noise pick up and in most applications will require a 10 nF bypass capacitor. The Current Limit Comparator threshold can be reduced by connecting a single resistor from Pin 2 to ground. This is the most economical programming method but it is somewhat less accurate than using the dual resistor method shown. This is due to the fact that the Reference Output is more accurate than the absolute values of the internal current source pull-up and terminating resistor. Motor soft acceleration during power-up can be accomplished by connecting a capacitor from Pin 2 to ground. During initial device power-up, the internal current source will charge capacitor Caccl thus gradually increasing the current limit threshold. The diode shown is optional and may not be required if there is sufficient time for the internal components to discharge the capacitor from when the power source is removed and then reapplied.
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Preliminary Specification
Figure 33- Pin Function Description
Pin 1 2 3 4 5 Function Phase 2 Output Current Limit Set Hall + Hall Reference Output Minimum Speed Set Non-Inverting Input Inverting Input Op Amp Output Speed Control Input Signal Gnd VDD Power Ground Slope Select Freq. Generator / Rotor Lock Phase 1 Output Description
aMC8500
Preliminary Specification - Subject to change without notice
Layout Considerations High frequency printed circuit layout techniques are required to prevent pulse jitter and the possibility of erratic operation. This can be caused by excessive noise pick-up imposed upon the Hall or Error Amplifier inputs. The printed circuit layout should contain as much copper ground as possible with separate low current signal and high current motor drive grounds that return back to the power supply input filter capacitor. Ceramic 0.1 µF bypass capacitors connected close to the integrated circuit VDD and Vref pins may also be required depending upon circuit board layout and the source voltage impedance. The use of bypass capacitors will provide a low impedance path to ground for filtering out high frequency noise. The signal and power ground pins along with the exposed thermal pad must be connected together at the package. All high current loops should be kept as short as possible with wide traces to minimize the generation of radiated electro magnetic interference, EMI. Wide copper trace connections with copious amounts of foil placed under the device will greatly enhance the devices ability to dissipate power.
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Preliminary Specification
aMC8500
Figure 34- Thermistor Sensing Variable Speed Temperature Regulator
Preliminary Specification - Subject to change without notice
Reference 5 R2 R6 H R1 T 7 R3 R4 8 9
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Preliminary Specification - Subject to change without notice
Op Amp
Thermal Shutdown
6 Oscillator
Min Speed Comp PWM Comp PWM Logic
Current Limit Latch R Q S Current Limit Comp 10 A
Digital Detector
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Preliminary Specification
aMC8500
Figure 35- Simistor Sensing Variable Speed Temperature Regulator
Preliminary Specification - Subject to change without notice
Reference R4 aSM121 7 R1 R3 R2 8 9 R6 R5 6 Oscillator
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Thermal Shutdown
Min Speed Comp PWM Comp PWM Logic
Current Limit Latch R Q S Current Limit Comp 10 A
Digital Detector
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Preliminary Specification
aMC8500
Figure 36- Thermistor Sensing Thermostatic Temperature Regulator
Preliminary Specification - Subject to change without notice
Reference
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Op Amp 7 8 9 Min Speed Comp Oscillator
Thermal Shutdown
Current Limit Latch R PWM Logic Q S Current Limit Comp 10 A
PWM Comp
Digital Detector
Thermostatic control can be accomplished by configuring the Op Amp as a non-inverting voltage comparator. The above table shows five different application examples with the calculated resistor values. In applications 1, 2, 4, and 5, the motor will switch from the programmed minimum setting to maximum speed as the sensor temperature rises above the required transition temperature. A controlled amount of positive feedback shifts the transition temperatures to provide thermal hysteresis as the sensor cools. In the third application requirement, the motor speed switches between zero and full speed. In this case the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature.
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Preliminary Specification
aMC8500
Figure 37 Simistor Sensing Thermostatic Temperature Regulator
Preliminary Specification - Subject to change without notice
Reference R2 R1 aSM121 H R3 8 9 5
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Preliminary Specification - Subject to change without notice
Op Amp
Thermal Shutdown
6 Oscillator
Min Speed Comp PWM Comp PWM Logic
Current Limit Latch R Q S Current Limit Comp 10 A
Digital Detector
Thermostatic control is achieved by configuring the Op Amp as a voltage comparator. The inverting input monitors the Simistor solid state thermal sensor while the non-inverting input is biased to a reference level. The above table shows five different application examples with the calculated resistor values. In applications 1, 2, 4, and 5, the motor speed switches from the programmed minimum setting to maximum as the sensor temperature rises above the required transition temperature. A controlled amount of positive feedback shifts the transition temperatures to provide thermal hysteresis as the sensor cools. In the third application requirement, the motor switches between zero and full speed. In this case the minimum speed set input is not required and the comparator must be disabled by connecting Pin 6 to Pin 14. Note that the total Reference load current must exceed 2.0 mA in order to disable the automatic power down feature.
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Preliminary Specification
Figure 38- Balanced Technology Extended (BTX) Closed Loop Speed Control
aMC8500
Duty Cycle to Voltage Converter
Control Signal Input 10 k
12 100 nF 5 330 nF 7 22 F FB Error 8 330 nF 9 SC 1M 6 Oscillator Min Speed Comp PWM Comp Reference Ref Op Amp Under Voltage Lockout
1 VDD 10 k FGRL Out
Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Preliminary Specification - Subject to change without notice
74AC86PC H
Thermal Shutdown Current Limit Latch R Q S Current Limit Comp 10 A
Temperature Controlled Clamp
T H 2.8 k 20 k 47 k 6.8 k Thermistor
PWM Logic Digital Detector
Frequency to Voltage Converter
Figure 39- Fan Speed versus Control Signal Duty Cycle for Various Inlet Air Temperatures 4800 36 Inlet Air Temperature °C 4000 Fan Speed (RPM) 3200 2400 1600 800 0 0
2600 2200 Fan Speed (RPM) 1800 1400
Figure 40- Fan Speed versus Motor Voltage for Various Control Signal Duty Cycles
12.0 12.4 12.8 Motor Voltage (V)
The above circuit controls fan speed in a closed loop manner that is proportional to the control signal duty cycle and inlet air temperature. A voltage indicating the required fan speed or Reference is applied to Pin 7 and is derived from the Duty Cycle to Voltage Converter and Temperature Controlled Clamp circuits. The Duty Cycle to Voltage Converter consists of an XOR gate buffer that drives a 10 k, 22 F low pass filter, with the high state level limited by the Temperature Controlled Clamp. A voltage indicating the actual fan speed or Feedback is applied to Pin 8 and is derived from the Frequency to Voltage Converter that consists of two XOR gates. The first XOR buffers the FGRL tachometer signal and connects to the second which is configured as an edge transition one-shot that drives a 100 k, 330 nF low pass filter. The Op Amp compares the difference between the Reference and Feedback voltages and generates an Error signal that drives Pin 6 in a corrective fashion causing the fan to run either faster or slower so that the Feedback voltage level becomes the same as the Reference. Performance data is shown in the above graphs. Note that the Error signal is applied to Pin 6 instead of Pin 10 and that Pin 10 must be biased between 1.0 V to 3.0 V for proper operation.
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Preliminary Specification
Figure 41- Digital Pulse Speed Control with Programmable Minimum Speed Set
aMC8500
Reference 5
Under Voltage Lockout Hall Amplifier Non-Overlap Commutation Fault Timer Power Down Kick Start
Motor Drives
Preliminary Specification - Subject to change without notice
Op Amp 7 8 9 453 909 6.2 k 2.7 k Pulse Input 10 k 36 k Q1 C1 0.1 10 6 Oscillator
Preliminary Specification - Subject to change without notice
Thermal Shutdown
Min Speed Comp PWM Comp PWM Logic
Current Limit Latch R Q S Current Limit Comp 10 A
Digital Detector
Figure 42- Speed Control Alarm
Reference Op Amp 7 8 9 6 Oscillator
VOH VOL Vth 0V 3.0 V
VOL Vth 0V 3.0 V
R2 Vth R1
Reference Op Amp
Speed Alarm Output
Oscillator
Min Speed Comp PWM Comp
Speed Control Input
The Op Amp and Reference can be used to generate a speed control alarm signal. Resistors R1 and R2 divide down the Reference output voltage to set trip threshold Vth. The Op Amp compares the speed control input voltage to the trip threshold and the output changes state when it is crossed. In the circuit on the left, the speed alarm output transitions from a low to high state as the Speed Control Input voltage increases. With the circuit on the right, the speed alarm output transitions from a high to low state as the speed control input voltage increases. Threshold hysteresis can be added to the circuit on the right by placing a resistor from Pin 9 to Pin 7.
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Preliminary Specification
aMC8500
Figure 43- Dual Fan Redundancy
12 Ref Op Amp UVLO Hall Amp Commutation 3 4 16 1
R1 1.0 M C1 1.0
R2 590
Drives
Preliminary Specification - Subject to change without notice
Timers Power Down
Min Spd Osc PWM PWM Logic Digital Detector
Latch R Q S Current Limit 10 A
R3 787
1 16 4 3 12 UVLO Hall Amp Commutation 15 Timers Power Down Ref
Drives
R2 590
R1 1.0 M C1 1.0
Op Amp
Latch R Q PWM Logic
Min Spd PWM Osc
2 10 nF Current Limit
10 Digital Detector
R3 787
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Preliminary Specification
aMC8500
Figure 44- QSOP16 Package Outline Drawing Top View Bottom View
Preliminary Specification - Subject to change without notice
Side View
End View
Detail A
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Preliminary Specification
aMC8500
Figure 45- SOIC16 Exposed Pad Package Outline Drawing
Preliminary Specification - Subject to change without notice
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Preliminary Specification
aMC8500
Data Sheet Classifications
Preliminary Specification This classification is shown on the heading of each page of a specification for products that are either under development (design and qualification), or in the formative planning stages. Andigilog reserves the right to change or discontinue these products without notice. New Release Specification This classification is shown on the heading of the first page only of a specification for products that are either under the later stages of development (characterization and qualification), or in the early weeks of release to production. Andigilog reserves the right to change the specification and information for these products without notice.
Preliminary Specification - Subject to change without notice
Fully Released Specification Fully released datasheets do not contain any classification in the first page header. These documents contain specification on products that are in full production. Andigilog will not change any guaranteed limits without written notice to the customers. Obsolete datasheets that were written prior to January 1, 2001 without any header classification information should be considered as obsolete and non-active specifications, or in the best case as Preliminary Specifications.