256-TAP DUAL-CHANNEL NON-VOLATILE DIGITAL POTENTIOMETER Publicati
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WMS7202
256-TAP DUAL-CHANNEL NON-VOLATILE DIGITAL POTENTIOMETER
Publication Release Date: January 2003 Revision
WMS7202
GENERAL DESCRIPTION
WMS7202 256-tap, dual-channel non-volatile digital potentiometer available 10K, 100K end-to-end resistances. These devices used three-terminal potentiometer terminal variable resistor wide variety applications. output each potentiometer determined wiper position, which varies linearly between terminal according content stored volatile Register (TR). settings provided either directly user through industry standard interface, non-volatile memory (NVMEM0~3) where previous settings stored. When changes made establish wiper position, value setting saved into nonvolatile memory location (NVMEM0~3) executing NVMEM save operation. Each channel four non-volatile memory locations (NVMEM0~3) that directly written read users through interface. Upon powerup content NVMEM0 automatically loaded Register. WMS7202 contains independent channels 14-pin PDIP, SOIC TSSOP packages operate over wide operating voltage range from 2.7V 5.5V. selectable output buffer builtin each channel those applications where output buffer required.
FEATURES
taps each potentiometer Dual independent, linear-taper channels package End-to-end resistance available 10K, 100K Selectable output buffer each channel Serial Interface data transfer potentiometer control Daisy-chain operation multiple devices Nonvolatile storage four wiper positions channel with power-on recall from NVMEM0 standby current (1µA Max. with output buffer inactive) Endurance 100K typical stores Register Data Retention years Industrial temperature range: 85°C Wide operating voltage range: 2.7V 5.5V Package option: 14-pin TSSOP, 14-pin SOIC, 14-pin PDIP
WMS7202
BLOCK DIAGRAM
Serial Interface
Register
Decoder
NVMEM0 (Non-volatile Memory Power recall) NVMEM1 (Non-volatile Memory NVMEM2 (Non-volatile Memory NVMEM3 (Non-volatile Memory Decoder Memory Control Register
NVMEM0 (Non-volatile Memory Power-on recall) NVMEM1 (Non-volatile Memory NVMEM2 (Non-volatile Memory NVMEM3 (Non-volatile Memory
Publication Release Date: January 2003 Revision
WMS7202
TABLE CONTENTS
GENERAL DESCRIPTION. FEATURES BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION DESCRIPTION FUNCTIONAL DESCRIPTION. 7.1. Potentiometer Rheostat Modes 7.1.1. Rheostat Configuration 7.1.2. Potentiometer Configuration 7.2. Programming Modes 7.3. Non-Volatile Memory (NVMEM) 7.3.1 Write Protect NVMEM Flow Control. 7.5. Daisy Chain 7.6. Serial Data Interface 7.7. Instruction Set. 7.8. Basic Operation 7.8.1 Sending Command 7.8.2 Wake Up/Sleep/Power Commands 7.8.3 Write Register (TR). 7.8.4 Programming Non-Volatile Memory (NVMEM). 7.8.5 Reading Registers NVMEM Locations TIMING DIAGRAMS. Absolute Maximum Ratings. ELECTRICAL CHARACTERISTICS 10.1 Test Circuits. TYPICAL APPLICATION CIRCUIT 11.1. Layout Considerations PACKAGE DRAWINGS DEMINSIONS. ORDERING INFORMATION. VERSION HISTORY
WMS7202
CONFIGURATION
TSSOP
PDIP
SOIC
Publication Release Date: January 2003 Revision
WMS7202
DESCRIPTION
TABLE DESCRIPTION NAME DESCRIPTION Serial Clock pin. Data Shifts time positive clock (CLK) edges Chip Select pin. When HIGH, WMS7202 deselected high impedance, (unless internal write cycle underway) device will standby state. enables WMS7202, placing active power mode. should noted that after power-up, HIGH transition required prior start operation. Serial Data Input pin. opcodes, byte addresses data written registers input this pin. Data latched rising edge serial clock. Serial Data Output with open-drain output. During read cycle, data shifted this pin. Data clocked falling edge serial clock except which clocked falling edge Also used daisy-chain several parts. Ready signal with active-LOW, open-drain output, acknowledges completion commands Hardware Write Protect pin. When active prevents changes present contents except retrieving NVMEM contents. Power Supply Ground pin, logic ground reference terminal potentiometer `1', equivalent terminal connection mechanical potentiometer terminal potentiometer `1', equivalent terminal connection mechanical potentiometer Wiper terminal potentiometer `1', equivalent wiper terminal mechanical potentiometer terminal potentiometer `2', equivalent terminal connection mechanical potentiometer. terminal potentiometer `2', equivalent terminal connection mechanical potentiometer. Wiper terminal potentiometer `2', equivalent wiper terminal mechanical potentiometer.
WMS7202
FUNCTIONAL DESCRIPTION
WMS7202 series, family 256-tap, nonvolatile digitally programmable potentiometers designed operate both potentiometer variable resistor depending upon output configuration selected. chip store four 9-bit words nonvolatile memory (NVMEM0 NVMEM3) word stored NVMEM0 will used register values when device powered WMS7202 controlled serial interface that allows setting register values well storing data nonvolatile memory. 7.1. POTENTIOMETER RHEOSTAT MODES WMS7202 operate either rheostat potentiometer (voltage divider). When potentiometer configuration there possible modes. without output buffer other mode with output buffer. Selecting mode done controlling data register. sets output buffer sets Each channel independently either buffer Off. Note that this only loading value NVMEM with instructions then loading register with instruction from NVMEM. This cannot controlled directly writing value chip when register set. 7.1.1. Rheostat Configuration WMS7202 acts terminal resistive element rheostat configuration where terminal either point pins resistor other terminal wiper (VW) pin. This configuration controls resistance between terminals resistance adjusted sending corresponding register setting commands WMS7202 loading pre-set register value from nonvolatile memory NVMEM0 MVMEM3. 7.1.2. Potentiometer Configuration potentiometer configuration input voltage connected point pins VB). voltage wiper will proportional voltage difference between wiper setting. resistance cannot directly measured this configuration. 7.2. PROGRAMMING MODES program modes available WMS7202: Direct program mode. register setting changed either loading predetermined value from external microcontroller using UP/DOWN commands. DOWN commands change register setting incrementally i.e., time. DOWN commands will wrap around ends scale. NVMEM restore mode. previously stored settings loaded into register from non-volatile memory. Four 9-bit non-volatile memories, available each channel store register settings. first register, NVMEM0, stores favorite default register setting that will loaded into register system power software power reset operation.
Publication Release Date: January 2003 Revision
WMS7202
7.3. NON-VOLATILE MEMORY (NVMEM) Each channel four NVMEM positions available storing output buffer operating mode potentiometer setting. These NVMEM positions directly written through using write command (#5) with address data bytes. Another command (#7) available that stores current output buffer operating mode potentiometer settings into selected NVMEM position. instruction byte decide which NVMEM position used. (See Table potentiometers loaded with value stored NVMEM position their respective channel power 7.3.1 Write Protect NVMEM Write-protect disables changes current content NVMEM regardless commands, except that NVMEM setting retrieved using commands Table Therefore, Write-Protect provides hardware NVMEM protection feature with tied Vss. which active logic LOW, should tied directly being used. FLOW CONTROL Reading writing NVMEM requires internal access cycle complete before next command sent. following commands have additional flow control using pin. Read Register (#2) Read NVMEM (#4) Program NVMEM (#5) Load Register(#6) Program NVMEM with Register (#7) will pulled HIGH when goes LOW, will stay HIGH indicating chip ready accept another command. After sending those commands, should polled determine when device ready accept additional data. This flow control used commands without performance penalty although only needed commands listed above.
WMS7202
7.5. DAISY CHAIN Multiple devices controlled same without need extra lines from microcontroller daisy chaining devices with first device connected next device shown figure Micro controller Device Device Device
FIGURE DAISY CHAIN CONFIGURATION complete command bits including instruction data bytes. When shifting bits first device chain, bits previous command will shifted out. devices daisy chain, total bits must sent where first bits will shifted second device bits shifted last will remain first device. Command data device shifted into device this will propagate Device when next bits shifted Device Command Data Data
Device
Command data device shifted into device Device correctly Device Command Data Data
Device Command
Data
Data
FIGURE DAISY CHAIN COMMAND EXAMPLE
Publication Release Date: January 2003 Revision
WMS7202
7.6. SERIAL DATA INTERFACE WMS7202 contains four-wire interface: (Serial Data Output) Used reading internal register contents daisy chaining multiple devices. (Serial Data Input) Used clocking commands potentiometer settings. (Chip Select) This must pulled before starting send command pulled HIGH signal command. This used control multiple devices bus. (Clock) bits shifted rising edge clock data shifted falling edge clock.
features this interface include: Independently programmable Read Write registers Direct parallel refresh registers from corresponding internal NVMEM registers Increment decrement instruction each register Nonvolatile storage present register values into four NVMEM registers available each channel Configurable output buffer amplifier allow both functions potentiometer variable resistor Four 9-bit non-volatile registers store four preset wiper positions first will recalled wiper position during power
serial interface uses compatible uniform 24-bit word format shown below. This format used members WMS720x family. data sent first. TABLE 24-BIT DATA WORD FORMAT
C3-C0 command bits that control operation digital potentiometer according command instructions shown Instruction Table Section 7.7. address bits that determine which channel activated, shown table below. WMS7202 only first codes used.
WMS7202
TABLE ADDRESS DECODE TABLE Channel
address bits that decide which NVMEM memory accessed, shown table below. TABLE ADDRESS DECODE TABLE NVMEM
D7-D0 data values loaded into Register wiper position, while used output mode. loaded into NVMEM0~3 first then "Load Register" command (#6) executed load into output-selection output mode. D8=0 sets output Buffer mode while D8=1 sets Buffer mode.
taken before command starts
taken HIGH after command sent
must valid rising edge clock valid falling edge clock
Note: multiple bits must always sent command will valid Bits marked don't care bits.
goes completion commands allow NVMEM program TSV. other commands, stays HIGH after command sent.
FIGURE COMMAND WAVEFORMS Publication Release Date: January 2003 Revision
WMS7202
7.7. INSTRUCTION TABLE INSTRUCTION
Inst Instruction Byte Data Byte Data Byte Operation (NOP). nothing Read Register output selection register Write Register with D7-D0 Read NVMEM pointed A3-A0 Program NVMEM pointed A3-A0 with D8-D0 Load Register output selection register with contents NVMEM pointed A3-A0 Program NVMEM pointed A3-A0 with contents Register output selection register Increment setting Down: Decrement setting Sleep: Discontinue clock supply logic memories Wake Clock supply logic memories Byte-erase NVMEM pointed A3-A0 Power Reset: Software reset part power state Operation
Note: C3-C0 command op-code; NVMEM address; channel address.
7.8. BASIC OPERATION This chapter describes sequences commands send WMS7202 different features.
7.8.1 Sending Command Take chip SLEEP mode. Check that write protect correctly writing NVMEM. Check that HIGH before issuing command. Pull before sending data device.
WMS7202
clock pulses sent each command. must valid rising edge clock, valid falling edge clock Take HIGH after command completed. command sent, wait HIGH before sending next command.
7.8.2 Wake Up/Sleep/Power Commands chip SLEEP mode after: applied Power Reset command sent SLEEP command sent
Before operations performed WAKE command must sent. When SLEEP command sent, chip retains resistor settings long chip powered cannot accept other commands than WAKE command. TABLE POWER RELATED COMMANDS Inst. Command Name: Wake Sleep Power Reset Command Byte 0001xxxx 1000xxxx 1001xxxx 0000xxxx Data Byte xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Data Byte xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx Comment Wake entire chip Send chip into power save mode Reset Chip Dummy instruction
commands above control entire chip. There independently power individual potentiometers.
7.8.3 Write Register (TR) microcontroller write value directly into register send increment decrement command control register. Alternatively, contents NVMEM location written register. only change output buffer mode write desired value into NVMEM location then load corresponding NVMEM location into register.
Publication Release Date: January 2003 Revision
WMS7202
TABLE WRITING REGISTERS Inst. Comman Name: Write Register Down Load Register Command Byte 0100 Data Byte xxxxxxxx Data Byte Comment Writes value register selected channel Increment register value Decrement register value Load selected NVMEM location into register
0111 1111
xxxxxxxx xxxxxxxx xxxxxxxx
xxxxxxxx xxxxxxxx xxxxxxxx
7.8.4 Programming Non-Volatile Memory (NVMEM) value stored NVMEM location bits, bits (D7-D0) register plus (D8) output buffer mode. NVMEM position must erased before writing There ways program value into NVMEM. Write value directly from microcontroller Load current potentiometer setting into NVMEM. TABLE PROGRAMMING NVMEM Inst. Command Name Erase NVMEM Program NVMEM Program NVMEM with Register Command Byte Data Byte xxxxxxxx Data Byte Comment Erases word pointed Writes value selected NVMEM register selected channel Takes current potentiometer settings saves selected NVMEM location.
xxxxxxxx
programming NVMEM, following sequence must followed: Erase word NVMEM location Program word NVMEM location
WMS7202
7.8.5 Reading Registers NVMEM Locations contents register channel NVMEM location read back through pin. When command sent, data clocked falling edge clock. Since daisy-chain operation requires data from command clocked when next command arrives, read command must followed another command correct data pin. TABLE READING REGISTERS Inst. Command Name: Read NVMEM Read Register Read Register Command Byte Data Byte xxxxxxxx Data Byte Comment Read value selected NVMEM location Read value selected register Output data
1100 0000
xxxxxxxx
read contents either register NVMEM location, following sequence must followed. Send desired read command select register read Send another command such read falling edge clock. other command could command, make sure that chip does change anything, send either another Read command command (#1).
Publication Release Date: January 2003 Revision
WMS7202
TIMING DIAGRAMS
tCYC tLEAD tDSU tLAC tRSU tWPSU tWPH tLRL tLAG
FIGURE WMS7202 TIMING DIAGRAM
WMS7202
TABLE TIMING PARAMETERS PARAMETER Clock Cycle Time Clock HIGH Time Clock Time Lead Time Time Setup Time Hold Time
Line Acquire Line Release
SYMBOL tCYC tLEAD tLAG tDSU tLAC tLRL tRSU tWPSU tWPH
MIN.
MAX.
UNIT
Propagation Delay Rise Fall Store NVMEM Save Time
Deselect Time
Startup Time
Setup Time Hold Time
Note: interface timing characteristics apply parts guaranteed design subject production test.
Publication Release Date: January 2003 Revision
WMS7202
ABSOLUTE MAXIMUM RATINGS
TABLE ABSOLUTE MAXIMUM RATINGS Condition Junction temperature Storage temperature Voltage applied (Vss 0.3V) (VDD 0.3V) -0.3 7.0V Value
Note: Exposure conditions beyond those listed under: Absolute Maximum Ratings, adversely affect life reliability device.
WMS7202
ELECTRICAL CHARACTERISTICS
TABLE ELECTRICAL CHARACTERISTICS
Parameters apply across specified operating ranges unless noted (VDD: 2.7V~5.5V; Temp: -40°C~85°C) Typical values: VDD=5V T=25°C
PARAMETER Rheostat Mode Nominal Resistance Different Linearity Integral Linearity Rheostat Tempco1 Wiper Resistance2
SYMBOL RAB/T
MIN.
MAX.
UNITS ppm/°
CONDITIONS open
Bits ppm/°
VDD=5V, I=VDD/RTotal VDD=2.7V, I=VDD/RTotal
Potentiometer Mode Resolution1 Different Linearity2 Integral Linearity2 Potentiometer Tempco1 Full Scale Error Zero Scale Error Resistor Terminal Voltage Range1 Terminal Capacitance1 Wiper Capacitance1 Dynamic Characteristics1
Vw/T VFSE VZSE VA,VB,VW
Code Code Full Scale Code Zero Scale
BW10K Bandwidth -3dB Settling Time BW50K BW100K
VDD=5V, VB=VSS
Code Full Scale
Code CL=30pf VDD=5.5V=VA, VB=VSS VO=1/2 scale VA=2.5V, VDD=5V, f=1kHz, VIN=1VRMS
Analog Output (Buffer enabled) Output Current2 IOUT Output Resistance2 Rout Total Harmonic Distortion1 Digital Inputs/Outputs Input High Voltage Input Voltage Output Voltage Input Leakage Current
0.08
0.7VDD 0.3VDD
IOL=2mA =VDD,Vin=Vss
Publication Release Date: January 2003 Revision
WMS7202
=VDD,Vin=VSS VDD=5V, 1Mhz Code VDD=5V, 1Mhz Code
Output Leakage Current Input Capacitance1 Output Capacitance1 Power Requirements Operating Voltage1 Operating Current Operating Current
COUT IDDR IDDW
LSB/V except NVMEM program During Nonvolatile memory program Buffer active, load Buffer inactive, Power Down, load VDD=5V±10%, Code=80h
Standby Current
ISB2 PSRR
Power Supply Rejection Ratio
Note: subject production test; Only Final Test; +2.7V 5.5V, unless otherwise noted.
WMS7202
10.1 TEST CIRCUITS
1LSB= V+/255 VMS*
±10% PSRR(dB) 20LOG( PSS(%/%)
WMS7202
*Assume infinite input impedance
WMS7202
VMS*
*Assume infinite input impedance
Potentiometer divider nonlinearity error test circuit (INL, DNL) Connection WMS7202
Power supply sensitivity test circuit (PSS, PSRR)
WMS7202
VOUT
*Assume infinite input impedance
2.5V Offset Capacitance test circuit
Resistor position nonlinearity error test circuit (Rheostat Operation: R-INL, R-DNL) WMS7202 /RTotal
WMS7202 OFFSET 2.5V
VOUT
*Assume infinite input impedance
Wiper resistance test circuit
Gain frequency test circuit FIGURE TEST CIRCUITS
Publication Release Date: January 2003 Revision
WMS7202
TYPICAL APPLICATION CIRCUIT
WMS7202
VOUT
VOUT
RABD
RAB(256
Total resistance potentiometer Wiper setting WMS7202
FIGURE PROGRAMMABLE INVERTING GAIN AMPLIFIER USING WMS7202
VOUT
WMS7202 VOUT
RAB(256 RABD
Total resistance potentiometer Wiper setting WMS7202 FIGURE PROGRAMMABLE NON-INVERTING GAIN AMPLIFIER USING WMS7202
WMS7202
32mA VREFH VREF 5.0v WMS7202
FIGURE WMS7202 TRIMMING VOLTAGE REFERENCE
WMS7202P-14
AUDIO TONE CONTROL EXAMPLE
FIGURE WMS7202 AUDIO TONE CONTROL
Publication Release Date: January 2003 Revision
WMS7202
WMS7202 CONTROL
WMS7202 R/B\
Vout
PROGRAMMABLE LOW-PASS FILTER
FIGURE PROGRAMMABLE LOW-PASS FILTER
WMS7202
11.1. LAYOUT CONSIDERATIONS 0.1µF bypass capacitor close possible recommended best performance. Often this done placing surface mount capacitor bottom side board, directly between pins. Care should taken separate analog digital traces. Sensitive traces should under device close bypass capacitors. dedicated plane analog ground helps reducing ground noise sensitive analog signals.
FIGURE WMS7202 LAYOUT
Publication Release Date: January 2003 Revision
WMS7202
PACKAGE DRAWINGS DEMINSIONS
BASE PLANE
SEATING PLANE
SYMBOL
DIMENSION (MM) MIN. MAX.
DIMENSION (INCH) MIN. 0.015 MAX.
0.381 0.406 1.397 0.457 1.524 0.25 18.80 7.62 6.25 19.05 7.925 6.35 2.54BSC 2.2921 8.382 8.89 9.398 19.30 8.230 6.45 0.508 1.651
0.016 0.055
0.018 0.060 0.010
0.020 0.065
0.740 0.300 0.246
0.750 0.312 0.250 BSC.
0.760 0.324 0.254
0.115 0.330 0.350 0.370
FIGURE PDIP 300MIL
WMS7202
0.25
SEATING PLANE SYMBOL DIMENSION (MM) MIN. 0.40 1.35 0.10 0.33 0.19 3.80 8.55 MAX. 1.75 0.25 0.51 0.25 4.00 8.75 DIMENSION (INCH) MIN. 0.053 0.004 0.013 0.008 0.150 0.337 MAX. 0.069 0.010 0.020 0.010 0.157 0.344 GAUGE PLANE
1.27 BSC. 5.80 6.20 0.10 1.27
0.050 BSC. 0.228 0.244 0.004 0.016 0.050
FIGURE SOIC 150MIL
Publication Release Date: January 2003 Revision
WMS7202
SEATING PLANE
DIMENSION (INCH) 1.20 0.05 0.80 0.50 0.90 0.60 6.40 4.30 0.19 4.90 5.00 0.076 0.65 4.40 4.50 0.30 5.10 0.169 0.007 0.193 0.197 0.006 0.026 0.15 1.05 0.75 0.002 0.031 0.020 0.035 0.024 0.252 0.173 0.177 0.012 0.201 0.043 0.006 0.041 0.030
DIMENSION (MM) SYMBOL D/mm MIN.
FIGURE TSSOP 4.4MM
WMS7202
ORDERING INFORMATION
Winbond's WinPot Part Number Description: WMS72
Winbond WinPot Products Features: Single channel with Interface Dual channels with Interface Quad channels with Interface
End-to-end Resistance: 010: 050: 100: 100K
Package Index: TSSOP SOIC PDIP
latest product information, access Winbond's worldwide website http://www.winbond-usa.com
Publication Release Date: January 2003 Revision
WMS7202
VERSION HISTORY
VERSION DATE June 2002 Jan. 2003 PAGE Initial issue Correct typos, Inst tables, values Specification DESCRIPTION
contents this document provided only guide applications Winbond products. Winbond makes representation warranties with respect accuracy completeness contents this publication reserves right discontinue make changes specifications product descriptions time without notice. license, whether express implied, intellectual property other right Winbond others granted this publication. Except forth Winbond's Standard Terms Conditions Sale, Winbond assumes liability whatsoever disclaims express implied warranty merchantability, fitness particular purpose infringement Intellectual property. Winbond products designed, intended, authorized warranted components systems equipments intended surgical implantation, atomic energy control instruments, airplane spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, other applications intended support sustain life. Further, Winbond products intended applications wherein failure Winbond products could result lead situation wherein personal injury, death severe property environmental injury could occur.
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Please note that data specifications subject change without notice. trademarks products companies mentioned this datasheet belong their respective owners. This product incorporates SuperFlash® technology licensed From
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