Qualification Accordance With AEC-Q100 Qualified Automotive Appli

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Qualification Accordance With AEC-Q100 Qualified Automotive Appli

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SN74LVC2G08 DUAL INPUT POSITIVE GATE
Qualification Accordance With
AEC-Q100 Qualified Automotive Applications Customer-Specific Configuration Control Supported Along With Major-Change Approval Supports Operation Inputs Accept Voltages Power Consumption, 10-µA ±24-mA Output Drive Typical VOLP (Output Ground Bounce) <0.8 25°C Typical VOHV (Output Undershoot) 25°C
Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds JESD Class Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 1000-V Charged-Device Model (C101)
PACKAGE (TOP VIEW)
Contact factory details. Q100 qualification data available request.
description/ordering information
This dual 2-input positive-AND gate designed 1.65-V 5.5-V operation. SN74LVC2G08 performs Boolean function positive logic. This device fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through device when powered down. ORDERING INFORMATION
-40°C 85°C SSOP PACKAGE Tape reel ORDERABLE PART NUMBER SN74LVC2G08IDCTRQ1 TOP-SIDE C08_
VSSOP Tape reel C08_ Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. DCT: actual top-side marking three additional characters that designate year, month, assembly/test site. DCU: actual top-side marking additional character that designates assembly/test site. Product Preview FUNCTION TABLE (each gate) INPUTS OUTPUT
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2004, Texas Instruments Incorporated
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G08 DUAL INPUT POSITIVE GATE
logic diagram (positive logic)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Voltage range applied output high-impedance power-off state, (see Note -0.5 Voltage range applied output high state, (see Notes -0.5 Input clamp current, Output clamp current, Continuous output current, Continuous current through ±100 Package thermal impedance, (see Note package 220°C/W package 227°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output current ratings observed. value provided recommended operating conditions table. package thermal impedance calculated accordance with JESD 51-7.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G08 DUAL INPUT POSITIVE GATE
recommended operating conditions (see Note
Operating Supply voltage Data retention only 1.65 1.95 1.65 1.95 1.65 High-level output current 1.65 Low-level output current 0.15 Input transition rise fall rate 1.65 0.65 0.35 ns/V UNIT
High-level input voltage
Low-level input voltage
Input voltage Output voltage
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G08 DUAL INPUT POSITIVE GATE
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER -100 Ioff inputs GND, input Other inputs TEST CONDITIONS 1.65 1.65 1.65 1.65 1.65 VCC-0.1 0.45 0.55 0.55 UNIT
typical values 25°C.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) 0.15 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN74LVC2G08 DUAL INPUT POSITIVE GATE
PARAMETER MEASUREMENT INFORMATION
VLOAD Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD
From Output Under Test (see Note
LOAD CIRCUIT INPUTS 0.15 tr/tf VCC/2 VCC/2 VCC/2 VLOAD 0.15 0.15 Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS Output Waveform (see Note Output Control tPZL tPZH VOLTAGE WAVEFORMS SETUP HOLD TIMES tPLZ VLOAD/2 tPHZ Data Input
Output Waveform VLOAD (see Note
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time, with transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS049B 1999 REVISED OCTOBER 2002
(R-PDSO-G8)
0,30 0,15
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,13
0,15 2,90 2,70 4,25 3,75
INDEX AREA
0,10 0,00 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion Falls within JEDEC MO-187 variation
3,15 2,75
Gage Plane 0,25 0,60 0,20
1,30
Seating Plane 0,10 4188781/C 09/02
POST OFFICE 655303
DALLAS, TEXAS 75265
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Qualification Accordance With AEC-Q100 Qualified Automotive Appli

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