3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) Digitally programma

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3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) Digitally programma

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PDU138
3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138)
Digitally programmable delay steps Monotonic delay-versus-address variation Precise stable delays Input outputs fully interfaced buffered fan-out capability Fits standard 16-pin socket Auto-insertable
data delay devices, inc.
PACKAGES
PDU138-xx PDU138-xxM
Military
FUNCTIONAL DESCRIPTION
PDU138-series device 3-bit digitally programmable delay line. delay, TDA, from input (IN) output (OUT) depends address code (A2-A0) according following formula: TINC
DESCRIPTIONS
Delay Line Input Non-inverted Output Address Address Address Output Enable Volts Ground
where address code, TINC incremental delay device, inherent delay device. incremental delay specified dash number device range from 0.5ns through 50ns, inclusively. enable (EN/) held during normal operation. When this signal brought HIGH, forced into state. address latched must remain asserted during normal operation.
SERIES SPECIFICATIONS
Total programmed delay tolerance: 1ns, whichever greater Inherent delay (TD0): typical (OUT) Setup time propagation delay: Address input setup (TAIS): 12ns typ. Disable output delay (TDISO): 12ns typ. Operating temperature: Temperature coefficient: 100PPM/°C (excludes TD0) Supply voltage VCC: 5VDC Supply current: ICCH 45ma ICCL 20ma Minimum pulse width: total delay
DASH NUMBER SPECIFICATIONS
Part Number PDU138-.5 PDU138-1 PDU138-2 PDU138-5 PDU138-10 PDU138-12 PDU138-15 PDU138-20 PDU138-40 PDU138-50 Incremental Delay Step (ns) Total Delay Change (ns) 14.0 17.5
NOTE: dash number between shown also available. 2002 Data Delay Devices
#02004
5/6/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU138
APPLICATION NOTES
ADDRESS UPDATE
PDU138 memory device. such, special precautions must taken when changing delay address order prevent spurious output signals. timing restrictions shown Figure After last signal edge delayed appeared pin, minimum time, TOAX, required before address lines change. This time given following relation: TOAX i-1) TINC where address codes, respectively. Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TOAX elapsed. similar situation occurs when using signal disable output while active. this case, unit must held disabled state until device able "clear" itself. This achieved holding signal high signal time given TDISH TINC Violation this constraint may, depending history input signal, cause spurious signals appear pin. possibility spurious signals persists until required TDISH elapsed.
INPUT RESTRICTIONS
There three types restrictions input pulse width period listed Characteristics table. recommended conditions those which delay tolerance specifications monotonicity guaranteed. suggested conditions those which signals will propagate through unit without significant distortion. absolute conditions those which unit will produce some type output given input. When operating unit between recommended absolute conditions, delays deviate from their values frequency. However, these deviations will remain constant from pulse pulse input pulse width period remain fixed. other words, delay unit exhibits frequency pulse width dependence when operated beyond recommended conditions. Please consult technical staff Data Delay Devices your application specific high-frequency requirements. Please note that increment tolerances listed represent design goal. Although most delay increments will fall within tolerance, they guaranteed throughout address range unit. Monotonicity however, guaranteed over addresses.
A2-A0 TAENS TENIS
TOAX TAIS
PWIN
TDISH
PWOU
TDISO
Figure Timing Diagram
#02004
5/6/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU138
DEVICE SPECIFICATIONS
TABLE CHARACTERISTICS
PARAMETER Total Programmable Delay Inherent Delay Disable Output Delay Address Enable Setup Time Address Input Setup Time Enable Input Setup Time Output Address Change Disable Hold Time Absolute Input Period Suggested Recommended Absolute Input Pulse Width Suggested Recommended SYMBOL TDISO TAENS TAIS TENIS TOAX TDISH PERIN PERIN PERIN PWIN PWIN PWIN 12.0 UNITS TINC
12.0 12.0 Text Text
TABLE ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage Input Voltage Storage Temperature Lead Temperature SYMBOL TSTRG TLEAD -0.3 -0.3 VDD+0.3 UNITS NOTES
TABLE ELECTRICAL CHARACTERISTICS
70C, 4.75V 5.25V) PARAMETER High Level Output Voltage Level Output Voltage High Level Output Current Level Output Current High Level Input Voltage Level Input Voltage Input Clamp Voltage Input Current Maximum Input Voltage High Level Input Current Level Input Current Short-circuit Output Current Output High Fan-out Output Fan-out SYMBOL IIHH 0.35 UNITS Unit Load NOTES MIN, MIN, MIN, MIN,
-1.0 20.0
-1.2 -0.6 -150 12.5
MIN, MAX, 7.0V MAX, 2.7V MAX, 0.5V
#02004
5/6/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013
PDU138
PACKAGE DIMENSIONS
.410
.820
.020
.280 .150 ±.030
.012 .300
.018 .700
.100
Commercial (PDU138-xx)
.410
.820
.020
.320 .150 ±.030
.012 .300
.018 .700
.100
Military (PDU138-xxM)
#02004
5/6/02
DATA DELAY DEVICES, INC.
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
PDU138
DELAY LINE AUTOMATED TESTING
TEST CONDITIONS
INPUT: Ambient Temperature: Supply Voltage (Vcc): 5.0V 0.1V Input Pulse: High 3.0V 0.1V 0.0V 0.1V Source Impedance: Max. Rise/Fall Time: Max. (measured between 0.6V 2.4V Pulse Width: PWIN Total Delay Period: PERIN Total Delay OUTPUT: Load: Cload: Threshold: FAST-TTL Gate 1.5V (Rising Falling)
NOTE: above conditions test only restrict operation device.
COMPUTER SYSTEM
PRINTER
PULSE GENERATOR TRIG DEVICE UNDER TEST (DUT) TRIG TIME INTERVAL COUNTER
Test Setup
PERIN PWIN TRISE INPUT SIGNAL
2.4V 1.5V 0.6V
TFALL
2.4V 1.5V 0.6V
TDAF
TDAR OUTPUT SIGNAL
1.5V
1.5V
Timing Diagram Testing
#02004
5/6/02
DATA DELAY DEVICES, INC.
Prospect Ave. Clifton, 07013

3-BIT PROGRAMMABLE DELAY LINE (SERIES PDU138) Digitally programma

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