Integrated High Performance Quad UARTs, 8-bit Local Bus/Parallel Port.
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OXmPCI954 DATA SHEET
Integrated High Performance Quad UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.
Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR# Arbitrary trigger levels receiver transmitter FIFO interrupts automatic in-band out-of-band flow control Infra-red (IrDA) receiver transmitter operation 9-bit data framing, well 5,6,7 bits Detection data receiver FIFO Global Interrupt Status readable FIFO levels facilitate implementation efficient device drivers. Local registers provide status/control device functions. multi-purpose pins, which configured input interrupt pins `wake-up'. Auto-detection wide range optional Microwirecompatible EEPROMs, re-configure device parameters. Function access, pre-configure each function prior handover generic device drivers. Operation memory mapping. 3.3V operation tolerance selected I/Os) Extended Operating Temp. Range -40C 105C 160-pin LQFP 176-pin VBGA package
Software compatible with OX16PCI954 Four 16C950 High performance UART channels 8-bit Pass-through Local (PCI Bridge) IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver) Efficient 32-bit, 33MHz, Multi-function target-only controller, fully compliant Local specification 3.0, Power Management Specification miniPCI Modes (with CLKRUN# D3cold support miniPCI modes) UARTs fully software compatible with 16C550-type devices. UART operation external clock source. 20MHz with crystal oscillator. Baud rates 60Mbps external clock mode 15Mbps asynchronous mode. 128-byte deep FIFO transmitter receiver Flexible clock prescaler, from 31.875 Automated in-band flow control using programmable Xon/Xoff both directions
DESCRIPTION
OXmPCI954 single chip solution miniPCI based serial parallel expansion add-in cards. dual function device, where function offers four ultra-high performance OX16C950 UARTs, function configurable either 8-bit Local bidirectional parallel port. Each UART channel OXmPCI954 fastest available PC-compatible UART, offering data rates 15Mbps 128-byte deep transmitter receiver FIFOs. deep FIFOs reduce overhead allow utilisation higher data rates. Each UART channel software compatible with widely used industry-standard 16C550 devices (and compatibles), well OX16C95x family high performance UARTs. addition increased performance FIFO size, UARTs also provide full OX16C95x enhanced features including automated in-band flow control, readable FIFO levels etc. enhance device driver efficiency reduce interrupt latency, internal UARTs have multi-port features such shadowed FIFO fill levels, global interrupt source register Good-Data Status, readable four adjacent DWORD registers visible logical functions space memory space. Expansion serial cards beyond four channels possible using 8-bit pass-through Local function. addressable space increased bytes, divided into four chip-select regions. This flexible expansion scheme caters cards with serial ports using external 16C950, 16C952, 16C954 compatible devices, composite applications such combined serial parallel port expansion cards. Serial port cards with ports with serial ports parallel port) designed without redefining device timing parameters. parallel port IEEE 1284 compliant SPP/EPP/ parallel port that fully supports existing Centronics interface. parallel port enabled place Local Bus. external transceiver required parallel port operation. applications that require local bus, parallel port, card designers assign Subsystem Vendor Subsystem directly using input pins. full flexibility, default configuration register values overwritten using optional Microwirecompatible serial EEPROM. This EEPROM also used provide function access pre-configure each UART into enhanced modes pre-configure devices local bus/parallel port, prior configuration accesses before control handed (generic) device drivers.
Oxford Semiconductor Ltd. External-Free Release Milton Park, Abingdon, Oxon, OX14 4SH, Tel: (0)1235 824900 Fax: +44(0)1235 821141
Oxford Semiconductor 2005 OXmPCI954 DataSheet DS-0019 June 2005
OXFORD SEMICONDUCTOR LTD.
OXmPCI954
REVISION HISTORY
2005 2005 DATE 17/12/2002 11/02/2003 23/06/2003 07/08/2003 12/1/2005 8/6/2005 REASON CHANGE SUMMARY CHANGE Preliminary DataSheet Revised Pin-out, Chip-naming Specified device modes added features supported device. Added Extended Operating temperature range -40C 105C. Corrected Information Diagram SUBVEN mode. Revisions additional 176-pin layout (was 160-pin flat pack) Revision additional green order code 160-pin LQFP layout
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OXmPCI954
TABLE CONTENTS
PERFORMANCE COMPARISON. OXMPCI954 DEVICE MODES. BLOCK DIAGRAM INFORMATION-160-PIN LQFP
MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH OX16PCI954. ENHANCED MODES OPERATION. DESCRIPTIONS. MODES (SOFTWARE) BACKWARDS COMPATIBLE WITH OX16PCI954. ENHANCED MODES OPERATION. DESCRIPTIONS.
INFORMATION-176-PIN VBGA
7.2.1 7.3.1 7.3.2 7.3.3 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.6.1 7.6.2 7.10
CONFIGURATION OPERATION TARGET CONTROLLER.
OPERATION CONFIGURATION SPACE CONFIGURATION SPACE REGISTER MAP. ACCESSING LOGICAL FUNCTIONS ACCESS INTERNAL UARTS. ACCESS 8-BIT LOCAL BUS. ACCESS PARALLEL PORT ACCESSING LOCAL CONFIGURATION REGISTERS. LOCAL CONFIGURATION CONTROL REGISTER `LCC' (OFFSET 0X00) MULTI-PURPOSE CONFIGURATION REGISTER `MIC' (OFFSET 0X04) LOCAL TIMING PARAMETER REGISTER `LT1' (OFFSET 0X08): LOCAL TIMING PARAMETER REGISTER `LT2' (OFFSET 0X0C): UART RECEIVER FIFO LEVELS `URL' (OFFSET 0X10). UART TRANSMITTER FIFO LEVELS `UTL' (OFFSET 0X14). UART INTERRUPT SOURCE REGISTER `UIS' (OFFSET 0X18). GLOBAL INTERRUPT STATUS CONTROL REGISTER `GIS' (OFFSET 0X1C) INTERRUPTS. POWER MANAGEMENT POWER MANAGEMENT FUNCTION POWER MANAGEMENT FUNCTION UNIQUE OPTION FUNCTION MINIPCI SUPPORT ENHANCED MODES ONLY STANDALONE MODE DEVICE DRIVERS OPERATION MODE SELECTION MODE. MODE. EXTENDED MODE MODE. MODE. MODE. REGISTER DESCRIPTION TABLES RESET CONFIGURATION HARDWARE RESET External-Free Release Page
8.1.1 8.1.2 8.1.3 8.1.4 8.1.5 8.1.6 8.3.1
INTERNAL OX16C950 UARTS
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8.3.2 SOFTWARE RESET TRANSMITTER RECEIVER FIFOS 8.4.1 FIFO CONTROL REGISTER `FCR' LINE CONTROL STATUS. 8.5.1 FALSE START DETECTION. 8.5.2 LINE CONTROL REGISTER `LCR'. 8.5.3 LINE STATUS REGISTER `LSR' INTERRUPTS SLEEP MODE. 8.6.1 INTERRUPT ENABLE REGISTER `IER'. 8.6.2 INTERRUPT STATUS REGISTER `ISR'. 8.6.3 INTERRUPT DESCRIPTION 8.6.4 SLEEP MODE MODEM INTERFACE 8.7.1 MODEM CONTROL REGISTER `MCR'. 8.7.2 MODEM STATUS REGISTER `MSR' OTHER STANDARD REGISTERS 8.8.1 DIVISOR LATCH REGISTERS `DLL DLM'. 8.8.2 SCRATCH REGISTER `SPR' AUTOMATIC FLOW CONTROL. 8.9.1 ENHANCED FEATURES REGISTER `EFR'. 8.9.2 SPECIAL CHARACTER DETECTION 8.9.3 AUTOMATIC IN-BAND FLOW CONTROL 8.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL 8.10 BAUD RATE GENERATION. 8.10.1 GENERAL OPERATION 8.10.2 CLOCK PRESCALER REGISTER `CPR'. 8.10.3 TIMES CLOCK REGISTER `TCR'. 8.10.4 EXTERNAL CLOCK MODE. 8.10.5 CRYSTAL OSCILLATOR CIRCUIT 8.11 ADDITIONAL FEATURES 8.11.1 ADDITIONAL STATUS REGISTER `ASR' 8.11.2 FIFO FILL LEVELS `TFL RFL' 8.11.3 ADDITIONAL CONTROL REGISTER `ACR'. 8.11.4 TRANSMITTER TRIGGER LEVEL `TTL' 8.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL `RTL' 8.11.6 FLOW CONTROL LEVELS `FCL' `FCH' 8.11.7 DEVICE IDENTIFICATION REGISTERS. 8.11.8 CLOCK SELECT REGISTER `CKS'. 8.11.9 NINE-BIT MODE REGISTER `NMR' 8.11.10 MODEM DISABLE MASK `MDM' 8.11.11 READABLE `RFC'. 8.11.12 GOOD-DATA STATUS REGISTER `GDS'. 8.11.13 PORT INDEX REGISTER `PIX'. 8.11.14 CLOCK ALTERATION REGISTER `CKA'
LOCAL
OVERVIEW OPERATION CONFIGURATION PROGRAMMING.
10.1 OPERATION MODE SELECTION 10.1.1 MODE 10.1.2 MODE. 10.1.3 MODE 10.1.4 MODE 10.2 PARALLEL PORT INTERRUPT DS-0019 External-Free Release Page
BIDIRECTIONAL PARALLEL PORT.
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OXmPCI954
10.3 REGISTER DESCRIPTION. 10.3.1 PARALLEL PORT DATA REGISTER `PDR' 10.3.2 FIFO ADDRESS 10.3.3 DEVICE STATUS REGISTER `DSR' 10.3.4 DEVICE CONTROL REGISTER `DCR'. 10.3.5 ADDRESS REGISTER `EPPA' 10.3.6 DATA REGISTERS `EPPD1-4' 10.3.7 DATA FIFO 10.3.8 TEST FIFO 10.3.9 CONFIGURATION REGISTER 10.3.10 CONFIGURATION REGISTER 10.3.11 EXTENDED CONTROL REGISTER `ECR'.
11.1 SPECIFICATION 11.1.1 ZONE HEADER 11.1.2 ZONE LOCAL CONFIGURATION REGISTERS. 11.1.3 ZONE IDENTIFICATION REGISTERS 11.1.4 ZONE CONFIGURATION REGISTERS 11.1.5 ZONE POWER MANAGEMENT DATA (AND DATA_SCALE ZONE) 11.1.6 ZONE FUNCTION ACCESS
SERIAL EEPROM
12.1
OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
13.1 13.2 13.3
ELECTRICAL CHARACTERISTICS.
LOCAL BUS. SERIAL PORTS
15.1 15.2
TIMING WAVEFORMS. PACKAGE INFORMATION.
160-PIN LQFP. 176-PIN VBGA
ORDERING INFORMATION
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PERFORMANCE COMPARISON
Feature Internal serial channels Integral IEEE 1284 EPP/ECP parallel port Multi-function device Support Power Management Zero wait-state write operation available Local interrupt pins DWORD access UART Interrupt Source Registers FIFO Levels Good-Data status Full Plug Play with external EEPROM Subsystem Vendor Subsystem with external EEPROM External baud rate clock baud rate normal mode baud rate clock mode FIFO depth Sleep mode Auto Xon/Xoff flow Auto CTS#/RTS# flow Auto DSR#/DTR# flow interrupt thresholds interrupt thresholds flow control thresholds Transmitter empty interrupt Readable status flow control Readable FIFO levels Clock prescaler options Rx/Tx disable Software reset Device 9-bit data frames RS485 buffer enable Infra-red (IrDA)
OXmPCI954
yes1 Mbps Mbps
16C554 Bridge Kbps
16C654 Bridge Mbps
Table OXmPCI954 performance compared with Bridge generic UART combinations
Note Zero wait-state applies only internal UARTs (after assertion DEVSEL#). Read operation incurs wait state.
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Improvements OXmPCI954 over discrete solutions
Higher degree integration: OXmPCI954 device offers four internal 16C950 highperformance UARTs 8-bit Local Bi-directional parallel port. Multi-function device: OXmPCI954 multi-function device enable users load individual device drivers internal serial ports, drivers peripheral devices connected Local drivers internal parallel port. Quad Internal OX16C950 UARTs OXmPCI954 device contains four ultra-high performance UARTs, which increase driver efficiency using features such 128-byte deep transmitter receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt flow control trigger levels readable FIFO levels. Data rates 60Mbps. Improved access timing: Access internal UARTs, require zero wait states. read transaction from internal UART complete within five clock cycles write transaction internal UART complete within four clock cycles. Reduces interrupt latency: OXmPCI954 device offers shadowed FIFO levels Interrupt status registers internal UARTs, pins. This reduces device driver interrupt latency. Power management: OXmPCI954 device complies with Power Management Specification Microsoft Communications Device-class Power Management Specification (2000). Both functions offer extended capabilities Power Management. This achieves significant power savings enabling device drivers power down functions. function this through switching channel clock, power state Wake-up (PME# generation) requested either functions. function this inputs UARTs power-state modem line inputs UARTs power-state function this MIO[2] input. Optional EEPROM: OXmPCI954 device reconfigured from external EEPROM, end-user's requirements. However, this normally required many applications default values sufficient typical applications. overrun detection mechanism built into eeprom controller prevents system from `hanging' incorrectly programmed eeprom. Subsystem Subsystem Vendor some cases Subsystem Subsystem Vendor input pins.
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OXMPCI954 DEVICE MODES
OXmPCI954 supports several modes operation. modes device (software) backwards compatible with OX16PCI954 device. There further modes that enhanced modes, which offer additional features over those available backwards compatible modes. Then, there standalone mode that allows synchronous local access internal UARTs, without form transactions. These modes summarized following table. Device Mode Mode Selection MODE(2:0) MODE(2:0) MODE(2:0) MODE(2:0) MODE(2:0) MODE(2:0) MODE(2:0) MODE(2:0) Functionality Function QUAD Uarts Function 8-bit Local Function QUAD Uarts Function Parallel Port Function QUAD Uarts Subsys ID/Subsys Vendor Device Pins Function QUAD Uarts (Unique BARs) Function 8-bit Local Function QUAD Uarts Function 8-bit Local Function QUAD Uarts Function Parallel Port TestMode (Reserved). Standalone Mode Backwards Compatible Enhanced Modes Backwards Compatible* Backwards Compatible* Backwards Compatible* Enhanced Mode Enhanced Mode Enhanced Mode
OXmPCI954 direct `drop-in' replacement part OX16PCI954 owing small pinout change voltage. device only compatible.
Enhanced Modes, following additional features made available over underlying functionality device.
88/M15 (MIO[11]) re-defined PCI/miniPCI Mode Selection Pin. Functionality normally associated with MIO[11] longer available. This results pins MIO[10:0] serving Multi-purpose pins. Function Function interrupts assert INTA# default). Local Registers provide additional Controls Status Indication. Function option allow each UART separately addressable Base Address Register Space) This option exercised device pins (MODE 011) using external EEPROM specified field local registers. Function Function Power Management Registers indicate Compatibility Power Management Specification Each function implements Power Management Data/Data Scale fields, returning user defined data. Availability Additional EEPROM Zones Power Management Data Zone Function Access Zone. Specifically MiniPCI Selection (Pin 88/M15 Enhanced Modes) Device INTB#' re-defined CLKRUN# pin. Compliant Mobile Design Guide revision modes (Pin 88/M15 Enhanced Modes) INTB# unused interrupt line. Device supports PME# generation from D3cold state preserves PME# context. This compliant Mini Specification, revision
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BLOCK DIAGRAM
MODE[2:0] FIFOSEL MIO[11]* Config. Interface SOUT{3:0] SIN[3:0]
MIO[11] mode selection pin, Enhanced Mode.
Function Quad UARTs
RTS[3:0] DTR{3:0] CTS{3:0] DSR{3:0]
AD[31:0] C/BE[3:0]#
Interface Data Control
DCD{3:0] RI{3:0]
PCI_CLK FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RESET# INTA# INTB#/CLKRUN# PME# (miniPCI) Interface
Interrupt Logic
Pins
MIO[11:0]*
PD[7:0]
ACK# BUSY Parallel Port SLCT ERR# SLIN# INIT# AFD# XTLI XTLO Clock Baud Rate Generator STB#
Function
UART_Clk_Out Local_Bus
LBA7:0] LBCS[3:0] LBD[7:0] Local LBWR#
EE_DI EEPROM Interface
EE_CS EE_CK EE_DO
LBRD# LBRST
DATA_DIR
OXmPCI954 Block Diagram
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INFORMATION-160-PIN LQFP
Modes (Software) Backwards Compatible with OX16PCI954. Mode `001': Quad UARTs Parallel Port
MODE[2:0]
SLCT ERR# SLIN# INIT# AFD# STB# PDOUT MIO8 MIO9 MIO10 MIO11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
Mode `000': Quad UARTs 8-bit Local
MODE[2:0]
LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# LBCLK LBA4 LBA5 LBA6 LBA7 LBDOUT LBD0 LBD1 LBD2 LBD3 LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 MIO11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
BUSY ACK# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 INTA# INTB# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
connect these pins:
Mode `010': Quad UARTs Assignable SubSystem Subsystem Vendor
MODE[2:0]
Sub_V_ID2 Sub_V_ID3 Sub_ID12 Sub_ID13 Sub_ID14 Sub_ID15 Sub_V_ID4 Sub_V_ID5 Sub_V_ID6 Sub_V_ID7 Sub_V_ID8 Sub_V_ID9 Sub_V_ID10 Sub_V_ID11 Sub_V_ID12 Sub_V_ID13 Sub_V_ID154 Sub_V_ID15 Sub_ID8 Sub_ID9 Sub_ID10 Sub_ID11 SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
Sub_V_ID1 Sub_V_ID0 Sub_ID7 Sub_ID6 Sub_ID5 Sub_ID4 Sub_ID3 Sub_ID2 Sub_ID1 Sub_ID0 INTA# INTB# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
connect these pins: 102,108,111,112,123,124
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AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
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AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
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Enhanced Modes Operation. Mode `100' QUAD UARTs 8-BIT Local Bus.
MODE[2:0]
Mode `011': Quad UARTs (Unique BARs) 8-bit Local
MODE[2:0]
LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# LBCLK LBA4 LBA5 LBA6 LBA7 LBDOUT LBD0 LBD1 LBD2 LBD3 LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 PCI/mini-PCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# LBCLK LBA4 LBA5 LBA6 LBA7 LBDOUT LBD0 LBD1 LBD2 LBD3 LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 PCI/mini-PCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB#/CLKRUN# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB#/CLKRUN# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2 EE_DI EE_CK
Mode `101' QUAD UARTs Parallel Port.
MODE[2:0]
SLCT ERR# SLIN# INIT# AFD# STB# PDOUT MIO8 MIO9 MIO10 PCI/MiniPCI SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL
STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
Mode `111' Standalone QUAD UART Mode
MODE[2:0]
UART_addr(2) UART_addr(3) UART_addr(4) Write# Read# Chip_Select# UART_data(0) UART_data(1) UART_data(2) UART_data(3) UART_data(4) UART_data(5) UART_data(6) UART_data(7) SIN3 RI3# DCD3# DSR3# CTS3# DTR3# RTS3#
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL
STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
BUSY ACK# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 INTA# INTB#/CLKRUN# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# UART_Ck_Out SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 TEST EE_DI EE_CK
UART_addr(1) UART_addr(0) Read_Data_Control Uart_Interrupt RST# Buffered_CLK
OXmPCI954-LQ-A
SOUT3 SOUT2 RTS2# DTR2# CTS2# DSR2# DCD2# RI2# SIN2 SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode0 Mode1 Mode2
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
connect these pins:
connect these pins:
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OXmPCI954
Descriptions
actual pinouts OXmPCI954 device (for various modes), please refer sections "Pin Information". mini-PCI Interface Mode 000, 001, 010, 011, 100, 139, 140, 141, 143, 144, 145, 147, 148, 151, 152, 155, 156, 157, 160, 149,
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed Address/Data
P_I/O P_I/O P_OD P_OD P_I/O P_OD
C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# Uart Interrupt INTB# CLKRUN# PME#
Command/Byte enable system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select system reset interrupt (All modes except Standalone Mode) Uart Interrupt (Standalone Mode Only) interrupt (All modes except Mini-PCI Mode) ClockRun# Line (mini-PCI modes Only) Power management event
NOTE interface utilised Standalone Mode. this mode, inputs tied their inactive states.
Serial port pins Modes
Dir1
Name FIFOSEL
O(h)
SOUT[3:0] IrDA_Out[3:0]
Description FIFO select. backward compatibility with 16C550, 16C650 16C750 devices UARTs' FIFO depth when FIFOSEL low. FIFO size increased when FIFOSEL high. unlatched state this readable software. FIFO size also setting FCR[5] when LCR[7] set, putting device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] corresponding channel enhanced mode UART serial data inputs UART IrDA data input when IrDA mode enabled (see above) Active-low modem data-carrier-detect input
I(h) I(h)
SIN[3:0] IrDA_In[3:0] DCD[3:0]#
I(h)
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Serial port pins Modes
Dir1 O(h)
Name DTR[3:0]#
Description Active-low modem data-terminal-ready output. automated DTR# flow control enabled, DTR# asserted deasserted receiver FIFO reaches falls below programmed thresholds, respectively. RS485 half-duplex mode, DTR# programmed reflect state transmitter empty automatically control direction RS485 transceiver buffer (see register ACR[4:3]) Transmitter clock (baud rate generator output). isochronous applications, transmitter clock asserted DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. automated RTS# flow control enabled, RTS# deasserted reasserted whenever receiver FIFO reaches falls below programmed thresholds, respectively. Active-low modem clear-to-send input. automated CTS# flow control enabled, upon deassertion CTS# pin, transmitter will complete current character enter idle mode until CTS# reasserted. Note: flow control characters transmitted regardless state CTS# pin. Active-low modem data-set-ready input. automated DSR# flow control enabled, upon deassertion DSR# pin, transmitter will complete current character enter idle mode until DSR# reasserted. Note: flow control characters transmitted regardless state DSR# External receiver clock isochronous applications. Rx_Clk_In selected when CKS[1:0] `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock used transmitter (and indirectly receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input 20MHz. External clock 60MHz.
O(h)
485_En[3:0]
O(h) O(h)
Tx_Clk_Out[3:0] RTS[3:0]#
I(h)
CTS[3:0]#
I(h)
DSR[3:0]#
I(h) I(h) I(h)
Rx_Clk_In[3:0] RI[3:0]# Tx_Clk_In[3:0] XTLO XTLI
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
8-bit local Mode 000, 011, 113, 114, 115, 104, 105, 106, 119, 120, 121, 100, Parallel port Mode 001,
Dir1 O(h) O(h) O(h) O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock drive external UARTs connected local bus. enabled disabled software. Local active-high reset Local active-low reset Local data enable. This used external transceivers; high when LBD[7:0] output mode when they input mode. Buffered clock. enabled disabled software Local active-low Chip-Select (Intel mode) Local active-low Data-Strobe (Motorola mode) Local active-low write-strobe (Intel mode) Local Read-not-Write control (Motorola mode) Local active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local address signals Local data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# asserted (low) peripheral indicate that successful data transfer taken place. Identical function ACK# (EPP mode). Paper Empty. Activated printer when runs paper. Busy (SPP mode). BUSY asserted (high) peripheral when ready accept data Wait (EPP mode). Handshake signal interlocked IEEE 1284 compliant cycles. Select (SPP mode). Asserted host select peripheral Address strobe (EPP mode) provides address read write strobe Peripheral selected. Asserted peripheral when selected. Error. Held peripheral during error condition. Initialise (SPP mode). Commands peripheral initialise. Initialise (EPP mode). Identical function mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read write strobe
I(h) I(h) I(h) I(h)
INTR# BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
OD(h) O(h)
I(h) I(h) OD(h) O(h) OD(h) O(h)
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Parallel port Mode 001, Dir1 OD(h) O(h) 100, I/O(h) Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used peripheral latch data currently available PD[7:0] Write (EPP mode). Indicates write cycle when read cycle when high Parallel data Parallel Port data enable. This should used external transceivers signalling; high when PD[7:0] output mode when they input mode.
Subsystem Subsystem Vendor pins Mode Dir1 Name Sub_ID[15:0] Sub_V_ID[15:0]
Description Subsystem After reset subsystem Function will default value assigned these pins Subsystem Vendor After reset subsystem vendor Function will default value assigned these pins.
Standalone Mode Mode 116, 119, 120, 121, 100,
Dir1 I(h) I(h) I(h) I(h) I(h) I/O(h)
Name Buffered_CLK Reset# Chip Select# Write Strobe# Read Strobe# Read Data Control# UART_Address[4:0] UART Data[7:0} Uart Interrupt
Description Clock drive device. Device Reset. Active Chip Select Signal Active Write Signal Active Read Signal Active Controls Bidirectional Buffers Uart Data (read/writes) data reads, writes. Address[4:3] Uart Selection Address[2:0] Uart register Selection Uart Write Data/Read Data Interrupt line. Active UART interrupts.
DS-0019
External-Free Release
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Multi-purpose External interrupt pins Mode Dir1 000,011,100 001/101 I/O(h) I/O(h) I/O(h) I/O(h)
Name MIO0 MIO1 MIO2 PME_In MIO[10:3]
Description Multi-purpose drive high low, assert interrupt Output Driving `0'. left No-connect. Multi-purpose drive high low, assert interrupt long LCC[6:5] "00"). Output Driving (when LCC[6:5] `00') left No-Connect. Multi-purpose When LCC[7] this drive high low, assert interrupt. Input power management event. When LCC[7] this input assert function PME#. Multi-purpose pins. drive high low, assert interrupt
125, 126, 127, 128,
Multi-purpose External interrupt pins Mode Dir1 000,001,010 011/100/101 I/O(h) I(h)
Name MIO[11] PCI/miniPCI
Description Multi-purpose pin. drive high low, assert interrupt PCI/miniPCI selection. Tied mode. Tied High miniPCI mode.
NOTE pins unused Standalone Mode operation must tied
EEPROM pins Mode
Dir1 IU(h)
Name EE_CK EE_CS EE_DI
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data with internal pull-up. When serial EEPROM connected, this should pulled using 1-10k resistor. When EEPROM used internal pull-up sufficient. connected external EEPROM's EE_DO used) EEPROM data out. connected external EEPROM's EE_DI used)
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Miscellaneous pins Mode 44,45
Dir1
Name MODE[2:0]
Description Mode selector Pins Function QUAD UART. Function 8bit Local OX16PCI954 Backwards Compatible Mode. Function QUAD UART. Function Parallel Port OX16PCI954 Backwards Compatible Mode. Function QUAD UART. Function unusable local pins used assign Subsystem Subsystem Vendor function OX16PCI954 Backwards Compatible Mode. Function QUAD UART (Uarts Unique BARs) Function 8bit Local Enhanced Mode. Function QUAD UART. Function 8bit Local Enhanced Mode. Function QUAD UART. Function Parallel Port Enhanced Mode. 110: Reserved Standalone QUAD UART mode.
Power ground 110, 118, 154, 103, 109, 117, 136, 142, 146, 153,
Power Supply (3.3V) Power Supply Ground (0V)
Table Descriptions
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OXFORD SEMICONDUCTOR LTD.
Note Direction key: P_I/O P_OD I(h) IU(h) I/O(h) O(h) OD(h) input output PCITristates bi-directional open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain connect Ground 3.3V power 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, tolerant LVTTL level, tolerant LVTTL level, tolerant Standard Output tolerant (High Voltage BI-Direct output mode) Standard Open-drain Output tolerant (High Voltage BI-Direct open-drain mode)
OXmPCI954
DS-0019
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
INFORMATION-176-PIN VBGA
Modes (Software) Backwards Compatible with OX16PCI954.
Mode `000': Quad UARTs 8-bit Local
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 RTS2# DCD2# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB# RST# INTA# MIO1 MIO0 MIO2 MIO3 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3# DTR2# RI2# MIO7 LBRST# LBA1 LBCS2# LBA6 LBD0 LBD7 SIN3 CTS3# SOUT2 DSR2# LBRST LBA2 LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# CTS2# LBA3 LBCS0# LBCS1# LBRD# LBA5 LBD1 LBD5 MIO8 MIO11 DCD3# DSR3# SOUT3
connect these pins:
Mode `001': Quad UARTs Parallel Port
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 RTS2# DCD2# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB# RST# INTA# MIO1 MIO2 MIO3 MIO4 MIO5 MIO6 STB# MIO9 DTR3# DTR2# RI2# MIO7 BUSY AFD# SIN3 CTS3# SOUT2 DSR2# ACK# SLCT SLIN# PDOUT MIO10 RI3# RTS3# CTS2# ERR# INIT# MIO8 MIO11 DCD3# DSR3# SOUT3
connect these pins: DS-0019 External-Free Release Page
OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Mode `010': Quad UARTs Assignable SubSystem Subsystem Vendor
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 RTS2# DCD2# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB# RST# INTA# SUB_ID1 SUB_ID0 SUB_ID2 SUB_ID3 SUB_ID4 SUB_ID5 SUB_ID6 SUB_V_ID0 SUB_ID15 SUB_V_ID7 SUB_ID7 SUB_V_ID3 SUB_ID12 SUB_ID13 SUB_V_ID5 SUB_V_ID9
SUB_V_ID1 SUB_V_ID2 SUB_ID14 SUB_V_ID6 SUB_V_ID4 SUB_V_ID11
SUB_V_ID10 SUB_V_ID8 SUB_V_ID12 SUB_ID9 DTR3# DTR2# RI2#
SUB_V_ID15 SUB_V_ID14 SUB_V_ID13 SIN3 CTS3# SOUT2 DSR2# SUB_ID10 RI3# RTS3# CTS2# SUB_ID8 SUB_ID11 DCD3# DSR3# SOUT3
connect these pins:
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Enhanced Modes Operation. 8-bit Local
Mode `011': Quad UARTs (Unique BARs)
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27
AD30 AD28
AD29 AD31 PME#
INTB#/ CLKRUN# RST# INTA#
MIO1 MIO0 MIO2 MIO3
MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3#
MIO7 LBRST# LBA1 LBCS2# LBA6 LBD0 LBD7 SIN3 CTS3# SOUT2 DSR2#
LBRST LBA2 LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# CTS2#
LBA3 LBCS0# LBCS1# LBRD# LBA5 LBD1 LBD5 MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
DTR1# CTS1# DSR1# XTLI
DCD1# XTLO
RI1# SIN2 UART_Ck _Out SIN1
RTS2# DCD2#
DTR2# RI2#
connect these pins:
Mode `100' QUAD UARTs 8-BIT Local Bus.
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 RTS2# DCD2# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB#/ CLKRUN# RST# INTA# MIO1 MIO0 MIO2 MIO3 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 DTR3# DTR2# RI2# MIO7 LBRST# LBA1 LBCS2# LBA6 LBD0 LBD7 SIN3 CTS3# SOUT2 DSR2# LBRST LBA2 LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 RI3# RTS3# CTS2# LBA3 LBCS0# LBCS1# LBRD# LBA5 LBD1 LBD5 MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
connect these pins:
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Mode `101' QUAD UARTs Parallel Port.
MODE[2:0]
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO Mode2 AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 UART_Ck _Out SIN1 RTS2# DCD2# C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB#/ CLKRUN# RST# INTA# MIO1 MIO2 MIO3 MIO4 MIO5 MIO6 STB# MIO9 DTR3# DTR2# RI2# MIO7 BUSY AFD# SIN3 CTS3# SOUT2 DSR2# ACK# SLCT SLIN# PDOUT MIO10 RI3# RTS3# CTS2# ERR# INIT# MIO8 PCI/ miniPCI DCD3# DSR3# SOUT3
connect these pins:
Mode `111' Standalone QUAD UART Mode
MODE[2:0]
Mode2 Mode0 Mode1 FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# SIN2 SIN1 RTS2# DCD2# Buffered _CLK RST# Uart Interrupt UART_ addr[0] Chip_ Select# UART_ data[2] UART_ data[4] DTR3# DTR2# RI2# UART_ addr[1] Read# UART_ data[0] UART_ data[7] SIN3 CTS3# SOUT2 DSR2# Read_Data _Control UART_ addr[2] UART_ data[3] UART_ data[6] RI3# RTS3# CTS2# UART_ addr[3] UART_ addr[4] Write# UART_ data[1] UART_ data[5] DCD3# DSR3# SOUT3
connect these pins:
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Descriptions
actual pinouts OXmPCI954 device (for various modes), please refer sections "Pin Information". mini-PCI Interface Mode 000, 001, 010, 011, 100, C9,A8,B9,C8,C7,A6,D6,C6, D5,A4,A3,B4,A2,B2,D3,C2, F2,G4,G2,H3,H2,J4,J1,J2, K1,K3,L4,L3,M1,N1,P1,M2 A5,B1,F1,K4
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed Address/Data
P_I/O P_I/O P_OD P_OD P_I/O P_OD
C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# Uart Interrupt INTB# CLKRUN# PME#
Command/Byte enable system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select system reset interrupt (All modes except Standalone Mode) Uart Interrupt (Standalone Mode Only) interrupt (All modes except Mini-PCI Mode) ClockRun# Line (mini-PCI modes Only) Power management event
NOTE interface utilised Standalone Mode. this mode, inputs tied their inactive states.
Serial port pins Modes
Dir1
Name FIFOSEL
R15,P13,M7,P6
O(h)
SOUT[3:0] IrDA_Out[3:0]
Description FIFO select. backward compatibility with 16C550, 16C650 16C750 devices UARTs' FIFO depth when FIFOSEL low. FIFO size increased when FIFOSEL high. unlatched state this readable software. FIFO size also setting FCR[5] when LCR[7] set, putting device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] corresponding channel enhanced mode UART serial data inputs UART IrDA data input when IrDA mode enabled (see above) Active-low modem data-carrier-detect input
L13,N10,R10,N5
I(h) I(h)
SIN[3:0] IrDA_In[3:0] DCD[3:0]#
N15,P11,P9,P5
I(h)
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Serial port pins Modes L12,P12,M8,N6
Dir1 O(h)
Name DTR[3:0]#
Description Active-low modem data-terminal-ready output. automated DTR# flow control enabled, DTR# asserted deasserted receiver FIFO reaches falls below programmed thresholds, respectively. RS485 half-duplex mode, DTR# programmed reflect state transmitter empty automatically control direction RS485 transceiver buffer (see register ACR[4:3]) Transmitter clock (baud rate generator output). isochronous applications, transmitter clock asserted DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. automated RTS# flow control enabled, RTS# deasserted reasserted whenever receiver FIFO reaches falls below programmed thresholds, respectively. Active-low modem clear-to-send input. automated CTS# flow control enabled, upon deassertion CTS# pin, transmitter will complete current character enter idle mode until CTS# reasserted. Note: flow control characters transmitted regardless state CTS# pin. Active-low modem data-set-ready input. automated DSR# flow control enabled, upon deassertion DSR# pin, transmitter will complete current character enter idle mode until DSR# reasserted. Note: flow control characters transmitted regardless state DSR# External receiver clock isochronous applications. Rx_Clk_In selected when CKS[1:0] `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock used transmitter (and indirectly receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input 20MHz. External clock 60MHz.
O(h)
485_En[3:0]
O(h) N14,N11,P7,R6 O(h)
Tx_Clk_Out[3:0] RTS[3:0]#
M13,R14,N8,M6
I(h)
CTS[3:0]#
P15,R13,P8,R5
I(h)
DSR[3:0]#
I(h) M14,R12,M10,R4 I(h) I(h)
Rx_Clk_In[3:0] RI[3:0]# Tx_Clk_In[3:0] XTLO XTLI
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
8-bit local Mode 000, 011, E12,E13,C15,B15 G12,G13,F15,G14,A15,C14,C13, K13,K14,K15,J12,J14,H12,H15, Parallel port Mode 001,
Dir1 O(h) O(h) O(h) O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock drive external UARTs connected local bus. enabled disabled software. Local active-high reset Local active-low reset Local data enable. This used external transceivers; high when LBD[7:0] output mode when they input mode. Buffered clock. enabled disabled software Local active-low Chip-Select (Intel mode) Local active-low Data-Strobe (Motorola mode) Local active-low write-strobe (Intel mode) Local Read-not-Write control (Motorola mode) Local active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local address signals Local data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# asserted (low) peripheral indicate that successful data transfer taken place. Identical function ACK# (EPP mode). Paper Empty. Activated printer when runs paper. Busy (SPP mode). BUSY asserted (high) peripheral when ready accept data Wait (EPP mode). Handshake signal interlocked IEEE 1284 compliant cycles. Select (SPP mode). Asserted host select peripheral Address strobe (EPP mode) provides address read write strobe Peripheral selected. Asserted peripheral when selected. Error. Held peripheral during error condition. Initialise (SPP mode). Commands peripheral initialise. Initialise (EPP mode). Identical function mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read write strobe
I(h) I(h) I(h) I(h)
INTR# BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
OD(h) O(h)
I(h) I(h) OD(h) O(h) OD(h) O(h)
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Parallel port Mode 001, Dir1 OD(h) O(h) K13,K14,K15,J12,J14,H12,H15, I/O(h) Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used peripheral latch data currently available PD[7:0] Write (EPP mode). Indicates write cycle when read cycle when high Parallel data Parallel Port data enable. This should used external transceivers signalling; high when PD[7:0] output mode when they input mode.
Subsystem Subsystem Vendor pins Mode Dir1 Name E12,E13,C15,B15,M15,L14,K12, Sub_ID[15:0] L15,A13,C12,B12,A12,D11,C11, A11,B11 K13,K14,K15,J12,J14,H12,H15, Sub_V_ID[15:0] H13,G12,G13,F15,G14,A15,C14, C13,D12
Description Subsystem After reset subsystem Function will default value assigned these pins Subsystem Vendor After reset subsystem vendor Function will default value assigned these pins.
Standalone Mode Mode B15,A15,C14,C13,D12 K13,K14,K15,J12,J14,H12,H15,
Dir1 I(h) I(h) I(h) I(h) I(h) I/O(h)
Name Buffered_CLK Reset# Chip Select# Write Strobe# Read Strobe# Read Data Control# UART_Address[4:0] UART Data[7:0} Uart Interrupt
Description Clock drive device. Device Reset. Active Chip Select Signal Active Write Signal Active Read Signal Active Controls Bidirectional Buffers Uart Data (read/writes) data reads, writes. Address[4:3] Uart Selection Address[2:0] Uart register Selection Uart Write Data/Read Data Interrupt line. Active UART interrupts.
DS-0019
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Multi-purpose External interrupt pins Mode Dir1 000,011,100 001/101 I/O(h) I/O(h) I/O(h) I/O(h)
Name MIO0 MIO1 MIO2 PME_In MIO[10:3]
Description Multi-purpose drive high low, assert interrupt Output Driving `0'. left No-connect. Multi-purpose drive high low, assert interrupt long LCC[6:5] "00"). Output Driving (when LCC[6:5] `00') left No-Connect. Multi-purpose When LCC[7] this drive high low, assert interrupt. Input power management event. When LCC[7] this input assert function PME#. Multi-purpose pins. drive high low, assert interrupt
L14,K12,L15,A13, C12,B12,A12,D11
Multi-purpose External interrupt pins Mode Dir1 000,001,010 011/100/101 I/O(h) I(h)
Name MIO[11] PCI/miniPCI
Description Multi-purpose pin. drive high low, assert interrupt PCI/miniPCI selection. Tied mode. Tied High miniPCI mode.
NOTE pins unused Standalone Mode operation must tied
EEPROM pins Mode
Dir1 IU(h)
Name EE_CK EE_CS EE_DI
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data with internal pull-up. When serial EEPROM connected, this should pulled using 1-10k resistor. When EEPROM used internal pull-up sufficient. connected external EEPROM's EE_DO used) EEPROM data out. connected external EEPROM's EE_DI used)
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
Miscellaneous pins Mode R2,N4,R3
Dir1
Name MODE[2:0]
Description Mode selector Pins Function QUAD UART. Function 8bit Local OX16PCI954 Backwards Compatible Mode. Function QUAD UART. Function Parallel Port OX16PCI954 Backwards Compatible Mode. Function QUAD UART. Function unusable local pins used assign Subsystem Subsystem Vendor function OX16PCI954 Backwards Compatible Mode. Function QUAD UART (Uarts Unique BARs) Function 8bit Local Enhanced Mode. Function QUAD UART. Function 8bit Local Enhanced Mode. Function QUAD UART. Function Parallel Port Enhanced Mode. 110: Reserved Standalone QUAD UART mode.
Power ground G1,H4,L1,R7,N9,M11,J15,F13, E14,B5,B3 H1,K2,L2,R11,G15,E15,D14,B10, B7,A1
Power Supply (3.3V) Power Supply Ground (0V)
Table Descriptions
DS-0019
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OXFORD SEMICONDUCTOR LTD.
Note Direction key: P_I/O P_OD I(h) IU(h) I/O(h) O(h) OD(h) input output PCITristates bi-directional open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain connect Ground 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, tolerant LVTTL level, tolerant LVTTL level, tolerant Standard Output tolerant (High Voltage BI-Direct output mode) Standard Open-drain Output tolerant (High Voltage BI-Direct open-drain mode)
OXmPCI954
3.3V power
DS-0019
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OXFORD SEMICONDUCTOR LTD.
OXmPCI954
CONFIGURATION OPERATION
drivers then access functions assigned addresses usual fashion, with improved data throughput provided PCI. Each function operates though separate device. However there Local Configuration Registers that used enable signals interrupts, configure timings, improve efficiency multi-port drivers. This architecture enables separate drivers installed each function. Generic port drivers hooked functions individually, more efficient multi-port drivers hook both functions, accessing Local Configuration Registers from either. registers default after reset suitable values typical applications such port serial, combo 4-port serial/1port parallel add-in cards. However, identification, control timing registers redefined using optional serial EEPROM.
OXmPCI954 multi-function, target-only device, compliant with Local Specification, Revision Power Management Specification, Revision 1.1. OXmPCI954 affords maximum configuration flexibility treating internal UART's, Local Parallel Port separate logical functions. Each function configuration space therefore recognised configured BIOS separately. functions used configured Mode Selection Pins (MODE[2:0]) shown section "OXmPCI954 Device Modes". OXmPCI954 configured system start-up software during bootstrap process that follows reset. system scans reads vendor device identification codes from devices finds. then loads device-driver software according this information configures I/O, memory interrupt resources. Device
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TARGET CONTROLLER
Operation
access while OXmPCI954 reading from serial EEPROM. OXmPCI954 performs medium-speed address decoding defined specification. asserts DEVSEL# signal clocks after FRAME# first sampled transaction frames which address chip. internal UARTs accessed with zero wait states inserted. Fast back-to-back transactions supported OXmPCI954 target, master perform faster sequences write transactions UARTs local when inter-frame turn-around cycle required. device supports combination byte-enables Configuration Registers Local Configuration Registers. byte-enable asserted, that byte unaffected write operation undefined data returned upon read. OXmPCI954 performs parity generation checking transactions defined standard. Note this entirely unrelated serial data parity which handled within UART functional modules themselves. parity error occurs during address phase, device will report error standard asserting SERR# signal. However that address/command combination decoded valid access, will still complete transaction though parity check correct. OXmPCI954 does support kind caching data buffering addition that already provided within UARTs transmit receive data FIFOs. general, registers UARTs local prefetched because there side-effects read.
OXmPCI954 responds following Configuration access: OXmPCI954 responds type configuration reads writes IDSEL signal asserted address selecting configuration registers function device will respond configuration transaction asserting DEVSEL#. Data transfer then follows. other configuration transaction will ignored OXmPCI954. reads/writes: address compared with addresses reserved Base Address Registers (BARs). address falls within assigned ranges, device will respond transaction asserting DEVSEL#. Data transfer follows this address phase. UARTs 8-bit Local controller, only byte accesses possible. accesses these regions, controller compares AD[1:0] with byte-enable signals defined specification. access always completed; however correct signal present transaction will have effect. Memory reads/writes: These treated same transactions, except that memory ranges used. Memory access single-byte regions always expanded DWORDs OXmPCI954. other words, OXmPCI954 reserves DWORD byte single-byte regions. device allows user define active byte lane using LCC[4:3] that Big-Endian systems hardware swap byte lane automatically. Memory mapped access single-byte regions, OXmPCI954 compares asserted byte-enable with selected byte-lane LCC[4:3] completes operation match occurs, otherwise access will complete normally bus, will have effect either internal UARTs local controller. other cycles (64-bit, special cycles, reserved encoding etc.) ignored.
Configuration space
OXmPCI954 dual-function device, where each logical function configuration space. required fields standard header implemented, plus Power Management Extended Capability register set. format configuration space shown following tables. general, writes registers that implemented ignored, reads from unimplemented registers return
OXmPCI954 will complete transactions disconnect-with-data, i.e. device will assert STOP# signal alongside TRDY#, ensure that Master does continue with burst access. exception this Retry, which will signalled response DS-0019
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7.2.1
Configuration Space Register
Predefined Region
Configuration Register Description
Device Status BIST
Vendor Command
Class Code Revision Header Type Reserved Reserved Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Reserved Subsystem Subsystem Vendor Reserved Reserved Cap_Ptr Reserved Reserved Reserved Interrupt Interrupt Line User Defined Region Power Management Capabilities (PMC) Data* Reserved Next Cap_ID Control/Status Register (PMCSR)
Offset Address
*Fields implemented Backwards Compatible Modes. Available only Enhanced Modes.
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Configuration Space Default Values Function
Register Name Function Reset Value Backwards Compatible Modes Enhanced Modes QUAD QUAD QUAD QUAD QUAD QUAD UART UART UART UART UART UART (SubSys Unique (Optional (Optional Unique Bar) Unique Bar) pins) 0x1415 0x9501 0x9504 0x9501 (0x9504) 0x0000 0x0290 0x00 0x070006 0x80 0x00000001 0x00000001 0x00000001 (0x00000001) 0x00000000 0x00000001 0x00000000 (0x00000001) 0x00000001 0x00000001 0x00000001 (0x00000001) 0x00000000 0x00000001 0x00000000 (0x00000001) NULL 0x00000001 NULL (0x00000001) NULL 0x00000000 NULL (0x00000000) 0x1415 0x0000 0x40 0x00 0x01 0x01 0x00 0x6C01 0x0000 0x00 (Not Implemented) 0x00 (Implemented) 0x6C02 (PCI mode) 0xEC02 (MiniPCI mode)
OXmPCI954
Program Read/Write EEPROM
Vendor Device Command Status Revision Class Code Header Subsystem Vendor Subsystem Cap. Interrupt Line Interrupt Next Capabilities Control/Status Register Data Register
W(Bit (Data Scale)
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Configuration Space Default Values Function
Register Name Function Reset Value Backwards Compatible Modes Enhanced Modes 8-BIT PARALLEL Disabled 8-BIT 8-BIT PARALLEL LOCAL PORT LOCAL LOCAL PORT 0x1415 0x9511 0x9513 0x9510 0x9511 0x9511 0x9513 0x0000 0x0290 0x00 0x068000 0x070101 0x068000 0x068000 0x068000 0x070101 0x80 0x00000001 0x00000000 0x00000001 0x00000000 0x00000000 0x00000000 0x00000001 0x00000001 0x00000000 NULL NULL 0x1415 0x0000 0x40 0x00 0x02 0x01 0x00 0x6C01 0x0000 0x00 (Not Implemented) 0x00 (Implemented) 0x6C02 (PCI mode) 0xEC02 (MiniPCI mode) 0x01 Program Read/Write EEPROM
Vendor Device Command Status Revision Class Code Header Subsystem Vendor Subsystem Cap. Interrupt Line Interrupt Next Capabilities Control/Status Register Data Register
W(Bit (Data Scale)
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Accessing logical functions
Access UARTs, Local Parallel Port achieved standard Memory mapping, addresses defined Base Address Registers (BARs) configuration space. BARs configured system allocate blocks Memory space logical functions, according size required function. addresses allocated then used access functions. mapping these BARs, which dependent upon mode device, shown following tables. Function QUAD UARTs Common Space Internal UARTs (I/O mapped) Internal UARTs (Memory mapped) Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused Function Local QUAD UARTs Unique mode Internal UART0 (I/O Mapped) Internal UART1 (I/O Mapped) Internal UART2 (I/O Mapped) Internal UART3 (I/O Mapped) Local configuration registers (I/O mapped) Internal UARTs/ Local configuration registers (Memory mapped)
Parallel port Local (I/O mapped) Parallel port base registers Local (Memory mapped) Parallel port extended registers Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused
7.3.1 access internal UARTs Memory Space
Base Address Registers internal UARTs dependent upon whether unique option been utilised Function Section "Unique Option" further Details. When this (unique bar) option selected, then function used access internal UARTs. function reserves 32-byte block space byte block memory space. Once access Memory access enable bits Command register (configuration space) set, UARTs accessed according following tables. UART Address (hex) Offset from Base Address Function0 space (hex) UART0 UART1 UART2 UART3
UART Address
Offset from Base Address Function0 Memory space (hex)
Table address internal UARTs (I/O memory)
Note Since memory space reserved full address used decoding, there number aliases UARTs allocated memory region
When unique option device been selected then BAR0 BAR3 used address each UART individually space, BAR5 used address UARTs Memory Space. function reserves 8-byte blocks space BAR0 BAR3 byte block memory space BAR5. Once access Memory access enable bits Command register (configuration space) set, UARTs accessed according following tables. Page
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UART Address (hex) UART Address
Offset from UARTs Base Address Function0 space (hex) UART0 UART1 UART2 UART3 (BAR0) (BAR1) (BAR2) (BAR3) Offset from Base Address Function0 Memory space (hex) UART0 UART1 UART2 UART3
maximum allowable block size allocated space (i.e. bytes), then access space byte aligned, LBA[7:0] equal AD[7:0] respectively. When user selects address range which less than bytes, corresponding upper address lines will logic zero. region divided into four chip-select regions when user selects second uppermost non-zero address chip-select decoding. example 32bytes space reserved, local address lines A[4:0] active remaining address lines zero. generate four chip-selects user should select Lower-Address-CS-Decode. this case A[4:3] will used internally decode chip-selects, asserting LBCS0# when address offset 00-07h, LBCS1# when offset 08-0Fh, LBCS2# when offset 10-17h, LBCS3# when offset 18-1Fh. region divided into chip-select regions selecting uppermost address decode chip selects. above example, user select Lower-Address-CS-Decode, thus using A[5:4] internally decode chip selects. this example LBA5 always zero, only chip-select lines LBCS0# LBCS1# will decoded into, asserting LBCS0# when address offset 000Fh LBCS1# when offset 10-1Fh. region allocated single chip-select region assigning address beyond selected range Lower-Address-CS-Decode (but above A8). above example, user selects LowerAddress-CS-Decode, A[6:5] will used internally decode chip-selects. this example LBA[7:5] always zero, only chip select line LBCS0# selected. this case address offset 00-1Fh asserts LBCS0# other chip-select lines remain inactive permanently. With default values, address local address accesses same internal UARTs (when UARTs common Base Address).
Note that unique mode operation, local registers memory space occupy same Base Address Register (BAR5) internal UARTs Memory Space. selects region accessed. Access addresses will directed internal UARTs, access addresses will directed local registers.
7.3.2
access 8-bit local
When local enabled (Modes 000, 011, 100), access works similar fashion internal UARTs. function reserves block space block memory space. block size user definable range bytes, memory range fixed bytes.
space
order minimise usage space, block size BAR0 Function1 user definable range bytes. Having assigned address range, user define adjacent address bits decode four chip selects internally. This facility allows glueless implementation local connecting four external peripheral chips. address range lower address chip-select decoding (Lower-Address-CS-Decode) defined Local Configuration register (see [26:20] section 7.4). 8-bit Local eight address lines (LBA[7:0]) that correspond maximum address space. DS-0019
Memory Space:
memory base address registers have allocated fixed size bytes address space. Since Local address lines OXmPCI954 only implements DWORD aligned accesses memory space, bytes addressable space chip select expanded Unlike access, memory access upper address lines always active internal chip-select decoding logic ignores user setting Lower-Address-CS-Decode (LT2[26:23]) uses AD[11:10] decode into chip-select regions. When Local accessed memory space, A[9:2] asserted LBA[7:0]. chip-select regions defined below. Page
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7.3.3
Local Chip-Select (Data-Strobe) LBCS0# (LBDS0#) LBCS1# (LBDS1#) LBCS2# (LBDS2#) LBCS3# (LBDS3#) Offset from Function1 (Memory space) Lower Address Upper Limit 000h 3FCh 400h 7FCh 800h BFCh C00h FFCh
access parallel port
When parallel port enabled (Mode 001, 101), access Parallel Port works definitions usual, except that there BARs corresponding sets registers defined operate IEEE1284 EPP/ECP bi-directional Parallel Port. user change space block size BAR0 over-writing default values LT2[25:20] using serial EEPROM (see section 7.4). example user reduce allocated space BAR0 bytes setting LT2[22:20] `001'. block size allocated BAR1 fixed Bytes. Legacy parallel ports expect upper register mapped 0x400 above base block, therefore BARs fixed with this relationship, generic parallel port drivers used operate device modes. Example: BAR0 0x00000379 bytes address 0x378) BAR1 0x00000779 bytes address 0x778) this relationship used, custom drivers will needed.
Table address local (memory)
Note: description given memory accesses Inteltype configuration Local Bus. Motorola-type configuration, chip select pins redefined data strobe pins. this mode Local offers address lines four data-strobe pins.
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Accessing Local configuration registers
local configuration registers device specific registers which accessed from either function. They mapped Memory Base Addresses typically BAR2 BAR3 each function. exception when device operates unique mode, which access local registers function will through BAR4 BAR5. transactions, access limited byte reads/writes. Memory Transactions, accesses Word Dword accesses, however little-endian systems such Intel 80x86 byte order will reversed. following table lists definitions local registers, with offsets (from Base Address Register) defined each local register.
7.4.1
Local Configuration Control register `LCC' (Offset 0x00)
This register defines control ancillary functions such Power Management, external clock reference signals serial EEPROM. individual bits described below. Bits Description Mode[1:0] Status. These bits return state Mode[1:0] pins. Enable UART clock output. When this set, buffered version UART clock output "UART_Clk_Out". When this low, UART_Clk_Out permanently low. Endian Byte-Lane Select memory access 8-bit peripherals. Select Data[7:0] Select Data[23:16] Select Data[15:8] Select Data[31:24] Memory access OXmPCI954 always DWORD aligned. When accessing 8-bit regions like internal UARTs, 8-bit Local parallel port, this option selects active byte lane. both architectures little endian, default value will used systems, however, some non-PC architectures need select byte lane. Power-down filter time. These bits define value internal filter time power-down interrupt request power management circuitry Function0. Once Function0 ready into power down mode, OXmPCI954 will wait specified filter time Function0 still power-down request mode, assert interrupt (see section 7.6). power-down request disabled seconds seconds seconds Function1 MIO2_PME Enable. value enables MIO2 PME_Status PMCSR register, hence assert PME# enabled. value disables MIO2 from setting PME_Status (see section 7.6). Reserved. These bits used test purposes. device driver must write zeros these bits. EEPROM Clock. read write EEPROM, toggle this generate EEPROM clock (EE_CK pin). EEPROM Chip Select. When EEPROM chip-select EE_CS activated (high). When EE_CS de-active (low). EEPROM Data Out. writes EEPROM, this output input-data EEPROM. This output EE_DO clocked into EEPROM EE_CK. EEPROM Data reads from EEPROM, this input output-data EEPROM connected EE_DI pin. EEPROM Valid. indicates that valid EEPROM program present External-Free Release Read/Write
EEPROM
Reset
23:8
0000h Page
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Bits
Description Reload configuration from EEPROM. Writing this re-loads configuration from EEPROM. This self-clearing after EEPROM read EEPROM Overrun Indication (when set). conjunction with (Valid EEPROM) this indicates whether successful eeprom download taken place. Successful download will have EEPROM_VALID EEPROM OVERRUN MODE[2] Status. Returns state MODE[2] pin.
Read/Write
EEPROM
Reset
7.4.2
Multi-purpose Configuration register `MIC' (Offset 0x04)
This register configures operation multi-purpose pins `MIO[11:0], well providing Enhanced Mode Features, follows. Bits Description MIO0 Configuration Register (When Device Mode `001'/'101'). MIO0 non-inverting input MIO0 inverting input MIO0 output driving MIO0 output driving When Parallel Port enabled, (Device Mode `001'/'101'), MIO[0] unused will remain forcing output mode. MIO1 Configuration Register (When LCC[6:5] `00'). MIO1 non-inverting input MIO1 inverting input MIO1 output driving MIO1 output driving When power-down mode Function enabled (LCC[6:5] `00'), MIO1 unused will remain forcing output mode. MIO2 Configuration Register (When LCC[7]='0'). MIO2 non-inverting input MIO2 inverting input MIO2 output driving MIO2 output driving When LCC[7] set, MIO2 re-defined PME_Input. polarity will controlled MIC[4]. sets sticky PME_Status Function1. MIO3 Configuration Register. MIO3 non-inverting input MIO3 inverting input MIO3 output driving MIO3 output driving MIO4 Configuration Register. MIO4 non-inverting input MIO4 inverting input MIO4 output driving MIO4 output driving
EEPROM
Read/Write
Reset
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Bits 11:10
Description MIO5 Configuration Register. MIO5 non-inverting input MIO5 inverting input MIO5 output driving MIO5 output driving MIO6 Configuration Register. MIO6 non-inverting input MIO6 inverting input MIO6 output driving MIO6 output driving MIO7 Configuration Register. MIO7 non-inverting input MIO7 inverting input MIO7 output driving MIO7 output driving MIO8 Configuration Register. MIO8 non-inverting input MIO8 inverting input MIO8 output driving MIO8 output driving MIO9 Configuration Register. MIO9 non-inverting input MIO9 inverting input MIO9 output driving MIO9 output driving MIO10 Configuration Register. MIO10 non-inverting input MIO10 inverting input MIO10 output driving MIO10 output driving MIO11 Configuration Register. MIO11 non-inverting input MIO11 inverting input MIO11 output driving MIO11 output driving Reserved. device driver must write zeros these bits. UART `Unique BAR' mode EEPROM When (1), sets Function such that each UART accessed through Base Address Register. This available only Enhanced Modes (and ignored pin-defined `unique bar' mode). enhanced modes, write transactions must affect status this bit. MiniPCI Mode Status When set, indicates that device operating miniPCI mode. When clear, device operating mode. This available only Enhanced Modes (and returns otherwise). Enhanced Mode Status When set, indicates that device operating Enhanced mode. When clear, device operating Backwards Compatible Mode. Clock Control Handling Power Management When (1), clock control circuitry handling CLKRUN# line controlled power management states function function This available only Enhanced Modes only relevant miniPCI mode operation. External-Free Release
EEPROM
Read/Write
Reset
13:12
15:14
17:16
19:18
21:20
23:22
25:24
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Bits
Description Disable Clock Control Circuitry (CLKRUN#) When (1), clock control circuitry handling CLKRUN# line disabled, allowing host stop PCI_CLK next available opportunity. Circuitry enabled default prevent clock stopping. This available only Enhanced Modes only relevant miniPCI mode operation. Parallel Port Filter Disable When disables noise filters parallel port data lines status lines. Filters enabled default. This available only Enhanced Modes only relevant parallel port.
EEPROM
Read/Write
Reset
7.4.3
Local Timing Parameter register `LT1' (Offset 0x08):
Local Timing Parameter registers (LT1 LT2) define operation timing parameters used Local Bus. timing parameters programmed 4-bit registers define assertion/de-assertion Local control signals. value programmed these registers defines number clock cycles after Reference Cycle when events occur, where reference Cycle defined clock cycles after master asserts IRDY# signal. following arrangement provides flexible approach users define desired timing their peripheral devices. timings refer Memory mapped access BAR0 BAR1 Function1. Bits Description Read Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during read operation from Local Bus.1 These bits unused Motorola-type interface. Read Chip-select De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins de-asserted (high) during read from Local Bus. These bits unused Motorola-type interface. Write Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during write operation Local Bus. These bits unused Motorola-type interface. Write Chip-select De-assertion (Intel-type interface). Defines number clock cycles after reference cycle when LBCS[3:0]# pins de-asserted (high) during write operation Local Bus. Read-not-Write De-assertion during write cycles (Motorola-type interface). Defines number clock cycles after reference cycle when LBRDWR# de-asserted (high) during write Local Bus. Read Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# asserted (low) during read from Local Bus. Read Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during read from Local Bus. DS-0019 External-Free Release Page Read/Write
EEPROM
Reset
parallel port)
11:8
15:12
19:16
parallel port)
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Bits 23:20
Description Read Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# deasserted (high) during read from Local Bus. Read Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during read from Local Bus. Write Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# asserted (low) during write Local Bus. Write Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during write Local Bus. Write Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# deasserted (high) during write Local Bus. Write Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during write cycle Local Bus.
Read/Write
EEPROM
Reset parallel port)
27:24
parallel port)
31:28
Note
Only values range (0-10 decimal) valid. Other values reserved. notes following page.
7.4.4
Bits 11:8
Local Timing Parameter register `LT2' (Offset 0x0C):
Description Write Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data during write operation Local Bus. Write Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during write operation Local Bus. Read Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data read operation from Local Bus. Read Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during beginning read cycle from Local Bus. Reserved. Space Block Size BAR0 Function1. Reserved Bytes Bytes Bytes Bytes Bytes Bytes Bytes Read/Write
EEPROM
Reset parallel port) `100' (=`010' parallel port)
15:12 19:16 22:20
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Bits 26:23
Description Local Chip-select Parameter `Lower-Address-CS-Decode'. space 8-bit Local 1000 0000 1001 0001 1010 0010 1011 0011 1100 0100 1101 0101 1110 0110 1111 0111 Reserved Local Software Reset. When this Local reset activated. When this Local reset de-activated. Local Clock Enable. When this Local clock (LBCK) enabled. When this LBCK permanently low. Local Clock buffered clock. Interface Type. When (=0) Local configured Inteltype operation, otherwise configured Motorola-type operation. Note that when Mode[1:0] `01', this hard wired
Read/Write
EEPROM
Reset `0001' (=`0010' parallel port)
28:27
Note Note Note
Only values range (0-10 decimal) valid. Other values reserved writing higher values causes interface retry accesses Local unable complete transaction clock cycles. Lower-Address-CS-Decode parameter described sections 7.3.2 Section These bits unused Memory access 8-bit Local which uses fixed decoding allocate regions chip selects. further information Local bus, section Local Bus, UARTs Parallel Port reset with reset. Addition, user issue Software Reset Command.
LT2[15:0] enable card designer control data during idle periods. default values will configure Local data pins remain forcing (LT2[7:4] Fh). LT[15:8] programmed place highimpedance beginning read cycle back forcing read cycle. systems that require data stay high-impedance, card designer should write appropriate value range LT2[7:4]. This will place data high impedance write cycle. Whenever value programmed LT2[7:4] does equal Local controller will ignore setting LT2[15:8] data will high-impedance outside write cycles. this case card designer should place external pull-ups data pins LBD[7:0]. While configuration data read from external EEPROM, pins remain high-impedance state. timing registers define Local timing parameters based signal changes relative reference cycle which defined clock cycles after IRDY# asserted first time frame. following parameters fixed relative reference cycle.
Local address pins LBA[7:0] asserted during reference cycle. write operation, Local data available during reference cycle, however buffers change direction programmed LT2[3:0]. Motorola type write operation, Read-not-Write (LBRDWR#) asserted (low) during reference cycle. read cycle this remains high throughout duration operation. default settings registers provide clock cycle address chip-select control signal set-up time, clock cycle address chip-select from control signal hold time, clock cycles pulse duration read write control signals clock cycle data hold time. These parameters acceptable using external OX16C950, OX16C952 OX16C954 devices connected Local Bus, Intel mode. Some redefinition will required operated Motorola mode. user should take great care when programming Local timing parameters. example defining value chip-select assertion which larger that value defined chip-select de-assertion defining chipselect assertion value which greater than control signal assertion will result obvious invalid local cycles. Page
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7.4.5
UART Receiver FIFO Levels `URL' (Offset 0x10)
receiver FIFO level internal UARTs shadowed Local configuration registers follows: Bits 15:8 23:16 31:24 Description UART0 Receiver FIFO Level (RFL[7:0]) UART1 Receiver FIFO Level (RFL[7:0]) UART2 Receiver FIFO Level (RFL[7:0]) UART3 Receiver FIFO Level (RFL[7:0]) Read/Write
EEPROM
Reset 0x00h 0x00h 0x00h 0x00h
7.4.6
UART Transmitter FIFO Levels `UTL' (Offset 0x14)
transmitter FIFO level internal UARTs shadowed Local configuration registers follows: Bits 15:8 23:16 31:24 Description UART0 Transmitter FIFO Level (TFL[7:0]) UART1 Transmitter FIFO Level (TFL[7:0]) UART2 Transmitter FIFO Level (TFL[7:0]) UART3 Transmitter FIFO Level (TFL[7:0]) Read/Write
EEPROM
Reset 0x00h 0x00h 0x00h 0x00h
7.4.7
UART Interrupt Source Register `UIS' (Offset 0x18)
UART Interrupt Source register described below: Bits 11:6 17:12 23:18 26:24 Description UART0 Interrupt Source Register (ISR[5:0]) UART1 Interrupt Source Register (ISR[5:0]) UART2 Interrupt Source Register (ISR[5:0]) UART3 Interrupt Source Register (ISR[5:0]) Reserved UART0 Good-Data Status UART1 Good-Data Status UART2 Good-Data Status UART3 Good-Data Status Global Good-Data Status. This logical bits i.e. Good-Data Status internal UARTs set. Read/Write
EEPROM
Reset
Good-Data status given internal UART when following conditions met: reads level0 (no-interrupt pending), level (receiver data available, level (receiver time-out) level (transmitter empty) interrupt LSR[7] clear there parity error, framing error break FIFO LSR[1] clear over-run error occurred
device driver software reads receiver FIFO levels (URL) followed this register, then Good-Data status given channel set, driver remove number bytes indicated FIFO level without need read line status register that channel. This feature enhances driver efficiency.
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given channel, Good-Data status set, then software driver should examine corresponding bits. example low, then driver should examine bits down obtain ISR[5:0] UART2. indicates level higher interrupt, interrupt change state modem lines detection flow control characters. device driver-software should then take appropriate measures would other 550/950 driver. When indicates level (receiver status) interrupt then driver examine Line Status Register (LSR) relevant channel. Since reading clears LSR[7], device driver-software should either flush empty contents receiver FIFO, otherwise Good-Data status will longer valid. UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) Global Interrupt Status register (GIS) allocated adjacent address offsets (10h 1Ch) Base Address Register. device driver-software read above registers single burst read operation. location offset registers such that FIFO levels usually read before status registers that status characters indicated receiver FIFO levels valid.
7.4.8
Bits
Global Interrupt Status Control Register `GIS' (Offset 0x1C)
Description UART Interrupt Status. These bits reflect internal interrupt states UART3 UART0, respectively.1 MIO0 Status (When device mode `001'/'101'). This reflects state internal MIO[0]. internal MIO[0] reflects non-inverted inverted state MIO0 pin.2 When device mode `001/'101', this reflects state Parallel Port Interrupt parallel port interrupt asserted INTB# backwards compatible modes INTA# enhanced modes, default. MIO1 Status (LCC[6:5]=`00'). This reflects state internal MIO[1]. internal MIO[1] reflects non-inverted inverted state MIO1 pin.2 Function Power-down Interrupt (LCC[6:5] `00'). this mode this sticky bit. When set, indicates power-down request issued Function would normally have asserted interrupt (see section 8.6). Reading this clears MIO[11:2] Status. These bits reflect state internal MIO[11:2]. internal MIO[11:2] reflect non-inverted inverted state MIO[11:2] pins respectively.2 UART Interrupt Mask. When these bits enable each internal UART assert interrupt respectively. When cleared (=0) they prevent respective channel from asserting interrupt.3 MIO[0] Interrupt Mask (When device mode `001'/'101'). When (=1) this enables MIO0 assert interrupt. When cleared (=0) prevents MIO0 from asserting interrupt.2 Parallel Port Interrupt Mask (When device mode `001/'101''). When (=1) this enables Parallel Port assert interrupt. When cleared (=0) prevents Parallel Port from asserting interrupt. MIO[1] Interrupt Mask (LCC[6:5]=`00'). When (=1) this enables MIO1 assert interrupt. When cleared (=0) prevents MIO1 from asserting interrupt.2 Function Power-down Interrupt Mask (LCC[6:5] `00'). When (=1) this enables power-down logic Function0 assert interrupt. When Read/Write
EEPROM
Reset 0x0h
XXXh
15:6 19:16
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OXmPCI954
Bits
Description cleared (=0) prevents power-down logic Function from asserting interrupt. Interrupt Mask. When (=1) these bits enable each MIO[11:2] assert interrupt respectively. When cleared (=0) they prevent respective pins from asserting interrupt.2
Read/Write
EEPROM
Reset 3FFh
31:22
Note Note
GIS[3:0] inverse UIS[18], UIS[12], UIS[6] UIS[0] respectively. Systems that require Local parallel port need read this register identify source interrupt long they read (offset 18h) register. returned value either direct state corresponding inverse configured Multi-purpose Configuration register `MIC' (offset 0x04). internal assert interrupt, inversion feature define each external interrupt defined active-low active-high, controlled register. When MIO[0] been set-up input output, this made generate interrupt when MIO[0] Interrupt Mask (bit (=1). This enables MIO[0] assert interrupt. When MIO[1] been set-up input output, this made generate interrupt when MIO[1] Interrupt Mask (bit (=1). This enables MIO[1] assert interrupt.
Note
UART Interrupt Mask register bits after hardware reset enable interrupt from internal UARTs. This will cater generic device-driver software that does access Local Configuration Registers. default setting UART Interrupt Mask bits changed using serial EEPROM. Note that even though default UART interrupts enabled this register, since after reset registers individual UARTs disables interrupts, interrupt will asserted after hardware reset. When Mode[2:0]=`010', pins used define Subsystem value, therefore interrupts pins disabled regardless state register. Interrupts Mask register bits after hardware reset enable interrupt from pins from boot default setting Interrupt Mask bits changed using serial EEPROM.
Note
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OXmPCI954
Interrupts
During system initialisation process device configuration, system-specific software reads interrupt field determine which any) interrupt used each function. programmes system interrupt router logically connect this interrupt system-specific interrupt vector (IRQ). then writes this routing information Interrupt Line field function's configuration space. Device driver software must then hook interrupt using information Interrupt Line field. Interrupt status sixteen sources interrupt available using register Local Configuration Register set, which accessed using Memory accessed from both logical functions. This facility enables each function snoop interrupts asserted from other function regardless interrupt routing. interrupt from each UART channel enabled using register register that UART. interrupt enabled active, then device will drive interrupt low. Generic device driver software will register enable interrupts. OXmPCI954 offers additional interrupt masking ability using GIS[19:16] (see section 7.4.8). internal UART channel assert interrupt interrupt enabled GIS[19:16]. interrupts enabled disabled individually using register Local configuration registers. When enabled, external device assert interrupt driving that pin. sense external interrupt pins (active-high active-low) defined register. parallel port also assert interrupt (but this will effectively disable MIO[0] interrupt).
Interrupts systems level-sensitive shared. There sixteen sources interrupt OXmPCI954, each UART channel twelve from Multi-Purpose pins (MIO11 MIO0). Parallel Port MIO[0] share same interrupt status (GIS[4]). Power Management powerdown interrupt internal UARTs (Function0) MIO[1] share status GIS[5]. Local uses pins pass interrupts controller. interrupts routed interrupt pins, INTA# INTB#. backwards compatible modes, default values Interrupt register results Function interrupts being asserted INTA# line Function1 interrupts being asserted INTB# line. enhanced modes, both Function Function interrupts assert INTA# line. These default routings modified writing Interrupt field configuration registers using serial EEPROM facility. Interrupt field normally considered hard-wired read-only value PCI. indicates system software which interrupt any) used function. interrupt only modified using serial EEPROM facility, card developers must invoke combination which violates specification. doubt, default routings should used. Following Table relates Interrupt field device used. Interrupt Device used None INTA# INTB# Reserved
Note that OXmPCI954 only interrupt pins INTA# INTB#. miniPCI mode, INTB# available interrupt line redefined dedicated CLKRUN# line.
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OXmPCI954
Power Management
7.6.1
Power Management Function
OXmPCI954 compliant with Power Management Specification Revision 1.1, enhanced modes. This indicated both functions their Power Management Capabilities Register (PMC). backwards compatibility modes, compliance version indicated. Each logical function implements Power Management registers supports power states miniPCI modes, PME# generation from D3cold also indicated which preserves PME# context through 3.3v Auxiliary power. section "miniPCI Support" further details. Power management accomplished handling power-down power-up ("power management event") requests, that asserted relevant function's interrupt PME# respectively. Each function assert PME# independently. Power-down requests defined Power Management specifications. device-specific feature requires bespoke device driver implementation. device driver either implement power-down itself special interrupt powerdown features offered device determine when function device ready power-down. worth noting that PME# can, certain cases, activate PME# signal when power removed from device. This will cause wake from Lowpower state D3(cold). ensure full cross-compatibility with system board implementations, isolator recommended (See Diagram). Power Management capabilities required, PME# treated no-connect.
Provided that necessary controls have been device's local configuration registers (LCC GIS), internal UARTs programmed issue powerdown requests and/or `wakeup' requests (power management events), function Function configured monitor activity serial channels, issue power-down interrupt when UARTs inactive interrupts pending both transmitters receivers idle). When serial channels indicating powerdown request only then will internal power management circuitry wait period time programmed into Power-Down Filter Time. This time defined local configuration register, LCC[7:5]). powerdown requests remain valid this time (this means that serial channels still inactive) then OXmPCI954 will issue powerdown interrupt this function's interrupt pin, this option enabled. Alternatively, device driver poll function powerdown status field local configuration register GIS[5] determine powerdown request. powerdown filter stops UARTs from issuing many powerdown interrupts whenever UARTs activity intermittent. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXmPCI954 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: internal clock internal UARTs shut down. interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled.
PME#
connector PME#
PME# Isolator Circuitry
device driver optionally assert/de-assert selected (design dependent) pins switch-off VCC, disable other external clocks, activate shut-down modes.
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device only issue wakeup request power management event, PME#) enabled this function's PME_En bit, bit-8 Power Management Register PMCSR. PME# assertion, immediate does powerdown filter timer. operates even powerdown filter time disabled. Like powerdown, wakeup requests function generated serial channel. means generate wakeup events from these sources will have been prior placing this function into powerdown states (including setting PME_En bit). each UART, when device (function powerstate only activity serial channel's line (the trailing edge pulse) will generate wakeup event. When device (function power-state then wake-ups configurable. this case, change state modem line (which enabled 16C950specific mask bit) change state serial input line (again, enabled 16C950-specific mask bit) issue wake request PME# pin. worth noting that after hardware reset these mask bits cleared enable wake assertion from modem lines line when powerstate wake operation from requires least mask enabled, device driver example disable masks with exception Ring Indicator, only modem ring wake computer. case wake request from serial input line EXT_DATA_IN (from power state then clock that channel turned serial data framing maintained. When function issues wake request from serial channels, PME_Status this function's power management registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue assert PME# inform device driver that power management wake event occurred. After wake event signalled, device driver expected return this function powerstate.
OXmPCI954
state pin(s) that issues powerdown request controlled register. This active high active Low. This state same state that asserts function interrupt normal functionality. assertion pins will result function powerdown request being made immediately. There powerdown filtering time associated with function powerdown request issued function's interrupt pin, this option enabled. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXmPCI954 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: Parallel Port placed power mode. Local Function placed power mode interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled. Function only issue wakeup request (power management event) enabled this function's PME_En bit, bit-8 Power Management Register PMCSR. Wakeup requests function only generated Multi_Purpose MIO[2]. means generate wakeup events from this source will have been prior placing this function into powerdown states state MIO[2] that results wakeup requests determined settings local configuration register MIC. soon correct logic invoked than power management event (wakeup) asserted. PME# event immediate. When function issues wake request, PME_Status this function's power management registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue Page
7.6.2
Power Management function
Provided that necessary controls have been device's local configuration registers (MIC GIS), Multi_Purpose pins (MIO[11:3]) programmed issue powerdown requests only MIO[2] generate `wakeup' requests (power management events), function Parallel Port Local function capable issuing powerdown requests power management events placed power state through power management involving pins. DS-0019
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assert PME# inform device driver that power management wake event occurred. After
OXmPCI954
wake event signalled, device driver expected return this function power-state
LCC[6:5]
GIS[21]
Power-down Filter Time
Operation Function power-down interrupt disabled. MIO[1] assert interrupt GIS[21] set. Function power-down interrupt disabled. GIS[5] reflects state internal power-down mode polling operation. MIO[1] interrupt disabled Function power-down enabled. GIS[5] reflects state internal power-down mode. MIO[1] interrupt disabled.
Table Function (UARTs) Power down interrupt settings
LCC[7]
MIC[5:4]
MIO2 Rising
MIO2 Falling
Function1 PME_Status Remains unchanged Gets Remains unchanged Gets Remains unchanged
Table Function (Local Bus) Wake-up configuration
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OXmPCI954
Unique Option Function
Space Dword Description UART UART UART UART Local Registers QUAD UARTs Local Registers Memory Space type bytes) bytes) bytes) bytes) bytes) Memory bytes
backwards compatible modes, access internal UARTs through common Base Address Register (BAR0). definitions Function backwards compatible modes, shown below. Space Dword Description Internal UARTs Internal UARTs Local Registers Local Registers NULL NULL type bytes) bytes) bytes) Memory bytes NULL NULL
Some device drivers would prefer that each UART accessible Base Address Register. This option available enhanced modes, either through selection device's mode pins utilising eeprom controller `unique mode seeprom' field, bit[26] local register. following table lists which device modes support this option. Device Mode Backwards Compatible Enhanced Backwards Compatible Backwards Compatible Backwards Compatible Enhanced Enhanced Enhanced Reserved Availability unique mode Default Available through EEPROM option Available through EEPROM option
NOTE that `Unique Mode' only affects region Function0. Function affected maintains configuration device mode pins.
this case, BAR0 BAR3 reserve bytes space allow access registers UART UART respectively. result this change, Base Address local registers defined BAR4, BAR5 becomes Memory Base Address register both internal UARTs Local Registers. purposes device drivers recognising this configuration, Device "9504" reserved must returned function when `unique bar' option been exercised. This Device automatically returned during configuration accesses when unique option selected device pins (MODE "011"). However, when this option selected EEPROM Enhanced modes) then EEPROM also required change Device function "9504" additionally downloading into Configuration Zone function Access UARTs Local Registers Memory Space unique mode, serves Memory Base Address Register internal UARTs Local Registers. When accessing BAR5, address determines access UARTs Local Registers. With Fields define which UART access, Fields define which UART register access. With Fields Define BYTE offset local registers. 00000b register, 00100h register. both cases, fields utilised zeros. This because DWORD used hold single Byte, Memory Space.
When `unique mode' option selected, Base Address Register Region Function changes follows.
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OXmPCI954
MiniPCI Support Enhanced Modes only
miniPCI mode, following changes take place device functionality definitions.
OXmPCI954 device operates miniPCI mode when 88/M15 tied HIGH Enhanced Modes. other cases, device operates mode. MiniPCI mode available backwards compatible modes. Function/Pin Z_INTA Z_INTB D3cold Support
MiniPCI mode interrupt both function function Redefined CLKRUN# interrupts available this PME# from Cold supported Available indicated Power Management Registers
Mode Interrupt pin. function function Enhanced Modes. interrupt function backwards Compatibility Mode. PME# cold supported. indicated Power Management Registers.
CLKRUN# OXmPCI954 device tolerant clock stopping PCI_CLK line, full UART functionality. While UARTs themselves dependent upon PCI_CLK line, crystal oscillator their main clock source, some parts device require that PCI_CLK operational stopped) allow reliable operation internal UARTs. Such parts include writing/reading UART registers interrupt handling. this reason, OXmPCI954 device implements CLKRUN# prevent host from stopping PCI_CLK (until such time needed). circuitry handling CLKRUN# line compliant CLKRUN# requirements defined Mobile Design Guide, version 1.1. Provided that Central Resource holds CLKRUN# line active (low), indicate that PCI_CLK enabled, then there intervention OXmPCI954 device which keeps it's side CLKRUN# driver inactive. CLKRUN# line bi-directional pin. When Central Resource synchronously de-asserts CLKRUN# line initially driven line high then leaving high impedance state) signal Central Resource's intention stop slow) PCI_CLK, then prevented from doing target that asserts (drives low) CLKRUN# line clock cycles following de-assertion. CLKRUN# line only asserted target clock cycles, during which time Central Resource expected drive (and hold) CLKRUN# line asserted, until next attempt host stop clock. this case, cycle repeats. DS-0019
default, clock control circuitry OXmPCI954 miniPCI mode) always enabled. This means that Central Resource prevented from stopping PCI_CLK times, requests Central Resource stop this clock de-asserting CLKRUN# line) target re-asserting CLKRUN# line 2-clock cycles later. This issue from power management point view this default behaviour prevent system from going into power state result system being partially shut-down need maintain PCI_CLKs OXmPCI954 based miniPCI card. clock control circuitry associated with CLKRUN# line been provided with controls help overcome this. miniPCI mode (Enhanced mode), local registers provide controls associated with CLKRUN# line. These Read-Write fields accessible transactions external EEPROM downloading into register Local Register Zone. Control CLKRUN# Circuitry Disable CLKRUN# Control Power Management Register Default State
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OXmPCI954
Bits 30:29
CLKRUN Circuitry Status CLKRUN#' Operation Enabled (Never Stop PCI-CLK) CLKRUN# Operation Power Management Control CLKRUN# Operation Disabled (Allow PCI_CLK stop) CLKRUN# Operation Disabled (Allow PCI_CLK stop)
device drivers host will required determine most suitable point disable clock control circuitry. Disabling clock control circuitry when OXmPCI954 device fully operational state state) recommended some hosts have been designed periodically attempt stop PCI_CLK normal routine. these cases, clock control circuitry been disabled then PCI_CLK will stopped next opportunity. large file transfers are/will taking place when this event occurred then this lead corrupted data being transmitted/received. additon Clkrun# Circuitry Disable bit, there additional control called Clkrun# Control Power Management. name suggests, this allows clock control logic associated with CLKRUN# line controlled Power Management states OXmPCI954 device. This hardware assist does require software involvement with exception enabling this field place (although this also achived external eeprom). When Clkrun Control Power Management selected, device makes knowledge that attempts host (Central Resource) place both functions into power state (states power management terminology) pre-empt condition host stopping PCI-CLK OXmPCI954 device order reduce power consumption card thus system. host expected stop PCI-CLK OXmPCI954 device when least functions fully operation state state). statemachine been built-in that handles clock control circuitry according states each function. This shown overleaf.
Clkrun# Circuitry Disable bit, allows device drivers disable (and re-enable) clock control circuitry associated with CLKRUN# line meet overall Power Management device system. When CLKRUN# circuitry disabled, then when CLKRUN# line deasserted Central Resource next available opportunity, attempt made target assert CLKRUN# line thereby allowing Central Resource stop PCI_CLK. Once PCI_CLK stopped, still possible re-enable clock circuitry writing disable field (with `0') Central Resource expected restart PCI_CLK sufficient time allow write transaction take place. Once transaction been completed, clock control circuitry will then prevent central resource from stopping PCI_CLK until clock control circuitry again disabled. While perfectly feasible that clock control circuitry disabled (re-enabled) leisure, clock control circuitry should only disabled prior device being placed into power states D2/D3 host, when operations other than wake-up expected from UARTs. Some interaction between
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OXmPCI954
Reset Enable CLKRUN#
CLKRUN# Circuitry Enabled (Either Function state)
Both Functions Placed Power State Disable CLKRUN#
CLKRUN# Disabled (Both Functions power State) PME# Event (wake-up) Enable CLKRUN# Both functions return fully operation state (D0) CLKRUN# Circuitry Enabled (both function power State)
When either functions PowerManagement state, CLKRUN# circuitry enabled prevent host from stopping PCI_CLK, times. When host places both functions into power states then, only then, CLKRUN# circuitry disabled. This means that host will able stop PCI_CLK next available opportunity, which likely purpose placing both functions into power state. Once power state, OXmPCI954 device driven PCI_CLKs controls would have been device drivers allow OXmPCI954 device generate `wake-up' PME# events. This PME# generation will Z_CTS Z_RI pins function0, MIO-2 function When OXmPCI954 generates PME# event, this event sufficient attention Central Resource that will kick-start host restart PCI_CLKs device. same PME# event used internally
enable CLKRUN# circuitry, that host attempts stop PCI_CLK before both functions placed back into (fully operational state) then prevented from doing CLKRUN# circuitry only disabled again cycle repeated) once both functions placed back into fully operation state host expected this following PME# wake-up event. OXmPCI954 device should only used with hosts that implement CLKRUN# line CLKRUN# protocol. Some hosts have CLKRUN# line necessarily implement CLKRUN# protocols, instead leaving CLKRUN# permanently held active (low) state. This will taken OXmPCI954 device PCI_CLK always running. Such hosts then remove PCI_CLK from OXmPCI954 device without notification CLKRUN# line when requesting SUSPEND function. This lead corrupted data when file transfers subsequently take place owing loss PCI_CLK.
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OXmPCI954
PME# Generation from Cold miniPCI mode, OXmPCI954 supports PME# generation from cold state. This indicated both functions' power management register (Power Management Capabilities) that indicates "PME# asserted from D3cold". applications (whether backwards compatible mode Enhanced Modes), register makes such indications Power Management Status PME# context will lost following Reset. PME# generation D3cold, OXmPCI954 required make auxiliary 3.3v power when main 3.3v power been removed. Chapter Local Power Management Interface Specification. This changeover to/from main/auxiliary power needs handled external circuitry that supplies OXmPCI954, such cause supply interruptions (dropouts) OXmPCI954 device concerned. Otherwise, this will result loss OXmPCI954's internal states. circuits must such that there sneak-paths between main 3.3v power Auxiliary 3.3v power these power planes isolated times (miniPCI cards cannot connect 3.3v 3.3v main, vice versa). When OXmPCI954 device been provide wake-up events (PME#), then OXmPCI954 device will generate PME# events Z_RI lines function MIO_2 line function when device cold state (while auxiliary powered). OXmPCI954 miniPCI mode preserves PME# context when device transitioned from cold (uninitialised) transition Hardware Reset invoked RST# line. PME# Context also preserved following soft reset when restoring function from D3hot state.
When preserving PME# context, OXmPCI954 maintains status following registers Status PME_En function's PMCSR register. Status PME_Status function's PMCSR register. result, this preserves Status PME# line. Preserving PME# Context issues that need handled host. These listed here reference purposes only. Since reset does affect status fields PME_En PME_Status, there possibility that when power first supplied OXmPCI954 device miniPCI mode operation) that state PME# line unknown (PME_status unknown). host controller must able handle this condition until these fields have been intialised writing them with appropriate values. This been noted Section 3.2.4 Power Management Specification revision 1.1, that states "system software required explicitly initialize PME# context, functions, during initial operating system load." when PME# generation from D3cold supported. D3cold state, when OXmPCI954 generates `wake-up' (PME#) event, then this status (PME# wakeup) persists when OXmPCI954 transitioned from D3cold state D0(uninitialised) Reset. host controller must able handle this condition until PME_status and/or PME_En bits have been wriiten with appropriate values disable PME# wake-up request.
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OXmPCI954
Standalone Mode
standalone mode OXmPCI954 device offers synchronous local access internal QUAD Uarts, without overheads associated Configuration registers (which held inactive). While perfectly possible that access internal QUAD UARTs this mode) through device that implements 8-bit local function, long relevant timings met, this mode been specifically designed used with 8-bit local function another OXmPCI954 device order expand number UARTs add-in card. Expansion UART channels already possible through devices such asynchronous OX16C954 device standalone mode offers additional means UART expansion. When OXmPCI954 utilised standalone mode, must wholly driven 8-bit local function driving OXmPCI954 device. particular, PCI_CLK Reset Signals permitted connected directly corresponding pins standalone device (for excessive loading considerations). following diagram indicates recommended connectivity between driving OXmPCI954 device standalone mode OXmPCI954 devices.
Quad UARTs PCI954 Standalone Mode)
Uart Signals {3:0}
Uart Signals {3:0}
PCI_CLK RESET#
Buffered_CLK, Local Reset# Local Trans
Quad UARTs PCI954 Standalone Mode)
Uart Signals {3:0}
Uart Data
PCI954 QUAD Uart 8-bit local (Backwards patible Enhanced Modes)
Quad UARTs PCI954 Standalone Mode)
Uart Signals {3:0}
Individual Chip Selects
Microwire Eeprom
Quad UARTs PCI954 Standalone Mode)
Uart Signals {3:0}
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OXmPCI954
following table lists recommended connections when interfacing more standalone devices, driving OXmPCI954. Standalone Mode Signal Buffered_Clk RST# Uart Interrupt OXmPCI954 (Driver) Signal Buffered_CLK Z_Local_Reset MIO(x) Comments signal standalone device(s) Reset# Signal standalone device(s) Uart Interrupt line standalone device connected unused driving OXmPCI954 device, pass over uart interrupt function1 interrupt driving device's Z_INTA/Z_INTB lines). multiple standalone devices, each uart interrupt must connected separate driving OXmPCI954. Uart Data Buffer Control Address[4:3] Selects UART Address[2:0] Selects UART register Each Standalone Device must have chip select signal driven each z_local_cs(x) driving mPCI954 device. Chip Select (Standalone0) Z-local_cs(0) Chip Select (Standalone1) Z-local_cs(1) Chip Select (Standalone2) Z-local_cs(2) Chip Select (Standalone3) Z-local_cs(3) Write signal standalone devices(s) Read signal standalone devices(s) Bidirectional UART read/write Data
Read Data Control Uart Addr [4:0] Chip Select
Local_Trans_En Local Address [4:0] Z_Local_CS(x)
Write# Read# Uart data [7:0]
IOW# IOR# Local_Data[7:0]
Since interface used standalone mode OXmPCI954 device, then inputs must tied their inactive states.
order support standalone devices, default LT1/LT2 values associated with 8-bit local function driving device need changed. standalone mode devices require several clock cycles read/write transactions local compared asynchronous counterpart, OX16C954. This means that access UARTS standalone devices inherently slower than accessing UARTs OX16C954 devices. There UART performance penalties. addition, size BAR0 function driving device required match address range standalone UARTs lower-CS decode needs that relevant z_local_cs line activated chip select standalone devices. changes LT1/LT2 shown following table. (all other local register values take default values). Description Read Chip-Select De-assertion Write Chip-Select De-assertion Read Control De-assertion Write Control De-assertion Write Data Assertion Write Data De-assertion Read Data Assertion Read Data De-assertion DS-0019 Value (Reset Value) Local Register Field LT1[7:4] LT1[15:12] LT1[23:20] LT1[31:28] LT2[3:0] LT2[7:4] LT2[11:8] LT2[15:12] Page
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OXmPCI954
Description Interfacing Single Standalone Devi
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