Dual 16C950 High performance UART channels 8-bit Pass-through Local (P
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OXmPCI952 DATA SHEET
Dual 16C950 High performance UART channels 8-bit Pass-through Local (PCI Bridge) IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver) Efficient 32-bit, 33MHz, Multi-function target-only controller, fully compliant Local specification 3.0, Power Management Specification miniPCI Modes (with CLKRUN# PME# generation D3cold state, miniPCI mode) UARTs fully software compatible with 16C550-type devices. UART operation external clock source. 20MHz with crystal oscillator. Baud rates 60Mbps external clock mode 15Mbps asynchronous mode. 128-byte deep FIFO transmitter receiver Flexible clock prescaler, from 31.875 Automated in-band flow control using programmable Xon/Xoff both directions Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#
Integrated High Performance Dual UARTs, 8-bit Local Bus/Parallel Port. 3.3v PCI/miniPCI interface.
Arbitrary trigger levels receiver transmitter FIFO interrupts automatic in-band out-of-band flow control Infra-red (IrDA) receiver transmitter operation 9-bit data framing, well 5,6,7 bits Detection data receiver FIFO Global Interrupt Status readable FIFO levels facilitate implementation efficient device drivers. Local registers provide status/control device functions. multi-purpose pins, which configured input interrupt pins `wake-up'. Auto-detection wide range Microwirecompatible EEPROMs, configure device parameters. Function access, pre-configure each function prior handover generic device drivers. Operation memory mapping. 3.3V operation tolerance selected I/Os) Extended Operating Temp. Range -40C 105C 160-pin LQFP/176-pin package
DESCRIPTION
OXmPCI952 single chip solution miniPCI based serial parallel expansion add-in cards. dual function device, where function offers ultra-high performance OX16C950 UARTs, function configurable either 8-bit Local bidirectional parallel port. Each UART channel OXmPCI952 fastest available PC-compatible UART, offering data rates 15Mbps 128-byte deep transmitter receiver FIFOs. deep FIFOs reduce overhead allow utilisation higher data rates. Each UART channel software compatible with widely used industry-standard 16C550 devices (and compatibles), well OX16C95x family high performance UARTs. addition increased performance FIFO size, UARTs also provide full OX16C95x enhanced features including automated in-band flow control, readable FIFO levels etc. enhance device driver efficiency reduce interrupt latency, internal UARTs have multi-port features such shadowed FIFO fill levels, global interrupt source register Good-Data Status, readable four adjacent DWORD registers visible logical functions space memory space. Expansion serial cards beyond channels possible using 8-bit pass-through Local function. addressable space increased bytes, divided into four chip-select regions. This flexible expansion scheme caters cards with serial ports using external 16C950, 16C952, 16C954 compatible devices, composite applications such combined serial parallel port expansion cards. parallel port IEEE 1284 compliant SPP/EPP/ parallel port that fully supports existing Centronics interface. parallel port enabled place Local Bus. external transceiver required parallel port operation. configuration register values programmed using external Microwirecompatible serial EEPROM. This EEPROM also used provide function access, pre-configure each UART into enhanced modes preconfigure devices local bus/parallel port, prior configuration accesses before control handed (generic) device drivers.
Oxford Semiconductor Ltd. External-Free Release Milton Park, Abingdon, Oxon, OX14 4SH, Tel: (0)1235 824900 Fax: +44(0)1235 821141
Oxford Semiconductor 2005 OXmPCI952 DataSheet DS-0020 June 2005
OXFORD SEMICONDUCTOR LTD.
OXmPCI952
REVISION HISTORY
2005 2005 DATE 05/09/2003 25/1/2005 8/6/2005 REASON CHANGE SUMMARY CHANGE Initial DataSheet Revisions additional 176-pin layout Revision additional green order code 160-pin LQFP layout
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TABLE CONTENTS
5.2.1 5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.4.6 5.4.7 5.4.8 5.6.1 5.6.2
BLOCK DIAGRAM INFORMATION-160-PIN LQFP
PINOUTS. DESCRIPTIONS. PINOUTS. DESCRIPTIONS.
INFORMATION-176-PIN BGA. CONFIGURATION OPERATION TARGET CONTROLLER.
OPERATION CONFIGURATION SPACE CONFIGURATION SPACE REGISTER MAP. ACCESSING LOGICAL FUNCTIONS ACCESS INTERNAL UARTS. ACCESS 8-BIT LOCAL BUS. ACCESS PARALLEL PORT ACCESSING LOCAL CONFIGURATION REGISTERS. LOCAL CONFIGURATION CONTROL REGISTER `LCC' (OFFSET 0X00) MULTI-PURPOSE CONFIGURATION REGISTER `MIC' (OFFSET 0X04) LOCAL TIMING PARAMETER REGISTER `LT1' (OFFSET 0X08): LOCAL TIMING PARAMETER REGISTER `LT2' (OFFSET 0X0C): UART RECEIVER FIFO LEVELS `URL' (OFFSET 0X10). UART TRANSMITTER FIFO LEVELS `UTL' (OFFSET 0X14). UART INTERRUPT SOURCE REGISTER `UIS' (OFFSET 0X18). GLOBAL INTERRUPT STATUS CONTROL REGISTER `GIS' (OFFSET 0X1C) INTERRUPTS. POWER MANAGEMENT POWER MANAGEMENT FUNCTION POWER MANAGEMENT FUNCTION MINIPCI SUPPORT. DEVICE DRIVERS
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.3.1 6.3.2 6.4.1 6.5.1 6.5.2 6.5.3
INTERNAL OX16C950 UARTS
OPERATION MODE SELECTION MODE. MODE. EXTENDED MODE MODE. MODE. MODE. REGISTER DESCRIPTION TABLES RESET CONFIGURATION HARDWARE RESET SOFTWARE RESET TRANSMITTER RECEIVER FIFOS FIFO CONTROL REGISTER `FCR' LINE CONTROL STATUS. FALSE START DETECTION. LINE CONTROL REGISTER `LCR'. LINE STATUS REGISTER `LSR' Page
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INTERRUPTS SLEEP MODE. 6.6.1 INTERRUPT ENABLE REGISTER `IER'. 6.6.2 INTERRUPT STATUS REGISTER `ISR'. 6.6.3 INTERRUPT DESCRIPTION 6.6.4 SLEEP MODE MODEM INTERFACE 6.7.1 MODEM CONTROL REGISTER `MCR'. 6.7.2 MODEM STATUS REGISTER `MSR' OTHER STANDARD REGISTERS 6.8.1 DIVISOR LATCH REGISTERS `DLL DLM'. 6.8.2 SCRATCH REGISTER `SPR' AUTOMATIC FLOW CONTROL. 6.9.1 ENHANCED FEATURES REGISTER `EFR'. 6.9.2 SPECIAL CHARACTER DETECTION 6.9.3 AUTOMATIC IN-BAND FLOW CONTROL 6.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL 6.10 BAUD RATE GENERATION. 6.10.1 GENERAL OPERATION 6.10.2 CLOCK PRESCALER REGISTER `CPR'. 6.10.3 TIMES CLOCK REGISTER `TCR'. 6.10.4 EXTERNAL CLOCK MODE. 6.10.5 CRYSTAL OSCILLATOR CIRCUIT 6.11 ADDITIONAL FEATURES 6.11.1 ADDITIONAL STATUS REGISTER `ASR' 6.11.2 FIFO FILL LEVELS `TFL RFL' 6.11.3 ADDITIONAL CONTROL REGISTER `ACR'. 6.11.4 TRANSMITTER TRIGGER LEVEL `TTL' 6.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL `RTL' 6.11.6 FLOW CONTROL LEVELS `FCL' `FCH' 6.11.7 DEVICE IDENTIFICATION REGISTERS. 6.11.8 CLOCK SELECT REGISTER `CKS'. 6.11.9 NINE-BIT MODE REGISTER `NMR' 6.11.10 MODEM DISABLE MASK `MDM' 6.11.11 READABLE `RFC'. 6.11.12 GOOD-DATA STATUS REGISTER `GDS'. 6.11.13 PORT INDEX REGISTER `PIX'. 6.11.14 CLOCK ALTERATION REGISTER `CKA'
LOCAL
OVERVIEW OPERATION CONFIGURATION PROGRAMMING. OPERATION MODE SELECTION MODE MODE. MODE MODE PARALLEL PORT INTERRUPT REGISTER DESCRIPTION. PARALLEL PORT DATA REGISTER `PDR' FIFO ADDRESS DEVICE STATUS REGISTER `DSR' DEVICE CONTROL REGISTER `DCR'. ADDRESS REGISTER `EPPA' DATA REGISTERS `EPPD1-4' Page
8.1.1 8.1.2 8.1.3 8.1.4 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6
BIDIRECTIONAL PARALLEL PORT
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8.3.7 8.3.8 8.3.9 8.3.10 8.3.11
OXmPCI952
DATA FIFO TEST FIFO CONFIGURATION REGISTER CONFIGURATION REGISTER EXTENDED CONTROL REGISTER `ECR'. SPECIFICATION ZONE HEADER ZONE LOCAL CONFIGURATION REGISTERS. ZONE IDENTIFICATION REGISTERS ZONE CONFIGURATION REGISTERS ZONE POWER MANAGEMENT DATA (AND DATA_SCALE ZONE) ZONE FUNCTION ACCESS MINIMUM PROGRAMMING REQUIREMENTS.
9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7
SERIAL EEPROM.
10.1 11.1 11.2 11.3
OPERATING CONDITIONS
ELECTRICAL CHARACTERISTICS
ELECTRICAL CHARACTERISTICS.
LOCAL BUS. SERIAL PORTS
13.1 13.2
TIMING WAVEFORMS. PACKAGE INFORMATION.
160-PIN LQFP PACKAGE 176-PIN PACKAGE.
ORDERING INFORMATION
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PERFORMANCE COMPARISON
Feature Internal serial channels Integral IEEE 1284 EPP/ECP parallel port Multi-function device Support Power Management Zero wait-state write operation available Local interrupt pins DWORD access UART Interrupt Source Registers FIFO Levels Good-Data status Full Plug Play with external EEPROM External baud rate clock baud rate normal mode baud rate clock mode FIFO depth Sleep mode Auto Xon/Xoff flow Auto CTS#/RTS# flow Auto DSR#/DTR# flow interrupt thresholds interrupt thresholds flow control thresholds Transmitter empty interrupt Readable status flow control Readable FIFO levels Clock prescaler options Rx/Tx disable Software reset Device 9-bit data frames RS485 buffer enable Infra-red (IrDA)
OXmPCI952
yes1 Mbps Mbps
16C552 Bridge Kbps
16C652 Bridge Mbps
Table OXmPCI952 performance compared with Bridge generic UART combinations
Note Zero wait-state applies only internal UARTs (after assertion DEVSEL#). Read operation incurs wait state.
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Improvements OXmPCI952 over discrete solutions
Higher degree integration: OXmPCI952 device offers internal 16C950 highperformance UARTs 8-bit Local Bi-directional parallel port. Multi-function device: OXmPCI952 multi-function device enable users load individual device drivers internal serial ports, drivers peripheral devices connected Local drivers internal parallel port. Dual Internal OX16C950 UARTs OXmPCI952 device contains ultra-high performance UARTs, which increase driver efficiency using features such 128-byte deep transmitter receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt flow control trigger levels readable FIFO levels. Data rates 60Mbps. Improved access timing: Access internal UARTs, require zero wait states. read transaction from internal UART complete within five clock cycles write transaction internal UART complete within four clock cycles. Reduces interrupt latency: OXmPCI952 device offers shadowed FIFO levels Interrupt status registers internal UARTs, pins. This reduces device driver interrupt latency. Power management: OXmPCI952 device complies with Power Management Specification Microsoft Communications Device-class Power Management Specification (2000). Both functions offer extended capabilities Power Management. This achieves significant power savings enabling device drivers power down functions. function this through switching channel clock, power state Wake-up (PME# generation) requested either functions. function this inputs UARTs power-state modem line inputs UARTs power-state function this MIO[2] input. External EEPROM: OXmPCI952 device configured from external EEPROM, meet end-user's requirements. overrun detection mechanism built into eeprom controller prevents system from `hanging' incorrectly programmed eeprom. eeprom required this device meet minimum programming requirements. Section 10.1.7
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BLOCK DIAGRAM
MODE FIFOSEL PCI/miniPCI Config. Interface SOUT{1:0] SIN[1:0]
Function Dual UARTs
RTS[1:0] DTR{1:0] CTS{1:0] DSR{1:0]
AD[31:0] C/BE[3:0]#
Interface Data Control
DCD{1:0] RI{1:0]
PCI_CLK FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RESET# INTA# INTB#/CLKRUN# PME# (miniPCI) Interface
Interrupt Logic
Pins
MIO[10:0]
PD[7:0]
ACK# BUSY Parallel Port SLCT ERR# SLIN# INIT# AFD# XTLI XTLO Clock Baud Rate Generator STB#
Function
UART_Clk_Out Local_Bus
LBA7:0] LBCS[3:0] LBD[7:0] Local LBWR#
EE_DI EEPROM Interface
EE_CS EE_CK EE_DO
LBRD# LBRST
DATA_DIR
OXmPCI952 Block Diagram
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INFORMATION-160-PIN LQFP
Pinouts Dual UARTs Parallel Port (Mode
SLCT ERR# SLIN# INIT# AFD# STB# PDOUT MIO8 MIO9 MIO10 PCI/mini-PCI
Dual UARTs 8-BIT Local (Mode
LBA2 LBA3 LBCS0# LBCS1# LBCS2# LBCS3# LBRD# LBWR# LBCLK LBA4 LBA5 LBA6 LBA7 LBDOUT LBD0 LBD1 LBD2 LBD3 LBD4 LBD5 LBD6 LBD7 MIO8 MIO9 MIO10 PCI/mini-PCI
LBA1 LBA0 LBRST LBRST# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 MIO0 INTA# INTB#/CLKRUN# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI952-LQ-A
UART_Ck_Out SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode EE_DI EE_CK
BUSY ACK# MIO7 MIO6 MIO5 MIO4 MIO3 MIO2 MIO1 INTA# INTB#/CLKRUN# RST# PME# AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 C/BE3# IDSEL AD23 AD22 AD21 AD20 AD19 AD18
OXmPCI952-LQ-A
SIN1 RI1# DCD1# XTLO XTLI DSR1# CTS1# DTR1# RTS1# SOUT1 SOUT0 RTS0# DTR0# CTS0# DSR0# DCD0# RI0# SIN0 FIFOSEL Mode EE_DI EE_CK
AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
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AD17 AD16 C/BE2# FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# SERR# C/BE1# AD15 AD14 AD13 AD12 AD11 AD10 C/BE0# EE_CS EE_DO
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Descriptions
actual pinouts OXmPCI952 device this package type, please refer section Pinouts. mini-PCI Interface Mode Mode 139, 140, 141, 143, 144, 145, 147, 148, 151, 152, 155, 156, 157, 160, 149,
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed Address/Data
P_I/O P_I/O P_OD P_OD P_I/O P_OD
C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# INTB# CLKRUN# PME#
Command/Byte enable system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select system reset Default Interrupt Line. Function Function Optional interrupt Line (PCI Mode) ClockRun# Line (mini-PCI mode) Power management event
Serial port pins Mode Mode
Dir1
Name FIFOSEL
O(h)
SOUT[1:0] IrDA_Out[1:0]
Description FIFO select. backward compatibility with 16C550, 16C650 16C750 devices UARTs' FIFO depth when FIFOSEL low. FIFO size increased when FIFOSEL high. unlatched state this readable software. FIFO size also setting FCR[5] when LCR[7] set, putting device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] corresponding channel enhanced mode UART serial data inputs UART IrDA data input when IrDA mode enabled (see above) Active-low modem data-carrier-detect input
I(h) I(h)
SIN[1:0] IrDA_In[1:0] DCD[1:0]#
I(h)
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Serial port pins Mode Mode
Dir1 O(h)
Name DTR[1:0]#
Description Active-low modem data-terminal-ready output. automated DTR# flow control enabled, DTR# asserted deasserted receiver FIFO reaches falls below programmed thresholds, respectively. RS485 half-duplex mode, DTR# programmed reflect state transmitter empty automatically control direction RS485 transceiver buffer (see register ACR[4:3]) Transmitter clock (baud rate generator output). isochronous applications, transmitter clock asserted DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. automated RTS# flow control enabled, RTS# deasserted reasserted whenever receiver FIFO reaches falls below programmed thresholds, respectively. Active-low modem clear-to-send input. automated CTS# flow control enabled, upon deassertion CTS# pin, transmitter will complete current character enter idle mode until CTS# reasserted. Note: flow control characters transmitted regardless state CTS# pin. Active-low modem data-set-ready input. automated DSR# flow control enabled, upon deassertion DSR# pin, transmitter will complete current character enter idle mode until DSR# reasserted. Note: flow control characters transmitted regardless state DSR# External receiver clock isochronous applications. Rx_Clk_In selected when CKS[1:0] `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock used transmitter (and indirectly receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input 20MHz. External clock 60MHz.
O(h)
485_En[1:0]
O(h) O(h)
Tx_Clk_Out[1:0] RTS[1:0]#
I(h)
CTS[1:0]#
I(h)
DSR[1:0]#
I(h) I(h) I(h)
Rx_Clk_In[1:0] RI[1:0]# Tx_Clk_In[1:0] XTLO XTLI
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8-bit local Mode 113, 114, 115, 104, 105, 106, 119, 120, 121, 100, Parallel port Mode
Dir1 O(h) O(h) O(h) O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock drive external UARTs connected local bus. enabled disabled software. Local active-high reset Local active-low reset Local data enable. This used external transceivers; high when LBD[7:0] output mode when they input mode. Buffered clock. enabled disabled software Local active-low Chip-Select (Intel mode) Local active-low Data-Strobe (Motorola mode) Local active-low write-strobe (Intel mode) Local Read-not-Write control (Motorola mode) Local active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local address signals Local data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# asserted (low) peripheral indicate that successful data transfer taken place. Identical function ACK# (EPP mode). Paper Empty. Activated printer when runs paper. Busy (SPP mode). BUSY asserted (high) peripheral when ready accept data Wait (EPP mode). Handshake signal interlocked IEEE 1284 compliant cycles. Select (SPP mode). Asserted host select peripheral Address strobe (EPP mode) provides address read write strobe Peripheral selected. Asserted peripheral when selected. Error. Held peripheral during error condition. Initialise (SPP mode). Commands peripheral initialise. Initialise (EPP mode). Identical function mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read write strobe
I(h) I(h) I(h) I(h)
INTR# BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
OD(h) O(h)
I(h) I(h) OD(h) O(h) OD(h) O(h)
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Parallel port Mode Dir1 OD(h) O(h) 100, I/O(h) Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used peripheral latch data currently available PD[7:0] Write (EPP mode). Indicates write cycle when read cycle when high Parallel data Parallel Port data enable. This should used external transceivers signalling; high when PD[7:0] output mode when they input mode.
Multi-purpose External interrupt pins Dir1 Mode Mode I/O(h) I/O(h) I/O(h) I/O(h)
Name MIO0 MIO1 MIO2 PME_In MIO[10:3]
Description Multi-purpose drive high low, assert interrupt Output Driving `0'. left No-connect. Multi-purpose drive high low, assert interrupt long LCC[6:5] "00"). Output Driving (when LCC[6:5] `00') left No-Connect. Multi-purpose When LCC[7] this drive high low, assert interrupt. Input power management event. When LCC[7] this input assert function PME#. Multi-purpose pins. drive high low, assert interrupt
125, 126, 127, 128,
EEPROM pins Mode Mode
Dir1 IU(h)
Name EE_CK EE_CS EE_DI
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data with internal pull-up. When serial EEPROM connected, this should pulled using 1-10k resistor. connected external EEPROM's EE_DO EEPROM data out. connected external EEPROM's EE_DI pin.
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Miscellaneous pins Dir1 Name MODE Description Mode selection Function Dual UART. Function 8-bit Local Function Dual UART. Function Parallel Port. I(h) PCI/miniPCI PCI/miniPCI selection Pin. Tied mode. Tied High miniPCI mode.
Power ground 110, 118, 154, 103, 109, 117, 136, 142, 146, 153,
Power Supply (3.3V)
Power Supply Ground (0V)
Table Descriptions
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Note Direction key: P_I/O P_OD I(h) IU(h) I/O(h) O(h) OD(h) input output PCITristates bi-directional open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain connect Ground 3.3V power 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, tolerant LVTTL level, tolerant LVTTL level, tolerant Standard Output tolerant (High Voltage BI-Direct output mode) Standard Open-drain Output tolerant (High Voltage BI-Direct open-drain mode)
OXmPCI952
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INFORMATION-176-PIN
Pinouts
Dual UARTs 8-BIT Local (Mode
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO AD21 AD17 AD12 EE_DI Mode0 AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS FIFOSEL RI0# SIN0 DCD0# DSR0# CTS0# DTR0# SOUT0 RTS0# SOUT1 RTS1# DTR1# CTS1# DSR1# XTLI DCD1# XTLO RI1# UART_Ck _Out SIN1 C/BE3# AD23 AD26 IDSEL AD24 AD25 AD27 AD30 AD28 AD29 AD31 PME# INTB#/ CLKRUN# RST# INTA# MIO1 MIO0 MIO2 MIO3 MIO4 MIO5 MIO6 LBA0 LBCS3# LBCLK LBA7 LBD2 LBD4 MIO9 MIO7 LBRST# LBA1 LBCS2# LBA6 LBD0 LBD7 LBRST LBA2 LBWR# LBA4 LBDOUT LBD3 LBD6 MIO10 LBA3 LBCS0# LBCS1# LBRD# LBA5 LBD1 LBD5 MIO8 PCI/ miniPCI
NC-Do connect these pins:
Dual UARTs Parallel Port (Mode
C/BE2# FRAME# TRDY# STOP# C/BE1# EE_CK
AD19 AD18 AD16 IRDY# PERR# AD15 AD13 AD11 EE_DO
AD21 AD17 AD12 EE_DI Mode0
AD22 AD20 DEVSEL# SERR# AD14 AD10 C/BE0# EE_CS FIFOSEL RI0#
C/BE3# AD23
AD26 IDSEL AD24 AD25
AD27
AD30 AD28
AD29 AD31 PME#
INTB#/ CLKRUN# RST# INTA#
MIO1 MIO2 MIO3
MIO4 MIO5 MIO6 STB# MIO9
MIO7 BUSY AFD#
ACK# SLCT SLIN# PDOUT MIO10
ERR# INIT# MIO8 PCI/ miniPCI
SIN0 DCD0# DSR0#
CTS0# DTR0# SOUT0 RTS0#
SOUT1 RTS1#
DTR1# CTS1# DSR1# XTLI
DCD1# XTLO
RI1# Uart_Ck _Out SIN1
NC-Do connect these pins: C15,D15 DS-0020 Page
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Descriptions
actual pinouts OXmPCI952 device this package type, please refer section Pinouts. mini-PCI Interface Mode Mode C9,A8,B9,C8,C7,A6,D6,C6, D5,A4,A3,B4,A2,B2,D3,C2, F2,G4,G2,H3,H2,J4,J1,J2, K1,K3,L4,L3,M1,N1,P1,M2 A5,B1,F1,K4
Dir1 P_I/O
Name AD[31:0]
Description Multiplexed Address/Data
P_I/O P_I/O P_OD P_OD P_I/O P_OD
C/BE[3:0]# FRAME# DEVSEL# IRDY# TRDY# STOP# SERR# PERR# IDSEL RST# INTA# INTB# CLKRUN# PME#
Command/Byte enable system clock Cycle Frame Device Select Initiator ready Target ready Target Stop request Parity System error Parity error Initialisation device select system reset Default Interrupt Line. Function Function Optional interrupt Line (PCI Mode) ClockRun# Line (mini-PCI mode) Power management event
Serial port pins Mode Mode
Dir1
Name FIFOSEL
M7,P6
O(h)
SOUT[1:0] IrDA_Out[1:0]
Description FIFO select. backward compatibility with 16C550, 16C650 16C750 devices UARTs' FIFO depth when FIFOSEL low. FIFO size increased when FIFOSEL high. unlatched state this readable software. FIFO size also setting FCR[5] when LCR[7] set, putting device into enhanced mode. UART serial data outputs UART IrDA data output when MCR[6] corresponding channel enhanced mode UART serial data inputs UART IrDA data input when IrDA mode enabled (see above) Active-low modem data-carrier-detect input
R10,N5
I(h) I(h)
SIN[1:0] IrDA_In[1:0] DCD[1:0]#
P9,P5
I(h)
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Serial port pins Mode Mode M8,N6
Dir1 O(h)
Name DTR[1:0]#
Description Active-low modem data-terminal-ready output. automated DTR# flow control enabled, DTR# asserted deasserted receiver FIFO reaches falls below programmed thresholds, respectively. RS485 half-duplex mode, DTR# programmed reflect state transmitter empty automatically control direction RS485 transceiver buffer (see register ACR[4:3]) Transmitter clock (baud rate generator output). isochronous applications, transmitter clock asserted DTR# pins (see register CKS[5:4]) Active-low modem request-to-send output. automated RTS# flow control enabled, RTS# deasserted reasserted whenever receiver FIFO reaches falls below programmed thresholds, respectively. Active-low modem clear-to-send input. automated CTS# flow control enabled, upon deassertion CTS# pin, transmitter will complete current character enter idle mode until CTS# reasserted. Note: flow control characters transmitted regardless state CTS# pin. Active-low modem data-set-ready input. automated DSR# flow control enabled, upon deassertion DSR# pin, transmitter will complete current character enter idle mode until DSR# reasserted. Note: flow control characters transmitted regardless state DSR# External receiver clock isochronous applications. Rx_Clk_In selected when CKS[1:0] `01'. Active-low modem Ring-Indicator input External transmitter clock. This clock used transmitter (and indirectly receiver) when CKS[6]='1'. Crystal oscillator output Crystal oscillator input 20MHz. External clock 60MHz.
O(h)
485_En[1:0]
O(h) P7,R6 O(h)
Tx_Clk_Out[1:0] RTS[1:0]#
N8,M6
I(h)
CTS[1:0]#
P8,R5
I(h)
DSR[1:0]#
I(h) M10,R4 I(h) I(h)
Rx_Clk_In[1:0] RI[1:0]# Tx_Clk_In[1:0] XTLO XTLI
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8-bit local Mode E12,E13,C15,B15 G12,G13,F15,G14,A15,C14, C13,D12 K13,K14,K15,J12,J14,H12, H15,H13 Parallel port Mode
Dir1 O(h) O(h) O(h) O(h) I/O(h)
Name UART_Clk_Out LBRST LBRST# LBDOUT LBCLK LBCS[3:0]# LBDS[3:0]# LBWR# LBRDWR# LBRD# Hi-Z LBA[7:0] LBD[7:0]
Description Buffered crystal output. This clock drive external UARTs connected local bus. enabled disabled software. Local active-high reset Local active-low reset Local data enable. This used external transceivers; high when LBD[7:0] output mode when they input mode. Buffered clock. enabled disabled software Local active-low Chip-Select (Intel mode) Local active-low Data-Strobe (Motorola mode) Local active-low write-strobe (Intel mode) Local Read-not-Write control (Motorola mode) Local active-low read-strobe (Intel mode) Permanent high impedance (Motorola mode) Local address signals Local data signals
Dir1 I(h)
Name ACK#
Description Acknowledge (SPP mode). ACK# asserted (low) peripheral indicate that successful data transfer taken place. Identical function ACK# (EPP mode). Paper Empty. Activated printer when runs paper. Busy (SPP mode). BUSY asserted (high) peripheral when ready accept data Wait (EPP mode). Handshake signal interlocked IEEE 1284 compliant cycles. Select (SPP mode). Asserted host select peripheral Address strobe (EPP mode) provides address read write strobe Peripheral selected. Asserted peripheral when selected. Error. Held peripheral during error condition. Initialise (SPP mode). Commands peripheral initialise. Initialise (EPP mode). Identical function mode. Auto Feed (SPP mode, open-drain) Data strobe (EPP mode) provides data read write strobe
I(h) I(h) I(h) I(h)
INTR# BUSY WAIT# SLIN# ADDRSTB# SLCT ERR# INIT# INIT# AFD# DATASTB#
OD(h) O(h)
I(h) I(h) OD(h) O(h) OD(h) O(h)
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Parallel port Mode Dir1 OD(h) O(h) K13,K14,K15,J12,J14,H12, H15,H13 I/O(h) Name STB# WRITE# PD[7:0] PDOUT Description Strobe (SPP mode). Used peripheral latch data currently available PD[7:0] Write (EPP mode). Indicates write cycle when read cycle when high Parallel data Parallel Port data enable. This should used external transceivers signalling; high when PD[7:0] output mode when they input mode.
Multi-purpose External interrupt pins Dir1 Mode Mode I/O(h) I/O(h) I/O(h) I/O(h)
Name MIO0 MIO1 MIO2 PME_In MIO[10:3]
Description Multi-purpose drive high low, assert interrupt Output Driving `0'. left No-connect. Multi-purpose drive high low, assert interrupt long LCC[6:5] "00"). Output Driving (when LCC[6:5] `00') left No-Connect. Multi-purpose When LCC[7] this drive high low, assert interrupt. Input power management event. When LCC[7] this input assert function PME#. Multi-purpose pins. drive high low, assert interrupt
L14,K12,L15,A13,C12,B12, A12,D11
EEPROM pins Mode Mode
Dir1 IU(h)
Name EE_CK EE_CS EE_DI
EE_DO
Description EEPROM clock EEPROM active-high Chip Select EEPROM data with internal pull-up. When serial EEPROM connected, this should pulled using 1-10k resistor. connected external EEPROM's EE_DO EEPROM data out. connected external EEPROM's EE_DI pin.
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Miscellaneous pins Dir1 Name MODE Description Mode selection Function Dual UART. Function 8-bit Local Function Dual UART. Function Parallel Port. I(h) PCI/miniPCI PCI/miniPCI selection Pin. Tied mode. Tied High miniPCI mode.
Power ground G1,H4,L1,R2,R7,N9,N10,M11,R12, P11,R13,R14,M13,P15,N15,M14,L 13,J15,F13,E14,B5,B3 H1,K2,L2,N4,R11,G15,E15,D14, B10,B7,A1
Power Supply (3.3V) Power Supply Ground (0V)
Table Descriptions
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Note Direction key: P_I/O P_OD I(h) IU(h) I/O(h) O(h) OD(h) input output PCITristates bi-directional open drain Input Input Input with internal pull-up Bi-Directional Output Output Open drain Open drain connect Ground 3.3V power 3.3v Only 3.3v Only 3.3v Only 3.3v Only LVTTL level LVTTL level, tolerant LVTTL level, tolerant LVTTL level, tolerant Standard Output tolerant (High Voltage BI-Direct output mode) Standard Open-drain Output tolerant (High Voltage BI-Direct open-drain mode)
OXmPCI952
CONFIGURATION OPERATION
drivers then access functions assigned addresses usual fashion, with improved data throughput provided PCI. Each function operates though separate device. However there Local Configuration Registers that used enable signals interrupts, configure timings, improve efficiency multi-port drivers. This architecture enables separate drivers installed each function. Generic port drivers hooked functions individually, more efficient multi-port drivers hook both functions, accessing Local Configuration Registers from either. registers default after reset suitable values typical applications such port serial, combo 2-port serial/1port parallel add-in cards. However, identification, control timing registers redefined using external serial EEPROM.
OXmPCI952 multi-function, target-only device, compliant with Local Specification Revision 3.0, Power Management Specification Revision 1.1. OXmPCI952 affords maximum configuration flexibility treating internal UART's, Local Parallel Port separate logical functions. Each function configuration space therefore recognised configured BIOS separately. functions used configured Mode Selection (pin 45). OXmPCI952 configured system start-up software during bootstrap process that follows reset. system scans reads vendor device identification codes from devices finds. then loads device-driver software according this information configures I/O, memory interrupt resources. Device
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TARGET CONTROLLER
Operation
this Retry, which will signalled response access while OXmPCI952 reading from serial EEPROM. OXmPCI952 performs medium-speed address decoding defined specification. asserts DEVSEL# signal clocks after FRAME# first sampled transaction frames which address chip. internal UARTs accessed with zero wait states inserted. Fast back-to-back transactions supported OXmPCI952 target, master perform faster sequences write transactions UARTs local when inter-frame turn-around cycle required. device supports combination byte-enables Configuration Registers Local Configuration Registers. byte-enable asserted, that byte unaffected write operation undefined data returned upon read. OXmPCI952 performs parity generation checking transactions defined standard. Note this entirely unrelated serial data parity which handled within UART functional modules themselves. parity error occurs during address phase, device will report error standard asserting SERR# signal. However that address/command combination decoded valid access, will still complete transaction though parity check correct. OXmPCI952 does support kind caching data buffering addition that already provided within UARTs transmit receive data FIFOs. general, registers UARTs local prefetched because there side-effects read.
OXmPCI952 responds following Configuration access: OXmPCI952 responds type configuration reads writes IDSEL signal asserted address selecting configuration registers function device will respond configuration transaction asserting DEVSEL#. Data transfer then follows. other configuration transaction will ignored OXmPCI952. reads/writes: address compared with addresses reserved Base Address Registers (BARs). address falls within assigned ranges, device will respond transaction asserting DEVSEL#. Data transfer follows this address phase. UARTs 8-bit Local controller, only byte accesses possible. accesses these regions, controller compares AD[1:0] with byte-enable signals defined specification. access always completed; however correct signal present transaction will have effect. Memory reads/writes: These treated same transactions, except that memory ranges used. Memory access single-byte regions always expanded DWORDs OXmPCI952. other words, OXmPCI952 reserves DWORD byte single-byte regions. device allows user define active byte lane using LCC[4:3] that Big-Endian systems hardware swap byte lane automatically. Memory mapped access single-byte regions, OXmPCI952 compares asserted byte-enable with selected byte-lane LCC[4:3] completes operation match occurs, otherwise access will complete normally bus, will have effect either internal UARTs local controller. other cycles (64-bit, special cycles, reserved encoding etc.) ignored.
Configuration space
OXmPCI952 dual-function device, where each logical function configuration space. required fields standard header implemented, plus Power Management Extended Capability register set. format configuration space shown following tables. general, writes registers that implemented ignored, reads from unimplemented registers return
OXmPCI952 will complete transactions disconnect-with-data, i.e. device will assert STOP# signal alongside TRDY#, ensure that Master does continue with burst access. exception
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5.2.1
Configuration Space Register
Predefined Region
Configuration Register Description
Device Status BIST
Vendor Command
Class Code Revision Header Type Reserved Reserved Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Base Address Register (BAR Reserved Subsystem Subsystem Vendor Reserved Reserved Cap_Ptr Reserved Reserved Reserved Interrupt Interrupt Line User Defined Region Power Management Capabilities (PMC) Data Reserved Next Cap_ID Control/Status Register (PMCSR)
Offset Address
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Configuration Space Default Values
OXmPCI952
Following external eeprom. "Minimum Programming Requirements". Section 10.1.7
Register Name Function DUAL UART Vendor Device Command Status Revision Class Code Header Subsystem Vendor Subsystem Cap. Interrupt Line Interrupt Next Capabilities Control/Status Register Data Register 0x9505
Mode Function 8-Bit LOCAL 0x1415 0x9511 0x0000 0x0290 0x00 0x070006 0x00000001 0x00000001 Unused Unused 0x00000001 0x00000000 0x068000 0x80 0x00000001 0x00000000 0x00000001 0x00000000 Unused Unused 0x1415 0x00000001 0x00000001 Unused Unused 0x00000001 0x00000000 0x070006 0x9505 Function DUAL UART
Mode Function PARALLEL PORT 0x9513 EEPROM W(Bit (Data Scale)
0x070101 0x00000001 0x00000001 0x00000001 0x00000000 Unused Unused
0x0000 0x40 0x00 0x01 0x01 0x00 0x6C02 (PCI mode) 0xEC02 (MiniPCI mode) 0x0000 0x00 (Implemented)
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Accessing logical functions
Access UARTs, Local Parallel Port achieved standard Memory mapping, addresses defined Base Address Registers (BARs) configuration space. BARs configured system allocate blocks Memory space logical functions, according size required function. addresses allocated then used access functions. mapping these BARs, which dependent upon mode device, shown following tables. Function Dual UARTs (Mode Mode Internal UART0 (I/O Mapped) Internal UART1 (I/O Mapped) Unused Unused Local configuration registers (I/O mapped) Internal UARTs/ Local configuration registers (Memory mapped) Function Local (Mode Parallel port (Mode Local (I/O mapped) Parallel port base registers Local (Memory mapped) Parallel port extended registers Local configuration registers (I/O mapped) Local configuration registers (Memory mapped) Unused Unused UART Address Offset from Base Address Function0 Memory space (hex) UART0 UART1
5.3.1 access internal UARTs Memory Space
BAR0 BAR1 used address UARTs individually space, BAR5 used address UARTs Memory Space. function reserves 8-byte block space BAR0 BAR1, byte block memory space BAR5. Once access Memory access enable bits Command register (configuration space) set, UARTs accessed according following tables. UART Address (hex) Offset from UARTs Base Address Function0 space (hex) UART0 UART1 (BAR0) (BAR1)
Note that local registers memory space occupy same Base Address Register (BAR5) internal Dual UARTs Memory Space. selects region accessed. Access addresses will directed internal UARTs, access addresses will directed local registers. When accessing local registers BAR5 (bit set) Fields Define BYTE offset local registers. 00000b register, 00100b register) both cases, fields utilised zeros. This because DWORD used hold single Byte, Memory Space
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above example, user selects LowerAddress-CS-Decode, A[6:5] will used internally decode chip-selects. this example LBA[7:5] always zero, only chip select line LBCS0# selected. this case address offset 00-1Fh asserts LBCS0# other chip-select lines remain inactive permanently.
5.3.2
access 8-bit local
When local enabled (mode access works similar fashion internal UARTs. function reserves block space block memory space. block size user definable range bytes, memory range fixed bytes.
Memory Space:
memory base address registers have allocated fixed size bytes address space. Since Local address lines OXmPCI952 only implements DWORD aligned accesses memory space, bytes addressable space chip select expanded Unlike access, memory access upper address lines always active internal chip-select decoding logic ignores user setting Lower-Address-CS-Decode (LT2[26:23]) uses AD[11:10] decode into chip-select regions. When Local accessed memory space, A[9:2] asserted LBA[7:0]. chip-select regions defined below. Local Chip-Select (Data-Strobe) LBCS0# (LBDS0#) LBCS1# (LBDS1#) LBCS2# (LBDS2#) LBCS3# (LBDS3#) Offset from Function1 (Memory space) Lower Address Upper Limit 000h 3FCh 400h 7FCh 800h BFCh C00h FFCh
space
order minimise usage space, block size BAR0 Function1 user definable range bytes. Having assigned address range, user define adjacent address bits decode four chip selects internally. This facility allows glueless implementation local connecting four external peripheral chips. address range lower address chip-select decoding (Lower-Address-CS-Decode) defined Local Configuration register (see [26:20] section 5.4). 8-bit Local eight address lines (LBA[7:0]) that correspond maximum address space. maximum allowable block size allocated space (i.e. bytes), then access space byte aligned, LBA[7:0] equal AD[7:0] respectively. When user selects address range which less than bytes, corresponding upper address lines will logic zero. region divided into four chip-select regions when user selects second uppermost non-zero address chip-select decoding. example 32bytes space reserved, local address lines A[4:0] active remaining address lines zero. generate four chip-selects user should select Lower-Address-CS-Decode. this case A[4:3] will used internally decode chip-selects, asserting LBCS0# when address offset 00-07h, LBCS1# when offset 08-0Fh, LBCS2# when offset 10-17h, LBCS3# when offset 18-1Fh. region divided into chip-select regions selecting uppermost address decode chip selects. above example, user select Lower-Address-CS-Decode, thus using A[5:4] internally decode chip selects. this example LBA5 always zero, only chip-select lines LBCS0# LBCS1# will decoded into, asserting LBCS0# when address offset 000Fh LBCS1# when offset 10-1Fh. region allocated single chip-select region assigning address beyond selected range Lower-Address-CS-Decode (but above A8). DS-0020
Table address local (memory)
Note: description given memory accesses Inteltype configuration Local Bus. Motorola-type configuration, chip select pins redefined data strobe pins. this mode Local offers address lines four data-strobe pins.
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5.3.3
access parallel port
When parallel port enabled (mode access Parallel Port works definitions usual, except that there BARs corresponding sets registers defined operate IEEE1284 EPP/ECP bi-directional Parallel Port. user change space block size BAR0 over-writing default values LT2[25:20] using serial EEPROM (see section 5.4). example user reduce allocated space BAR0 bytes setting LT2[22:20] `001'. block size allocated BAR1 fixed Bytes. Legacy parallel ports expect upper register mapped 0x400 above base block, therefore BARs fixed with this relationship, generic parallel port drivers used operate device modes. Example: BAR0 0x00000379 bytes address 0x378) BAR1 0x00000779 bytes address 0x778) this relationship used, custom drivers will needed.
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Accessing Local configuration registers
local configuration registers device specific registers which accessed from either function. local configuration registers exist behind BAR4 BAR5 function behind BAR2 BAR3 function transactions, access limited byte reads/writes. Memory Transactions, accesses Word Dword accesses, however little-endian systems such Intel 80x86 byte order will reversed. following table lists definitions local registers, with offsets (from Base Address Register) defined each local register.
5.4.1
Local Configuration Control register `LCC' (Offset 0x00)
This register defines control ancillary functions such Power Management, external clock reference signals serial EEPROM. individual bits described below. Bits Description Mode Status. This returns state Mode pin. Reserved. Enable UART clock output. When this set, buffered version UART clock output "UART_Clk_Out". When this low, UART_Clk_Out permanently low. Endian Byte-Lane Select memory access 8-bit peripherals. Select Data[7:0] Select Data[23:16] Select Data[15:8] Select Data[31:24] Memory access OXmPCI952 always DWORD aligned. When accessing 8-bit regions like internal UARTs, 8-bit Local parallel port, this option selects active byte lane. both architectures little endian, default value will used systems, however, some non-PC architectures need select byte lane. Power-down filter time. These bits define value internal filter time power-down interrupt request power management circuitry Function0. Once Function0 ready into power down mode, OXmPCI952 will wait specified filter time Function0 still power-down request mode, assert interrupt (see section 5.6). power-down request disabled seconds seconds seconds Function1 MIO2_PME Enable. value enables MIO2 PME_Status PMCSR register, hence assert PME# enabled. value disables MIO2 from setting PME_Status (see section 5.6). Reserved. These bits used test purposes. device driver must write zeros these bits. EEPROM Clock. read write EEPROM, toggle this generate EEPROM clock (EE_CK pin). EEPROM Chip Select. When EEPROM chip-select EE_CS activated (high). When EE_CS de-active (low). EEPROM Data Out. writes EEPROM, this output input-data EEPROM. This output EE_DO clocked into EEPROM EE_CK. EEPROM Data reads from EEPROM, this input output-data EEPROM connected EE_DI pin. EEPROM Valid. indicates that valid EEPROM program present Read/Write
EEPROM
Reset
23:8
0000h Page
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Bits
Description Reload configuration from EEPROM. Writing this re-loads configuration from EEPROM. This self-clearing after EEPROM read EEPROM Overrun Indication (when set). conjunction with (Valid EEPROM) this indicates whether successful eeprom download taken place. Successful download will have EEPROM_VALID EEPROM OVERRUN Reserved.
Read/Write
EEPROM
Reset
5.4.2
Multi-purpose Configuration register `MIC' (Offset 0x04)
This register configures operation multi-purpose pins `MIO[10:0], well providing further device controls status, follows. Bits Description MIO0 Configuration Register (When Device Mode `001'/'101'). MIO0 non-inverting input MIO0 inverting input MIO0 output driving MIO0 output driving When Parallel Port enabled, (Device Mode `001'/'101'), MIO[0] unused will remain forcing output mode. MIO1 Configuration Register (When LCC[6:5] `00'). MIO1 non-inverting input MIO1 inverting input MIO1 output driving MIO1 output driving When power-down mode Function enabled (LCC[6:5] `00'), MIO1 unused will remain forcing output mode. MIO2 Configuration Register (When LCC[7]='0'). MIO2 non-inverting input MIO2 inverting input MIO2 output driving MIO2 output driving When LCC[7] set, MIO2 re-defined PME_Input. polarity will controlled MIC[4]. sets sticky PME_Status Function1. MIO3 Configuration Register. MIO3 non-inverting input MIO3 inverting input MIO3 output driving MIO3 output driving MIO4 Configuration Register. MIO4 non-inverting input MIO4 inverting input MIO4 output driving MIO4 output driving
EEPROM
Read/Write
Reset
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Bits 11:10
Description MIO5 Configuration Register. MIO5 non-inverting input MIO5 inverting input MIO5 output driving MIO5 output driving MIO6 Configuration Register. MIO6 non-inverting input MIO6 inverting input MIO6 output driving MIO6 output driving MIO7 Configuration Register. MIO7 non-inverting input MIO7 inverting input MIO7 output driving MIO7 output driving MIO8 Configuration Register. MIO8 non-inverting input MIO8 inverting input MIO8 output driving MIO8 output driving MIO9 Configuration Register. MIO9 non-inverting input MIO9 inverting input MIO9 output driving MIO9 output driving MIO10 Configuration Register. MIO10 non-inverting input MIO10 inverting input MIO10 output driving MIO10 output driving Reserved. device driver must write zeros these bits. Reserved. device driver must write zeros these bits. Reserved. write transactions must affect status this bit.
EEPROM
Read/Write
Reset
13:12
15:14
17:16
19:18
21:20
23:22 25:24
(following eeprom)
MiniPCI Mode Status When set, indicates that device operating miniPCI mode. When clear, device operating mode. Reserved Clock Control Handling Power Management When (1), clock control circuitry handling CLKRUN# line controlled power management states function function This only relevant miniPCI mode operation. Disable Clock Control Circuitry (CLKRUN#) When (1), clock control circuitry handling CLKRUN# line disabled, allowing host stop PCI_CLK next available opportunity. Circuitry enabled default prevent clock stopping. This only relevant miniPCI mode operation.
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Bits
Description Parallel Port Filter Disable When disables noise filters parallel port data lines status lines. Filters enabled default. This only relevant parallel port.
EEPROM
Read/Write
Reset
5.4.3
Local Timing Parameter register `LT1' (Offset 0x08):
Local Timing Parameter registers (LT1 LT2) define operation timing parameters used Local Bus. timing parameters programmed 4-bit registers define assertion/de-assertion Local control signals. value programmed these registers defines number clock cycles after Reference Cycle when events occur, where reference Cycle defined clock cycles after master asserts IRDY# signal. following arrangement provides flexible approach users define desired timing their peripheral devices. timings refer Memory mapped access BAR0 BAR1 Function1. Bits Description Read Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during read operation from Local Bus.1 These bits unused Motorola-type interface. Read Chip-select De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins de-asserted (high) during read from Local Bus. These bits unused Motorola-type interface. Write Chip-select Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBCS[3:0]# pins asserted (low) during write operation Local Bus. These bits unused Motorola-type interface. Write Chip-select De-assertion (Intel-type interface). Defines number clock cycles after reference cycle when LBCS[3:0]# pins de-asserted (high) during write operation Local Bus. Read-not-Write De-assertion during write cycles (Motorola-type interface). Defines number clock cycles after reference cycle when LBRDWR# de-asserted (high) during write Local Bus. Read Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# asserted (low) during read from Local Bus. Read Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during read from Local Bus. Read Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBRD# deasserted (high) during read from Local Bus. Read Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during read from Local Bus. DS-0020 Page Read/Write
EEPROM
Reset
parallel port)
11:8
15:12
19:16
parallel port)
23:20
parallel port)
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OXmPCI952
Bits 27:24
Description Write Control Assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# asserted (low) during write Local Bus. Write Data-strobe Assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins asserted (low) during write Local Bus. Write Control De-assertion (Intel-type interface). Defines number clock cycles after Reference Cycle when LBWR# deasserted (high) during write Local Bus. Write Data-strobe De-assertion (Motorola-type interface). Defines number clock cycles after Reference Cycle when LBDS[3:0]# pins de-asserted (high) during write cycle Local Bus.
Read/Write
EEPROM
Reset parallel port)
31:28
Note
Only values range (0-10 decimal) valid. Other values reserved. notes following page.
5.4.4
Bits 11:8
Local Timing Parameter register `LT2' (Offset 0x0C):
Description Write Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data during write operation Local Bus. Write Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during write operation Local Bus. Read Data Assertion. This register defines number clock cycles after Reference Cycle when pins actively drive data read operation from Local Bus. Read Data De-assertion. This register defines number clock cycles after Reference Cycle when pins high-impedance during beginning read cycle from Local Bus. Reserved. Space Block Size BAR0 Function1. Reserved Bytes Bytes Bytes Bytes Bytes Bytes Bytes Read/Write
EEPROM
Reset parallel port) `100' (=`010' parallel port)
15:12 19:16 22:20
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Bits 26:23
Description Local Chip-select Parameter `Lower-Address-CS-Decode'. space 8-bit Local 1000 0000 1001 0001 1010 0010 1011 0011 1100 0100 1101 0101 1110 0110 1111 0111 Reserved Local Software Reset. When this Local reset activated. When this Local reset de-activated. Local Clock Enable. When this Local clock (LBCK) enabled. When this LBCK permanently low. Local Clock buffered clock. Interface Type. When (=0) Local configured Inteltype operation, otherwise configured Motorola-type operation. Note that when Mode[1:0] `01', this hard wired
Read/Write
EEPROM
Reset `0001' (=`0010' parallel port)
28:27
Note Note Note
Only values range (0-10 decimal) valid. Other values reserved writing higher values causes interface retry accesses Local unable complete transaction clock cycles. Lower-Address-CS-Decode parameter described sections 5.3.2 Section These bits unused Memory access 8-bit Local which uses fixed decoding allocate regions chip selects. further information Local bus, section Local Bus, UARTs Parallel Port reset with reset. Addition, user issue Software Reset Command.
LT2[15:0] enable card designer control data during idle periods. default values will configure Local data pins remain forcing (LT2[7:4] Fh). LT[15:8] programmed place highimpedance beginning read cycle back forcing read cycle. systems that require data stay high-impedance, card designer should write appropriate value range LT2[7:4]. This will place data high impedance write cycle. Whenever value programmed LT2[7:4] does equal Local controller will ignore setting LT2[15:8] data will high-impedance outside write cycles. this case card designer should place external pull-ups data pins LBD[7:0]. While configuration data read from external EEPROM, pins remain high-impedance state. timing registers define Local timing parameters based signal changes relative reference cycle which defined clock cycles after IRDY# asserted first time frame. following parameters fixed relative reference cycle.
Local address pins LBA[7:0] asserted during reference cycle. write operation, Local data available during reference cycle, however buffers change direction programmed LT2[3:0]. Motorola type write operation, Read-not-Write (LBRDWR#) asserted (low) during reference cycle. read cycle this remains high throughout duration operation. default settings registers provide clock cycle address chip-select control signal set-up time, clock cycle address chip-select from control signal hold time, clock cycles pulse duration read write control signals clock cycle data hold time. These parameters acceptable using external OX16C950, OX16C952 OX16C954 devices connected Local Bus, Intel mode. Some redefinition will required operated Motorola mode. user should take great care when programming Local timing parameters. example defining value chip-select assertion which larger that value defined chip-select de-assertion defining chipselect assertion value which greater than control signal assertion will result obvious invalid local cycles.
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5.4.5
UART Receiver FIFO Levels `URL' (Offset 0x10)
receiver FIFO level internal UARTs shadowed Local configuration registers follows: Bits 15:8 31:16 Description UART0 Receiver FIFO Level (RFL[7:0]) UART1 Receiver FIFO Level (RFL[7:0]) Reserved Read/Write
EEPROM
Reset 0x00h 0x00h 0x0000h
5.4.6
UART Transmitter FIFO Levels `UTL' (Offset 0x14)
transmitter FIFO level UARTs shadowed Local configuration registers follows: Bits 15:8 31:16 Description UART0 Transmitter FIFO Level (TFL[7:0]) UART1 Transmitter FIFO Level (TFL[7:0]) Reserved Read/Write
EEPROM
Reset 0x00h 0x00h 0x0000h
5.4.7
UART Interrupt Source Register `UIS' (Offset 0x18)
UART Interrupt Source register described below: Bits 11:6 26:12 30:29 Description UART0 Interrupt Source Register (ISR[5:0]) UART1 Interrupt Source Register (ISR[5:0]) Reserved UART0 Good-Data Status UART1 Good-Data Status Reserved Global Good-Data Status. This logical bits i.e. Good-Data Status internal UARTs set. Read/Write
EEPROM
Reset XXXh
Good-Data status given internal UART when following conditions met: reads level0 (no-interrupt pending), level (receiver data available, level (receiver time-out) level (transmitter empty) interrupt LSR[7] clear there parity error, framing error break FIFO LSR[1] clear over-run error occurred
device driver software reads receiver FIFO levels (URL) followed this register, then Good-Data status given channel set, driver remove number bytes indicated FIFO level without need read line status register that channel. This feature enhances driver efficiency. given channel, Good-Data status set, then software driver should examine corresponding bits. example low, then driver should examine bits down obtain ISR[5:0] UART1. indicates level higher interrupt, interrupt change state modem lines detection flow control characters. device driver-software should then take appropriate measures would other 550/950 driver. When indicates level (receiver status) interrupt then driver examine Line Status Register (LSR) relevant channel. DS-0020 Page
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OXmPCI952
Since reading clears LSR[7], device driver-software should either flush empty contents receiver FIFO, otherwise Good-Data status will longer valid. UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) Global Interrupt Status register (GIS) allocated adjacent address offsets (10h 1Ch) Base Address Register. device driver-software read above registers single burst read operation. location offset registers such that FIFO levels usually read before status registers that status characters indicated receiver FIFO levels valid.
5.4.8
Bits
Global Interrupt Status Control Register `GIS' (Offset 0x1C)
Description UART Interrupt Status. These bits reflect internal interrupt states UART1 UART0, respectively.1 Reserved. MIO0 Status (When device mode This reflects state internal MIO[0]. internal MIO[0] reflects non-inverted inverted state MIO0 pin.2 When device mode this reflects state Parallel Port Interrupt. MIO1 Status (LCC[6:5]=`00'). This reflects state internal MIO[1]. internal MIO[1] reflects non-inverted inverted state MIO1 pin.2 Function Power-down Interrupt (LCC[6:5] `00'). this mode this sticky bit. When set, indicates power-down request issued Function would normally have asserted interrupt (see section 8.6). Reading this clears MIO[10:2] Status. These bits reflect state internal MIO[10:2]. internal MIO[10:2] reflect non-inverted inverted state MIO[10:2] pins respectively.2 Reserved. UART Interrupt Mask. When these bits enable internal UARTs assert interrupt respectively. When cleared (=0) they prevent respective channel from asserting interrupt.3 Reserved MIO[0] Interrupt Mask (When device mode When (=1) this enables MIO0 assert interrupt. When cleared (=0) prevents MIO0 from asserting interrupt.2 Parallel Port Interrupt Mask (When device mode When (=1) this enables Parallel Port assert interrupt. When cleared (=0) prevents Parallel Port from asserting interrupt. MIO[1] Interrupt Mask (LCC[6:5]=`00'). When (=1) this enables MIO1 assert interrupt. When cleared (=0) prevents MIO1 from asserting interrupt.2 Function Power-down Interrupt Mask (LCC[6:5] `00'). When (=1) this enables power-down logic Function0 assert interrupt. When cleared (=0) prevents power-down logic Function from asserting interrupt. Read/Write
EEPROM
Reset 0x0h 0x0h
XXXh
14:6 17:16 19:16
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OXmPCI952
Bits 30:22
Description Interrupt Mask. When (=1) these bits enable each MIO[10:2] assert interrupt respectively. When cleared (=0) they prevent respective pins from asserting interrupt.2 Reserved.
Read/Write
Reset 1FFh
Note Note
GIS[3:0] inverse UIS[18], UIS[12], UIS[6] UIS[0] respectively. Systems that require Local parallel port need read this register identify source interrupt long they read (offset 18h) register. returned value either direct state corresponding inverse configured Multi-purpose Configuration register `MIC' (offset 0x04). internal assert interrupt, inversion feature define each external interrupt defined active-low active-high, controlled register. When MIO[0] been set-up input output, this made generate interrupt when MIO[0] Interrupt Mask (bit (=1). This enables MIO[0] assert interrupt. When MIO[1] been set-up input output, this made generate interrupt when MIO[1] Interrupt Mask (bit (=1). This enables MIO[1] assert interrupt.
Note
UART Interrupt Mask register bits after hardware reset enable interrupt from both internal UARTs. This will cater generic device-driver software that does access Local Configuration Registers. default setting UART Interrupt Mask bits changed using serial EEPROM. Note that even though default UART interrupts enabled this register, since after reset registers individual UARTs disables interrupts, interrupt will asserted after hardware reset.
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OXmPCI952
Interrupts
During system initialisation process device configuration, system-specific software reads interrupt field determine which any) interrupt used each function. programmes system interrupt router logically connect this interrupt system-specific interrupt vector (IRQ). then writes this routing information Interrupt Line field function's configuration space. Device driver software must then hook interrupt using information Interrupt Line field. Interrupt status thirteen sources interrupt available using register Local Configuration Register set, which accessed using Memory accessed from both logical functions. This facility enables each function snoop interrupts asserted from other function regardless interrupt routing. interrupt from each UART channel enabled using register register that UART. interrupt enabled active, then device will drive interrupt low. Generic device driver software will register enable interrupts. OXmPCI952 offers additional interrupt masking ability using GIS[17:16] (see section 5.4.8). internal UART channel assert interrupt interrupt enabled GIS[17:16]. interrupts enabled disabled individually using register Local configuration registers. When enabled, external device assert interrupt driving that pin. sense external interrupt pins (active-high active-low) defined register. parallel port also assert interrupt (but this will effectively disable MIO[0] interrupt).
Interrupts systems level-sensitive shared. There thirteen sources interrupt OXmPCI952, each UART channel eleven from Multi-Purpose pins (MIO10 MIO0). Parallel Port MIO[0] share same interrupt status (GIS[4]). Power Management powerdown interrupt internal UARTs (Function0) MIO[1] share status GIS[5]. Local uses pins pass interrupts controller. Function Function interrupts assert INTA# line, default. These default routings modified writing Interrupt field configuration registers using serial EEPROM facility. Interrupt field normally considered hard-wired read-only value PCI. indicates system software which interrupt any) used function. interrupt only modified using serial EEPROM facility, card developers must invoke combination which violates specification. doubt, default routings should used. Following Table relates Interrupt field device used. Interrupt Device used None INTA# INTB# Reserved
Note that OXmPCI952 only interrupt pins INTA# INTB#. miniPCI mode, INTB# available interrupt line redefined dedicated CLKRUN# line.
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Power Management
5.6.1
Power Management Function
OXmPCI952 compliant with Power Management Specification Revision 1.1. This indicated both functions their Power Management Capabilities Register (PMC). Each logical function implements Power Management registers supports power states miniPCI modes, PME# generation from D3cold also indicated which preserves PME# context through 3.3v Auxiliary power. section "miniPCI Support" further details. Power management accomplished handling power-down power-up ("power management event") requests, that asserted relevant function's interrupt PME# respectively. Each function assert PME# independently. Power-down requests defined Power Management specifications. device-specific feature requires bespoke device driver implementation. device driver either implement power-down itself special interrupt powerdown features offered device determine when function device ready power-down. worth noting that PME# can, certain cases, activate PME# signal when power removed from device. This will cause wake from Lowpower state D3(cold). ensure full cross-compatibility with system board implementations, isolator recommended (See Diagram). Power Management capabilities required, PME# treated no-connect.
Provided that necessary controls have been device's local configuration registers (LCC GIS), internal UARTs programmed issue powerdown requests and/or `wakeup' requests (power management events), function Function configured monitor activity serial channels, issue power-down interrupt when both UARTs inactive interrupts pending both transmitters receivers idle). When both serial channels indicating powerdown request only then will internal power management circuitry wait period time programmed into Power-Down Filter Time. This time defined local configuration register, LCC[7:5]). powerdown requests remain valid this time (this means that both serial channels still inactive) then OXmPCI952 will issue powerdown interrupt this function's interrupt pin, this option enabled. Alternatively, device driver poll function powerdown status field local configuration register GIS[5] determine powerdown request. powerdown filter stops UARTs from issuing many powerdown interrupts whenever UARTs activity intermittent. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXmPCI952 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: internal clock internal UARTs shut down. interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled. device driver optionally assert/de-assert selected (design dependent) pins switch-off VCC, disable other external clocks, activate shut-down modes. device only issue wakeup request power management event, PME#) enabled this function's PME_En bit, bit-8 Power Management Register
PME#
connector PME#
PME# Isolator Circuitry
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PMCSR. PME# assertion, immediate does powerdown filter timer. operates even powerdown filter time disabled. Like powerdown, wakeup requests function generated each serial channel. means generate wakeup events from these sources will have been prior placing this function into powerdown states (including setting PME_En bit). each UARTs, when device (function powerstate only activity serial channel's line (the trailing edge pulse) will generate wakeup event. When device (function power-state then wake-ups configurable. this case, change state modem line (which enabled 16C950-specific mask bit) change state serial input line (again, enabled 16C950specific mask bit) issue wake request PME# pin. worth noting that after hardware reset these mask bits cleared enable wake assertion from modem lines line when powerstate wake operation from requires least mask enabled, device driver example disable masks with exception Ring Indicator, only modem ring wake computer. case wake request from serial input line EXT_DATA_IN (from power state then clock that channel turned serial data framing maintained. When function issues wake request from serial channels, PME_Status this function's power management registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue assert PME# inform device driver that power management wake event occurred. After wake event signalled, device driver expected return this function powerstate.
OXmPCI952
state pin(s) that issues powerdown request controlled register. This active high active Low. This state same state that asserts function interrupt normal functionality. assertion pins will result function powerdown request being made immediately. There powerdown filtering time associated with function powerdown request issued function's interrupt pin, this option enabled. Upon power down interrupt, device driver change power-state device (function required. Note that power-state function only changed device driver point will OXmPCI952 change power state. powerdown interrupt merely informs device driver that this logical function ready power down. Before placing device into lower power states, driver must provide means function generate `wakeup' (power management) event. Whenever device driver changes function powerstate state device takes following actions: Parallel Port placed power mode. Local Function placed power mode interrupts disabled regardless values contained registers. Access Memory BARs disabled. However, access configuration space still enabled. Function only issue wakeup request (power management event) enabled this function's PME_En bit, bit-8 Power Management Register PMCSR. Wakeup requests function only generated Multi_Purpose MIO[2]. means generate wakeup events from this source will have been prior placing this function into powerdown states state MIO[2] that results wakeup requests determined settings local configuration register MIC. soon correct logic invoked than power management event (wakeup) asserted. PME# event immediate. When function issues wake request, PME_Status this function's power management registers (PMCSR[15]) will set. This sticky which will only cleared writing While PME_En (PMCSR[8]) remains set, PME_Status will continue assert PME# inform device driver that Page
5.6.2
Power Management function
Provided that necessary controls have been device's local configuration registers (MIC GIS), Multi_Purpose pins (MIO[10:3]) programmed issue powerdown requests only MIO[2] generate `wakeup' requests (power management events), function Parallel Port Local function capable issuing powerdown requests power management events placed power state through power management involving pins.
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power management wake event occurred. After wake event signalled, device driver expected return this function power-state
OXmPCI952
LCC[6:5]
GIS[21]
Power-down Filter Time
Operation Function power-down interrupt disabled. MIO[1] assert interrupt GIS[21] set. Function power-down interrupt disabled. GIS[5] reflects state internal power-down mode polling operation. MIO[1] interrupt disabled Function power-down enabled. GIS[5] reflects state internal power-down mode. MIO[1] interrupt disabled.
Table Function (UARTs) Power down interrupt settings
LCC[7]
MIC[5:4]
MIO2 Rising
MIO2 Falling
Function1 PME_Status Remains unchanged Gets Remains unchanged Gets Remains unchanged
Table Function (Local Bus) Wake-up configuration
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MiniPCI Support
miniPCI mode, following changes take place device functionality definitions.
OXmPCI952 device operates miniPCI mode when (PCI/miniPCI Selection pin) tied HIGH. Otherwise, device operates mode.
Function/Pin Z_INTA Z_INTB D3cold Support
MiniPCI mode interrupt both function function Redefined CLKRUN# interrupts available this PME# from Cold supported Available indicated Power Management Registers
Mode Interrupt pin. both function function Optional interrupt Unused default. PME# cold supported. indicated Power Management Registers.
CLKRUN# OXmPCI952 device tolerant clock stopping PCI_CLK line, full UART functionality. While UARTs themselves dependent upon PCI_CLK line, crystal oscillator their main clock source, some parts device require that PCI_CLK operational stopped) allow reliable operation internal UARTs. Such parts include writing/reading UART registers interrupt handling. this reason, OXmPCI952 device implements CLKRUN# prevent host from stopping PCI_CLK (until such time needed). circuitry handling CLKRUN# line compliant CLKRUN# requirements defined Mobile Design Guide, version 1.1. Provided that Central Resource holds CLKRUN# line active (low), indicate that PCI_CLK enabled, then there intervention OXmPCI952 device which keeps it's side CLKRUN# driver inactive. CLKRUN# line bi-directional pin. When Central Resource synchronously de-asserts CLKRUN# line initially driven line high then leaving high impedance state) signal Central Resource's intention stop slow) PCI_CLK, then prevented from doing target that asserts (drives low) CLKRUN# line clock cycles following de-assertion. CLKRUN# line only asserted target clock cycles, during which time Central Resource expected drive (and hold) CLKRUN# line asserted, until next attempt host stop clock. this case, cycle repeats. default, clock control circuitry OXmPCI952 miniPCI mode) always enabled. This means that Central Resource prevented from stopping PCI_CLK DS-0020
times, requests Central Resource stop this clock de-asserting CLKRUN# line) target re-asserting CLKRUN# line 2-clock cycles later. This issue from power management point view this default behaviour prevent system from going into power state result system being partially shut-down need maintain PCI_CLKs OXmPCI952 based miniPCI card. clock control circuitry associated with CLKRUN# line been provided with controls help overcome this. miniPCI mode, local registers provide controls associated with CLKRUN# line. These Read-Write fields accessible transactions external EEPROM downloading into register Local Register Zone. Control CLKRUN# Circuitry Disable CLKRUN# Control Power Management Register Default State
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OXmPCI952
most suitable point disable clock control circuitry. Disabling clock control circuitry when OXmPCI952 device fully operational state state) recommended some hosts have been designed periodically attempt stop PCI_CLK normal routine. these cases, clock control circuitry been disabled then PCI_CLK will stopped next opportunity. large file transfers are/will taking place when this event occurred then this lead corrupted data being transmitted/received. addition Clkrun# Circuitry Disable bit, there additional control called Clkrun# Control Power Management. name suggests, this allows clock control logic associated with CLKRUN# line controlled Power Management states OXmPCI952 device. This hardware assist does require software involvement with exception enabling this field place (although this also achived external eeprom). When Clkrun Control Power Management selected, device makes knowledge that attempts host (Central Resource) place both functions into power state (states power management terminology) pre-empt condition host stopping PCI-CLK OXmPCI952 device order reduce power consumption card thus system. host expected stop PCI-CLK OXmPCI952 device when least functions fully operation state state). statemachine been built-in that handles clock control circuitry according states each function. This shown overleaf.
Bits 30:29
CLKRUN Circuitry Status CLKRUN#' Operation Enabled (Never Stop PCI-CLK) CLKRUN# Operation Power Management Control CLKRUN# Operation Disabled (Allow PCI_CLK stop) CLKRUN# Operation Disabled (Allow PCI_CLK stop)
Clkrun# Circuitry Disable bit, allows device drivers disable (and re-enable) clock control circuitry associated with CLKRUN# line meet overall Power Management device system. When CLKRUN# circuitry disabled, then when CLKRUN# line deasserted Central Resource next available opportunity, attempt made target assert CLKRUN# line thereby allowing Central Resource stop PCI_CLK. Once PCI_CLK stopped, still possible re-enable clock circuitry writing disable field (with `0') Central Resource expected restart PCI_CLK sufficient time allow write transaction take place. Once transaction been completed, clock control circuitry will then prevent central resource from stopping PCI_CLK until clock control circuitry again disabled. While perfectly feasible that clock control circuitry disabled (re-enabled) leisure, clock control circuitry should only disabled prior device being placed into power states D2/D3 host, when operations other than wake-up expected from UARTs. Some interaction between device drivers host will required determine
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OXmPCI952
Reset Enable CLKRUN#
CLKRUN# Circuitry Enabled (Either Function state)
Both Functions Placed Power State Disable CLKRUN#
CLKRUN# Disabled (Both Functions power State) PME# Event (wake-up) Enable CLKRUN# Both functions return fully operation state (D0) CLKRUN# Circuitry Enabled (both function power State)
When either functions PowerManagement state, CLKRUN# circuitry enabled prevent host from stopping PCI_CLK, times. When host places both functions into power states then, only then, CLKRUN# circuitry disabled. This means that host will able stop PCI_CLK next available opportunity, which likely purpose placing both functions into power state. Once power state, OXmPCI952 device driven PCI_CLKs controls would have been device drivers allow OXmPCI952 device generate `wake-up' PME# events. This PME# generation will Z_CTS Z_RI pins function0, MIO-2 function When OXmPCI952 generates PME# event, this event sufficient attention Central Resource that will kick-start host restart PCI_CLKs device. same PME# event used internally
enable CLKRUN# circuitry, that host attempts stop PCI_CLK before both functions placed back into (fully operational state) then prevented from doing CLKRUN# circuitry only disabled again cycle repeated) once both functions placed back into fully operation state host expected this following PME# wake-up event. OXmPCI952 device should only used with hosts that implement CLKRUN# line CLKRUN# protocol. Some hosts have CLKRUN# line necessarily implement CLKRUN# protocols, instead leaving CLKRUN# permanently held active (low) state. This will taken OXmPCI952 device PCI_CLK always running. Such hosts then remove PCI_CLK from OXmPCI952 device without notification CLKRUN# line when requesting SUSPEND function. This lead corrupted data when file transfers subsequently take place owing loss PCI_CLK.
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PME# Generation from Cold miniPCI mode, OXmPCI952 supports PME# generation from cold state. This indicated both functions' power management register (Power Management Capabilities) that indicates "PME# asserted from D3cold". modes, register makes such indications Power Management Status PME# context will lost following Reset. PME# generation D3cold, OXmPCI952 required make auxiliary 3.3v power when main 3.3v power been removed. Chapter Local Power Management Interface Specification. This changeover to/from main/auxiliary power needs handled external circuitry that supplies OXmPCI952, such cause supply interruptions (dropouts) OXmPCI952 device concerned. Otherwise, this will result loss OXmPCI952's internal states. circuits must such that there sneak-paths between main 3.3v power Auxiliary 3.3v power these power planes isolated times (miniPCI cards cannot connect 3.3v 3.3v main, vice versa). When OXmPCI952 device been provide wake-up events (PME#), then OXmPCI952 device will generate PME# events Z_RI lines function MIO_2 line function when device cold state (while auxiliary powered). OXmPCI952 miniPCI mode preserves PME# context when device transitioned from cold (uninitialised) transition Hardware Reset invoked RST# line. PME# Context also preserved following soft reset when restoring function from D3hot state.
When preserving PME# context, OXmPCI952 maintains status following registers function's PMCSR register. Status PME_Status function's PMCSR register. result, this preserves Status PME# line. Preserving PME# Context issues that need handled host. These listed here reference purposes only. Since reset does affect status fields PME_En PME_Status, there possibility that when power first supplied OXmPCI952 device miniPCI mode operation) that state PME# line unknown (PME_status unknown). host controller must able handle this condition until these fields have been intialised writing them with appropriate values. This been noted Section 3.2.4 Power Management Specification revision 1.1, that states "system software required explicitly initialize PME# context, functions, during initial operating system load." when PME# generation from D3cold supported. D3cold state, when OXmPCI952 generates `wake-up' (PME#) event, then this status (PME# wakeup) persists when OXmPCI952 transitioned from D3cold state D0(uninitialised) Reset. host controller must able handle this condition until PME_status and/or PME_En bits have been wriiten with appropriate values disable PME# wake-up request. Status PME_En
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Device Drivers
This section been provided external device driver development. Device Drivers required know whether device operating miniPCI environments, purposes fine-tuning drivers match feature content OXmPCI952 device. order device drivers distinguish between these modes operation, some fields existing local registers have been defined indicate mode operation. These follows Local Register Register (DWORD offset 00h) Status MODE (Read only) Local Register Register (DWORD offset 04h) MiniPCI Status (Read Only) CLKRUN control Power Management
(R/W field miniPCI application) Disable CLKRUN control (R/W field MiniPCI) Disable Parallel Port Filter (R/W field Parallel Port)
expected that device drivers will inspect least) register determine device operating miniPCI environment. This information required order make controls miniPCI applications. Device drivers will already know what functions present (such 8-bit local Parallel Port) virtue Device that automatically presented operating system during initial configuration.
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INTERNAL OX16C950 UARTS
Each UART channels OXmPCI952 operates individually OX16C950 high-performance serial port. Each channel full registers, share common clock FIFOSEL pin. After device reset, common configuration state loaded into both channels, after this time each channel operated individually through byte block addressable space.
Operation mode selection
Each channel backward compatible with 16C450, 16C550, 16C654 16C750 UARTs. operation ports depends number mode settings, which referred throughout this section. modes, conditions corresponding FIFO depth tabulated below: UART Mode Extended 9501 FIFO size FCR[0] Enhanced mode (EFR[4]=1) FCR[5] (guarded with LCR[7] FIFOSEL
Note mode configuration identical configuration
Table UART Mode Configuration increased writing FCR[5]. Note that access FCR[5] protected LCR[7]. i.e., FCR[5], software should first LCR[7] temporarily remove guard. Once FCR[5] set, software should clear LCR[7] normal operation. 16C750 additional features available long UART into Enhanced mode; i.e. ensure EFR[4] `0'. These features are: Deeper FIFOs Automatic RTS/CTS out-of-band flow control Sleep mode
6.1.1
Mode
After hardware reset, FIFO Control Register (`FCR') cleared, hence UARTs compatible with 16C450. transmitter receiver FIFOs (referred `Transmit Holding Register' `Receiver Holding Register' respectively) have depth one. This referred `Byte mode'. When FCR[0] cleared, other mode selection parameters ignored.
6.1.2
Mode
Connect FIFOSEL GND. After hardware reset, writing FCR[0] will increase FIFO size providing compatibility with 16C550 devices.
6.1.5
Mode
6.1.3
Extended Mode
Connect FIFOSEL VDD. Writing FCR[0] will increase FIFO size 128, thus providing device with deep FIFOs.
6.1.4
Mode
compatibility with 16C750, connect FIFOSEL GND. Writing FCR[0] will increase FIFO size similar fashion 16C750, FIFO size further
UART compatible with 16C650 when EFR[4] set, i.e. device Enhanced mode. software drivers usually device Enhanced mode, running drivers UART channels will result compatibility with deep FIFOs, long FCR[0] set. This regardless state FIFOSEL pin. Note that emulation mode OXmPCI952 provides 128-deep FIFOs rather than provided legacy 16C654.
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enhanced (650) mode device following features available over those provided generic 550. (Note: some these similar those provided mode, enabled using different registers). Deeper FIFOs Sleep mode Automatic in-band flow control Special character detection Infra-red "IrDA-format" transmit receive mode Transmit trigger levels Optional clock prescaler
OXmPCI952
trigger levels enabled when ACR[5] where bits ignored. Then arbitrary trigger levels defined RTL, TTL, registers (see section 6.11). Additional Status Register (`ASR') offers flow control status local remote transmitters. FIFO levels readable using registers. UART flexible prescaler capable dividing system clock value between 31.875 steps 0.125. divides system clock arbitrary value "M+N/8" format, where 3-bit binary numbers programmed CPR[7:3] CPR[2:0] respectively. This arrangement offers great deal flexibility when choosing input clock frequency synthesise arbitrary baud rates. default division value provide backward compatibility with 16C650 devices. user apply external clock transmitter receiver DSR# respectively. transmitter clock instead asserted DTR# pin. external clock options selected through register (offset 0x02 ICR). also possible define over-sampling rate used transmitter receiver clocks. 16C450/16C550 compatible devices employ times over-sampling, where there clock cycles bit. However UART channels employ over-sampling rate from programming register. This allows data rates increased 460.8 Kbps using 1.8432MHz clock, Mbps using clock. default value after reset this register 0x00, which corresponds cycle sampling clock. Writing 0x01, 0x02 0x03 will also result cycle sampling clock. program value value from necessary write this value into i.e. device cycle sampling clock would necessary write 0x0D TCR. further information section 6.10.3 UARTs also offer 9-bit data frames multi-drop industrial applications.
6.1.6
Mode
additional features offered mode generally only apply when UART Enhanced mode (EFR[4]='1'). Provided FCR[0] set, Enhanced mode FIFO size regardless state FIFOSEL. Note that mode configuration identical that mode, however additional specific features enabled using Additional Control Register `ACR' (see section 6.11.3). addition larger FIFOs higher baud rates, enhancements mode over emulation mode are: Selectable arbitrary trigger levels receiver transmitter FIFO interrupts Improved automatic flow control using selectable arbitrary thresholds DSR#/DTR# automatic flow control Transmitter receiver optionally disabled Software reset device Readable FIFO fill levels Optional generation RS-485 buffer enable signal Four-byte device identification (0x16C9500A) Readable status automatic in-band out-ofband flow control External clock modes (see section 6.10.4) Flexible "M+N/8" clock prescaler (see section 6.10.2) Programmable sample clock allow data rates Mbps (see section 6.10.3). 9-bit data mode Readable register
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Register description tables
Each UART accessed through 8-byte block space through memory space). Since there more than registers, mapping also dependent state Line Control Register `LCR' Additional Control Register `ACR': LCR[7]=1 enables divider latch registers DLM. specifies data format used both transmitter receiver. Writing 0xBF unused format) enables access compatible register set. Writing this value will LCR[7] leaves LCR[6:0] unchanged. Therefore, data format transmitter receiver data affected. Write desired value exit from this selection. ACR[7]=1 enables read access specific status registers. ACR[6]=1 enables read access Indexed Control Register (ICR) registers described page
Register Name 650/950 Mode 550/750 Mode mode mode mode 550/750 Mode 650/950 Mode Normal 9-bit data mode Address interrupt mask interrupt mask
Data transmitted Data received Special Char. Sleep Detect mode Alternate Unused sleep mode Trigger Trigger Level Level Trigger FIFO Unused Level Size Unused FIFOs enabled Divisor latch access break Interrupt priority (Enhanced mode) Force parity Flow Control XON-Any Empty even parity Enable Internal Loop Back Break Parity enable Modem interrupt mask Stat interrupt mask THRE interrupt mask RxRDY interrupt mask
Trigger Enable
Flush
Flush
Enable FIFO
Interrupt priority (All modes) Number stop bits
Interrupt pending Data length
Unused Baud prescale Data Error IrDA mode Empty
OUT2 (Int
OUT1
Framing Error
Parity Error
Overrun Error
RxRDY
Normal 9-bit data Unused mode data Additional Standard Registers These registers require divisor latch access (LCR[7]) Divisor latch bits [7:0] (Least significant byte) Divisor latch bits [15:8] (Most significant byte)
data Delta Trailing edge Temporary data storage register Indexed control register offset value bits
Delta
Delta
Table Standard Compatible Registers
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Register Name XON1 9-bit mode XON2 9-bit mode XOFF1 9-bit mode XOFF2 9-bit mode
Address
access these registers must 0xBF Special Enhance In-band flow control mode flow Flow char mode control control detect Character Special character Character Special Character XOFF Character Special character XOFF Character Special character
Table Compatible Registers
Register Name 1,6,7 3,8,9
Address
Idle
FIFO size
FIFOSEL
Remote Disabled
Disabled
Special Char Detect Number characters receiver FIFO
Number characters transmitter FIFO Data read/written depends value written prior access this register (see Table
Table Specific Registers
Register access notes:
Note Requires LCR[7] Note Requires ACR[7] Note Requires that last value written 0xBF Note read this register ACR[7] must Note read this register ACR[6] must Note Requires ACR[7] Note Only bits this register written Note read this register ACR[6] must Note This register acts window through which read write registers Indexed Control Register
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Register Name
Offset 0x00
Additiona Status Enable
Indexed Control Register definition Read Trigger control Enable Level Enable
PIDX
0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0X0F 0X10 0x12 0x13
FCR[7] Mode Unused Unused Unused Unused
Auto Disable Disable Flow Control Enable "integer" part "fractional" part clock prescaler clock prescaler Unused N-times clock selection bits [3:0] BDOUT Receiver Select Mode Clock Sel[1:0] Transmitter Interrupt Trigger Level (0-127) Receiver Interrupt Trigger Level (1-127) Automatic Flow Control Lower Trigger Level (0-127) Automatic Flow Control Higher Trigger level (1-127) Hardwired byte (0x16) Hardwired byte (0xC9) Hardwired byte (0x50) Hardwired revision byte (0x0A) Writing 0x00 this register will reset UART (Except register) SChar SChar SChar SChar Modem Trailing wakeup Wakeup edge Wakeup disable Disable disable disable FCR[5] FCR[4] FCR[3] FCR[2]
Unused FCR[6]
9th-bit Int. Wakeup disable FCR[1]
Enable Wakeup disable FCR[0] Good data status Invert internal clock
Hardwired Port Index 0x00, 0x01, 0x02, 0x03 according which UART Res. Res. Invert Invert Unused Write Write internal signal clock
Table Indexed Control Register
Note offset column indicates value that must written into prior reading writing Indexed Control Registers ICR. Offset values listed table reserved future must used.
read write Indexed Controlled Registers following procedure: Writing registers: Ensure that last value written 0xBF (reserved compatible register access value). Write desired offset (address 111b). Write desired value (address 101b). Reading from registers: Ensure that last value written 0xBF (see above). Write 0x00 offset select ACR. (ICR read enable) writing x1xxxxxxb address 101b. Ensure that other bits changed.
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(Software drivers should keep copy contents elsewhere since reading involves overwriting ACR!) Write desired offset (address 111b). Read desired value from (address 101b). Write 0x00 offset select ACR. Clear writing x0xxxxxxb ICR, thus enabling access standard registers again.
OXmPCI952
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6.3.1
Reset Configuration
Hardware Reset 6.3.2 Software Reset
After hardware reset, writable registers reset 0x00, with following exceptions: DLL, which reset 0x01. CPR, which reset 0x20. state read-only registers following hardware reset follows: RHR[7:0]: RFL[6:0]: TFL[6:0]: LSR[7:0]: Indeterminate 00000002 00000002 0x60 signifying that both transmitter transmitter FIFO empty MSR[3:0]: 00002 MSR[7:4]: Dependent modem input lines DCD, respectively ISR[7:0]: 0x01, i.e. interrupts pending ASR[7:0]: 1xx000002 reset state output signals tabulated below: Signal SOUT RTS# DTR# Reset state Inactive High Inactive High Inactive High
additional feature available OX16C950 UART software resetting serial channel. This command same effect single channel hardware reset except does reset clock source selections (i.e. register). reset UART write 0x00 Channel Software Reset register `CSR'.
Table Output Signal Reset State
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Transmitter receiver FIFOs
Byte mode FIFO mode. This will return zero after clearing FIFOs. FCR[2]: Flush logic change. logic Flushes contents THR, same manner FCR[1] does RHR.
Both transmitter receiver have associated holding registers (FIFOs), referred transmitter holding register (THR) receiver holding register (RHR) respectively. normal operation, when transmitter finishes transmitting byte will remove next data from proceed transmit empty, will wait until data written into empty last character being transmitted been completed (i.e. transmitter shift register empty) transmitter said idle. Similarly, when receiver finishes receiving byte, will transfer bottom RHR. full, overrun condition will occur (see section 6.5.3). Data written into bottom queue read from queue completely asynchronously operation transmitter receiver. size FIFOs dependent setting register. When Byte mode, these FIFOs only accept byte time before indicating that they full; this compatible with 16C450. When FIFO mode, size FIFOs either (compatible with 16C550) 128. Data written when full lost. Data read from when empty invalid. empty full status FIFOs indicated Line Status Register `LSR' (see section 6.5.3). Interrupts generated when UART ready data transfer to/from FIFOs. number items each FIFO also read back from transmitter FIFO level (TFL) receiver FIFO level (RFL) registers (see section 6.11.2).
Trigger levels:
FCR[3]: trigger level enable logic Transmit trigger levels enabled logic Transmit trigger levels disabled When FCR[3]=0, transmitter trigger level always thus ignoring FCR[5:4]. Alternatively, 950-mode trigger levels using ACR[5]. FCR[5:4]: Compatible trigger levels 450, extended modes: transmitter interrupt trigger levels FCR[5:4] ignored. mode: mode transmitter interrupt trigger levels following values: FCR[5:4] Transmit Interrupt Trigger level
Table Transmit Interrupt Trigger Levels These levels only apply when Enhanced mode when FCR[3] set, otherwise trigger level transmitter empty interrupt will generated enabled) falls below trigger level. Mode: compatible mode, transmitter trigger level FCR[4] unused FCR[5] defines FIFO depth follows: FCR[5]=0: FIFO size bytes. FCR[5]=1: FIFO size bytes. non-Enhanced mode when FIFOSEL low, FCR[5] writable only when LCR[7] set. Note that Enhanced mode, FIFO size increased bytes when FCR[0] set. Page
6.4.1 FIFO Control Register `FCR' FIFO setup:
FCR[0]: Enable FIFO mode logic Byte mode. logic FIFO mode. This should enabled before setting FIFO trigger levels. FCR[1]: Flush logic change. logic Flushes contents This only operative when already FIFO mode. automatically flushed whenever changing between DS-0020
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mode: Setting ACR[5]=1 enables 950-mode trigger levels using register (see section 6.11.4), FCR[5:4] ignored.
OXmPCI952
mode: similar fashion transmitter trigger levels, setting ACR[5]=1 enables 950-mode receiver trigger levels. FCR[7:6] ignored. [7:6] Mode Ext.
FIFO Size
trigger levels
FCR[7:6]: Compatible Trigger levels 450, 550, extended 550, modes: receiver FIFO trigger levels defined using FCR[7:6]. interrupt trigger level upper flow control trigger level where appropriate defined table below. defines lower flow control trigger level. Separate upper lower flow control trigger levels introduce hysteresis element in-band out-of-band flow control (see section 6.9). Byte mode (450-mode) trigger levels
FIFO Size
FIFO Size
Table Compatible Receiver Trigger Levels receiver data interrupt will generated enabled) Receiver FIFO Level (`RFL') reaches upper trigger level.
6.5.1
Line Control Status
False Start Detection
affected. Write desired value exit from this selection. LCR[1:0]: Data length LCR[1:0] Determines data length serial characters. Note however, that these values ignored 9-bit data framing mode, i.e. when NMR[0] set. LCR[1:0] Data length bits bits bits bits
falling edge start bit, receiver will wait re-synchronise receiver's sampling clock onto centre start bit. start valid line still this mid-bit sample receiver will proceed read data character. Verifying start prevents noise generating spurious character generation. Once first stop been sampled, received data transferred receiver will then wait transition (signifying next start bit). receiver will continue receiving data even full receiver been disabled (see section 6.11.3) order maintain framing synchronisation. only difference that received data does transferred RHR.
Table Data Length Configuration LCR[2]: Number stop bits LCR[2] defines number stop bits serial character. LCR[2] Data length 5,6,7,8 6,7,8 stop bits
6.5.2
Line Control Register `LCR'
specifies data format that common both transmitter receiver. Writing 0xBF enables access EFR, XON1, XOFF1, XON2 XOFF2, registers. This value (0xBF) corresponds unused data format. Writing value 0xBF will LCR[7] leaves LCR[6:0] unchanged. Therefore, data format transmitter receiver data
Table Stop Number Configuration
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LCR[5:3]: Parity type selected parity type will generated during transmission checked receiver, which produce parity error result. 9-bit mode parity disabled LCR[5:3] ignored. LCR[5:3] Parity type parity parity Even parity Parity forced Parity forced
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Parity error flag will when data item error cleared following read LSR. 9-bit mode LSR[2] longer flag corresponds received data RHR. LSR[3]: Received data framing error logic framing error. logic Data been received with invalid stop bit. This status cleared same manner LSR[2]. When framing error occurs, UART will re-synchronise assuming that error sampling start next data item. LSR[4]: Received break error logic receiver break error. logic receiver received break. break condition occurs when line goes (normally signifying start bit) stays throughout start, data, parity first stop bit. (Note that line sampled rate). zero character with associated break flag will transferred receiver will then wait until line returns high. LSR[4] break flag will when this data item gets cleared following read LSR. LSR[5]: empty logic Transmitter FIFO (THR) empty. logic Transmitter FIFO (THR) empty. LSR[6]: Transmitter empty logic transmitter idle logic empty transmitter completed character shift register idle mode. (I.e. whenever transmitter shift register both empty.) LSR[7]: Receiver data error logic Either there receiver data errors FIFO cleared read LSR. logic least parity error, framing error break indication FIFO. mode LSR[7] permanently cleared, otherwise this will when erroneous character transferred from receiver RHR. cleared when read. Note that 16C550 this only cleared when erroneous data removed from FIFO. 9-bit data framing mode parity permanently disabled, this affected LSR[2].
Table Parity Configuration LCR[6]: Transmission break logic Break transmission disabled. logic Forces transmitter data output SOUT alert communication terminal, send zeros IrDA mode. responsibility software driver ensure that break duration longer than character period recognised remotely break rather than data. LCR[7]: Divisor latch enable logic Access registers disabled. logic Access registers enabled.
6.5.3
Line Status Register `LSR'
This register provides status data transfer CPU. LSR[0]: data available logic empty: data available logic empty: data available read. LSR[1]: overrun error logic overrun error. logic Data received when full. overrun error occurred. error flagged when data would normally have been transferred RHR. LSR[2]: Received data parity error logic parity error normal mode received data 9-bit mode. logic Data been received that have correct parity normal mode received data 9-bit mode.
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Interrupts Sleep Mode
9-bit data mode, receiver detect four special characters programmed Special Character Registers (see page 50). When IER[5] set, level interrupt asserted when receiver character matches values programmed. 650/950 modes (non-9-bit data framing): logic Disable special character receive interrupt. logic Enable special character receive interrupt. 16C650 compatible mode when device Enhanced mode (EFR[4]=1), this enables detection special characters. enables both detection XOFF characters (when in-band flow control enabled EFR[3:0]) detection XOFF2 special character (when enabled EFR[5]). mode (non-9-bit data framing): logic Disable alternate sleep mode. logic Enable alternate sleep mode whereby internal clock channel switched off. 16C750 compatible mode (i.e. non-Enhanced mode), this used alternate sleep mode same effect IER[4]. IER[6]: interrupt mask logic Disable interrupt. logic Enable interrupt. This enable only operative Enhanced mode (EFR[4]=1). non-Enhanced mode, interrupt permanently enabled IER[7]: interrupt mask logic Disable interrupt. logic Enable interrupt. This enable only operative Enhanced mode (EFR[4]=1). non-Enhanced mode, interrupt permanently enabled.
serial channel interrupts asserted INTA# pin. interrupts enabled disabled using register interrupt mask (see section 5.4.8) register. Unlike generic 16C550 devices, interrupt disabled using implementation-specific MCR[3].
6.6.1
Interrupt Enable Register `IER'
Serial channel interrupts enabled using Interrupt Enable Register (`IER'). IER[0]: Receiver data available interrupt mask logic Disable receiver ready interrupt. logic Enable receiver ready interrupt. IER[1]: Transmitter empty interrupt mask logic Disable transmitter empty interrupt. logic Enable transmitter empty interrupt. IER[2]: Receiver status interrupt Normal mode: logic Disable receiver status interrupt. logic Enable receiver status interrupt. 9-bit data mode: logic Disable receiver status address interrupt. logic Enable receiver status address interrupt. 9-bit mode (i.e. when NMR[0] set), reception character with address-bit (i.e. bit) generate level interrupt IER[2] set. IER[3]: Modem status interrupt mask logic Disable modem status interrupt. logic Enable modem status interrupt. IER[4]: Sleep mode logic Disable sleep mode. logic Enable sleep mode whereby internal clock channel switched off. Sleep mode described section 6.6.4. IER[5]: Special character interrupt mask alternate sleep mode 9-bit data framing mode: logic Disable received special character interrupt. logic Enable received special character interrupt.
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Level 6.6.2 Interrupt Status Register `ISR'
source highest priority interrupt pending indicated contents Interrupt Status Register `ISR'. There nine sources interrupt levels priority highest) shown Table Level Interrupt source interrupt pending Receiver status error Address-bit detected 9-bit mode Receiver data available Receiver time-out Transmitter empty Modem status change In-band flow control XOFF Special character (XOFF2) Special character 9-bit mode change state ISR[5:0]
note
Receiver data available interrupt (ISR[5:0]='000100'): This interrupt active whenever receiver FIFO level above interrupt trigger level.
Level
Receiver time-out interrupt (ISR[5:0]='001100'): receiver time-out event, which cause interrupt, will occur when following conditions true: UART FIFO mode There data RHR. There been read period time greater than time-out period. There been data written into period time greater than time-out period. time-out period four times character period (including start stop bits) measured from centre first stop last data item received. Reading first data item clears this interrupt.
000001 000110 000100 001100 000010 000000 010000
100000
Level
Transmitter empty interrupt (ISR[5:0]='000010'): This interrupt when transmit FIFO level falls below trigger level. cleared read level interrupt writing more data that trigger level exceeded. Note that when 16C950 mode trigger levels enabled (ACR[5]=1) transmitter trigger level zero selected (TTL=0x00), transmitter empty interrupt will only asserted when both transmitter FIFO transmitter shift register empty SOUT line returned idle marking state.
Table Interrupt Status Identification Codes
Note1: Note2: Note3: ISR[0] indicates whether interrupts pending. Interrupts priority levels cannot occur unless UART Enhanced mode. ISR[5] only used modes. mode, when FIFO size when FIFO size 128. other modes permanently
ISR[6] ISR[7] indicated whether FIFO's enabled. When enable FIFOs both bits when either 128, note they also mirror fcr[0].
Level
Modem change interrupt (ISR[5:0]='000000'): This interrupt modem change flag (MSR[0], MSR[1], MSR[2] MSR[3]) becoming active changes input modem lines. This interrupt cleared following read MSR.
6.6.3 Level
Interrupt Description
Receiver status error interrupt (ISR[5:0]='000110'): Normal (non-9-bit) mode: This interrupt active whenever LSR[1], LSR[2], LSR[3] LSR[4] set. These flags cleared following read LSR. This interrupt masked with IER[2]. 9-bit mode: This interrupt active whenever LSR[1], LSR[2], LSR[3] LSR[4] set. receiver error interrupt LSR[1], LSR[3] LSR[4] masked with IER[3]. `address-bit' received interrupt masked with NMR[1]. software driver differentiate between receiver status error received address-bit (9th data bit) interrupt examining LSR[1] LSR[7]. 9-bit mode LSR[7] only when LSR[3] LSR[4] affected LSR[2] (i.e. data bit).
Level
Receiver in-band flow control (XOFF) detect interrupt, Receiver special character (XOFF2) detect interrupt, Receiver special character interrupt interrupt 9-bit mode (ISR[5:0]='010000'): level interrupt only occur Enhanced-mode when following conditions met: valid XOFF character received while in-band flow control enabled. received character matches XOFF2 while special character detection enabled, i.e. EFR[5]=1. received character matches special character 9-bit mode (see section 6.11.9). cleared read level interrupt.
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Level
changed interrupt (ISR[5:0]='100000'): This interrupt whenever CTS# RTS# pins changes state from high. cleared read level interrupt.
UART loopback mode (MCR[4]=0). Changes modem input lines
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