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CM71-10114-3E

32-BIT MICROCONTROLLER

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
CM71-10114-3E
32-BIT MICROCONTROLLER
MB91301 Series HARDWARE MANUAL
32-BIT MICROCONTROLLER
MB91301 Series HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
I Objectives and Intended Reader Thank you for using Fujitsu semiconductor products. The MB91301 series is a standard microcontroller that has a 32-bit high-performance RISC CPU as well as built-in I / O resources and bus control mechanisms for embedded controller that requires high-performance and high-speed CPU processing. Although the MB91301 series basically uses external bus access to support a vast address space accessed by a 32-bit CPU, it has a 4 KB instruction cache memory and 4 KB RAM (for data) to increase the speed at which the CPU executes instructions. The MB91301 series is most suitable for embedded applications, such as digital video cameras, navigation systems, and DVD players, that require a high level of CPU processing power. The MB91301 series is one of the FR60 series of microcontrollers, which are based on the FR30 / 40 family of CPUs. It has enhanced bus access and is optimized for high-speed use. This manual is intended for engineers who will develop products using the MB91301 series and describes the functions and operations of the MB91301 series. Read this manual thoroughly. For more information on instructions, see the "Instructions Manual". I Trademarks FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Limited. I License Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips.
I Structure of This Manual This manual consists of the following 20 chapters and an appendix. CHAPTER 1 OVERVIEW This chapter provides basic information required to understand the MB91301 series, and covers features, a block diagram, and functions. CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling the MB91301 series. CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the functions of the MB91301 series. It covers architecture, specifications, and instructions. CHAPTER 4 EXTERNAL BUS INTERFACE The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I / O devices. This chapter explains each function of the external bus interface and its operation. CHAPTER 5 I / O PORT This chapter describes the I / O ports and the configuration and functions of registers. CHAPTER 6 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. CHAPTER 7 PPG TIMER This chapter describes the U-TIMER, the configuration and functions of registers, and UTIMER operation. CHAPTER 8 U-TIMER This chapter describes the external interrupt and NMI controller, the configuration and functions of registers, and operation of the external interrupt and NMI controller. CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the functions and operation of the delayed interrupt module. CHAPTER 10 DELAYED INTERUPT MODULE This chapter describes the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function. CHAPTER 11 INTERRUPT CONTROLLER This chapter describes the A / D converter, the configuration and functions of registers, and A / D converter operation. CHAPTER 12 A / D CONVERTER This chapter describes the UART, the configuration and functions of registers, and UART operation. CHAPTER 13 UART This chapter describes the I2C interface, the configuration and functions of registers, and I2C interface operation.
How To Read This Manual
I Terms Used in This Manual The following defines principal terms used in this manual. Term I-bus Meaning 32 bit bus for internal instructions. In the FR series, which is based on an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-bus. Internal 32-bit data bus. An internal resource is connected to the D-bus. Internal instructions and data are multiplexed on a Princeton bus. The F-bus is connected to the I-bus and D-bus via a switch. The F-bus is connected to built-in resources such as ROM and RAM. External interface bus. The X-bus is connected to the external interface module. Data and instructions are multiplexed on an external bus. Internal 16-bit data bus. The R-bus is connected to the F-bus via an adapter. An I-O, clock generator, and interrupt controller are connected to the R-bus. Since addresses and data are multiplexed on an R-bus that is 16 bits wide, more than one cycle is required for the CPU to access these resources. Execution unit for operations. System clock. Clock generated by the clock generator for each of the internal resources connected to the R-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, or 1 / 16 (or 1 / 2, 1 / 4, 1 / 6, or 1 / 32) frequency clock as determined by the divide-by rate specified by the B3 to B0 bits in the clock generator DIVR0 register. System clock. Operating clock for the CPU and each of the other resources connected to a bus other than the R-bus and X-bus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, .., 1 / 16 (or 1 / 2, 1 / 4, 1 / 6, .., 1 / 32) frequency clock as determined by the divided-by rate specified by the P3 to P0 bits in the clock generator DIVR0 register. System clock. Operating clock for the external resources connected to the Xbus. This clock has the same frequency as the source oscillation at its maximum, but becomes a 1, 1 / 2, 1 / 3, 1 / 4, 1 / 5, 1 / 6, 1 / 7, .., 1 / 16 (or 1 / 2, 1 / 4, 1 / 6, .., 1 / 32) frequency clock as determined by the divided-by rate specified by the T3 to T0 bits in the clock generator DIVR1 register.
D-bus F-bus
X-bus
R-bus
E-unit CLKP
PREFACE How To Read This Manual
CHAPTER 1
OVERVIEW .................................................. 1
Features of the MB91301 Series .................................................... 2 Block Diagram .................................................................. 7 External Dimensions .............................................................. 9 Pin Layout ..................................................................... 11 Pin No. Table .................................................................. 13 List of Pin Functions ............................................................. 15 I / O Circuit Types ................................................................ 31
CHAPTER 2
HANDLING THE DEVICE ..................................... 35
Precautions on Handling the Device ................................................. 36 Precautions on Handling Power Supplies ............................................. 42
CHAPTER 3
CPU AND CONTROL UNITS ................................... 43
3.12 Clock Generation Control ........................................................ 3.12.1 PLL Controls ............................................................... 3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .......................... 3.12.3 Clock Distribution ............................................................ 3.12.4 Clock Division .............................................................. 3.12.5 Block Diagram of Clock Generation Controller ..................................... 3.12.6 Register of Clock Generation Controller .......................................... 3.12.7 Peripheral Circuits of Clock Controller ............................................ 3.13 Device State Control ............................................................ 3.13.1 Device States and State Transitions ............................................. 3.13.2 Low-power Modes ........................................................... 3.14 Operating Modes ..............................................................
CHAPTER 4
EXTERNAL BUS INTERFACE ................................ 143
CHAPTER 5
I / O PORT ................................................. 259
Overview of the I / O Port ......................................................... 260 I / O Port Registers .............................................................. 262
CHAPTER 6
16-BIT RELOAD TIMER ...................................... 271
Overview of the 16-bit Reload Timer ............................................... 16-bit Reload Timer Registers .................................................... Control Status Register (TMCSR) ............................................... 16-bit Timer Register (TMR) ................................................... 16-bit Reload Register (TMRLR) ................................................ 16-bit Reload Timer Operation .................................................... Operating States of the Counter ................................................... Precautions on Using the 16-bit Reload Timer ........................................
CHAPTER 7
PPG TIMER ............................................... 283
Overview of PPG Timer ......................................................... Block Diagram of PPG Timer ..................................................... Registers of PPG Timer ......................................................... Control status registers (PCNH, PCNL) .......................................... PPG cycle set register (PCSR) ................................................. PPG duty set register (PDUT) .................................................. PPG timer register (PTMR) .................................................... General control register 10 (GCN10) ............................................. General control register 20 (GCN20) ............................................. PPG Operation ................................................................ One-shot Operation ............................................................ PPG Timer Interrupt Source and Timing Chart ........................................ Activating Multiple Channels by Using the General Control Register ....................... ix
Notes on Use of the PPG Timer ................................................... 307
CHAPTER 8
U-TIMER .................................................. 309
Overview of the U-TIMER ........................................................ 310 U-TIMER Registers ............................................................. 311 U-TIMER Operation ............................................................ 315
CHAPTER 9
EXTERNAL INTERRUPT AND NMI CONTROLLER ................ 317
9.1 Overview of the External Interrupt and NMI Controller .................................. 9.2 External Interrupt and NMI Controller Registers ....................................... 9.2.1 Interrupt Enable Register (ENIR) ................................................ 9.2.2 External Interrupt Source Register (EIRR) ........................................ 9.2.3 External Interrupt Request Level Setting Register (ELVR) ............................ 9.3 Operation of the External Interrupt and NMI Controller .................................
CHAPTER 10 DELAYED INTERUPT MODULE ............................... 327
10.1 10.2 10.3 Overview of the Delayed Interrupt Module ........................................... 328 Delayed Interrupt Module Registers ................................................ 329 Operation of the Delayed Interrupt Module ........................................... 330
CHAPTER 11 INTERRUPT CONTROLLER .................................. 331
11.1 Overview of the Interrupt Controller ................................................ 11.2 Interrupt Controller Registers ..................................................... 11.2.1 Interrupt Control Register (ICR) ................................................. 11.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) .................... 11.3 Interrupt Controller Operation ..................................................... 11.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ................ 332 334 336 338 339 345
CHAPTER 12 A / D CONVERTER .......................................... 347
12.1 Overview of the A / D Converter .................................................... 12.2 A / D Converter Registers ......................................................... 12.2.1 Control Status Register (ADCS) ................................................ 12.2.2 Data Register (ADCR) ........................................................ 12.2.3 Conversion result register (ADCR0 to 3) .......................................... 12.3 A / D Converter Operation ........................................................ 12.4 Precautions on the Using A / D Converter ............................................ 348 350 351 356 357 358 360
CHAPTER 13 UART .................................................... 361
13.1 Overview of the UART .......................................................... 13.2 UART Registers ............................................................... 13.2.1 Serial Mode Register (SMR) ................................................... 13.2.2 Serial Control Register (SCR) .................................................. 13.2.3 Serial Input Data Register (SIDR) / Serial Output Data Register (SODR) .................. 13.2.4 Serial Status Register (SSR) ................................................... 13.2.5 DRCL Register ............................................................. 13.3 UART Operation ............................................................... 13.3.1 Asynchronous (Start-stop Synchronization) Mode .................................. x 362 364 365 367 370 371 374 375 376
13.3.2 CLK Synchronous Mode ...................................................... 13.3.3 Occurrence of Interrupts and Timing for Setting Flags ............................... 13.4 Example of Using the UART ...................................................... 13.5 Example of Setting U-TIMER Baud Rates and Reload Values ...........................
CHAPTER 14 DMA CONTROLLER (DMAC) ................................. 385
14.1 Overview of the DMA Controller (DMAC) ............................................ 386 14.2 DMA Controller (DMAC) Registers ................................................. 388 14.2.1 Control / Status Registers A (DMACA0 to 4) ........................................ 390 14.2.2 Control / Status Registers B (DMACB0 to 4) ........................................ 395 14.2.3 Transfer Source / Transfer Destination Address Setting Registers (DMASA0 to 4 / DMADA0 to 4) ...................................................................... 402 14.2.4 DMAC All-Channel Control Register (DMACR) ..................................... 404 14.2.5 Other Functions ............................................................. 406 14.3 DMA Controller (DMAC) Operation ................................................ 407 14.3.1 Setting a Transfer Request .................................................... 410 14.3.2 Transfer Sequence .......................................................... 411 14.3.3 General Aspects of DMA Transfer ............................................... 415 14.3.4 Addressing Mode ............................................................ 417 14.3.5 Data Types ................................................................ 418 14.3.6 Transfer Count Control ....................................................... 419 14.3.7 CPU Control ............................................................... 420 14.3.8 Hold Arbitration ............................................................. 421 14.3.9 Operation from Starting to End / Stopping .......................................... 422 14.3.10 DMAC Interrupt Control ....................................................... 426 14.3.11 Channel Selection and Control ................................................. 427 14.3.12 Supplement on External Pin and Internal Operation Timing ........................... 429 14.4 Operation Flowcharts ........................................................... 432 14.5 Data Bus ..................................................................... 435 14.6 DMA External Interface .......................................................... 438 14.6.1 Input Timing of the DREQx Pin ................................................. 439 14.6.2 FR30 Compatible Mode of DACK ............................................... 441
CHAPTER 15 BIT SEARCH MODULE ...................................... 443
15.1 15.2 15.3 Overview of the Bit Search Module ................................................ 444 Bit Search Module Registers ..................................................... 445 Bit Search Module Operation ..................................................... 447
CHAPTER 16 I2C INTERFACE ............................................ 449
16.1 16.2 16.3 16.4 16.5 16.6 Overview of the I2C Interface ..................................................... I2C Interface Registers .......................................................... Block Diagram of I2C Interface .................................................... Detailed on Registers of the I2C Interface ........................................... I2C Interface Operation .......................................................... Operation Flowcharts ........................................................... 450 451 453 454 469 474
CHAPTER 17 16-bit Free-run Timer ....................................... 477
Overview of 16-bit Free-run Timer ................................................. Registers of the 16-bit Free-run Timer .............................................. Block Diagram of the 16-bit Free-run Timer .......................................... Details on Registers of the 16-bit Free-run Timer ...................................... Operation of the 16-bit Free-run Timer .............................................. Precautions on Using the 16-bit Free-run Timer .......................................
CHAPTER 18 Input Capture .............................................. 489
18.1 18.2 18.3 18.4 18.5 Overview of Input Capture ....................................................... Input Capture Registers ......................................................... Block Diagram of Input Capture ................................................... Details on Registers of Input Capture ............................................... Operation of 16-bit Input Capture .................................................. 490 491 492 493 495
CHAPTER 19 Program Loader Mode (Supported only by the MB91302A (IPL integrated model)) 497
19.1 19.2 19.3 19.4 Overview of the Program Loader Mode ............................................. Setting the Program Loader ...................................................... Operations in the Program Loader Mode ............................................ Example of Using the Program Loader Mode to Write to Flash Memory .................... 498 499 501 512
20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Introduction ................................................................... Memory Map .................................................................. Specifications for REALOS / FR Embedded in MB91302A-010 ............................ Section Allocation .............................................................. Startup Routine ................................................................ Initial Settings for SOFTUNE Workbench and REALOS / FR ............................. Mode Pins, Mode Vectors, and Reset Vectors ........................................ Chip Evaluation System ......................................................... 516 517 518 520 521 522 530 533
APPENDIX ............................................................. 535
APPENDIX A I / O MAP ................................................................ APPENDIX B INTERRUPT VECTOR .................................................... APPENDIX C PIN STATE IN EACH CPU STATE ........................................... APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA .................................. D.1 C Compiler (fcc911) ............................................................ D.2 Assembler (fasm911) ........................................................... D.3 Linker (flnk911) ............................................................... D.4 Debugger (sim911, eml911, mon911) .............................................. APPENDIX E INSTRUCTION LISTS ..................................................... E.1 How to Read the Instruction Lists ................................................. E.2 FR Family Instruction Lists ....................................................... 536 548 552 566 567 570 572 573 574 575 579
CHAPTER 1
OVERVIEW
This chapter provides basic information required to understand the MB91301 series, and covers features, a block diagram, and functions. 1.1 "Features of the MB91301 Series" 1.2 "Block Diagram" 1.3 "External Dimensions" 1.4 "Pin Layout" 1.5 "Pin No. Table" 1.6 "List of Pin Functions" 1.7 "Input-output Circuit Forms"
CHAPTER 1 OVERVIEW
Features of the MB91301 Series
The MB91301 series is a standard single-chip microcontroller that has a 32-bit highperformance RISC CPU as well as built-in I / O resources and bus control mechanisms for embedded controller requiring high-performance and high-speed CPU processing. Although the MB91301 series basically uses external bus access to support a vast address space accessed by a 32-bit CPU, it has a 4 KB instruction cache memory and 4 KB RAM to increase the speed at which the CPU executes instructions. This model is an FR60 series model that is based on the FR30 / 40-family of CPUs. It has enhanced bus access and is optimized for high-speed use. The MB91301 series is most suitable for embedded applications, such as digital video cameras, navigation systems, and DVD players, that require a high level of CPU processing power.
I Features of the MB91301 Series The MB91301 series has the line-up of series embeded the each of program in built-in ROM. ROM variation Products MB91302A MB91301 I FR CPU · · · · · · · · · · 32-bit RISC, load / store architecture, five pipelines Operating frequency of 68 MHz (Internal maximum value), 68 MHz (External maximum value) PLL used, original oscillation at 17 MHz 32-bit general-purpose register x 16 16-bit fixed-length instructions (basic instructions), one instruction per cycle Memory-to-memory transfer, bit processing, instructions, including barrel shift, etc. instructions appropriate for embedded applications Function entry and exit instructions, multi load / store instructions-instructions compatible with high-level languages Instructions for entry / exit functions, multiple load / store instructions for the register contents, instructions for high-level languages. Register interlock function to facilitate assembly-language coding Branch instruction with a delay slot allowing a decrease in overhead for branch processing Built-in multiplier / instruction-level support · · · 2 Signed 32-bit multiplication: 5 cycles Signed 16-bit multiplication: 3 cycles O X Real time OS internal version IPL (internal program loader) internal version O X User ROM version O X No ROM version
Interrupts (saving of PC and PS): 6 cycles, 16 priority levels
CHAPTER 1 OVERVIEW I Bus Interface · · · · · · · Maximum operating frequency of 68 MHz (at using SRAM) 24-bit address can be fully output (16 MB space) 8-, 16- and 32-bit data I / O Prefetch buffer installed Unused data and address pins can be used as general-purpose I / O ports. Totally independent 8-area chip select output that can be defined at a minimum of 64 KB Support of interfaces for various memory modules · · · · · · · · · · · · · · Asynchronous SRAM, asynchronous ROM / FLASH Page-mode ROM / FLASHROM (a page-size of 1, 2, 4, or 8 can be selected) Burst-mode ROM / FLASH (MBM29BL160D / 161D / 162D etc.) SDRAM (or FCRAM type, CAS Latency1 to 8, 2 / 4 bank product) Address / data multiplexed bus (8 - bit / 16 - bit width only)
Basic bus cycle: 2 cycles Automatic wait cycle generator (Max 15 cycles) that can be programmed for each area and can insert waits External wait cycles due to RDY input Endian setting of byte ordering (big / little) CS0 are, however, is only big endian Write disable setting (read only data) Enable / disable set of captureing to the built-in cache Enable / disable set of prefetch function Supports fly-by DMA transfer that enables independent I / O wait control External bus arbitration using BRQ and BGRNT is enabled
I Built-in Memory · · DATA RAM: 4KB ROM: 4FB (MB91302A)
Built-in 8KB DATA RAM and 8 KB DATA / Instruction RAM in MB91V301 Built-in 8 KB DATA RAM, 8 KB DATA / instruction RAM and 8 KB emulation RAM in MB91V301A I Instruction Cache · · · · · Capacity of 4 KB 2 way set associative 128 block / way, 4 entry (4 words) / block Lock function allows specific program codes to stay resident in cache Instruction RAM function: A part of the instruction cache not in use can be used as RAM
I DMAC (DMA Controller) · 5 channels (2 channels for external to request)
CHAPTER 1 OVERVIEW · · · · · · 3 transfer sources (external pins, internal peripherals, software) Internal peripheral can be selected at each channel as the transfer factor Addressing mode with 32-bit full address specifications (increase, decrease, fixed) Transfer modes (demand transfer, burst transfer, step transfer, block transfer) Fly-by transfer supported (three channels between external I / O and external memory) Transfer data size that can be selected from 8, 16, and 32 bits
I Bit Search Module · Searches for the position of the first bit varying between 1 and 0 in the MSB of a word
I Reload Timer (including One Channel for REALOS) · · I UART · · · · · · · · UART full-duplex double buffer Independent 3 channels Data length: 7 to 9 bits (no parity), 8 to 8 bits (parity) Either asynchronous (start-stop synchronization) or CLK synchronous communication can be selected. Multi processor mode Built-in 16-bit timer (U-TIMER) as boud rate generater: generatin arbitrary baud rates An external clock can be used as the transfer clock. Error detection functions (parity, frame, overrun) 16-bit timer 3 channels Internal clock: 2-clock cycle resolution, selectable from 2, 8 or 32 dividen frequency
I Interrupt Controller · · · · Total of 9 external interrupts (one unmaskable pin (NMI) and eight regular interrupt pins (INT7 to INT0)) Internal interrupt source: UART, DMAC, A / D, UTIMER, delay interrupt, I2C, free-running timer and ICU The I2C, free - running timer, and ICU are sources unique to the MB91302A and MB91V301A. Priority level can be defined as programmable (16 levels) except for the unmaskable pin
I A / D Converter (sequential conversion type) · · · · 10-bit resolution, 4 channels Sequential comparison and conversion type: peripheral clock (CLKP) 140 clock cycle conversion time (about 4.1 µs / ch at 34MHz operating) Built-in sample and hold circuit Conversion modes (single-shot conversion mode, scan conversion mode, and repeat conversion mode)
CHAPTER 1 OVERVIEW · I I2C Interface · · · · Master / slave transmission and reception Clock synchronization function Arbitration function The I2C bus interface is only for MB91302A, MB91301A. Causes of startup (select from software, external triggers, and internal timer)
I Free Run Timer · · · 16-bit 1channel Input capture 4 channels Free run timer is only for MB9130A an MB91V301A.
I Other Interval Timers · · · 16-bit timer: 3 channels (U-TIMER) PPG timer: 4channels Watchdog timer 1 channel
CMOS technology ·
Power voltages ·
On chip Device Support Unit (DSU4) is installed in MB91V301 / V301A.
CHAPTER 1 OVERVIEW I
Product Line-up
MB91301
Type External ROM version (for volume production) 4 KB (only for data)
MB91V301
Evaluation version (For evaluation and development) 16 KB (data 8 KB+8 KB)
MB91302A
Mask ROM product (for volume production) 4 KB (only for data) 4 KB ROM has non-ROM model, the optimal real time OS internal model1, and the IPL (Internal Program Loader) internal model2 by adding the user ROM model. LQFP-144 (0.4 mm pitch) Currently in production
MB91V301A
Evaluation version (For evaluation and development) 16 KB (data 8 KB+8 KB)
8 KB (RAM)
DSU Package Other
LQFP-144 (0.4 mm pitch) Currently in production
DSU4 PGA-179 Currently available
2: The ROM stores the IPL (Internal Program Loader). Loading various programs can be executed from the external system by the internal UART / SIO. Using this function, for example, writing on board to the Flash memory connected to the external can be executed.
CHAPTER 1 OVERVIEW
Block Diagram
Figure 1.2-1 "Block Diagram" is a block diagram of the MB91301 series.
I Block Diagram Figure 1.2-1 BLOCK DIAGRAM (MB91301, MB91V301)
FR CPU Core
I-Cache 4 KB
DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD
Bit search RAM 4 KB (stack) Bus Converter
DMAC 5 ch
X0, X1 MD0 MD2 INIT
External memory I / F
A23 A00 D31 D16 D15 D0 RD, WR WR0 WR3 CS0 CS7 RDY BRQ BGRNT SYSCLK MCLK AS MCLKE SRAS SCAS SWE DQMUU, L DQMLU, L LBA BAA PPG0 PPG3 TRG0 TRG3
Interrupt controller
SDRAM I / F INT0 INT7 NMI SIN0 SIN2 SOT0 SOT2 SCK0 SCK2
8 ch External interrupts
3 ch UART
4 ch PPG timer
3 ch U-TIMER
AN0 AN3 AVR, ATG AVRH, AVCC AVSS / AVRL TIN0 TIN2 4 ch A / D
3 ch Reload timer
CHAPTER 1 OVERVIEW Figure 1.2-2 BLOCK DIAGRAM (MB91302A, MB91V301A) FR CPU Core
32 32 DMAC 5 ch
I-Cache 4 KB
DREQ0, 1 DACK0, 1 DEOP0, 1 IOWR IORD
Bit search
MB91302A : RAM 4 KB MB91V301A : RAM 8 KB (stack)
MB91302A : RAM 4 KB MB91V301A : RAM 8 KB
Bus Converter
X0, X1 MD0 2 INIT
32 16 Adapter
External memory I / F
Clock control
A23 00 D31 16 D15 0 RD, WR WR0 WR3 CS0 CS7 RDY BRQ BGRNT SYSCLK MCLK AS MCLKE SRAS SCAS SWE DQMUU, L DQMLU, L LBA BAA PPG0 3 TRG0 3
Interrupt controller
SDRAM I / F INT0 7 NMI SIN0 2 SOT0 2 SCK0 2
8 ch External interrupts
3 ch UART
4 ch PPG timer
3 ch U-TIMER
AN0 3 ATG AVRH, AVCC AVSS / AVRL TIN0 2 4 ch A / D
SDA0, 1 SCL0, 1
3 ch Reload timer
Free Run Timer
ICU0 3
: ROM has non-ROM model, the optimal real time OS internal model, and the IPL (Internal Program Loader) internal model by adding the user ROM model.
CHAPTER 1 OVERVIEW
External Dimensions
The MB91301 series is available in one type of package.
I Dimensions Figure 1.3-1 PGA-179C-A03
PGA-179C-A03
EIAJ code :PGA179-C-S15U-2
179-pin ceramic PGA Lead pitch Pin matrix Sealing method 2.54mm(100mil) 15 Metal seal
(PGA-179C-A03)
179-pin ceramic PGA (PGA-179C-A03)
1.27(.050)TYP DIA
35.56(1.400) REF
INDEX
INDEX AREA
0.46 -0.05 DIA .018 -.002 38.10-0.51 SQ (1.500-.020) 6.10(.240) MAX
Dimensions in mm (inches).
1994 FUJITSU LIMITED R179004SC-3-2
Dimensions in mm values. Note: The values in parentheses are reference (inches).
CHAPTER 1 OVERVIEW Figure 1.3-2 FPT-144P-M12
FPT-144P-M12
(FPT-144P-M12)
Code (Reference)
144-pin plastic LQFP (FPT-144P-M12)
Note 1) : These dimensions include resin protrusion. Resin protrusion is +0.25(.010)Max(each side). Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
Details of "A" part 1.50 -0.10 .059 -.004
(Mounting height)
INDEX
LEAD No.
2003 FUJITSU LIMITED F144024S-c-3-3
Dimensions in mm (inches). Note: The values in parentheses are reference values.
CHAPTER 1 OVERVIEW
Pin Layout
This section shows the pin layout of the MB91301 series.
I Pin Layout of the MB91V301 / V301A Figure 1.4-1 "Pin Layout of the MB91V301 / V301A" is a diagram of the pin layout of the MB91V301 / V301A. Figure 1.4-1 Pin Layout of the MB91V301 / V301A
Top View PGA-179C-A03
CHAPTER 1 OVERVIEW I Pin Layout of the MB91301 / 302A
Figure 1.4-2 Pin Layout of the MB91301 / 302A
D10 / P12 D09 / P11 D08 / P10 Vcc Vss D07 / P07 D06 / P06 D05 / P05 D04 / P04 D03 / P03 D02 / P02 D01 / P01 D00 / P00 Vcc Vss CS7 / PA7 CS6 / PA6 CS5 / PPG2 / PA5 CS4 / TRG2 / PA4 CS3 / PA3 CS2 / PA2 CS1 / PA1 CS0 / PA0 Vcc NMI INIT MD2 MD1 MD0 Vcc Vss X1 X0 Vcc IORD / PB7 IOWR / PB6 P13 / D11 P14 / D12 P15 / D13 P16 / D14 P17 / D15 Vss Vcc P20 / D16 P21 / D17 P22 / D18 P23 / D19 P24 / D20 P25 / D21 P26 / D22 P27 / D23 Vss Vcc D24 D25 D26 D27 D28 D29 D30 D31 Vss Vcc P80 / RDY P81 / BGRNT P82 / BRQ RD DQMUU / WRO P85 / DQMUL / WR1 P86 / DQMLU / WR2 P87 / DQMLL / WR3 P90 / SYSCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
MB91301, MB91302A (Top View)
DEOP1 / PPG1 / PB5 DACK1 / TRG1 / PB4 DREQ1 / PB3 DEOPO / PB2 DACK0 / PB1 DREQ0 / PB0 C Vss TIN2 / TRG3 / PH2 TIN1 / PPG3 / PH1 TIN0 / PH0 TRG0 / PJ7 PPG0 / PJ6 SCK1 / PJ5 SOT1 / PJ4 SIN1 / PJ3 SCK0 / PJ2 SOT0 / PJ1 SIN0 / PJ0 Vcc INT7 / SCK2 / PG7 INT6 / SOT2 / PG6 INT5 / SIN2 / PG5 INT4 / ATG / PG4 / FRC INT3 / PG3 / ICU3 INT2 / PG2 / ICU2 INT1 / PG1 / ICU1 INT0 / PG0 / ICU0 AVss / AVRL AN0 AN1 AN2 AN3 AVR ANRH AVcc
P91 / MCLKE P92 / MCLK P93 P94 / SRAS / LBA / AS P95 / SCAS / BAA P96 / SWE / WR Vss Vcc A00 A01 A02 A03 A04 A05 A06 A07 Vss Vcc A08 A09 A10 A11 A12 A13 A14 A15 Vss P60 / A16 P61 / A17 P62 / A18 P63 / A19 P64 / A20 / SDA0 P65 / A21 / SCL0 P66 / A22 / SDA1 P67 / A23 / SCL1 Vcc
CHAPTER 1 OVERVIEW
Pin No. Table
The pin No. table of the MB91V301 / V301A is shown.
I Pin No. Table Table 1.5-1 MB91V301 / V301A Pin No. Table (Package: PGA-179C-A03)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 E5 C3 C4 B3 A1 D5 A2 C5 B4 A3 D6 C6 B5 B6 A4 A5 D7 C7 B7 A6 A7 B8 D8 C8 A8 A9 B9 C9 D9 A10 PIN N.C. P13 / D11 VSS VCC P14 / D12 P15 / D13 P16 / D14 P17 / D15 VSS VCC P20 / D16 P21 / D17 P22 / D18 P23 / D19 P24 / D20 P25 / D21 P26 / D22 P27 / D23 VSS VCC D24 D25 D26 D27 VSS VCC D28 D29 D30 D31 Pin Name No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PIN B10 C10 A11 B11 D10 C11 A12 B12 A13 D11 C12 B13 A14 B14 D12 E11 C13 D13 C14 A15 E12 B15 E13 D14 C15 F12 F13 E14 F14 D15 VSS VCC P80 / RDY P81 / BGRNT P82 / BRQ RD DQMUU / WR0 P85 / DQMUL / WR1 P86 / DQMLU / WR2 P87 / DQMLL / WR3 VSS VCC P90 / SYSCLK P91 / MCLKE P92 / MCLK P93 VSS VCC Pin Name No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 PIN E15 G12 G13 G14 F15 G15 H14 H12 H13 H15 J15 J14 J13 J12 K15 K14 K13 L15 L14 K12 L13 M15 M14 N15 L12 M13 N14 P15 P14 M12 A07 VSS VCC A08 A09 A10 A11 A12 A13 A14 A15 VSS VCC P60 / A16 P61 / A17 P62 / A18 P63 / A19
SDA0 / P64 / A20 SDA0 MB91V301A only SCL0 / P65 / A21 SCL0 MB91V301A only SDA1 / P66 / A22 SDA1 MB91V301A only SCL1 / P67 / A23 SCL1 MB91V301A only
Pin Name
P94 / SRAS / LABA / AS 79 P95 / SCAS / BAA P96 / SWE / WR VSS VCC A00 A01 A02 A03 A04 A05 A06 80 81 82 83 84 85 86 87 88 89 90
VCC VCC EWR3 EWR2 EWR1 EWR0 ECS EMRAM ICD3
CHAPTER 1 OVERVIEW Table 1.5-1 MB91V301 / V301A Pin No. Table (Package: PGA-179C-A03)
No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PIN L11 N13 N12 P13 R15 M11 R14 N11 P12 R13 M10 N10 P11 P10 R12 R11 M9 N9 P9 R10 R9 P8 M8 N8 R8 R7 P7 N7 M7 R6 ICD2 ICD1 ICD0 VSS VCC BREAK ICLK ICS2 ICS1 ICS0 TRST C AVCC AVRH AVR AN3 AN2 AN1 AN0 AVSS / AVRL
INT0 / PG0 / ICU0 ICU0 MB91V301A only INT1 / PG1 / ICU1 ICU1 MB91V301A only INT2 / PG2 / ICU2 ICU2 MB91V301A only INT3 / PG3 / ICU3 ICU3 MB91V301A only
Pin Name
No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 P6 N6 R5 P5
Pin Name SOT0 / PJ1 SCK0 / PJ2 SIN1 / PJ3 SOT1 / PJ4 SCK1 / PJ5 PPG0 / PJ6 TRG0 / PJ7 TIN0 / PH0 TIN1 / PPG3 / PH1 TIN2 / TRG3 / PH2 VSS C DREQ0 / PB0 DACK0 / PB1 DEOP0 / PB2 DREQ1 / PB3 DACK1 / TRG1 / PB4 DEOP1 / PPG1 / PB5 IOWR / PB6 IORD / PB7 VCC VSS X0 X1 VSS VCC MD0 MD1 MD2 VCC
No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 L1 J4 J3 J2 K1 J1 H2 H4 H3 H1 G1 G2 G3 G4 F1 F2 F3 E1 E2 F4 E3 D1 D2 C1 E4 D3 C2 B1 B2 D4
PIN VCC INIT NMI VSS VCC
Pin Name
CS0 / PA0 CS1 / PA1 CS2 / PA2 CS3 / PA3 CS4 / TRG2 / PA4 CS5 / PPG2 / PA5 CS6 / PA6 CS7 / PA7 VSS VCC D00 / P00 D01 / P01 D02 / P02 D03 / P03 VSS VCC D04 / P04 D05 / P05 D06 / P06 D07 / P07 VSS VCC D08 / P10 D09 / P11 D10 / P12
INT4 / ATG / PG4 / FRCK 145 FRCK MB91V301A only
INT5 / SIN2 / PG5 INT6 / SOT2 / PG6 INT7 / SCK2 / PG7 VCC SIN0 / PJ0
CHAPTER 1 OVERVIEW
List of Pin Functions
This section describes the pin functions of the MB91301 series.
I Description of Pin Functions Table 1.6-1 lists the pin of the MB91301 series and their functions. Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
132 to 139
166 to 169, 172 to 175
D00 to D07 P00 to P07 D08 to D15 P10 to P17 D16 to D23 P20 to P27
External data bus bits 0 to 7. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode.
142 to 144, 1 to 5
178 to 180, 2, 5 to 8
External data bus bits 08 to 15. It is available in the external bus mode. Can be used as ports in 8-bit or 16-bit external bus mode.
External data bus bits 16 to 23. It is available in the external bus mode. Can be used as ports in 8-bit external bus mode.
21 to 24, 27 to 30 33
D24 to D31 RDY
External data bus bits 24 to 31. It is available in the external bus mode. RDY External ready input. The pin has this function when external ready input is enabled. Active level is "H". P80 General purpose input / output port. The pin has this function when external ready input is disabled.
BGRNT
BGRNT Acknowledge output for external bus release. Outputs "L" when the external bus is released. The pin has this function when output is enabled. P81 General purpose input / output port. The pin has this function when output is disabled for external bus release acknowledge.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
BRQ External bus release request input. Input "1" to request release of the external bus. The pin has this function when input is enabled. P82 General purpose input / output port. The pin has this function when the external bus release request input is disabled.
RD External bus read strobe output. This pin is enabled at external bus mode. WR0 External bus write strobe output. This pin is enabled at external bus mode. When WR is used as the write strobe, this becomes the byte-enable pin (UUB). Select signal (DQMUU) of D31 to D24 at using of SDRAM. WR1 External bus write strobe output. The pin has this function when WR1 output is enabled. When WR1 is used as the write strobe, this becomes the byte-enable pin (ULB). P85 General purpose input / output port. The pin has this function when the external bus write-enable output is disabled.
WR0 / DQMUU
WR1 / DQMUL
WR2 / DQMLU
WR2 External bus write strobe output. The pin has this function when WR2 output is enabled. When WR2 is used as the write strobe, this becomes the byte-enable pin (LUB). P86 General purpose input / output port. The pin has this function when the external bus write-enable output is disabled.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
WR3 / DQMLL
WR3 External bus write strobe output. The pin has this function when WR3 output is enabled. When WR3 is used as the write strobe, this becomes the byte-enable pin (LLB). P87 General purpose input / output port. The pin has this functions when the external bus write-enable output is disabled.
SYSCLK
SYSCLK System clock output. The pin has this function when system clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop mode.) P90 General purpose input / output port. The pin has this function when system clock output is disabled.
MCLKE P91
MCLKE Clock enable signal for memory. P91 General purpose input / output port. The pin has this function when clock enable output is disabled.
MCLK Memory clock output. The pin has this function when memory clock output is enabled. This outputs the same clock as the external bus operating frequency. (Output halts in stop and sleep mode.) P92 General purpose input / output port. The pin has this function when memory clock output is disabled.
P93 General purpose input / output port.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
AS Address strobe output. The pin has this function without EDRAM area, when ASE bit of port function register 9 is enabled. LBA Address strobe output for burst flash ROM. The pin has this function in normal accessed area that is set over "1", when ASE bit of port function register 9 is enabled. SRAS RAS single for SDRAM. This pin has this function for accessing to SDRAM area, when ASE bit of port function register 9 is enabled. P94 General purpose input / output port. The pin has this function, when ASE bit of port function register 9 is set as the general purpose port.
BAA Address advance output for burst Flash ROM. The pin has this function when BAAE bit of port function register is enabled. SCAS CAS signal for SDRAM. This pin has this function in SDRAM area, when BAAE bit of port function register is enabled. P95 General purpose input / output port. The pin has this function when BAAE bit of port function register is general purpose port.
WR Memory write strobe output. This pin has this function when WEXE bit of port function register is enabled. SWR Write output for SDRAM. This pin has this function when WEXE bit of port function register is enabled. P96 General purpose input / output port. This pin has this function when WEXE bit of port function register is general purpose port.
A00 to A07 A08 to A15
External address bit 0 to 7. External address bit 8 to 15.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
A16 to A19 P60 to P63
External address bit 16 to 19. It can be used as ports when external address bus is unused. Can be used as ports when external bus is 8-bit mode.
SDA0 Data I / O pin for I2C bus. This function is enable when typical operation of I2C is enable. The port output must remain off unless intentionally turned on. (Open drain output) (This function is only for MB91302A, MB91V301A.) A20 External address bus bit 20. This function is enable during prohibited I2C operation and using external bus. P64 General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus.
SCL0 CLK I / O pin for I2C bus. This function is enable when typical operation of I2C is enable. The port output must remain off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) A21 External address bit 21. This function is enable during prohibited I2C operation and using external bus. P65 General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
SDA1 DATA I / O pin for I2C bus. This function is enable when typical operation of I2C is enable. The output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) A22 External address bit 20. This function is enable during prohibited I2C operation and using external bus. P66 General-purpose I / O port. This function is enable during prohibited I2C and nonused external address bus.
SCL1 CLK I / O pin for I2C bus. This function is enable when typical operation of I2C is enable. The port output must remains off unless intentionally turned on. (open drain output) (This function is only for MB91302A, MB91V301A.) A23 External address bit 21. This function is enable during prohibited I2C operation and unusing external address bus. P67 General-purpose I / O port. This function is enable during prohibited I2C operation and nonused external address bus.
106 to 109
AN0 to AN4
Analog input pin.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
111 to 114
INT0 to INT3
INT0 to INT3 External interrupt inputs. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. Refer to "Chapter 9 Figure 9.3-2" for active level settiing. PG0 to PG3 General purpose input / output ports.
PG0 to PG3 ICU0 to ICU3 -
ICU0 to ICU3 Input capture input pins. These inputs are used continuously when selected as input capture inputs. In this case, do not output to these ports unless doing so intentionally. (This function is only for MB91302A and MB91V301A.) V INT4 External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. Refer to "Chapter 9 Figure 9.3-2" for active level settiing. ATG External trigger input for A / D converter. This input is used continuously when selected as the A / D converter start trigger. In this case, do not output to this port unless doing so intentionally. PG4 General purpose input / output ports.
PG4 FRCK -
FRCK External clock input pin of freerun timer. These inputs are used continuously when using as external clock input pin of free-run timer. In this case, do not output to these ports unless doing so intentionallt. (This function is only for MB91302A and MB90V301A.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
INT5 External interrupt input. These inputs are used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. Refer to "Chapter 9 Figure 9.3-2" for active level settiing. SIN2 UART2 data input pin. This input is used continuously when UART2 is performing input. In this case, do not output to this port unless doing so intentionally. PG5 General purpose input / output port.
PG5 87 117 INT6 L V
INT6 External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. Refer to "Chapter 9 Figure 9.3-2" for active level settiing. SOT2 UART2 data output pin. The pin has this function when UART2 data output is enabled. PG6 General purpose input / output port.
PG6 88 118 INT7 L V
INT7 External interrupt input. This input is used continuously when the corresponding external interrupt is enabled. In this case, do not output to these ports unless doing so intentionally. Refer to "Chapter 9 Figure 9.3-2" for active level settiing. SCK2 UART2 clock input / output pin. The pin has this function when UART2 clock output is enabled. PG7 General purpose input / output port.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
SIN0 UART0 data input pin. This input is used continuously when UART0 is performing input. In this case, do not output to this port unless doing so intentionally. PJ0 General purpose input / output port.
PJ0 91 121 SOT0 J U
SOT0 UART0 data output pin. The pin has this function when UART0 data output is enabled. PJ1 General purpose input / output port.
PJ1 92 122 SCK0 K U
SCK0 UART0 clock input / output pin. The pin has this function when UART0 clock output is enabled. PJ2 General purpose input / output port.
PJ2 93 123 SIN1 K U
SIN1 UART1 data input pin. This input is used continuously when UART1 is performing input. In this case, do not output to this port unless doing so intentionally. PJ3 General purpose input / output port.
PJ3 94 124 SOT1 J U
SOT1 UART1 data output pin. The pin has this function when UART1 data output is enabled. PJ4 General purpose input / output port.
PJ4 95 125 SCK1 K U
SCK1 UART1 clock input / output pin. The pin has this function when UART1 clock output is enabled. PJ5 General purpose input / output port.
PJ5 96 126 PPG0 J U
PPG0 PPG timer output. This pin has this function when PPG0 output is enabled. PJ6 General purpose input / output port.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
TRG0 External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "Chapter 7 EGS1, EGS0: Trigger input edge select bit" for active level setting. PJ7 General purpose input / output port.
PJ7 98 128 TIN0 J
TIN0 Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "Chapter 6 MOD2, MOD1 and MOD0 operating mode select bit" for active level. PH0 General purpose input / output port.
PH0 99 129 TIN1 J
TIN1 Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "Chapter 6 MOD2, MOD1 and MOD0 operating mode select bit" for active level. PPG3 PPG timer output. The pin has this function when PPG3 output is enabled. PH1 General purpose input / output port.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
TIN2 Reload timer input. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "Chapter 6 MOD2, MOD1 and MOD0 operating mode select bit" for active level. TRG3 External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "Chap 7 EGS1, EGS0: Trigger input edge select bit" for active level setting. PH2 General purpose input / output port.
PH2 103 133 DREQ0 J
DREQ0 External input for DMA transfer requests. This input is used continuously when the corresponding external input for DMA transfer requests are enabled. In this case, do not output to this port unless doing so intentionally. Refer to "14.3.1 Setting a Transfer Request" for active level setting. PB0 General purpose input / output port.
PB0 104 134 DACK0 J
DACK0 External acknowledge output for DMA transfer requests. The pin has this function when external acknowledge output for DMA transfer requests is enabled. PB1 General purpose input / output port.
PB1 105 135 DEOP0 J
DEOP0 Completion output for DMA external transfer. The pin has this function when tompletion output for DMA external transfer is enabled. PB2 General purpose input / output port.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
DREQ1
DREQ1 External input for DMA transfer requests. This input is used continuously when external input for DMA transfer request is enabled. In this case, do not output to this port unless doing so intentionally. Refer to "14.3.1 Setting a Transfer Request" for active level. PB3 General purpose input / output port. The pin has this function when completion output and stop input are disabled for DMA transfer.
DACK1
DACK1 External acknowledge output for DMA transfer requests. The pin has this function when external acknowledge output for DMA transfer requests is enabled. TRG1 External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to this port and external acknowledge output for DMA transfer request unless doing so intentionally. PB4 General purpose input / output port.
PB4 108 138 DEOP1 J
DEOP1 Completion output for DMA external transfer. The pin has this function when completion output for DMA external transfer is enabled. PPG1 PPG timer output. The pin has this function when PPE1 bit is enabled. PB5 General purpose input / output port.
PPG1 PB5 109 139 IOWR C
IOWR Write strobe output for DMA fly-by transfer. The pin has this function when outputting a write strobe for DMA fly-by transfer is enabled. PB6 General purpose input / output port. The pin has this function when outputting a write strobe for DMA fly-by transfer is disabled.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
IORD Read strobe output for DMA flyby transfer. The pin has this function when outputting a read strobe for DMA fly-by transfer is enabled. PB7 General purpose input / output port. The pin has this function when outputting a read strobe for DMA fly-by transfer is disabled.
112 113 116 to 118
143 144 147 to 149
X0 X1 MD0 to MD2
Clock (oscillation) input. Clock (oscillation) output. MD0 to MD2 Mode pins to 0 to 2. The levels applied to these pins set the basic operating mode. Connect VCC or VSS. External reset input (Reset to initialize settings) ("L" active) NMI (Non Maskable Interrupt) input ("L" active) CS0 Chip select 0 output. The pin has this function when CS0 area of CSER (Chip Select Enable Register) is enabled and the specified CS0XE bit of port function register is enabled. PA0 General purpose input / output port. The pin has this function when CS0XE bit of port function register is general purpose port.
INIT NMI CS0
CS1 Chip select 1 output. The pin has this function when CS1 area of CSER is enabled and the specified CS1XE bit of port function register is enabled. PA1 General purpose input / output port. The pin has this function when chip select 1 output is disabled.
CS2 Chip select 2 output. The pin has this function when CS2 area of CSER is enabled and the specified CS2XE bit of port function register is enabled. PA2 General purpose input / output port. The pin has this function when chip select 2 output is disabled.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
CS3 Chip select 3 output. The pin has this function when CS3 area of CSER is enabled and the specified CS3XE bit of port function register is enabled. PA3 General purpose input / output port. The pin has this function when chip select 3 output is disabled.
CS4 Chip select 4 output. The pin has this function when CS4 area of CSER is enabled and the specified CS4XE bit of port function register is enabled. TRG2 External trigger input for PPG timer. This input is used continuously when the corresponding timer input is enabled. In this case, do not output to chip select and this port unless doing so intentionally. Refer to "Chap 7 EGS1, EGS0 trigger input edge select bit" for active level setting. PA4 General purpose input / output port. The pin has this function when chip select 4 output is disabled.
CS5 Chip select 5 output. The pin has this function when CS5 area of CSER is enabled and the specified CS5XE bit of port function register is enabled. PPG2 PPG timer output. The pin has this function when PPE2 bit is enabled. PA5 General purpose input / output port. The pin has this function when chip select 5 output and PPG timer output are disabled.
PPG2 PA5
CS6 Chip select 6 output. The pin has this function when CS6 area of CSER is enabled and the specified CS6XE bit of port function register is enabled. PA6 General purpose input / output port. The pin has this function when chip select 6 output are disabled.
CHAPTER 1 OVERVIEW Table 1.6-1 List of pin function (except for power supply, and GND pins)
Pin no. MB91301 / 302A
MB91V301 / V301A
Pin name
I / O circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
CS7 Chip select 7 output. The pin has this function when CS7 area of CSER is enabled and the specified CS7XE bit of port function register is enabled. PA7 General purpose input / output port. The pin has this function when chip select 7 output is disabled.
: Shaded pins are only present on the MB91V301. Table 1.6-2 Power supply and GND pins Pin no. MB91301 / 302A 6, 16, 26, 43, 53, 63, 101, 114, 130, 140 7, 17, 27, 44, 54, 72, 89, 111, 121, 115, 131, 141 73 74 75 80 102 MB91V301 / V301A 3, 9, 19, 25, 31, 41, 47, 52, 62, 72, 94, 131, 142, 145, 154, 164, 170, 176 4, 10, 20, 26, 32, 42, 48, 53, 63, 73, 82, 83, 95, 119, 141, 146, 150, 151, 155, 165, 171, 177 103 104 105 110 1 102, 132 VSS GND pins. Connect all pins at the same potential. 3 V power supply pins. Connect all pins at the same potential. Pin name Function
AVCC AVRH AVR AVSS / AVRL OPEN C
Analog power supply pin for A / D converter Reference power supply pin for A / D converter Capacitor coupling pin for the A / D converter Analog GND pin for A / D converter Open pin. Use at open Capacitor coupling pin for the internal regulator
Table 1.6-3 Tool pins Pin no. MB91301 / 302A MB91V301 / V301A 97 101 ICLK TRST Pin name I / O circuit type S Q Clock output Tool reset Function
CHAPTER 1 OVERVIEW Table 1.6-3 Tool pins Pin no. MB91301 / 302A MB91V301 / V301A 98 to 100 ICS2 to ICS0 ICD3 to ICD0 BREAK EMRAM ECS EWR3 to EWR0 Pin name I / O circuit type N Function
Device status output (during TRC) DSU4 operation status output (during EML) Trace information output (during TRC) Program / data I / O (duuring EML) DSU4 break reqest input Emulation memory detection Chip select for emuration memory Write strobe for emuration memory
CHAPTER 1 OVERVIEW
I / O Circuit Types
This section describes the I / O circuit types.
I I / O Circuit Types Table 1.7-1 I / O Circuit Types Type A
Circuit
Remarks Oscillation feedback resistance approx. 1 M Clock input
Digital input
C Digital output Digital output
Digital input Standby control
CHAPTER 1 OVERVIEW Table 1.7-1 I / O Circuit Types (Continued) Type D Circuit Analog input With switch Remarks
Analog input Channel control G CMOS level output No standby control
Digital input Standby control
Digital input M CMOS level hysteresis input no standby control
O Digital input P Digital input
Input buffer CMOS level input
Digital input
STANDBY CONTROL
U Digital output Digital output Digital input
STANDBY CONTROL
V Digital output Digital output Digital input
CHAPTER 2
HANDLING THE DEVICE
This chapter provides precautions on handling the MB91301 series. 2.1 "Precautions on Handling the Device" 2.2 "Precautions on Handling Power Supplies"
CHAPTER 2 HANDLING THE DEVICE
Precautions on Handling the Device
This section contains information on preventing a latch up and on the handling of pins.
I Preventing a Latch up A latch up can occur if, on a CMOS IC, a voltage higher than VCC or a voltage lower than VSS is applied to an input or output pin or a voltage higher than the rating is applied between VCC and VSS. A latch up, if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. I Handling of Pins The following are precautions on treating various pins and on quartz oscillation circuits. Unused input pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pull-up or pull-down resistor. Power supply pins If more than one VCC or VSS pin exists, those that must be kept at the same potential are designed to be connected to one other inside the device to prevent malfunctions such as latch up. Be sure to connect the pins to a power supply and ground external to the device to minimize undesired electromagnetic radiation, prevent strobe signal malfunctions due to an increase in ground level, and conform to the total output current rating. Given consideration to connecting the current supply source to VCC or VSS of the device at the lowest impedance possible. It is also recommended that a ceramic capacitor of around 0.1 µF be connected between VCC and VSS at circuit points close to the device as a bypass capacitor. Quartz oscillation circuit Noise near the X0 or X1 pin may cause the device to malfunction. Design printed circuit boards so that X0, X1, the quartz oscillator (or ceramic oscillator), and the bypass capacitor to ground are located as near to one another as possible. It is strongly recommended that printed circuit board artwork that surrounds the X0 and X1 pins with ground be used to increase the expectation of stable operation.
CHAPTER 2 HANDLING THE DEVICE External clock When using an external clock, in general supply it to the X0 pin while also supplying a reversephase clock to the X1 pin simultaneously. In this case, do not use the STOP mode (oscillation stop mode), use an external resistor of about 1 k to be inserted, since the X1 pin stops with H level output in STOP mode and collision between the outputs must be prevented. Additionally, the X0 pin can be used only if an external clock is supplied at 12.5 MHz. The following figure shows an example of using an external clock. Figure 2.1-1 Using an external clock (normal)
X0 X1 MB91301 series
Note: Stop mode (oscillation stop mode) can not be used.
Figure 2.1-2 Using an external clock (less than 12.5 MHz)
X0 Open X1 MB91301 series
Treatment of NC and OPEN pins Pins marked as "NC" or "OPEN" must be left open-circuit. Mode pins (MD0 to MD2) These pins must be directly connected to VCC or VSS when they are used. Keep the pattern length between a mode pin on a printed circuit board and VCC or VSS as short as possible so that they can be connected at a low impedance. I Precautions on Use MB91301 series Clock controller Reservea regulator wait time or an oscillation stabilization wait time when an L-level signal is input to INIT. Notes on during operation of PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. MCLK and SYSCLK MCLK is stopped in sleep and stop modes, and SYSCLK is stopped only in stop mode. Use MCLK and SYSCLK appropriately according to the purpose of use.
In addition, please set I flag, ILM, and ICR to diverge to the interruption handler that is the return factor after the standby returns. (2) Do not do the following when the monitor debugger is used. - Set the break point to the above - mentioned instruction row. - Execute the step for the above - mentioned instruction row. Prefetch When allowing prefetch from an area that has been set as a little endian area, limit access to the area to word access (i.e., access in units of 32 bits). The area cannot be accessed correctly by byte or half-word accesses. I / O port access Only byte accesses are allowed to I / O ports. Switching the function of a common port Use the port function register (PFR) to switch the function of a pin which also serves as a port. However, use an external bus setting to switch the function of a bus pin. D-bus memory Do not set a code area in D-bus memory. No instruction fetch is performed to the D-bus. Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control. Do not set a data area in I-bus memory.
CHAPTER 2 HANDLING THE DEVICE I-bus memory Do not set a stack area or vector table in I-bus memory. It may cause a hang during EIT processing (including RETI). Recovery from the hang requires a reset. Do not perform DMA transfer to I-bus memory. Notes on the PS register Since some instructions manipulate the PS register earlier, the following exceptions may cause the interrupt handler to break or the PS flag to update its display setting when the debugger is being used. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. · The following operations may be performed when the instruction immediately followed by a DIVOU / DIVOS instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c) breaks in response to a data event or emulator menu:
1. D0 and D1 flags are updated earlier. 2. The EIT handler (user interrupt / NMI or emulator) is executed. 3. Upon returning from the EIT, the DIVOU / DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as those in (1) above. · The following operations are performed when the ORCCR / STILM / MOV Ri and PS instructions are executed to enable interruptions when a user interrupt or NMI trigger event has occurred.
1. The PS register is updated earlier. 2. The EIT handler (user interrupt / NMI) is executed. 3. Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as that in (1) above. R15 (General purpose register) When any of the following instructions is executed, the SSP or USP value is not used as R15, resulting in an incorrect value written to memory. AND OR EOR XCHB R15, @Ri R15, @Ri R15, @Ri @Rj, R15 ANDH ORH EORH R15, @Ri R15, @Ri R15, @Ri ANDB ORB EORB R15, @Ri R15, @Ri R15, @Ri
: R15 is a virtual register. When a program attempts to access R15, the SSP or USP is accessed depending on the status of the "S" flag as an SP flag. When coding the above ten instructions using an assembler, specify a general-purpose register other than R15. RETI instruction Please do not neither control register of the instruction cache nor the data access to RAM of the instruction cache immediately before the instruction of RETI. Watchdog timer function The watchdog timer function of this model monitors whether a program holds over a reset within a specified time. It also resets the CPU if the reset is not held over because of uncontrollable program operation. After the watchdog timer function is enabled, it keeps operating until a reset occurs.
CHAPTER 2 HANDLING THE DEVICE The watchdog timer function usually holds over CPU reset automatically when program execution by the CPU stops. For the relevant exception conditions, see "3.12.7 Peripheral Circuits of Clock Controller". The reset by the watchdog timer function might not occur if the above status is caused by uncontrollable system operation. If it might occur, a reset (INIT) request must be input from the external INIT pin. A / D converter When the device is turned on or returns from a reset or stop, it takes time for the external capacitor to be charged, requiring the A / D converter to wait for at least 10 ms. I Unique to the evaluation chip MB91V301 / 301A Tool reset On an evaluation board, use the chip with INIT and TRST connected together. Single-stepping the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and lowinterrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. Simultaneous occurrences of a software break and a user interrupt / NMI When a software break and a user interrupt / NMI take place at the same time, the emulator debugger can cause the following phenomena: · · The debugger stops pointing to a location other than the programmed breakpoints. The halted program is not re-executed correctly.
If these phenomena occur, use a hardware break instead of the software break. If the monitor debugger has been used, avoid setting any break at the relevant location. Operand break A stack pointer placed in an area set for a DSU operand break can cause a malfunction. Do not apply a data event break to access to the area containing the address of a system stack pointer. ICE startup sequence When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area being used before downloading. After turning on the power to the target, the states of the RDX and WR0X to WR3X pins are undefined until you perform the above setting. Accordingly, include enabling pull-up as part of the startup sequence. If using these pins as general-purpose ports, set as output ports to prevent conflict with the output signals during the time the pin states are undefined. External bus width Pin name RD WR0 WR1 (P85) WR2 (P86) WR3 (P87) 32 bit Pull-up Pull-up Pull-up Pull-up Pull-up 16 bit Pull-up Pull-up Pull-up 8 bit Pull-up Pull-up
CHAPTER 2 HANDLING THE DEVICE
Precautions on Handling Power Supplies
This section provides precautions on power supplies with regard to pin handling and processing when power is turned on.
I Processing after Power-on Immediately after power-on, be sure to apply a reset that initializes settings (INIT) from the INIT pin. To provide for an oscillation stabilization wait time and regulator stabilization wait time immediately after power-on, continue to input the L level to the INIT pin as long as the oscillation stabilization wait time required by the oscillating circuit. (Initialization by INIT from the INIT pin sets the oscillation stabilization wait time to the minimum value.) I External clock Input after Power-on After power-on, be sure to input an external clock until the oscillation stabilization wait is canceled. I Indeterminate Output When the Power Is Turned On When the power is turned on, the output pin may remain unstable until the internal power supply becomes stable. I Notes on Using the Internal DC-DC Regulator and A / D Converter The MB91301 series contains a regulator. Be sure to supply power to the VCC pin at 3.3 V and add a bypass capacitor of about 4.7 µF for the regulator to the C pin. The regulator contains an A / D converter and supplies power to AVCC at 3.3 V. Be sure to insert a capacitor of at least 0.05 µF between the AVR and AVSS / AVRL pins. Figure 2.2-1 Notes on Using the Internal DC-DC Regulator and A / D Converter
3.3V 3.3V
Vcc AVcc AVRH
C 4.7 µF Vss
0.05 µF
AVR AVss / AVRL Vss
MB91301
CHAPTER 3
CPU AND CONTROL UNITS
This chapter provides basic information required to understand the functions of the MB91301 series. It covers architecture, specifications, and instructions. 3.1 "Memory Space" 3.2 "Internal Architecture" 3.3 "Instruction Cache" 3.4 "Dedicated Registers" 3.5 "General-Purpose Registers" 3.6 "Data Structure" 3.7 "Word Alignment" 3.8 "Memory Map" 3.9 "Branch Instructions" 3.10 "EIT (Exception, Interrupt, and Trap)" 3.11 "Reset (Device Initialization)" 3.12 "Clock Generation Control" 3.13 "Device State Control" 3.14 "Operating Modes"
CHAPTER 3 CPU AND CONTROL UNITS
Memory Space
The MB91301 series has a logical address space of 4 GB (232 addresses), which the CPU accesses linearly.
I Memory Map Figure 3.1-1 "Memory Map" shows the memory space of the MB91301 series.
CHAPTER 3 CPU AND CONTROL UNITS Figure 3.1-1 Memory Map
0000 0000H
Direct addre ssing area see "II / O MAP" I / O
0000 0400H
I / O 0001 0000H 0002 0000H
I-RAM
0003 E000H
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
Internal RAM 4 Kbytes
Access prohibited
0003 F000H
Internal RAM 8 Kbytes Internal RAM 8 Kbytes Access prohibited
Internal RAM 8 Kbytes Internal RAM 8 Kbytes Access prohibited External area
Internal RAM 8 Kbytes
0004 0000H
0004 2000H
External area
0006 0000H 000E 0000H
Access prohibited Access prohibited
External area External area
External area
000F E000H
000F F000H
Internal ROM 4 Kbytes2
0010 0000H
Internal ROM 4Kbytes2
Internal RAM 8 Kbytes emulation
Access prohibited
FFFF FFFFH
External area
1 : On specific area between 10000H and 2000H, 4 Kbyte RAM can be used. Refer to "IINSTRUCTION CACHE". 2 : The real time OS internal model stores the real time OS kernel. The program loader internal model stores the program loader. 3 : Non-ROM model supports the external ROM external bus mode only. Note : Internal ROM emulation : only MB91V301A Note: Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see "IMODE SETTINGS".)
CHAPTER 3 CPU AND CONTROL UNITS Direct addressing area The areas in the address space listed below are used for input-output. These areas called the direct addressing area. The address of an operand can be directly specified in an instruction. The size of the direct addressing area varies according to the size of data to be accessed: · · · Byte data access: 0 to 0FFH Halfword data access: 0 to 1FFH Word data access: 0 to 3FFH
CHAPTER 3 CPU AND CONTROL UNITS
Internal Architecture
The MB91301 series is a high-performance core based on RISC architecture and advanced instructions for embedded applications.
I Features
RISC architecture used Basic instruction: One instruction per cycle 32-bit architecture General-purpose register: 32 bits x 16 4 GB linear memory space
Multiplier insta