FR60 32-BIT MICROCONTROLLER MB91301 Series HARDWARE MANUAL
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CM71-10114-3E
FR60
32-BIT MICROCONTROLLER
MB91301 Series HARDWARE MANUAL
FR60
32-BIT MICROCONTROLLER
MB91301 Series HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
Objectives Intended Reader Thank using Fujitsu semiconductor products. MB91301 series standard microcontroller that 32-bit high-performance RISC well built-in resources control mechanisms embedded controller that requires high-performance high-speed processing. Although MB91301 series basically uses external access support vast address space accessed 32-bit CPU, instruction cache memory (for data) increase speed which executes instructions. MB91301 series most suitable embedded applications, such digital video cameras, navigation systems, players, that require high level processing power. MB91301 series FR60 series microcontrollers, which based FR30/40 family CPUs. enhanced access optimized high-speed use. This manual intended engineers will develop products using MB91301 series describes functions operations MB91301 series. Read this manual thoroughly. more information instructions, "Instructions Manual". Trademarks which abbreviation FUJITSU RISC controller, product Fujitsu Limited. License Purchase Fujitsu components conveys license under Philips Patent Rights use, these components system provided that system conforms Standard Specification defined Philips.
Structure This Manual This manual consists following chapters appendix. CHAPTER OVERVIEW This chapter provides basic information required understand MB91301 series, covers features, block diagram, functions. CHAPTER HANDLING DEVICE This chapter provides precautions handling MB91301 series. CHAPTER CONTROL UNITS This chapter provides basic information required understand functions MB91301 series. covers architecture, specifications, instructions. CHAPTER EXTERNAL INTERFACE external interface controller controls interfaces with internal chips with external memory devices. This chapter explains each function external interface operation. CHAPTER PORT This chapter describes ports configuration functions registers. CHAPTER 16-BIT RELOAD TIMER This chapter describes 16-bit reload timer, configuration functions registers, 16-bit reload timer operation. CHAPTER TIMER This chapter describes U-TIMER, configuration functions registers, UTIMER operation. CHAPTER U-TIMER This chapter describes external interrupt controller, configuration functions registers, operation external interrupt controller. CHAPTER EXTERNAL INTERRUPT CONTROLLER This chapter describes functions operation delayed interrupt module. CHAPTER DELAYED INTERUPT MODULE This chapter describes interrupt controller, configuration functions registers, interrupt controller operation. also presents example using hold request cancellation request function. CHAPTER INTERRUPT CONTROLLER This chapter describes converter, configuration functions registers, converter operation. CHAPTER CONVERTER This chapter describes UART, configuration functions registers, UART operation. CHAPTER UART This chapter describes interface, configuration functions registers, interface operation.
CHAPTER CONTROLLER (DMAC) This chapter describes controller (DMAC), configuration functions registers, DMAC operation. CHAPTER SEARCH MODULE This chapter describes search module, configuration functions registers, search module operation. CHAPTER INTERFACE This chapter describes search module, configuration functions registers, search module operation. CHAPTER 16-bit Free-run Timer This chapter describes search module, configuration functions registers, search module operation. CHAPTER Input Capture This chapter describes search module, configuration functions registers, search module operation. CHAPTER Program Loader Mode (Supported only MB91302A (IPL integrated model)) This chapter describes search module, configuration functions registers, search module operation. CHAPTER Real time Embedded MB91302A User's Guide This chapter describes search module, configuration functions registers, search module operation. APPENDIX This appendix consists following parts: map, interrupt vector, states state, notes using little endian area, instruction lists. appendix contains detailed information that could included main text reference material programming.
contents this document subject change without notice. Customers advised consult with FUJITSU sales representatives before ordering. information, such descriptions function application circuit examples, this document presented solely purpose reference show examples operations uses Fujitsu semiconductor device; Fujitsu does warrant proper operation device with respect based such information. When develop equipment incorporating device based such information, must assume responsibility arising such information. Fujitsu assumes liability damages whatsoever arising information. information this document, including descriptions function schematic diagrams, shall construed license exercise intellectual property right, such patent right copyright, other right Fujitsu third party does Fujitsu warrant non-infringement third-party' intellectual property right other right using such information. Fujitsu assumes liability infringement intellectual property rights other rights third parties which would result from information contained herein. products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated accompanying fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), requiring extremely high reliability (i.e., submersible repeater artificial satellite). Please note that Fujitsu will liable against and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. products described this document represent goods technologies subject certain restrictions export under Foreign Exchange Foreign Trade Japan, prior authorization Japanese government will required export those products from Japan.
©2004 FUJITSU LIMITED Printed Japan
Read This Manual
Terms Used This Manual following defines principal terms used this manual. Term I-bus Meaning internal instructions. series, which based internal Harvard architecture, independent buses used instructions data. converter connected I-bus. Internal 32-bit data bus. internal resource connected D-bus. Internal instructions data multiplexed Princeton bus. F-bus connected I-bus D-bus switch. F-bus connected built-in resources such RAM. External interface bus. X-bus connected external interface module. Data instructions multiplexed external bus. Internal 16-bit data bus. R-bus connected F-bus adapter. I-O, clock generator, interrupt controller connected R-bus. Since addresses data multiplexed R-bus that bits wide, more than cycle required access these resources. Execution unit operations. System clock. Clock generated clock generator each internal resources connected R-bus. This clock same frequency source oscillation maximum, becomes 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/16 1/2, 1/4, 1/6, 1/32) frequency clock determined divide-by rate specified bits clock generator DIVR0 register. System clock. Operating clock each other resources connected other than R-bus X-bus. This clock same frequency source oscillation maximum, becomes 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/16 1/2, 1/4, 1/6, 1/32) frequency clock determined divided-by rate specified bits clock generator DIVR0 register. System clock. Operating clock external resources connected Xbus. This clock same frequency source oscillation maximum, becomes 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/16 1/2, 1/4, 1/6, 1/32) frequency clock determined divided-by rate specified bits clock generator DIVR1 register.
D-bus F-bus
X-bus
R-bus
E-unit CLKP
CLKB
CLKT
PREFACE Read This Manual
CHAPTER
OVERVIEW
Features MB91301 Series Block Diagram External Dimensions Layout Table List Functions Circuit Types
CHAPTER
HANDLING DEVICE
Precautions Handling Device Precautions Handling Power Supplies
CHAPTER
CONTROL UNITS
Memory Space Internal Architecture Instruction Cache 3.3.1 Configuration Instruction Cache 3.3.2 Configuration Control Registers 3.3.3 Instruction Cache Statuses Settings 3.3.4 Setting Instruction Cache Before Dedicated Registers 3.4.1 Program Status (PS) Register General-Purpose Registers Data Structure Word Alignment Memory Branch Instructions 3.9.1 Operation Branch Instructions with Delay Slot 3.9.2 Operation Branch Instruction without Delay Slot 3.10 (Exception, Interrupt, Trap) 3.10.1 Interrupt Levels 3.10.2 Interrupt Control Register (ICR) 3.10.3 System Stack Pointer(SSP) 3.10.4 Table Base Register (TBR) 3.10.5 Multiple Processing 3.10.6 Operations 3.11 Reset (Device Initialization) 3.11.1 Reset Levels 3.11.2 Reset Sources 3.11.3 Reset Sequence 3.11.4 Oscillation Stabilization Wait Time 3.11.5 Reset Operation Modes
3.12 Clock Generation Control 3.12.1 Controls 3.12.2 Oscillation Stabilization Wait Time Lock Wait Time 3.12.3 Clock Distribution 3.12.4 Clock Division 3.12.5 Block Diagram Clock Generation Controller 3.12.6 Register Clock Generation Controller 3.12.7 Peripheral Circuits Clock Controller 3.13 Device State Control 3.13.1 Device States State Transitions 3.13.2 Low-power Modes 3.14 Operating Modes
CHAPTER
EXTERNAL INTERFACE
Overview External Interface External Interface Registers 4.2.1 Area Select Registers 0-7(ASR0-7) 4.2.2 Area Configuration Registers (ACR0-7) 4.2.3 Area Wait Register (AWR0-7) 4.2.4 Memory setting register (MCRA SDRAM/FCRAM auto precharge mode) 4.2.5 Memory setting register (MCRB FCRAM auto precharge mode) 4.2.6 Wait Registers DMAC (IOWR0, 4.2.7 Chip Select Enable Register (CSER) 4.2.8 Cache Enable Register (CHER) 4.2.9 Pin/Timing Control Register (TCR) 4.2.10 Refresh Control Register (RCR) Setting Example Chip Select Area Endian Access 4.4.1 Endian Access 4.4.2 Little Endian Access 4.4.3 Comparison Endian Little Endian External Access Operation Ordinary interface 4.5.1 Basic Timing 4.5.2 Operation Byte Control Type 4.5.3 Read Write Operation 4.5.4 Write Write Operation 4.5.5 Auto-Wait Cycle 4.5.6 External Wait Cycle 4.5.7 Synchronous Write Enable Output 4.5.8 Delay Setting 4.5.9 RD/WRn Setup RD/WRn Hold Setting 4.5.10 Fly-By Transfer (I/O Memory) 4.5.11 Fly-By Transfer (Memory I/O) Burst Access Operation Address/data Multiplex Interface Prefetch Operation SDRAM/FCRAM Interface Operation
viii
4.9.1 Self Refresh 4.9.2 Power-on Sequence 4.9.3 Connecting SDRAM/FCRAM Many Areas 4.9.4 Address Multiplexing Format 4.9.5 Memory Connection Example 4.10 Access Operation 4.10.1 Fly-By Transfer (I/O Memory) 4.10.2 Fly-By Transfer (Memory I/O) 4.10.3 Fly-By Transfer (I/O SDRAM/FCRAM) 4.10.4 Fly-By Transfer (SDRAM/FCRAM I/O) 4.10.5 2-Cycle Transfer (Internal External I/O, RAM) 4.10.6 2-Cycle Transfer (External I/O) 4.10.7 2-Cycle Transfer (I/O External) 4.10.8 2-Cycle Transfer (I/O SDRAM/FCRAM) 4.10.9 2-Cycle Transfer (SDRAM/FCRAM I/O) 4.11 Arbitration 4.12 Procedure Setting Register 4.13 Notes Using External Interface
CHAPTER
PORT
Overview Port Port Registers
CHAPTER
6.2.1 6.2.2 6.2.3
16-BIT RELOAD TIMER
Overview 16-bit Reload Timer 16-bit Reload Timer Registers Control Status Register (TMCSR) 16-bit Timer Register (TMR) 16-bit Reload Register (TMRLR) 16-bit Reload Timer Operation Operating States Counter Precautions Using 16-bit Reload Timer
CHAPTER
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6
TIMER
Overview Timer Block Diagram Timer Registers Timer Control status registers (PCNH, PCNL) cycle register (PCSR) duty register (PDUT) timer register (PTMR) General control register (GCN10) General control register (GCN20) Operation One-shot Operation Timer Interrupt Source Timing Chart Activating Multiple Channels Using General Control Register
Notes Timer
CHAPTER
U-TIMER
Overview U-TIMER U-TIMER Registers U-TIMER Operation
CHAPTER
EXTERNAL INTERRUPT CONTROLLER
Overview External Interrupt Controller External Interrupt Controller Registers 9.2.1 Interrupt Enable Register (ENIR) 9.2.2 External Interrupt Source Register (EIRR) 9.2.3 External Interrupt Request Level Setting Register (ELVR) Operation External Interrupt Controller
CHAPTER DELAYED INTERUPT MODULE
10.1 10.2 10.3 Overview Delayed Interrupt Module Delayed Interrupt Module Registers Operation Delayed Interrupt Module
CHAPTER INTERRUPT CONTROLLER
11.1 Overview Interrupt Controller 11.2 Interrupt Controller Registers 11.2.1 Interrupt Control Register (ICR) 11.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) 11.3 Interrupt Controller Operation 11.4 Example Using Hold Request Cancellation Request Function (HRCR)
CHAPTER CONVERTER
12.1 Overview Converter 12.2 Converter Registers 12.2.1 Control Status Register (ADCS) 12.2.2 Data Register (ADCR) 12.2.3 Conversion result register (ADCR0 12.3 Converter Operation 12.4 Precautions Using Converter
CHAPTER UART
13.1 Overview UART 13.2 UART Registers 13.2.1 Serial Mode Register (SMR) 13.2.2 Serial Control Register (SCR) 13.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) 13.2.4 Serial Status Register (SSR) 13.2.5 DRCL Register 13.3 UART Operation 13.3.1 Asynchronous (Start-stop Synchronization) Mode
13.3.2 Synchronous Mode 13.3.3 Occurrence Interrupts Timing Setting Flags 13.4 Example Using UART 13.5 Example Setting U-TIMER Baud Rates Reload Values
CHAPTER CONTROLLER (DMAC)
14.1 Overview Controller (DMAC) 14.2 Controller (DMAC) Registers 14.2.1 Control/Status Registers (DMACA0 14.2.2 Control/Status Registers (DMACB0 14.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 4/DMADA0 14.2.4 DMAC All-Channel Control Register (DMACR) 14.2.5 Other Functions 14.3 Controller (DMAC) Operation 14.3.1 Setting Transfer Request 14.3.2 Transfer Sequence 14.3.3 General Aspects Transfer 14.3.4 Addressing Mode 14.3.5 Data Types 14.3.6 Transfer Count Control 14.3.7 Control 14.3.8 Hold Arbitration 14.3.9 Operation from Starting End/Stopping 14.3.10 DMAC Interrupt Control 14.3.11 Channel Selection Control 14.3.12 Supplement External Internal Operation Timing 14.4 Operation Flowcharts 14.5 Data 14.6 External Interface 14.6.1 Input Timing DREQx 14.6.2 FR30 Compatible Mode DACK
CHAPTER SEARCH MODULE
15.1 15.2 15.3 Overview Search Module Search Module Registers Search Module Operation
CHAPTER INTERFACE
16.1 16.2 16.3 16.4 16.5 16.6 Overview Interface Interface Registers Block Diagram Interface Detailed Registers Interface Interface Operation Operation Flowcharts
CHAPTER 16-bit Free-run Timer
17.1 17.2 17.3 17.4 17.5 17.6
Overview 16-bit Free-run Timer Registers 16-bit Free-run Timer Block Diagram 16-bit Free-run Timer Details Registers 16-bit Free-run Timer Operation 16-bit Free-run Timer Precautions Using 16-bit Free-run Timer
CHAPTER Input Capture
18.1 18.2 18.3 18.4 18.5 Overview Input Capture Input Capture Registers Block Diagram Input Capture Details Registers Input Capture Operation 16-bit Input Capture
CHAPTER Program Loader Mode (Supported only MB91302A (IPL integrated model))
19.1 19.2 19.3 19.4 Overview Program Loader Mode Setting Program Loader Operations Program Loader Mode Example Using Program Loader Mode Write Flash Memory
CHAPTER Real time Embedded MB91302A User's Guide
20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Introduction Memory Specifications REALOS/FR Embedded MB91302A-010 Section Allocation Startup Routine Initial Settings SOFTUNE Workbench REALOS/FR Mode Pins, Mode Vectors, Reset Vectors Chip Evaluation System
APPENDIX
APPENDIX APPENDIX INTERRUPT VECTOR APPENDIX STATE EACH STATE APPENDIX NOTES USING LITTLE ENDIAN AREA Compiler (fcc911) Assembler (fasm911) Linker (flnk911) Debugger (sim911, eml911, mon911) APPENDIX INSTRUCTION LISTS Read Instruction Lists Family Instruction Lists
CHAPTER
OVERVIEW
This chapter provides basic information required understand MB91301 series, covers features, block diagram, functions. "Features MB91301 Series" "Block Diagram" "External Dimensions" "Pin Layout" "Pin Table" "List Functions" "Input-output Circuit Forms"
CHAPTER OVERVIEW
Features MB91301 Series
MB91301 series standard single-chip microcontroller that 32-bit highperformance RISC well built-in resources control mechanisms embedded controller requiring high-performance high-speed processing. Although MB91301 series basically uses external access support vast address space accessed 32-bit CPU, instruction cache memory increase speed which executes instructions. This model FR60 series model that based FR30/40-family CPUs. enhanced access optimized high-speed use. MB91301 series most suitable embedded applications, such digital video cameras, navigation systems, players, that require high level processing power.
Features MB91301 Series MB91301 series line-up series embeded each program built-in ROM. variation Products MB91302A MB91301 32-bit RISC, load/store architecture, five pipelines Operating frequency (Internal maximum value), (External maximum value) [PLL used, original oscillation MHz] 32-bit general-purpose register 16-bit fixed-length instructions (basic instructions), instruction cycle Memory-to-memory transfer, processing, instructions, including barrel shift, etc.; instructions appropriate embedded applications Function entry exit instructions, multi load/store instructions-instructions compatible with high-level languages Instructions entry/exit functions, multiple load/store instructions register contents, instructions high-level languages. Register interlock function facilitate assembly-language coding Branch instruction with delay slot allowing decrease overhead branch processing Built-in multiplier/instruction-level support Signed 32-bit multiplication: cycles Signed 16-bit multiplication: cycles Real time internal version (internal program loader) internal version User version version
Interrupts (saving PS): cycles, priority levels
CHAPTER OVERVIEW Interface Maximum operating frequency using SRAM) 24-bit address fully output space) 32-bit data Prefetch buffer installed Unused data address pins used general-purpose ports. Totally independent 8-area chip select output that defined minimum Support interfaces various memory modules Asynchronous SRAM, asynchronous ROM/FLASH Page-mode ROM/FLASHROM page-size selected) Burst-mode ROM/FLASH (MBM29BL160D/161D/162D etc.) SDRAM FCRAM type, Latency1 bank product) Address/data multiplexed bit/16 width only)
Basic cycle: cycles Automatic wait cycle generator (Max cycles) that programmed each area insert waits External wait cycles input Endian setting byte ordering (big/little) are, however, only endian Write disable setting (read only data) Enable/disable captureing built-in cache Enable/disable prefetch function Supports fly-by transfer that enables independent wait control External arbitration using BGRNT enabled
Built-in Memory DATA RAM: ROM: (MB91302A)
Built-in DATA DATA/Instruction MB91V301 Built-in DATA RAM, DATA/instruction emulation MB91V301A Instruction Cache Capacity associative block/way, entry words)/block Lock function allows specific program codes stay resident cache Instruction function: part instruction cache used
DMAC (DMA Controller) channels channels external request)
CHAPTER OVERVIEW transfer sources (external pins, internal peripherals, software) Internal peripheral selected each channel transfer factor Addressing mode with 32-bit full address specifications (increase, decrease, fixed) Transfer modes (demand transfer, burst transfer, step transfer, block transfer) Fly-by transfer supported (three channels between external external memory) Transfer data size that selected from bits
Search Module Searches position first varying between word
Reload Timer (including Channel REALOS) UART UART full-duplex double buffer Independent channels Data length: bits parity), bits (parity) Either asynchronous (start-stop synchronization) synchronous communication selected. Multi processor mode Built-in 16-bit timer (U-TIMER) boud rate generater: generatin arbitrary baud rates external clock used transfer clock. Error detection functions (parity, frame, overrun) 16-bit timer; channels Internal clock: 2-clock cycle resolution, selectable from dividen frequency
Interrupt Controller Total external interrupts (one unmaskable (NMI) eight regular interrupt pins (INT7 INT0)) Internal interrupt source: UART, DMAC, A/D, UTIMER, delay interrupt, I2C, free-running timer I2C, free running timer, sources unique MB91302A MB91V301A. Priority level defined programmable levels) except unmaskable
Converter (sequential conversion type) 10-bit resolution, channels Sequential comparison conversion type: peripheral clock (CLKP) clock cycle conversion time (about µs/ch 34MHz operating) Built-in sample hold circuit Conversion modes (single-shot conversion mode, scan conversion mode, repeat conversion mode)
CHAPTER OVERVIEW Interface Master/slave transmission reception Clock synchronization function Arbitration function interface only MB91302A, MB91301A. Causes startup (select from software, external triggers, internal timer)
Free Timer 16-bit 1channel Input capture channels Free timer only MB9130A MB91V301A.
Other Interval Timers 16-bit timer: channels (U-TIMER) timer: 4channels Watchdog timer; channel
Other Features built-in oscillation circuit clock source which multiplication selected. INIT provided reset pin. Additionally, watchdog timer reset software resets provided. Stop mode sleep mode supported low-power modes Gear function Allows arbitrary different operating clock frequencies peripherals. gear clock factor selected from among options: 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, 1/8,., 1/16. Note that maximum operating frequency peripherals MHz. Built-in time base timer Packages MB91301/302A (FPT-144P-M12) MB91V301/V301A (PGA-179C-A03) 0.25 Power supply (analog power supply): using internal regulator)
CMOS technology
Power voltages
chip Device Support Unit (DSU4) installed MB91V301/V301A.
CHAPTER OVERVIEW
Product Line-up
MB91301
Type External version (for volume production) (only data)
MB91V301
Evaluation version (For evaluation development) (data KB+8
MB91302A
Mask product (for volume production) (only data) non-ROM model, optimal real time internal model*1, (Internal Program Loader) internal model*2 adding user model. LQFP-144 (0.4 pitch) Currently production
MB91V301A
Evaluation version (For evaluation development) (data KB+8
(RAM)
Package Other
LQFP-144 (0.4 pitch) Currently production
DSU4 PGA-179 Currently available
DSU4 PGA-179 Currently available
Fujitsu product real time REALOS/FR conforming µITORN stored optimized with MB91302A. details built-in service call type specification user task, "CHAPTER Real time Embedded MB91302A User's Guide" following manual; FAMILY SOFTUNE REALOS/ USER'S GUIDE FAMILY SOFTUNE REALOS/ KERNEL MANUAL FR-V/ FAMILY CONFORMING µITRON4.0 SPECIFICATIONS SOFTUNE REALOS CONFIGURATOR MANUAL FR-V/ F2MC FAMILY SOFTUNE REALOS ANALYZER MANUAL
stores (Internal Program Loader). Loading various programs executed from external system internal UART/SIO. Using this function, example, writing board Flash memory connected external executed.
CHAPTER OVERVIEW
Block Diagram
Figure 1.2-1 "Block Diagram" block diagram MB91301 series.
Block Diagram Figure 1.2-1 BLOCK DIAGRAM (MB91301, MB91V301)
Core
I-Cache
DREQ0, DREQ1 DACK0, DACK1 DEOP0, DEOP1 IOWR IORD
search (stack) Converter
DMAC
INIT
<Symbol>= Clock control
External memory
BGRNT SYSCLK MCLK MCLKE SRAS SCAS DQMUU, DQMLU,L PPG0 PPG3 TRG0 TRG3
Interrupt controller
SDRAM INT0 INT7 SIN0 SIN2 SOT0 SOT2 SCK0 SCK2
External interrupts
UART
timer
U-TIMER
PORT
AVR, AVRH, AVCC AVSS/AVRL TIN0 TIN2
PORT
Reload timer
CHAPTER OVERVIEW Figure 1.2-2 BLOCK DIAGRAM (MB91302A, MB91V301A) Core
DMAC
I-Cache
DREQ0,1 DACK0, DEOP0, IOWR IORD
search
MB91302A MB91V301A (stack)
MB91302A MB91V301A
Converter
INIT
Adapter
External memory
Clock control
BGRNT SYSCLK MCLK MCLKE SRAS SCAS DQMUU, DQMLU,L PPG0 TRG0
Interrupt controller
SDRAM INT0 SIN0 SOT0 SCK0
External interrupts
UART
timer
U-TIMER
PORT
AVRH, AVCC AVSS/AVRL TIN0
PORT
SDA0, SCL0,
Reload timer
Free Timer
FRCK
ICU0
non-ROM model, optimal real time internal model, (Internal Program Loader) internal model adding user model.
CHAPTER OVERVIEW
External Dimensions
MB91301 series available type package.
Dimensions Figure 1.3-1 PGA-179C-A03
PGA-179C-A03
EIAJ code :PGA179-C-S15U-2
179-pin ceramic Lead pitch matrix Sealing method 2.54mm(100mil) Metal seal
(PGA-179C-A03)
179-pin ceramic (PGA-179C-A03)
2.54-0.25 (.100-.010)
1.27(.050)TYP
35.56(1.400)
INDEX
INDEX AREA
0.46 -0.05 .018 -.002 38.10-0.51 (1.500-.020) 6.10(.240)
+.007
+0.18
1.27-0.25 (.050-.010) 3.40 -0.36 .134 -.014
+0.41 +.016
Dimensions (inches).
1994 FUJITSU LIMITED R179004SC-3-2
Dimensions values. Note: values parentheses reference (inches).
CHAPTER OVERVIEW Figure 1.3-2 FPT-144P-M12
FPT-144P-M12
144-pin plastic LQFP Lead pitch Package width package length Lead shape Sealing method Mounting height Weight 0.40 16.0 16.0 Gullwing Plastic mold 1.70 0.88
(FPT-144P-M12)
Code (Reference)
144-pin plastic LQFP (FPT-144P-M12)
18.00±0.20(.709±.008)SQ +0.40 +.016 *16.00 -0.10 .630 -.004
Note These dimensions include resin protrusion. Resin protrusion +0.25(.010)Max(each side). Note Pins width pins thickness include plating thickness. Note Pins width include cutting remainder.
0.08(.003)
Details part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8°
0.60±0.15 (.024±.006) 0.10±0.05 (.004±.002) (Stand off) 0.25(.010)
LEAD
0.40(.016)
0.18±0.035 .007±.001
0.07(.003)
0.145 -0.03 .006
+0.05 +.002 -.001
2003 FUJITSU LIMITED F144024S-c-3-3
Dimensions (inches). Note: values parentheses reference values.
CHAPTER OVERVIEW
Layout
This section shows layout MB91301 series.
Layout MB91V301/V301A Figure 1.4-1 "Pin Layout MB91V301/V301A" diagram layout MB91V301/V301A. Figure 1.4-1 Layout MB91V301/V301A
INDEX
View PGA-179C-A03
CHAPTER OVERVIEW Layout MB91301/302A
Figure 1.4-2 Layout MB91301/302A
D10/P12 D09/P11 D08/P10 D07/P07 D06/P06 D05/P05 D04/P04 D03/P03 D02/P02 D01/P01 D00/P00 CS7/PA7 CS6/PA6 CS5/PPG2/PA5 CS4/TRG2/PA4 CS3/PA3 CS2/PA2 CS1/PA1 CS0/PA0 INIT IORD/PB7 IOWR/PB6 P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P80/RDY P81/BGRNT P82/BRQ DQMUU/WRO P85/DQMUL/WR1 P86/DQMLU/WR2 P87/DQMLL/WR3 P90/SYSCLK
MB91301,MB91302A (Top View)
DEOP1/PPG1/PB5 DACK1/TRG1/PB4 DREQ1/PB3 DEOPO/PB2 DACK0/PB1 DREQ0/PB0 TIN2/TRG3/PH2 TIN1/PPG3/PH1 TIN0/PH0 TRG0/PJ7 PPG0/PJ6 SCK1/PJ5 SOT1/PJ4 SIN1/PJ3 SCK0/PJ2 SOT0/PJ1 SIN0/PJ0 INT7/SCK2/PG7 INT6/SOT2/PG6 INT5/SIN2/PG5 INT4/ATG/PG4/FRC INT3/PG3/ICU3 INT2/PG2/ICU2 INT1/PG1/ICU1 INT0/PG0/ICU0 AVss/AVRL ANRH AVcc
P91/MCLKE P92/MCLK P94/SRAS/LBA/AS P95/SCAS/BAA P96/SWE/WR P60/A16 P61/A17 P62/A18 P63/A19 P64/A20/SDA0 P65/A21/SCL0 P66/A22/SDA1 P67/A23/SCL1
CHAPTER OVERVIEW
Table
table MB91V301/V301A shown.
Table Table 1.5-1 MB91V301/V301A Table (Package: PGA-179C-A03)
N.C. P13/D11 P14/D12 P15/D13 P16/D14 P17/D15 P20/D16 P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 Name P80/RDY P81/BGRNT P82/BRQ DQMUU/WR0 P85/DQMUL/WR1 P86/DQMLU/WR2 P87/DQMLL/WR3 P90/SYSCLK P91/MCLKE P92/MCLK Name P60/A16 P61/A17 P62/A18 P63/A19
SDA0/P64/A20 SDA0;MB91V301A only SCL0/P65/A21 SCL0;MB91V301A only SDA1/P66/A22 SDA1;MB91V301A only SCL1/P67/A23 SCL1;MB91V301A only
Name
P94/SRAS/LABA/AS P95/SCAS/BAA P96/SWE/WR
EWR3 EWR2 EWR1 EWR0 EMRAM ICD3
CHAPTER OVERVIEW Table 1.5-1 MB91V301/V301A Table (Package: PGA-179C-A03)
ICD2 ICD1 ICD0 BREAK ICLK ICS2 ICS1 ICS0 TRST AVCC AVRH AVSS/AVRL
INT0/PG0/ICU0 ICU0;MB91V301A only INT1/PG1/ICU1 ICU1;MB91V301A only INT2/PG2/ICU2 ICU2;MB91V301A only INT3/PG3/ICU3 ICU3;MB91V301A only
Name
Name SOT0/PJ1 SCK0/PJ2 SIN1/PJ3 SOT1/PJ4 SCK1/PJ5 PPG0/PJ6 TRG0/PJ7 TIN0/PH0 TIN1/PPG3/PH1 TIN2/TRG3/PH2 DREQ0/PB0 DACK0/PB1 DEOP0/PB2 DREQ1/PB3 DACK1/TRG1/PB4 DEOP1/PPG1/PB5 IOWR/PB6 IORD/PB7
INIT
Name
CS0/PA0 CS1/PA1 CS2/PA2 CS3/PA3 CS4/TRG2/PA4 CS5/PPG2/PA5 CS6/PA6 CS7/PA7 D00/P00 D01/P01 D02/P02 D03/P03 D04/P04 D05/P05 D06/P06 D07/P07 D08/P10 D09/P11 D10/P12
INT4/ATG/PG4/FRCK FRCK;MB91V301A only
INT5/SIN2/PG5 INT6/SOT2/PG6 INT7/SCK2/PG7 SIN0/PJ0
CHAPTER OVERVIEW
List Functions
This section describes functions MB91301 series.
Description Functions Table 1.6-1 lists MB91301 series their functions. Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
169,
External data bits available external mode. used ports 8-bit 16-bit external mode.
144,
180,
External data bits available external mode. used ports 8-bit 16-bit external mode.
External data bits available external mode. used ports 8-bit external mode.
External data bits available external mode. [RDY] External ready input. this function when external ready input enabled. Active level "H". [P80] General purpose input/output port. this function when external ready input disabled.
BGRNT
[BGRNT] Acknowledge output external release. Outputs when external released. this function when output enabled. [P81] General purpose input/output port. this function when output disabled external release acknowledge.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
[BRQ] External release request input. Input request release external bus. this function when input enabled. [P82] General purpose input/output port. this function when external release request input disabled.
[RD] External read strobe output. This enabled external mode. [WR0] External write strobe output. This enabled external mode. When used write strobe, this becomes byte-enable (UUB). Select signal (DQMUU) using SDRAM. [WR1] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (ULB). [P85] General purpose input/output port. this function when external write-enable output disabled.
WR0/ DQMUU
WR1/ DQMUL
WR2/ DQMLU
[WR2] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (LUB). [P86] General purpose input/output port. this function when external write-enable output disabled.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
WR3/ DQMLL
[WR3] External write strobe output. this function when output enabled. When used write strobe, this becomes byte-enable (LLB). [P87] General purpose input/output port. this functions when external write-enable output disabled.
SYSCLK
[SYSCLK] System clock output. this function when system clock output enabled. This outputs same clock external operating frequency. (Output halts stop mode.) [P90] General purpose input/output port. this function when system clock output disabled.
MCLKE
[MCLKE] Clock enable signal memory. [P91] General purpose input/output port. this function when clock enable output disabled.
MCLK
[MCLK] Memory clock output. this function when memory clock output enabled. This outputs same clock external operating frequency. (Output halts stop sleep mode.) [P92] General purpose input/output port. this function when memory clock output disabled.
[P93] General purpose input/output port.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
[AS] Address strobe output. this function without EDRAM area, when port function register enabled. [LBA] Address strobe output burst flash ROM. this function normal accessed area that over "1", when port function register enabled. [SRAS] single SDRAM. This this function accessing SDRAM area, when port function register enabled. [P94] General purpose input/output port. this function, when port function register general purpose port.
SRAS
[BAA] Address advance output burst Flash ROM. this function when BAAE port function register enabled. [SCAS] signal SDRAM. This this function SDRAM area, when BAAE port function register enabled. [P95] General purpose input/output port. this function when BAAE port function register general purpose port.
SCAS
[WR] Memory write strobe output. This this function when WEXE port function register enabled. [SWR] Write output SDRAM. This this function when WEXE port function register enabled. [P96] General purpose input/output port. This this function when WEXE port function register general purpose port.
External address External address
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
External address used ports when external address unused. used ports when external 8-bit mode.
SDA0
[SDA0] Data bus. This function enable when typical operation enable. port output must remain unless intentionally turned (Open drain output) (This function only MB91302A, MB91V301A.) [A20] External address This function enable during prohibited operation using external bus. [P64] General-purpose port. This function enable during prohibited nonused external address bus.
SCL0
[SCL0] bus. This function enable when typical operation enable. port output must remain unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) [A21] External address This function enable during prohibited operation using external bus. [P65] General-purpose port. This function enable during prohibited nonused external address bus.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
SDA1
[SDA1] DATA bus. This function enable when typical operation enable. output must remains unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) [A22] External address This function enable during prohibited operation using external bus. [P66] General-purpose port. This function enable during prohibited nonused external address bus.
SCL1
[SCL1] bus. This function enable when typical operation enable. port output must remains unless intentionally turned (open drain output) (This function only MB91302A, MB91V301A.) [A23] External address This function enable during prohibited operation unusing external address bus. [P67] General-purpose port. This function enable during prohibited operation nonused external address bus.
Analog input pin.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
INT0 INT3
[INT0 INT3] External interrupt inputs. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. Refer "Chapter Figure 9.3-2" active level settiing. [PG0 PG3] General purpose input/ output ports.
ICU0 ICU3
[ICU0 ICU3] Input capture input pins. These inputs used continuously when selected input capture inputs. this case, output these ports unless doing intentionally. (This function only MB91302A MB91V301A.) [INT4] External interrupt input. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. Refer "Chapter Figure 9.3-2" active level settiing. [ATG] External trigger input converter. This input used continuously when selected converter start trigger. this case, output this port unless doing intentionally. [PG4] General purpose input/output ports.
INT4
FRCK
[FRCK] External clock input freerun timer. These inputs used continuously when using external clock input free-run timer. this case, output these ports unless doing intentionallt. (This function only MB91302A MB90V301A.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
INT5
[INT5] External interrupt input. These inputs used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. Refer "Chapter Figure 9.3-2" active level settiing. [SIN2] UART2 data input pin. This input used continuously when UART2 performing input. this case, output this port unless doing intentionally. [PG5] General purpose input/output port.
SIN2
INT6
[INT6] External interrupt input. This input used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. Refer "Chapter Figure 9.3-2" active level settiing. [SOT2] UART2 data output pin. this function when UART2 data output enabled. [PG6] General purpose input/output port.
SOT2
INT7
[INT7] External interrupt input. This input used continuously when corresponding external interrupt enabled. this case, output these ports unless doing intentionally. Refer "Chapter Figure 9.3-2" active level settiing. [SCK2] UART2 clock input/output pin. this function when UART2 clock output enabled. [PG7] General purpose input/output port.
SCK2
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
SIN0
[SIN0] UART0 data input pin. This input used continuously when UART0 performing input. this case, output this port unless doing intentionally. [PJ0] General purpose input/output port.
SOT0
[SOT0] UART0 data output pin. this function when UART0 data output enabled. [PJ1] General purpose input/output port.
SCK0
[SCK0] UART0 clock input/output pin. this function when UART0 clock output enabled. [PJ2] General purpose input/output port.
SIN1
[SIN1] UART1 data input pin. This input used continuously when UART1 performing input. this case, output this port unless doing intentionally. [PJ3] General purpose input/output port.
SOT1
[SOT1] UART1 data output pin. this function when UART1 data output enabled. [PJ4] General purpose input/output port.
SCK1
[SCK1] UART1 clock input/output pin. this function when UART1 clock output enabled. [PJ5] General purpose input/output port.
PPG0
[PPG0] timer output. This this function when PPG0 output enabled. [PJ6] General purpose input/output port.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
TRG0
[TRG0] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. Refer "Chapter EGS1, EGS0: Trigger input edge select bit" active level setting. [PJ7] General purpose input/output port.
TIN0
[TIN0] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. Refer "Chapter MOD2, MOD1 MOD0 operating mode select bit" active level. [PH0] General purpose input/output port.
TIN1
[TIN1] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. Refer "Chapter MOD2, MOD1 MOD0 operating mode select bit" active level. [PPG3] timer output. this function when PPG3 output enabled. [PH1] General purpose input/output port.
PPG3
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
TIN2
[TIN2] Reload timer input. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. Refer "Chapter MOD2, MOD1 MOD0 operating mode select bit" active level. [TRG3] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port unless doing intentionally. Refer "Chap EGS1, EGS0: Trigger input edge select bit" active level setting. [PH2] General purpose input/output port.
TRG3
DREQ0
[DREQ0] External input transfer requests. This input used continuously when corresponding external input transfer requests enabled. this case, output this port unless doing intentionally. Refer "14.3.1 Setting Transfer Request" active level setting. [PB0] General purpose input/output port.
DACK0
[DACK0] External acknowledge output transfer requests. this function when external acknowledge output transfer requests enabled. [PB1] General purpose input/output port.
DEOP0
[DEOP0] Completion output external transfer. this function when tompletion output external transfer enabled. [PB2] General purpose input/output port.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
DREQ1
[DREQ1] External input transfer requests. This input used continuously when external input transfer request enabled. this case, output this port unless doing intentionally. Refer "14.3.1 Setting Transfer Request" active level. [PB3] General purpose input/output port. this function when completion output stop input disabled transfer.
DACK1
[DACK1] External acknowledge output transfer requests. this function when external acknowledge output transfer requests enabled. [TRG1] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output this port external acknowledge output transfer request unless doing intentionally. [PB4] General purpose input/output port.
TRG1
DEOP1
[DEOP1] Completion output external transfer. this function when completion output external transfer enabled. [PPG1] timer output. this function when PPE1 enabled. [PB5] General purpose input/output port.
PPG1 IOWR
[IOWR] Write strobe output fly-by transfer. this function when outputting write strobe fly-by transfer enabled. [PB6] General purpose input/output port. this function when outputting write strobe fly-by transfer disabled.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
IORD
[IORD] Read strobe output flyby transfer. this function when outputting read strobe fly-by transfer enabled. [PB7] General purpose input/output port. this function when outputting read strobe fly-by transfer disabled.
Clock (oscillation) input. Clock (oscillation) output. [MD0 MD2] Mode pins levels applied these pins basic operating mode. Connect VSS. External reset input (Reset initialize settings) ("L" active) (Non Maskable Interrupt) input ("L" active) [CS0] Chip select output. this function when area CSER (Chip Select Enable Register) enabled specified CS0XE port function register enabled. [PA0] General purpose input/output port. this function when CS0XE port function register general purpose port.
INIT
[CS1] Chip select output. this function when area CSER enabled specified CS1XE port function register enabled. [PA1] General purpose input/output port. this function when chip select output disabled.
[CS2] Chip select output. this function when area CSER enabled specified CS2XE port function register enabled. [PA2] General purpose input/output port. this function when chip select output disabled.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
[CS3] Chip select output. this function when area CSER enabled specified CS3XE port function register enabled. [PA3] General purpose input/output port. this function when chip select output disabled.
[CS4] Chip select output. this function when area CSER enabled specified CS4XE port function register enabled. [TRG2] External trigger input timer. This input used continuously when corresponding timer input enabled. this case, output chip select this port unless doing intentionally. Refer "Chap EGS1, EGS0 trigger input edge select bit" active level setting. [PA4] General purpose input/output port. this function when chip select output disabled.
TRG2
[CS5] Chip select output. this function when area CSER enabled specified CS5XE port function register enabled. [PPG2] timer output. this function when PPE2 enabled. [PA5] General purpose input/output port. this function when chip select output timer output disabled.
PPG2
[CS6] Chip select output. this function when area CSER enabled specified CS6XE port function register enabled. [PA6] General purpose input/output port. this function when chip select output disabled.
CHAPTER OVERVIEW Table 1.6-1 List function (except power supply, pins)
MB91301/ 302A
MB91V301/ V301A
name
circuit type MB91301, MB91V301 MB91302A, MB91V301A
Function
[CS7] Chip select output. this function when area CSER enabled specified CS7XE port function register enabled. [PA7] General purpose input/output port. this function when chip select output disabled.
Shaded pins only present MB91V301. Table 1.6-2 Power supply pins MB91301/302A 101, 114, 130, 111, 121, 115, 131, MB91V301/V301A 131, 142, 145, 154, 164, 170, 119, 141, 146, 150, 151, 155, 165, 171, 102, pins. Connect pins same potential. power supply pins. Connect pins same potential. name Function
AVCC AVRH AVSS/AVRL OPEN
Analog power supply converter Reference power supply converter Capacitor coupling converter Analog converter Open pin. open Capacitor coupling internal regulator
Table 1.6-3 Tool pins MB91301/302A MB91V301/V301A ICLK TRST name circuit type Clock output Tool reset Function
CHAPTER OVERVIEW Table 1.6-3 Tool pins MB91301/302A MB91V301/V301A ICS2 ICS0 ICD3 ICD0 BREAK EMRAM EWR3 EWR0 name circuit type Function
Device status output (during TRC) DSU4 operation status output (during EML) Trace information output (during TRC) Program/data (duuring EML) DSU4 break reqest input Emulation memory detection Chip select emuration memory Write strobe emuration memory
CHAPTER OVERVIEW
Circuit Types
This section describes circuit types.
Circuit Types Table 1.7-1 Circuit Types Type
Circuit
Remarks Oscillation feedback resistance approx. Clock input
Standby control CMOS hysteresis input with pull-up resistor Pull-up resistor value approx. (Typ)
Digital input
Digital output Digital output
CMOS level with standby control
Digital input Standby control
CHAPTER OVERVIEW Table 1.7-1 Circuit Types (Continued) Type Circuit Analog input With switch Remarks
Analog input Channel control CMOS level output standby control
Digital input Pull-up control Digital output Digital output With Pull-up control Pull-up resistor value approx. (Typ) CMOS level with standby control With Pull-up control
Digital input Standby control Pull-up control Digital output Digital output With Pull-up control Pull-up resistor value approx. (Typ) CMOS level output CMOS level hysteresis input with standby control
Digital input Standby control
CHAPTER OVERVIEW Table 1.7-1 Circuit Types (Continued) Type Circuit Pull-up control Digital output Digital output Remarks With Pull-up control Pull-up resistor value approx. (Typ) CMOS level output CMOS level hysteresis input standby control
Digital input CMOS level hysteresis input standby control
Digital input Digital output Digital output Output buffer CMOS level output
Digital input Digital input
Input buffer CMOS level input
Input buffer with pull-down Pull-down resistor value approx. (Typ)
Input buffer with Pull-up Pull-up resistor value approx. (Typ) Digital input
CHAPTER OVERVIEW Table 1.7-1 Circuit Types (Continued) Type Digital output Digital output Circuit Remarks buffer with pull-down CMOS level output Pull-up resistor value approx. (Typ)
Digital input Digital output Digital output buffer CMOS level output
Digital input Pull-up control Digital output with open-drain control Digital output open-drain output CMOS level With standby control Pull-up register value approx. (Typ)
Digital input
STANDBY CONTROL
Digital output Digital output Digital input
STANDBY CONTROL
CMOS level output CMOS level hysteresis input with standby control tolerant
Digital output Digital output Digital input
CMOS level output CMOS level hysteresis input without standby control tolerant
CHAPTER
HANDLING DEVICE
This chapter provides precautions handling MB91301 series. "Precautions Handling Device" "Precautions Handling Power Supplies"
CHAPTER HANDLING DEVICE
Precautions Handling Device
This section contains information preventing latch handling pins.
Preventing Latch latch occur CMOS voltage higher than voltage lower than applied input output voltage higher than rating applied between VSS. latch occurs, significantly increases power supply current cause thermal destruction element. When CMOS very careful exceed maximum rating. Handling Pins following precautions treating various pins quartz oscillation circuits. Unused input pins leave unused input open, since cause malfunction. Handle example, using pull-up pull-down resistor. Power supply pins more than exists, those that must kept same potential designed connected other inside device prevent malfunctions such latch sure connect pins power supply ground external device minimize undesired electromagnetic radiation, prevent strobe signal malfunctions increase ground level, conform total output current rating. Given consideration connecting current supply source device lowest impedance possible. also recommended that ceramic capacitor around connected between circuit points close device bypass capacitor. Quartz oscillation circuit Noise near cause device malfunction. Design printed circuit boards that quartz oscillator ceramic oscillator), bypass capacitor ground located near another possible. strongly recommended that printed circuit board artwork that surrounds pins with ground used increase expectation stable operation.
CHAPTER HANDLING DEVICE External clock When using external clock, general supply while also supplying reversephase clock simultaneously. this case, STOP mode (oscillation stop mode), external resistor about inserted, since stops with level output STOP mode collision between outputs must prevented. Additionally, used only external clock supplied 12.5 MHz. following figure shows example using external clock. Figure 2.1-1 Using external clock (normal)
MB91301 series
Note: Stop mode (oscillation stop mode) used.
Figure 2.1-2 Using external clock (less than 12.5 MHz)
Open MB91301 series
Treatment OPEN pins Pins marked "NC" "OPEN" must left open-circuit. Mode pins (MD0 MD2) These pins must directly connected when they used. Keep pattern length between mode printed circuit board short possible that they connected impedance. Precautions MB91301 series Clock controller Reservea regulator wait time oscillation stabilization wait time when L-level signal input INIT. Notes during operation clock mode clock mode selected, microcontroller attempt working with selfoscillating circuit even when there external oscillator external clock input stopped. Performance this operation, however, cannot guaranteed. MCLK SYSCLK MCLK stopped sleep stop modes, SYSCLK stopped only stop mode. MCLK SYSCLK appropriately according purpose use.
CHAPTER HANDLING DEVICE Pull-up resistor control pull-up resistor connected used external pin, ratings cannot guaranteed. Even port that already pull-up resistor invalid stop mode (HIZ hardware standby mode. search module Only word access allowed BSD0, BSD1, BDSC registers. power consumption mode sure following sequences after using same period standby mode (TBCR: time base counter control register bit8 SYNCS bit) when putting standby mode. (LDI (LDI LDUB LDUB #value_of_standby, #_STCR, R12) @12) Writing standby control register (STCR) @R12, STCR read synchronous standby @R12, Dummy read STCR five NOPs timing adjustment
addition, please flag, ILM, diverge interruption handler that return factor after standby returns. following when monitor debugger used. break point above mentioned instruction row. Execute step above mentioned instruction row. Prefetch When allowing prefetch from area that been little endian area, limit access area word access (i.e., access units bits). area cannot accessed correctly byte half-word accesses. port access Only byte accesses allowed ports. Switching function common port port function register (PFR) switch function which also serves port. However, external setting switch function pin. D-bus memory code area D-bus memory. instruction fetch performed D-bus. Instruction fetches D-bus area result incorrect data interpreted code, which cause microcontroller lose control. data area I-bus memory.
CHAPTER HANDLING DEVICE I-bus memory stack area vector table I-bus memory. cause hang during processing (including RETI). Recovery from hang requires reset. perform transfer I-bus memory. Notes register Since some instructions manipulate register earlier, following exceptions cause interrupt handler break flag update display setting when debugger being used. microcontroller designed carry reprocessing correctly upon returning from such event, performs operations before after specified either case. following operations performed when instruction immediately followed DIVOU/DIVOS instruction halted user interrupt NMI, single-stepped, breaks response data event emulator menu:
flags updated earlier. handler (user interrupt/NMI emulator) executed. Upon returning from EIT, DIVOU/DIVOS instruction executed flags updated same values those above. following operations performed when ORCCR/STILM/MOV instructions executed enable interruptions when user interrupt trigger event occurred.
register updated earlier. handler (user interrupt/NMI) executed. Upon returning from EIT, above instructions executed register updated same value that above. (General purpose register) When following instructions executed, SSP* USP* value used R15, resulting incorrect value written memory. XCHB R15, R15, R15, @Rj, ANDH EORH R15, R15, R15, ANDB EORB R15, R15, R15,
virtual register. When program attempts access R15, accessed depending status flag flag. When coding above instructions using assembler, specify general-purpose register other than R15. RETI instruction Please neither control register instruction cache data access instruction cache immediately before instruction RETI. Watchdog timer function watchdog timer function this model monitors whether program holds over reset within specified time. also resets reset held over because uncontrollable program operation. After watchdog timer function enabled, keeps operating until reset occurs.
CHAPTER HANDLING DEVICE watchdog timer function usually holds over reset automatically when program execution stops. relevant exception conditions, "3.12.7 Peripheral Circuits Clock Controller". reset watchdog timer function might occur above status caused uncontrollable system operation. might occur, reset (INIT) request must input from external INIT pin. converter When device turned returns from reset stop, takes time external capacitor charged, requiring converter wait least Unique evaluation chip MB91V301/301A Tool reset evaluation board, chip with INIT TRST connected together. Single-stepping RETI instruction interrupt occurs frequently during single stepping, execute only relevant processing routine repeatedly after single-stepping RETI. This will prevent main routine lowinterrupt-level programs from being executed. single-step RETI instruction avoidance purposes. When debugging relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. Simultaneous occurrences software break user interrupt/NMI When software break user interrupt /NMI take place same time, emulator debugger cause following phenomena: debugger stops pointing location other than programmed breakpoints. halted program re-executed correctly.
these phenomena occur, hardware break instead software break. monitor debugger been used, avoid setting break relevant location. Operand break stack pointer placed area operand break cause malfunction. apply data event break access area containing address system stack pointer. startup sequence When using ICE, when start debugging, ensure that configuration correctly area being used before downloading. After turning power target, states WR0X WR3X pins undefined until perform above setting. Accordingly, include enabling pull-up part startup sequence. using these pins general-purpose ports, output ports prevent conflict with output signals during time states undefined. External width name (P85) (P86) (P87) Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up Pull-up
CHAPTER HANDLING DEVICE output ports. Configuration batch file example batch file below sets mode vector sets configuration register download area. values appropriate hardware wait, timing, other settings. MODR (0x7fd) =Enable memory+16 External mem/byte 0x7fd=0x5 ASR0 (0x640) 0x0010_0000 0x002f_ffff mem/halfword 0x640=0x0010 ACR0 (0x642) [3:0]=0101:2 MByte [1:0]=01:16 width, automatically from MODR [1:0]=00:1 burst SREN=0:Disable PFEN=1:Enable fetch buffer WREN=1:Enable Write operation LEND=0: endian TYPE [3:0]=0010:WEX: Disable mem/harfword 0x642=0x5462 AWR0 (0x660) W15-12=0010:auto wait=2 WR07, 06=01:RD, delay=1cycle W05, 04=01:WR->WR delay=1cycle (for WEX) =1:MCLK->RD/WR delay=0.5cycle :for async Memory =0:ADR->CS delay=0 =0:ADR->RD/WR setup 0cycle =RD/WR->ADR hold 0cycle mem/halfword 0x660=0x2058 Emulation memory SRAM emulation memory built target board, SRAM accessed signal, +BYTE control signal used. (The external initialized mode accessing RDX, RDnX after reset.)
CHAPTER HANDLING DEVICE
Precautions Handling Power Supplies
This section provides precautions power supplies with regard handling processing when power turned
Processing after Power-on Immediately after power-on, sure apply reset that initializes settings (INIT) from INIT pin. provide oscillation stabilization wait time regulator stabilization wait time immediately after power-on, continue input level INIT long oscillation stabilization wait time required oscillating circuit. (Initialization INIT from INIT sets oscillation stabilization wait time minimum value.) External clock Input after Power-on After power-on, sure input external clock until oscillation stabilization wait canceled. Indeterminate Output When Power Turned When power turned output remain unstable until internal power supply becomes stable. Notes Using Internal DC-DC Regulator Converter MB91301 series contains regulator. sure supply power bypass capacitor about regulator pin. regulator contains converter supplies power AVCC sure insert capacitor least 0.05 between AVSS/AVRL pins. Figure 2.2-1 Notes Using Internal DC-DC Regulator Converter
3.3V 3.3V
AVcc AVRH
0.05
AVss/AVRL
MB91301
CHAPTER
CONTROL UNITS
This chapter provides basic information required understand functions MB91301 series. covers architecture, specifications, instructions. "Memory Space" "Internal Architecture" "Instruction Cache" "Dedicated Registers" "General-Purpose Registers" "Data Structure" "Word Alignment" "Memory Map" "Branch Instructions" 3.10 "EIT (Exception, Interrupt, Trap)" 3.11 "Reset (Device Initialization)" 3.12 "Clock Generation Control" 3.13 "Device State Control" 3.14 "Operating Modes"
CHAPTER CONTROL UNITS
Memory Space
MB91301 series logical address space (232 addresses), which accesses linearly.
Memory Figure 3.1-1 "Memory Map" shows memory space MB91301 series.
CHAPTER CONTROL UNITS Figure 3.1-1 Memory
(MB91302A) (Single chip mode) (MB91302A) Internal External mode (MB91V301A) (MB91301/302A) (MB91V301) Internal External Internal External External mode External mode mode (MODR register (MODR register ROAM=1) ROMA=1) (MB91V301/ V301A) External External mode
0000 0000H
Direct addre ssing area "II/O MAP"
Direct addre ssing area "II/O MAP"
Direct addre ssing area "II/O MAP"
Direct addre ssing area "II/O MAP"
Direct addre ssing area "II/O MAP"
Direct addre ssing area "II/O MAP"
0000 0400H
0001 0000H 0002 0000H
I-RAM
I-RAM
I-RAM
I-RAM
I-RAM
I-RAM
0003 E000H
Access prohibited
Internal Kbytes
Access prohibited
Internal Kbytes
Access prohibited
Internal Kbytes
Access prohibited
Access prohibited
Access prohibited
0003 F000H
Internal Kbytes Internal Kbytes Access prohibited
Internal Kbytes Internal Kbytes Access prohibited External area
Internal Kbytes
0004 0000H
0004 2000H
External area
0006 0000H 000E 0000H
Access prohibited Access prohibited
External area External area
External area
000F E000H
000F F000H
Internal Kbytes*2
0010 0000H
Internal 4Kbytes*2
Internal Kbytes emulation
Access prohibited
FFFF FFFFH
External area
External area
External area
External area
External area
specific area between 10000H 2000H, Kbyte used. Refer "IINSTRUCTION CACHE". real time internal model stores real time kernel. program loader internal model stores program loader. Non-ROM model supports external external mode only. Note Internal emulation only MB91V301A Note: Each mode depending mode vector fetch after INIT negated. (For mode setting, "IMODE SETTINGS".)
CHAPTER CONTROL UNITS Direct addressing area areas address space listed below used input-output. These areas called direct addressing area. address operand directly specified instruction. size direct addressing area varies according size data accessed: Byte data access: 0FFH Halfword data access: 1FFH Word data access: 3FFH
CHAPTER CONTROL UNITS
Internal Architecture
MB91301 series high-performance core based RISC architecture advanced instructions embedded applications.
Features
RISC architecture used Basic instruction: instruction cycle 32-bit architecture General-purpose register: bits linear memory space
Multiplier installed 32-bit 32-bit multiplication: cycles 16-bit 16-bit multiplication: cycles
Enhanced interrupt processing function Quick response speed: cycles Support multiple interrupts Level mask function: levels
Enhanced instructions operations Memory-to-memory transfer instruction Bit-processing instructions
Efficient code Basic instruction word length: bits Low-power consumption Sleep stop modes Gear function
CHAPTER CONTROL UNITS Internal Architecture MB91301 series uses Harvard architecture, which separate buses instructions data. on-chip instruction cache connected instruction (I-bus). 32-bit/16-bit converter connected (F-bus), providing interface between peripheral resources. Harvard/Princeton converter connected both Ibus D-bus, providing interface between controllers. Figure 3.2-1 "Internal Architecture" shows connections internal architecture. Figure 3.2-1 Internal Architecture
FR65E
address address data Drta data Princeton converter External date Harvard External address
32bit
Address
16bit converter
Data
R-bus
F-bus
Peripheral resources
Internal
controller
CHAPTER CONTROL UNITS compact implementation 32-bit RISC MB91301 series architecture. Five instruction pipe lines used execute instruction cycle. pipeline consists following stages: Instruction fetch (IF): Outputs instruction address fetch instruction. Instruction decode (ID): Decodes fetched instruction. Also reads register. Execution (EX): Executes arithmetic operation. Memory access (MA): Performs load store access memory. Write-back (WB): Writes operation result loaded memory data) register Figure 3.2-2 Instruction Pipelines
Instruction Instruction Instruction Instruction Instruction Instruction
Instructions never executed randomly. Instruction enters pipeline before Instruction always reaches write-back stage before Instruction general, instruction executed cycle. However, multiple cycles required execute load/store instruction with memory wait, branch instruction without delay slot, multiple-cycle instruction. execution instructions slows down instructions supplied fast enough. Instruction cache existence on-chip instruction cache enables construction high-performance system without added costs high-speed external memory related control logic. instruction cache supply instructions even when external slow. details instruction cache, Section "Instruction Cache". 32-bit/16-bit converter 32-bit/16-bit converter provides interface between F-bus accessed with 32-bit width R-bus accessed with 16-bit width enables data access from builtin peripheral circuits. performs 32-bit access R-bus, 32-bit/16-bit converter translates access into 16-bit accesses. Some built-in peripheral circuits have limitations access width.
CHAPTER CONTROL UNITS Harvard/Princeton converter Harvard/Princeton converter coordinates instruction data accesses provide smooth interface between external buses. Harvard architecture with separate buses instructions data. other hand, controller that performs control external buses Princeton architecture with single bus. Harvard/Princeton converter assigns priorities instruction data accesses from control accesses controller. This function allows order external accesses permanently optimized. Overview Instructions MB91301 series supports general RISC instructions well logical operation, manipulation, direct addressing instructions optimized embedded applications. Each instruction bits long (some instructions bits long), resulting superior efficiency memory use. list instruction sets, appendix instruction classified into following function groups: Arithmetic operation Load store Branch Logical operation manipulation Direct addressing Other
Arithmetic operation Arithmetic operation instructions include standard arithmetic operation instructions (addition, subtraction, comparison) shift instructions (logical shift arithmetic shift). addition subtraction instructions include operation with carries with multiple-wordlength operations operation that does change flag values, convenience address calculations. Furthermore, 32-bit-by-32-bit 16-bit-by-16-bit multiplication instructions 32-bit-by-32bit step division instruction provided. Additionally, immediate data transfer instruction that sets immediate data register register-to-register transfer instruction provided. arithmetic operation instruction executed using general-purpose registers multiplication division registers CPU. Load store Load store instructions read write external memory. They also used read write peripheral circuit (I/O) chip. Load store instructions have three access lengths: byte, halfword, word. addition indirect memory addressing general registers, indirect memory addressing registers with displacements registers with register incrementing decrementing provided some instructions. Branch branch group includes branch, call, interrupt, return instructions. Some branch instructions have delay slots while others not. These optimized according application. more information about branch instructions, Section "Branch Instructions".
CHAPTER CONTROL UNITS Logical operation manipulation Logical operation instructions perform AND, logical operations between general-purpose registers general-purpose register memory (and I/O). manipulation instructions directly manipulate contents memory (and I/O). They access memory using general register indirect addressing. Direct addressing Direct addressing instructions used access between general-purpose register between memory. High-speed high-efficiency access achieved since address directly specified instruction instead using register indirect addressing. Indirect memory addressing registers with register incrementing decrementing provided some instructions. Other types instructions Other types instructions include instructions that provide flag setting, stack manipulation, sign/ zero extension, other functions register. Also, function entry exit instructions that support high-level languages register multi-load/store instructions provided.
CHAPTER CONTROL UNITS
Instruction Cache
This section describes instruction cache detail.
Overview instruction cache temporary storage memory. When low-speed external memory accesses instruction code, instruction cache internally stores code already accessed once time increase access speed subsequent uses. instruction cache data enables software-based direct read access write access when mode set. turn instruction cache then off, sure subroutine described precautions Section 3.3.4 "Setting Instruction Cache Before Use".
CHAPTER CONTROL UNITS
3.3.1
Configuration Instruction Cache
This section describes configuration instruction cache.
Overview Specifications following overview instruction cache specifications: basic instruction length: bytes Block layout method: 2-way associative Block: consists blocks. block consists bytes blocks). block consists bytes access unit) Configuration Instruction Cache Figure 3.3-1 "Configuration Instruction Cache" shows configuration instruction cache. Figure 3.3-1 Configuration Instruction Cache
bytes Cache blocks Cache
bytes
bytes
bytes Subblock
bytes Subblock Block
Subblock Subblock
Subblock Subblock
Subblock
Subblock
Block
Cache blocks Cache Subblock Subblock Subblock Subblock Block Subblock Subblock Subblock Subblock Block
CHAPTER CONTROL UNITS Instruction Cache Tags Figure 3.3-2 "Configuration Instruction Cache Tags" shows configuration instruction cache tags. Figure 3.3-2 Configuration Instruction Cache Tags
Address
Blank
ETLK
SBV3 SBV2
SBV1 SBV0 TAGV Empty
Subblock valid Entry lock Address
valid
Empty ETLK
SBV3 SBV2
SBV1 SBV0 TAGV
Empty
Subblock valid Entry lock
valid
following describes functions instruction cache bits. [Bits Address address tag, high-order bits memory address instruction cached corresponding block stored. instruction data stored block Block Memory Address which calculated address-tag address used check matching instruction address requested access CPU. Based result check, following operations occurs: requested instruction data exists cache (hit) data transferred from cache within cycle. requested instruction data does exist cache (miss) data acquired external access acquired cache simultaneously.
CHAPTER CONTROL UNITS [Bits block valid SBV*=1, instruction data address indicated been entered corresponding block. Normally, instructions stored block (except immediate data transfer instruction). [Bit valid Indicates whether address value valid. this block becomes invalid regardless block valid (when flushed). [Bit (only Exists only instruction cache Indicates whether, selected set, entry last accessed Indicates that last accessed entry belongs LRU=1 LRU=0. [Bit Entry lock Locks into cache entries block corresponding tag. entries locked ETLK=1 (there updating) cache miss occurs. However, invalid blocks updated. both Ways cache miss occurs while entries locked, cycle required cache miss decision lost then external memory accessed. Note: neither control register instruction cache data access instruction cache immediately before instruction RETI.
CHAPTER CONTROL UNITS
3.3.2
Configuration Control Registers
Control registers include cache size register (ISIZE) instruction cache register (ICHCR). This section describes functions these registers.
Configuration Cache Size Register (ISIZE) Figure 3.3-3 "Configuration Control Register (ISIZE) bits" shows configuration cache size register (ISIZE) bits. Figure 3.3-3 Configuration Control Register (ISIZE) Bits
00000307H
Initial value
SIZE1 SIZE0 -10B
following describes functions cache size register (ISIZE) bits. [Bits SIZE1, SIZE0 These bits capacity instruction cache. Depending setting, cache size, IRAM capacity, address used mode vary shown Figure 3.3-4 "Address RAM". have changed cache capacity, sure flush cache unlock entries before turning cache. Table 3.3-1 Cache Size Registers SIZE1 SIZE0 (Initial value) Setting prohibited Capacity
CHAPTER CONTROL UNITS Figure 3.3-4 Address
Address 00010000H 00010200H 00010400H 00010600H 00010800H 00010FFFH 00014000H 00014200H 00014400H 00014600H 00014800H 00014FFFH 00018000H 00018200H 00018400H 00018 600H 00018 800H 00018 FFFH 0001C000H 0001C200H 0001C400H 0001C600H 0001C800H 0001CFFFH Cache Cache TAG1 Cache Cache TAG1 Cache Cache TAG1 <TAG1> <TAG1> TAG2 <TAG1> TAG2 <TAG1> TAG2 <TAG2> <TAG2> IRAM1 $RAM1 <TAG2> $RAM1 IRAM1 <IRAM1> IRAM2 <$RAM1> $RAM2 <$RAM1> $RAM2 IRAM2 <IRAM2> <$RAM2> <$RAM2> <IRAM2> <IRAM1> <TAG2> $RAM1 IRAM1 <$RAM1> $RAM2 IRAM2 <$RAM2> IRAM2 <IRAM2> IRAM1 <IRAM1> Cache Cache TAG1 <TAG1> <TAG1> <TAG1> <TAG1> TAG2 <TAG2> <TAG2> <TAG2> <TAG2> $RAM1 IRAM1 <$RAM1> $RAM2 IRAM2 <$RAM2>
TAG1.TAG RAM(way1) TAG2.TAG RAM(way2) >.Mirror area on/off.RAM bit=I/O 00010000H 00010004H 00010008 0001000CH 00010010H 00010014H
$RAM1.Cache RAM(way1) IRAM1.I-Bus RAM(way1) $RAM2.Cache RAM(way2) IRAM1.I-Bus RAM(way2)
Entry address Mirror Entry address Mirror
CacheRAM 00018000H 00018004 00018008 0001800CH 00018010 00018014
Instruction Instruction Instruction Instruction Instruction Instruction
address(SBV0) address(SBV1) address(SBV2) address(SBV3) address(SBV0) address(SBV1)
Figure 3.3-5 Memory Allocation Cache Size
Address 000H 200H 400H 600H 000H 200H 400H 600H
Cache $RAM1
Cache $RAM1 IRAM1 $RAM2
Cache $RAM1 IRAM1 $RAM2 IRAM2
Cache IRAM1
$RAM2 IRAM2
IRAM2
CHAPTER CONTROL UNITS Figure 3.3-6 Cache area
ROMAB=0 ROM) Address 00000000H Direct area 00010000H 00020000H 00030000H 00040000H IRAM
ROMAB=1 (ROM) Direct area IRAM (Even D-bus area cache areas cached through bus.)
Internal
00100000H Cache area FFFFFFFFH
Cache area
Each chip-select area non-cacheable area.
Instruction Cache Control Register (ICHCR) instruction cache control register (ICHCR: I-CacHe Control Register) controls instruction cache operation. Writing ICHCR does affect cache operation instruction fetched during subsequent three cycles. Figure 3.3-7 "Configuration Instruction Cache Control Register (ICHCR) bits" shows configuration instruction cache control register. Figure 3.3-7 Configuration Instruction Cache Control Register (ICHCR) bits
000003E7H
Initial value 0-000000B
GBLK ALFL EOLK ELKR FLSH ENAB
CHAPTER CONTROL UNITS following describes functions instruction cache control register (ICHCR) bits. [Bit (RAM mode) this mode set. mode, ENAB turn instruction cache. [Bit GBLK (Global lock) This locks current entries instruction cache. miss occurs when GBLK=1, valid entry instruction cache updated. However, invalid subblocks updated. instruction data fetch operation this time same when entries locked. [Bit ALFL (Autolock fail) This (ALFL) locking attempted entry that already locked. during entry autolock, entry update attempted entry that already locked, entry locked instruction cache regardless what user intends. Reference this debugging program similar purpose. Clear this writing [Bit EOLK (Entry autolock) This either enables disables autolock setting entry instruction cache. entry accessed this (EOLK) (only miss occurs) locked when hardware sets entry lock instruction cache After this point, locked entry subject update when instruction cache miss occurs. However, invalid subblocks updated. ensure that entry locked, flush cache this bit. [Bit ELKR (Entry lock clear) This specifies clearing entry lock instruction cache tags. cycle following which this (ELKR) entry lock cache tags cleared However, content this held only clock cycle cleared second later clock cycles. [Bit FLSH (Flush) This specifies flushing instruction cache. this (FLSH) flush instruction cache. However, content this held only clock cycle cleared second later clock cycles. [Bit ENAB (Enable) This either enables disables instruction cache. this (ENAB) instruction cache disabled instruction access from becomes external directly without going through instruction cache. disabled state, contents instruction cache maintained.
CHAPTER CONTROL UNITS
3.3.3
Instruction Cache Statuses Settings
This section describes state instruction cache each operating modes instruction cache.
Instruction Cache Status Each Operating Mode Table 3.3-2 "Status Instruction Cache Each Operating Mode" shows state instruction cache each operating mode. disable flush states encountered manipulation similar instruction changed only related bit. Table 3.3-2 Status Instruction Cache Each Operating Mode Just after reset Cache memory Address Subblock valid Entry lock valid Global lock Autolock fail Entry autolock Control register Entry lock clear Enable Flush Contents undefined Contents undefined Contents undefined Contents undefined Contents undefined Contents undefined Normal mode Unlocked fail Unlocked clearing Disabled flushed Disable Previous state maintained rewritable while disabled Previous state maintained rewritable while disabled Previous state maintained rewritable while disabled Previous state maintained rewritable while disabled Previous state maintained rewritable while disabled Previous state maintained Flushable while disabled Previous state maintained Flushable while disabled Previous state maintained Rewritable while disabled Previous state maintained Rewritable while disabled Previous state maintained Rewritable while disabled Previous state maintained Rewritable while disabled Disabled Previous state maintained Rewritable while disabled Flush Previous state maintained Previous state maintained Previous state maintained Previous state maintained Entry lock cleared entries invalid Previous state maintained Previous state maintained Previous state maintained Previous state maintained Previous state maintained Previous state maintained Flushed cycle following memory access Returned thereafter
Updating Entries Instruction Cache Entries instruction cache updated shown Table 3.3-3 "Updating Entries
CHAPTER CONTROL UNITS Instruction Cache". Table 3.3-3 Updating Entries Instruction Cache Unlock Miss updated Loads memory updates contents entries instruction cache. updated updated miss. Updated subblock invalid. Lock
Areas Cacheable Instruction Cache instruction cache cache only internal space (RAM8KB) external space. Even contents external memory updated transfer, coherence cached instructions maintained. this case, maintain cache coherence flushing cache. Each chip select area cacheable area. Setting cacheable area, however, carries penalty more cycle than when with instruction cache turned off.
CHAPTER CONTROL UNITS
3.3.4
Setting Instruction Cache Before
This section describes instruction cache before used.
Setup Procedure Before using instruction cache, follows: Initialization Before instruction cache used, must cleared. FLSH ELKR bits register delete past data. #0x000003C7, #0B00000110, I-Cache control register address FLSH (Bit ELKR (Bit Write register
This initializes instruction cache. Enabling instruction cache (ON) enable instruction cache, ENAB #0x000003e7, #0B00000001, I-Cache control register address ENAB (Bit Write register
subsequent instruction access loaded into instruction cache. instruction cache enabled same time initialized. #0x000003e7, #0B00000111, I-Cache control register address ENAB (Bit FLSH (Bit ELKR (Bit Write register
CHAPTER CONTROL UNITS Disabling instruction cache (OFF) disable instruction cache, ENAB #0x000003e7, #0B00000000, I-Cache control register address ENAB (Bit Write register
this state maintained (which same after reset), instruction cache virtually does exist thus does nothing. good idea turn instruction cache overhead seems problem. Locking complete contents cache Lock instruction cache that instructions contains removed, leaving nothing GBLK register Also ENAB since otherwise instruction cache turned locked instructions instruction cache used. #0x000003e7, #0B00100001, I-Cache control register address ENAB (Bit GBLK (Bit Write register
CHAPTER CONTROL UNITS Locking specific instruction instruction cache lock specific group instructions (subroutines, etc.) instruction cache, EOLK before executing instructions. locked instruction accessed highspeed internal ROM. #0x000003e7, #0B00001001, I-Cache control register address ENAB (Bit EOLK (Bit Write register
Depending number memory waits, this becomes valid with next later instruction following instruction. When locking group instructions completed, EOLK #0x000003e7, #0B00000001, I-Cache control register address ENAB (Bit EOLK (Bit Write register
Clearing instruction cache lock Clear lock information instruction locked with EOLK described above. #0x000003e7, #0B00000000, #0B00000101, I-Cache control register address Cache disable Write register ELKR (Bit Write register
Only lock information cleared. Locked instructions replaced sequentially with instructions depending state maintained bit.
CHAPTER CONTROL UNITS
Dedicated Registers
dedicated registers specific purposes. program counter (PC), program status (PS), table base register (TBC), return pointer (RP), system stack pointer (SSP), user stack pointer (USP), multiply divide registers (MDH/MDL) provided.
List Dedicated Registers register consists bits. Figure 3.4-1 "Dedicated Registers" shows dedicated registers. Figure 3.4-1 Dedicated Registers
Program counter Program status Table base register Return pointer System stack pointer User stack pointer
Multiply divide registers
Program Counter (PC) This section describes functions program counter (PC: Program Counter). program counter (PC) consists bits shown below:
[Initial value] XXXXXXXXH
program counter indicates address instruction being executed. updated when instruction executed, only odd-number address specified branch address. however, invalid instruction must placed address that multiple initial value upon reset undefined.
CHAPTER CONTROL UNITS Table Base Register (TBR) This section describes functions table base register (TBR: Table Base Register). table base register (TBR) consists bits shown below:
[Initial value] 000FFC00H
table base register holds first address vector table used during processing. initial value upon reset 000FFC00H. Return Pointer (RP) This section describes functions return pointer (RP: Return Pointer). return pointer (RP) consists bits shown below:
[Initial value] XXXXXXXXH
return pointer holds return address from subroutine. When CALL instruction executed, value transferred When instruction executed, contents transferred initial value upon reset undefined. System Stack Pointer (SSP) This section describes functions system stack pointer (SSP: System Stack Pointer). system stack pointer (SSP) consists bits shown below:
system stack pointer.
Initial value] 00000000H
This register used general-purpose register flag condition code register (CCR) also specified explicitly. This register also used stack pointer that specifies stack which contents saved occurs. initial value upon reset 00000000H.
CHAPTER CONTROL UNITS User Stack Pointer (USP) This section describes functions user stack pointer (USP: User Stack Pointer). user stack pointer (USP) consists bits shown below:
user stack pointer.
Initial value] XXXXXXXXH
This register used general-purpose register flag condition code register (CCR) also specified explicitly. initial value upon reset undefined. This register cannot used RETI instruction. Multiply Divide Registers (MDH/MDL) This section describes functions multiply divide registers (MDH/MDL: Multiply Divide register). multiply divide registers (MDH/MDL) consist bits shown below:
multiply divide registers. Each register bits long. initial value upon reset undefined. Functions when multiplication executed 32-bit-by-32-bit multiplication, 64-bit-long operation result stored multiply divide registers follows: MDH: High-order bits MDL: Low-order bits
16-bit-by-16-bit multiplication, result stored multiply divide registers follows: MDH: Undefined MDL: 32-bit result
Functions when division executed When calculation started, dividend stored MDL. When DIV0S/DIV0U, DIV1, DIV2, DIV3, DIV4S instructions executed perform division, result stored follows: MDH: Remainder MDL: Quotient
CHAPTER CONTROL UNITS
3.4.1
Program Status (PS) Register
program status register (PS: Program Status) holds program status. register consists three parts: ILM, SCR, CCR. undefined bits reserved. During reading, always read. Writing disabled.
Program Status (PS) Register program status (PS) register consists condition code register (CCR), system condition code register (SCR), interrupt level mask (ILM) register.
location
Condition code register (CCR)
condition code register (CCR: Condition Code Register) following configuration:
[Initial value] -00XXXXB
following describes functions these bits. [Bit (Stack flag) This specifies stack pointer used general-purpose register R15. settings this shown following table. Value Description system stack pointer (SSP) used general-purpose register R15. When occurs, this automatically Note that value saved stack value before cleared. user stack pointer (USP) used general-purpose register R15.
This cleared reset. this when RETI instruction executed.
CHAPTER CONTROL UNITS [Bit (Interrupt enable flag) This enables disables user interrupt request. settings this shown following table. Value Description User interrupts disabled. When instruction executed, this cleared Note that value saved stack value before cleared. User interrupts enabled. mask processing user interrupt request controlled value held register.
This cleared reset. [Bit (Negative flag) This indicates sign used when operation result handled integer expressed two's complement. settings this shown following table. Value Description Indicates that operation result positive value. Indicates that operation result negative value.
initial state this upon reset undefined. [Bit (Zero flag) This indicates whether operation result settings this shown following table. Value Description Indicates that operation result Indicates that operation result
initial state this upon reset undefined. [Bit (Overflow flag) This indicates whether overflow occurred result operation when operand used operation handled integer expressed two's complement. settings this shown following table. Value Description Indicates that overflow occurred result operation. Indicates that overflow occurred result operation.
initial state this upon reset undefined.
CHAPTER CONTROL UNITS [Bit (Carry flag) This indicates whether carry borrow occurred from highest operation. settings this shown following table. Value Description Indicates that carry borrow have occurred. Indicates that carry borrow occurred.
initial state this upon reset undefined. System condition code register (SCR) system condition code register (SCR: System Condition code Register) following configuration:
[Initial value] XX0B
following describes functions system condition code register (SCR) bits. [Bits (Step division flag) These bits hold intermediate data obtained when step division executed. change these bits while division processing being executed. perform other processing while executing step division, save restore value register ensure that step division restarted. initial state this upon reset undefined. these bits, execute DIV0S instruction with dividend divisor referenced. forcibly clear these bits, execute DIV0U instruction. [Bit (Step trace trap flag) This specifies whether step trace trap enabled. settings this shown following table. Value step trace trap disabled. step trace trap enabled. With this setting, user user interrupts prohibited. Description
This initialized reset. step trace trap function used emulator. When emulator used, this function cannot used user program.
CHAPTER CONTROL UNITS Interrupt level mask (ILM) register interrupt level mask (ILM) register following configuration:
ILM1
[Initial value] 01111B
ILM4 ILM3 ILM2
interrupt level mask (ILM) register holds interrupt level mask value. value held register used level mask. accepts only interrupt requests sent with interrupt level higher than level indicated ILM. highest level (00000B) lowest level (11111B). Values that program have limit. original value between value must between instruction that sets value between executed, specified value plus transferred. original value between arbitrary value between set. This register initialized (01111B) reset. Note: Since some instructions process register first, interrupt processing routines lead breaks during debugging updating register flag following exceptions. Whichever case, program designed reprocess correctly after returning from ensure that operation before after conforms specifications. following operations occur when user interrupt/NMI received, step execution performed, break occurs data event emulator menu immediately preceding DIVOU/DIVOS instruction. flag precede renewed. processing routine (user interruption, emulator) executed. After returning from EIT, DIVOU/DIVOS instructions executed flags updated same value (1). When each ORCCR/STILM/MOV instruction executed permit interrupting with user interruption factor generated, following operations done. register precedes updated. processing routine (user interruption NMI) executed. After returning from EIT, above instructions executed register updated same value (1).
CHAPTER CONTROL UNITS
General-Purpose Registers
Registers general-purpose registers. These registers used accumulator operation pointer memory access.
General-purpose Registers Figure 3.5-1 "Configuration General-purpose Registers" shows configuration general-purpose registers. Figure 3.5-1 Configuration General-purpose Registers
Initial value XXXX XXXXH
XXXX XXXXH 0000 0000H
these registers, following intended special applications therefore enhanced instructions provided them: R13: Virtual accumulator R14: Frame pointer R15: Stack pointer
initial value upon reset undefined through 00000000H (SSP value) R15.
CHAPTER CONTROL UNITS
Data Structure
MB91301 series uses following data ordering methods: ordering Byte ordering
Ordering MB91301 series uses little endian method ordering. Figure 3.6-1 "Bit Configuration Ordering" shows configuration ordering. Figure 3.6-1 Configuration Ordering
Byte Ordering MB91301 series uses endian method byte ordering.
Figure 3.6-2 "Configuration Byte Ordering" shows configuration byte ordering. Figure 3.6-2 Configuration Byte Ordering
Memory Address
10101010 11001100 11111111 00010001
10101010
Address (n+1) 11001100 Address (n+2) 11111111 Address (n+3) 00010001
CHAPTER CONTROL UNITS
Word Alignment
Since instructions data accessed byte units, addresses which they placed depend instruction length data width.
Program Access program MB91301 series must placed address that multiple program counter (PC) updated when instruction executed. only odd-number address specified branch address. however, invalid instruction must placed address that multiple odd-number address exception exists. Data Access data MB91301 series accessed, forced alignment applied address based width. Word access: address must multiple (The lowest-order bits forcibly 00.) Halfword access: address must multiple (The lowest-order forcibly Byte access:
During word halfword data access, some bits result calculating effective address forcibly example, @(R13, addressing mode, register before addition used without change calculation (even lowest-order loworder bits masked. register before calculation masked. [Example] @(R13, R2),
Addition result Address
00002222H 00000003H
00002225H Lower bits forcibly masked 00002224H
CHAPTER CONTROL UNITS
Memory
This section shows memory MB91301 series.
Memory address space memory bits linear. Figure 3.8-1 "Memory Map" shows memory map. Figure 3.8-1 Memory
0000 0000H Byte data 0000 0100H Halfword data 0000 0200H Word data 0000 0400H Direct addressing area
000F FC00H Vector table initial area 000F FFFFH
FFFF FFFFH
Direct addressing area following areas address space areas I/O. When direct addressing used these areas, operand address directly specified instruction. size address area which address directly specified varies determined data length follows: Byte data bits): 0FFH Halfword data bits): 1FFH Word data bits): 3FFH
Vector table initial area area from 000FFC00H 000FFFFFH initial vector table area. place vector table that will used during processing address rewriting TBR. Initialization reset places table this address.
CHAPTER CONTROL UNITS
Branch Instructions
operation with without delay slot specified branch instruction used MB91301 series.
Branch Instructions with Delay Slot Instructions written follows perform branch operation with delay slot: JMP:D BRA:D BC:D BV:D BLE:D label9 label9 label9 label9 CALL:D BNO:D BNC:D BNV:D BGT:D label12 label9 label9 label9 label9 CALL:D BEQ:D BN:D BLT:D BLS:D label9 label9 label9 label9 RET:D BNE:D BP:D BGE:D BHI:D label9 label9 label9 label9
Branch Instructions without Delay Slot Instructions written follows perform branch operation without delay slot: label9 label9 label9 label9 CALL label12 label9 label9 label9 label9 CALL label9 label9 label9 label9 label9 label9 label9 label9
CHAPTER CONTROL UNITS
3.9.1
Operation Branch Instructions with Delay Slot
operation with delay slot, instruction located just after branch instruction (placed "delay slot") executed before instruction that branches executed.
Operation Branch Instruction with Delay Slot Since instruction delay slot executed before branch operation, apparent execution speed cycle. However, instruction must placed delay slot there valid instruction there. [Example] List instructions BRA:D LABEL Branch destination LABEL Branch instruction Delay slot Executed before branch
conditional branch instruction used, instruction placed delay slot executed whether condition branching met. delay branch instruction used, order execution some instructions seems reversed. However, this occurs only updating instructions executed specified order other operations (register update reference, etc.) following concrete example. JMP:D CALL:D instruction referenced JMP:D CALL:D instruction affected even though updated instruction delay slot. [Example] LDI:32 JMP:D LDI:8 #Label, Branch Label effect branch destination address
CHAPTER CONTROL UNITS RET:D instruction referenced RET:D instruction affected even though updated instruction delay slot. [Example] RET:D Bcc:D instruction flag referenced Bcc:D instruction affected instruction delay slot. [Example] BC:D ANDCCR CALL:D instruction referenced instruction delay slot CALL:D instruction, data that been updated CALL:D instruction read. [Example] CALL:D Limitations Branch Instruction with Delay Slot Label Updating branching Transferring execution result above CALL:D Overflow Flag change Branch execution result above instruction This flag update referenced above branch instruction. Branch address defined beforehand effect return operation
Instructions that placed delay slot Only instruction meeting following conditions executed delay slot. One-cycle instruction Instruction other than branch instruction Instruction whose operation affected even though order changed one-cycle instruction instruction denoted Number Cycles column list instructions
CHAPTER CONTROL UNITS Step trace trap step trace trap does occur between execution branch instruction with delay slot delay slot. Interrupt/NMI interrupt/NMI accepted between execution branch instruction with delay slot delay slot. Undefined instruction exception undefined instruction exception does occur there undefined instruction delay slot. undefined instruction delay slot, operates instruction.
CHAPTER CONTROL UNITS
3.9.2
Operation Branch Instruction without Delay Slot
operation without delay slot, instructions executed order which they specified. instruction immediately following branch never executed before
Operation Branch Instruction without Delay Slot [Example] List instructions LABEL Branch destination LABEL Branch instruction (without delay slot) executed
branch instruction without delay slot executed cycles branch occurs cycle branch occurs. Since appropriate instruction placed delay slot, this instruction results more efficient instruction code than branch instruction with delay slot with specified. both optimal execution speed code efficiency, select operation with delay slot valid instruction placed delay slot; otherwise, select operation without delay slot.
CHAPTER CONTROL UNITS
3.10 (Exception, Interrupt, Trap)
EIT, generic term exception, interrupt, trap, refers suspending program execution event occurs during execution then executing another program.
(Exception, Interrupt, Trap) exception event that occurs related execution context. Execution restarts from instruction that caused exception. interrupt event that occurs independently execution context. event caused hardware. trap event that occurs related execution context. Some traps, such system calls, specified program. Execution restarts from instruction following that caused trap. Features Causes following causes EIT: Reset User interrupt (internal resource, external interrupt) Delayed interrupt Undefined instruction exception Trap instruction (INT) Trap instruction (INTE) Step trace trap No-coprocessor trap Coprocessor error trap Multiple interrupt supported interruption. level mask function levels available user) interruption. Trap instruction (INT) (hardware/software) emulator startup
Return from RETI instruction return from EIT.
CHAPTER CONTROL UNITS
3.10.1 Interrupt Levels
interrupt levels managed with five bits.
Interrupt Levels Table 3.10-1 "EIT Interrupt Levels" shows allocation levels. Table 3.10-1 Interrupt Levels Level Binary 00000 00011 00100 Decimal (Reserved system) (Reserved system) INTE instruction Step trace trap (Reserved system) (Reserved system) (for user) Interrupt Interrupt Interrupt User interrupts prohibited original value between program cannot value this range.
00101 01110 01111 10000 10001 11110 11111
Interrupts prohibited
Operation possible levels interrupt level does affect undefined instruction exception, no-coprocessor trap, coprocessor error trap, instruction. does change ILM, either.
CHAPTER CONTROL UNITS Flag flag that specifies whether interrupt permitted prohibited. This flag provided register. Value Description Interrupts prohibited Cleared instruction executed. Note that value saved stack value before cleared. Interrupts permitted mask processing interrupt request controlled value register.
Interrupt Level Mask (ILM) Register register (Bits that holds interrupt level mask value. accepts only interrupt request sent with interrupt level higher than level indicated ILM. highest level (00000B) lowest level (11111B). Values that program have limit. original value between value must between instruction that sets value between executed, specified value plus transferred. original value between value between set. Note: STILM instruction this register. Level Mask Interrupt interrupt request occurs, interrupt level (Table 3.10-1 "EIT Interrupt Levels") interrupt source compared with level mask value held ILM. request meeting following condition masked accepted: Interrupt level cause Level mask value
CHAPTER CONTROL UNITS
3.10.2 Interrupt Control Register (ICR)
interrupt control register (ICR: Interrupt Control Register), located interrupt controller, sets level interrupt request. provided each interrupt request inputs. mapped space accessed from through bus.
Configuration Interrupt Control Register (ICR) following shows configuration interrupt control register (ICR) bits.
Initial value Initial value -11111B
ICR4 ICR3 ICR2 ICR1 ICR0
following describes functions interrupt control register (ICR) bits. [Bit ICR4 This always [Bits ICR3 These bits low-order bits interrupt level corresponding interrupt source. They read written Together with value between ICR. Mapping Interrupt Control Register (ICR) Table 3.10-2 "Interrupt Sources, Interrupt Control Registers, Interrupt Vectors" shows relationship between interrupt sources, interrupt control register, interrupt vectors. Table 3.10-2 Interrupt Sources, Interrupt Control Registers, Interrupt Vectors Corresponding interrupt vector Interrupt source IRQ00 IRQ01 IRQ02 IRQ45 IRQ46 IRQ47 Interrupt control register Number Address Hexadecimal ICR00 ICR01 ICR02 ICR45 ICR46 ICR47 00000440H 00000441H 00000442H 0000046DH 0000046EH 0000046FH Decimal 3BCH 3B8H 3B4H 308H 304H 300H
Note: CHAPTER "INTERRUPT CONTROLLERS".
CHAPTER CONTROL UNITS
3.10.3 System Stack Pointer(SSP)
system stack pointer (SSP) used point stack save restore data when accepted return operation occurs.
System Stack Pointer(SSP) system stack pointer (SSP: System Stack Pointer) consists bits shown below:
[Initial value] 00000000H
Eight subtracted from register value during processing eight added register value during return operation from that occurs when RETI instruction executed. system stack pointer (SSP) initialized 00000000H reset. also used general-purpose register flag Interrupt Stack value saved restored from area pointed system stack pointer (SSP). After interrupt occurs, stored address indicated stored address indicated plus This situation shown Figure 3.10-1 "Interrupt Stack". Figure 3.10-1 Interrupt Stack
[Example]
[Before interrupt] 80000000H Memory
[After interrupt] 7FFFFFF8H
80000000H 7FFFFFFCH 7FFFFFF8H
80000000H 7FFFFFFCH 7FFFFFF8H
CHAPTER CONTROL UNITS
3.10.4 Table Base Register (TBR)
table base register (TBR: Table Base Register) indicates beginning address vector table EIT.
Table Base Register (TBR) table base register (TBR) consists bits shown below:
[Initial value] 000FFC00H
Obtain vector address adding offset value predetermined cause. table base register (TBR) initialized 000FFC00H reset. Vector Table area from address indicated table base register (TBR) vector area EIT. size each vector bytes. relationship between vector number vector address expressed follows: vctadr vctofs (3FCH vct) vctadr: Vector address vctofs: Vector offset vct: Vector number low-order bits addition result always handled area from 000FFC00H 000FFFFFH initial area vector table upon reset. Special functions allocated some vectors.
CHAPTER CONTROL UNITS Table 3.10-3 "Vector Table" shows vector table architecture. Table 3.10-3 Vector Table Interrupt number Interrupt source Decimal Reset Mode vector Reserved system Reserved system Reserved system Reserved system Reserved system No-coprocessor trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap request (tool) Undefined instruction exception request External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt External Interrupt Reload Timer Reload Timer Reload Timer UART0 (reception completed) UART1 (reception completed) Hexadecimal Interrupt level Fixed 15(FH) ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH Default address 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH
CHAPTER CONTROL UNITS Table 3.10-3 Vector Table (Continued) Interrupt number Interrupt source Decimal UART2 (reception completed) UART0 (transmission completed) UART1 (transmission completed) UART2 (transmission completed) DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) PPG0 PPG1 PPG2 PPG3 Reserved system U-TIMER0 U-TIMER1 U-TIMER2 Time base timer overflow I/FO* I/FI* Reserved system Reserved system 16bit free-runtimer* ICU0 (fetch)* ICU1 (fetch)* ICU2 (fetch)* ICU3 (fetch)* Reserved system Reserved system Reserved system Hexadecimal Interrupt level ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 Offset 388H 384H 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H Default address 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H
CHAPTER CONTROL UNITS Table 3.10-3 Vector Table (Continued) Interrupt number Interrupt source Decimal Reserved system Reserved system Reserved system Delayed interrupt source Reserved system (used REALOS) Reserved system (used REALOS) Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Reserved system Used instruction Hexadecimal Interrupt level ICR44 ICR45 ICR46 ICR47 Offset 30CH 308H 304H 300H 2FCH 2F8H 2F4H 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH 000H Default address 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH 000FFC00H
Reserved system (MB91301, MB91V301)
CHAPTER CONTROL UNITS
3.10.5 Multiple Processing
multiple causes occur same time, repeats operation selecting accepting causes, executing sequence, then detecting causes again. there more causes acc
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